1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2016 Broadcom 4 */ 5 6 #include <linux/array_size.h> 7 #include <linux/bits.h> 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/interrupt.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/types.h> 18 19 #include <linux/iio/iio.h> 20 21 /* Below Register's are common to IPROC ADC and Touchscreen IP */ 22 #define IPROC_REGCTL1 0x00 23 #define IPROC_REGCTL2 0x04 24 #define IPROC_INTERRUPT_THRES 0x08 25 #define IPROC_INTERRUPT_MASK 0x0c 26 #define IPROC_INTERRUPT_STATUS 0x10 27 #define IPROC_ANALOG_CONTROL 0x1c 28 #define IPROC_CONTROLLER_STATUS 0x14 29 #define IPROC_AUX_DATA 0x20 30 #define IPROC_SOFT_BYPASS_CONTROL 0x38 31 #define IPROC_SOFT_BYPASS_DATA 0x3C 32 33 /* IPROC ADC Channel register offsets */ 34 #define IPROC_ADC_CHANNEL_REGCTL1 0x800 35 #define IPROC_ADC_CHANNEL_REGCTL2 0x804 36 #define IPROC_ADC_CHANNEL_STATUS 0x808 37 #define IPROC_ADC_CHANNEL_INTERRUPT_STATUS 0x80c 38 #define IPROC_ADC_CHANNEL_INTERRUPT_MASK 0x810 39 #define IPROC_ADC_CHANNEL_DATA 0x814 40 #define IPROC_ADC_CHANNEL_OFFSET 0x20 41 42 /* Bit definitions for IPROC_REGCTL2 */ 43 #define IPROC_ADC_AUXIN_SCAN_ENA BIT(0) 44 #define IPROC_ADC_PWR_LDO BIT(5) 45 #define IPROC_ADC_PWR_ADC BIT(4) 46 #define IPROC_ADC_PWR_BG BIT(3) 47 #define IPROC_ADC_CONTROLLER_EN BIT(17) 48 49 /* Bit definitions for IPROC_INTERRUPT_MASK and IPROC_INTERRUPT_STATUS */ 50 #define IPROC_ADC_AUXDATA_RDY_INTR BIT(3) 51 #define IPROC_ADC_INTR 9 52 #define IPROC_ADC_INTR_MASK (0xFF << IPROC_ADC_INTR) 53 54 /* Bit definitions for IPROC_ANALOG_CONTROL */ 55 #define IPROC_ADC_CHANNEL_SEL 11 56 #define IPROC_ADC_CHANNEL_SEL_MASK (0x7 << IPROC_ADC_CHANNEL_SEL) 57 58 /* Bit definitions for IPROC_ADC_CHANNEL_REGCTL1 */ 59 #define IPROC_ADC_CHANNEL_ROUNDS 0x2 60 #define IPROC_ADC_CHANNEL_ROUNDS_MASK (0x3F << IPROC_ADC_CHANNEL_ROUNDS) 61 #define IPROC_ADC_CHANNEL_MODE 0x1 62 #define IPROC_ADC_CHANNEL_MODE_MASK (0x1 << IPROC_ADC_CHANNEL_MODE) 63 #define IPROC_ADC_CHANNEL_MODE_TDM 0x1 64 #define IPROC_ADC_CHANNEL_MODE_SNAPSHOT 0x0 65 #define IPROC_ADC_CHANNEL_ENABLE 0x0 66 #define IPROC_ADC_CHANNEL_ENABLE_MASK 0x1 67 68 /* Bit definitions for IPROC_ADC_CHANNEL_REGCTL2 */ 69 #define IPROC_ADC_CHANNEL_WATERMARK 0x0 70 #define IPROC_ADC_CHANNEL_WATERMARK_MASK \ 71 (0x3F << IPROC_ADC_CHANNEL_WATERMARK) 72 73 #define IPROC_ADC_WATER_MARK_LEVEL 0x1 74 75 /* Bit definitions for IPROC_ADC_CHANNEL_STATUS */ 76 #define IPROC_ADC_CHANNEL_DATA_LOST 0x0 77 #define IPROC_ADC_CHANNEL_DATA_LOST_MASK \ 78 (0x0 << IPROC_ADC_CHANNEL_DATA_LOST) 79 #define IPROC_ADC_CHANNEL_VALID_ENTERIES 0x1 80 #define IPROC_ADC_CHANNEL_VALID_ENTERIES_MASK \ 81 (0xFF << IPROC_ADC_CHANNEL_VALID_ENTERIES) 82 #define IPROC_ADC_CHANNEL_TOTAL_ENTERIES 0x9 83 #define IPROC_ADC_CHANNEL_TOTAL_ENTERIES_MASK \ 84 (0xFF << IPROC_ADC_CHANNEL_TOTAL_ENTERIES) 85 86 /* Bit definitions for IPROC_ADC_CHANNEL_INTERRUPT_MASK */ 87 #define IPROC_ADC_CHANNEL_WTRMRK_INTR 0x0 88 #define IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK \ 89 (0x1 << IPROC_ADC_CHANNEL_WTRMRK_INTR) 90 #define IPROC_ADC_CHANNEL_FULL_INTR 0x1 91 #define IPROC_ADC_CHANNEL_FULL_INTR_MASK \ 92 (0x1 << IPROC_ADC_IPROC_ADC_CHANNEL_FULL_INTR) 93 #define IPROC_ADC_CHANNEL_EMPTY_INTR 0x2 94 #define IPROC_ADC_CHANNEL_EMPTY_INTR_MASK \ 95 (0x1 << IPROC_ADC_CHANNEL_EMPTY_INTR) 96 97 #define IPROC_ADC_WATER_MARK_INTR_ENABLE 0x1 98 99 /* Number of time to retry a set of the interrupt mask reg */ 100 #define IPROC_ADC_INTMASK_RETRY_ATTEMPTS 10 101 102 #define IPROC_ADC_READ_TIMEOUT (HZ*2) 103 104 #define iproc_adc_dbg_reg(dev, priv, reg) \ 105 do { \ 106 u32 val; \ 107 regmap_read(priv->regmap, reg, &val); \ 108 dev_dbg(dev, "%20s= 0x%08x\n", #reg, val); \ 109 } while (0) 110 111 struct iproc_adc_priv { 112 struct regmap *regmap; 113 struct mutex mutex; 114 int irqno; 115 int chan_val; 116 int chan_id; 117 struct completion completion; 118 }; 119 120 static void iproc_adc_reg_dump(struct iio_dev *indio_dev) 121 { 122 struct device *dev = &indio_dev->dev; 123 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); 124 125 iproc_adc_dbg_reg(dev, adc_priv, IPROC_REGCTL1); 126 iproc_adc_dbg_reg(dev, adc_priv, IPROC_REGCTL2); 127 iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_THRES); 128 iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_MASK); 129 iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_STATUS); 130 iproc_adc_dbg_reg(dev, adc_priv, IPROC_CONTROLLER_STATUS); 131 iproc_adc_dbg_reg(dev, adc_priv, IPROC_ANALOG_CONTROL); 132 iproc_adc_dbg_reg(dev, adc_priv, IPROC_AUX_DATA); 133 iproc_adc_dbg_reg(dev, adc_priv, IPROC_SOFT_BYPASS_CONTROL); 134 iproc_adc_dbg_reg(dev, adc_priv, IPROC_SOFT_BYPASS_DATA); 135 } 136 137 static irqreturn_t iproc_adc_interrupt_thread(int irq, void *data) 138 { 139 u32 channel_intr_status; 140 u32 intr_status; 141 u32 intr_mask; 142 struct iio_dev *indio_dev = data; 143 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); 144 145 /* 146 * This interrupt is shared with the touchscreen driver. 147 * Make sure this interrupt is intended for us. 148 * Handle only ADC channel specific interrupts. 149 */ 150 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_STATUS, &intr_status); 151 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &intr_mask); 152 intr_status = intr_status & intr_mask; 153 channel_intr_status = (intr_status & IPROC_ADC_INTR_MASK) >> 154 IPROC_ADC_INTR; 155 if (channel_intr_status) 156 return IRQ_WAKE_THREAD; 157 158 return IRQ_NONE; 159 } 160 161 static irqreturn_t iproc_adc_interrupt_handler(int irq, void *data) 162 { 163 irqreturn_t retval = IRQ_NONE; 164 struct iproc_adc_priv *adc_priv; 165 struct iio_dev *indio_dev = data; 166 unsigned int valid_entries; 167 u32 intr_status; 168 u32 intr_channels; 169 u32 channel_status; 170 u32 ch_intr_status; 171 172 adc_priv = iio_priv(indio_dev); 173 174 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_STATUS, &intr_status); 175 dev_dbg(&indio_dev->dev, "iproc_adc_interrupt_handler(),INTRPT_STS:%x\n", 176 intr_status); 177 178 intr_channels = (intr_status & IPROC_ADC_INTR_MASK) >> IPROC_ADC_INTR; 179 if (intr_channels) { 180 regmap_read(adc_priv->regmap, 181 IPROC_ADC_CHANNEL_INTERRUPT_STATUS + 182 IPROC_ADC_CHANNEL_OFFSET * adc_priv->chan_id, 183 &ch_intr_status); 184 185 if (ch_intr_status & IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK) { 186 regmap_read(adc_priv->regmap, 187 IPROC_ADC_CHANNEL_STATUS + 188 IPROC_ADC_CHANNEL_OFFSET * 189 adc_priv->chan_id, 190 &channel_status); 191 192 valid_entries = ((channel_status & 193 IPROC_ADC_CHANNEL_VALID_ENTERIES_MASK) >> 194 IPROC_ADC_CHANNEL_VALID_ENTERIES); 195 if (valid_entries >= 1) { 196 regmap_read(adc_priv->regmap, 197 IPROC_ADC_CHANNEL_DATA + 198 IPROC_ADC_CHANNEL_OFFSET * 199 adc_priv->chan_id, 200 &adc_priv->chan_val); 201 complete(&adc_priv->completion); 202 } else { 203 dev_err(&indio_dev->dev, 204 "No data rcvd on channel %d\n", 205 adc_priv->chan_id); 206 } 207 regmap_write(adc_priv->regmap, 208 IPROC_ADC_CHANNEL_INTERRUPT_MASK + 209 IPROC_ADC_CHANNEL_OFFSET * 210 adc_priv->chan_id, 211 (ch_intr_status & 212 ~(IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK))); 213 } 214 regmap_write(adc_priv->regmap, 215 IPROC_ADC_CHANNEL_INTERRUPT_STATUS + 216 IPROC_ADC_CHANNEL_OFFSET * adc_priv->chan_id, 217 ch_intr_status); 218 regmap_write(adc_priv->regmap, IPROC_INTERRUPT_STATUS, 219 intr_channels); 220 retval = IRQ_HANDLED; 221 } 222 223 return retval; 224 } 225 226 static int iproc_adc_do_read(struct iio_dev *indio_dev, 227 int channel, 228 u16 *p_adc_data) 229 { 230 int read_len = 0; 231 u32 val; 232 u32 mask; 233 u32 val_check; 234 int failed_cnt = 0; 235 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); 236 237 mutex_lock(&adc_priv->mutex); 238 239 /* 240 * After a read is complete the ADC interrupts will be disabled so 241 * we can assume this section of code is safe from interrupts. 242 */ 243 adc_priv->chan_val = -1; 244 adc_priv->chan_id = channel; 245 246 reinit_completion(&adc_priv->completion); 247 /* Clear any pending interrupt */ 248 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_STATUS, 249 IPROC_ADC_INTR_MASK | IPROC_ADC_AUXDATA_RDY_INTR, 250 ((0x0 << channel) << IPROC_ADC_INTR) | 251 IPROC_ADC_AUXDATA_RDY_INTR); 252 253 /* Configure channel for snapshot mode and enable */ 254 val = (BIT(IPROC_ADC_CHANNEL_ROUNDS) | 255 (IPROC_ADC_CHANNEL_MODE_SNAPSHOT << IPROC_ADC_CHANNEL_MODE) | 256 (0x1 << IPROC_ADC_CHANNEL_ENABLE)); 257 258 mask = IPROC_ADC_CHANNEL_ROUNDS_MASK | IPROC_ADC_CHANNEL_MODE_MASK | 259 IPROC_ADC_CHANNEL_ENABLE_MASK; 260 regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_REGCTL1 + 261 IPROC_ADC_CHANNEL_OFFSET * channel), 262 mask, val); 263 264 /* Set the Watermark for a channel */ 265 regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_REGCTL2 + 266 IPROC_ADC_CHANNEL_OFFSET * channel), 267 IPROC_ADC_CHANNEL_WATERMARK_MASK, 268 0x1); 269 270 /* Enable water mark interrupt */ 271 regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_INTERRUPT_MASK + 272 IPROC_ADC_CHANNEL_OFFSET * 273 channel), 274 IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK, 275 IPROC_ADC_WATER_MARK_INTR_ENABLE); 276 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val); 277 278 /* Enable ADC interrupt for a channel */ 279 val |= (BIT(channel) << IPROC_ADC_INTR); 280 regmap_write(adc_priv->regmap, IPROC_INTERRUPT_MASK, val); 281 282 /* 283 * There seems to be a very rare issue where writing to this register 284 * does not take effect. To work around the issue we will try multiple 285 * writes. In total we will spend about 10*10 = 100 us attempting this. 286 * Testing has shown that this may loop a few time, but we have never 287 * hit the full count. 288 */ 289 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check); 290 while (val_check != val) { 291 failed_cnt++; 292 293 if (failed_cnt > IPROC_ADC_INTMASK_RETRY_ATTEMPTS) 294 break; 295 296 udelay(10); 297 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_MASK, 298 IPROC_ADC_INTR_MASK, 299 ((0x1 << channel) << 300 IPROC_ADC_INTR)); 301 302 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check); 303 } 304 305 if (failed_cnt) { 306 dev_dbg(&indio_dev->dev, 307 "IntMask failed (%d times)", failed_cnt); 308 if (failed_cnt > IPROC_ADC_INTMASK_RETRY_ATTEMPTS) { 309 dev_err(&indio_dev->dev, 310 "IntMask set failed. Read will likely fail."); 311 read_len = -EIO; 312 goto adc_err; 313 } 314 } 315 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check); 316 317 if (wait_for_completion_timeout(&adc_priv->completion, 318 IPROC_ADC_READ_TIMEOUT) > 0) { 319 320 /* Only the lower 16 bits are relevant */ 321 *p_adc_data = adc_priv->chan_val & 0xFFFF; 322 read_len = sizeof(*p_adc_data); 323 324 } else { 325 /* 326 * We never got the interrupt, something went wrong. 327 * Perhaps the interrupt may still be coming, we do not want 328 * that now. Lets disable the ADC interrupt, and clear the 329 * status to put it back in to normal state. 330 */ 331 read_len = -ETIMEDOUT; 332 goto adc_err; 333 } 334 mutex_unlock(&adc_priv->mutex); 335 336 return read_len; 337 338 adc_err: 339 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_MASK, 340 IPROC_ADC_INTR_MASK, 341 ((0x0 << channel) << IPROC_ADC_INTR)); 342 343 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_STATUS, 344 IPROC_ADC_INTR_MASK, 345 ((0x0 << channel) << IPROC_ADC_INTR)); 346 347 dev_err(&indio_dev->dev, "Timed out waiting for ADC data!\n"); 348 iproc_adc_reg_dump(indio_dev); 349 mutex_unlock(&adc_priv->mutex); 350 351 return read_len; 352 } 353 354 static int iproc_adc_enable(struct iio_dev *indio_dev) 355 { 356 u32 val; 357 u32 channel_id; 358 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); 359 int ret; 360 361 /* Set i_amux = 3b'000, select channel 0 */ 362 ret = regmap_clear_bits(adc_priv->regmap, IPROC_ANALOG_CONTROL, 363 IPROC_ADC_CHANNEL_SEL_MASK); 364 if (ret) { 365 dev_err(&indio_dev->dev, 366 "failed to write IPROC_ANALOG_CONTROL %d\n", ret); 367 return ret; 368 } 369 adc_priv->chan_val = -1; 370 371 /* 372 * PWR up LDO, ADC, and Band Gap (0 to enable) 373 * Also enable ADC controller (set high) 374 */ 375 ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val); 376 if (ret) { 377 dev_err(&indio_dev->dev, 378 "failed to read IPROC_REGCTL2 %d\n", ret); 379 return ret; 380 } 381 382 val &= ~(IPROC_ADC_PWR_LDO | IPROC_ADC_PWR_ADC | IPROC_ADC_PWR_BG); 383 384 ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val); 385 if (ret) { 386 dev_err(&indio_dev->dev, 387 "failed to write IPROC_REGCTL2 %d\n", ret); 388 return ret; 389 } 390 391 ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val); 392 if (ret) { 393 dev_err(&indio_dev->dev, 394 "failed to read IPROC_REGCTL2 %d\n", ret); 395 return ret; 396 } 397 398 val |= IPROC_ADC_CONTROLLER_EN; 399 ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val); 400 if (ret) { 401 dev_err(&indio_dev->dev, 402 "failed to write IPROC_REGCTL2 %d\n", ret); 403 return ret; 404 } 405 406 for (channel_id = 0; channel_id < indio_dev->num_channels; 407 channel_id++) { 408 ret = regmap_write(adc_priv->regmap, 409 IPROC_ADC_CHANNEL_INTERRUPT_MASK + 410 IPROC_ADC_CHANNEL_OFFSET * channel_id, 0); 411 if (ret) { 412 dev_err(&indio_dev->dev, 413 "failed to write ADC_CHANNEL_INTERRUPT_MASK %d\n", 414 ret); 415 return ret; 416 } 417 418 ret = regmap_write(adc_priv->regmap, 419 IPROC_ADC_CHANNEL_INTERRUPT_STATUS + 420 IPROC_ADC_CHANNEL_OFFSET * channel_id, 0); 421 if (ret) { 422 dev_err(&indio_dev->dev, 423 "failed to write ADC_CHANNEL_INTERRUPT_STATUS %d\n", 424 ret); 425 return ret; 426 } 427 } 428 429 return 0; 430 } 431 432 static void iproc_adc_disable(struct iio_dev *indio_dev) 433 { 434 u32 val; 435 int ret; 436 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); 437 438 ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val); 439 if (ret) { 440 dev_err(&indio_dev->dev, 441 "failed to read IPROC_REGCTL2 %d\n", ret); 442 return; 443 } 444 445 val &= ~IPROC_ADC_CONTROLLER_EN; 446 ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val); 447 if (ret) { 448 dev_err(&indio_dev->dev, 449 "failed to write IPROC_REGCTL2 %d\n", ret); 450 return; 451 } 452 } 453 454 static void iproc_adc_disable_action(void *indio_dev) 455 { 456 iproc_adc_disable(indio_dev); 457 } 458 459 static int iproc_adc_read_raw(struct iio_dev *indio_dev, 460 struct iio_chan_spec const *chan, 461 int *val, 462 int *val2, 463 long mask) 464 { 465 u16 adc_data; 466 int err; 467 468 switch (mask) { 469 case IIO_CHAN_INFO_RAW: 470 err = iproc_adc_do_read(indio_dev, chan->channel, &adc_data); 471 if (err < 0) 472 return err; 473 *val = adc_data; 474 return IIO_VAL_INT; 475 case IIO_CHAN_INFO_SCALE: 476 switch (chan->type) { 477 case IIO_VOLTAGE: 478 *val = 1800; 479 *val2 = 10; 480 return IIO_VAL_FRACTIONAL_LOG2; 481 default: 482 return -EINVAL; 483 } 484 default: 485 return -EINVAL; 486 } 487 } 488 489 static const struct iio_info iproc_adc_iio_info = { 490 .read_raw = &iproc_adc_read_raw, 491 }; 492 493 #define IPROC_ADC_CHANNEL(_index, _id) { \ 494 .type = IIO_VOLTAGE, \ 495 .indexed = 1, \ 496 .channel = _index, \ 497 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 498 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 499 .datasheet_name = _id, \ 500 } 501 502 static const struct iio_chan_spec iproc_adc_iio_channels[] = { 503 IPROC_ADC_CHANNEL(0, "adc0"), 504 IPROC_ADC_CHANNEL(1, "adc1"), 505 IPROC_ADC_CHANNEL(2, "adc2"), 506 IPROC_ADC_CHANNEL(3, "adc3"), 507 IPROC_ADC_CHANNEL(4, "adc4"), 508 IPROC_ADC_CHANNEL(5, "adc5"), 509 IPROC_ADC_CHANNEL(6, "adc6"), 510 IPROC_ADC_CHANNEL(7, "adc7"), 511 }; 512 513 static int iproc_adc_probe(struct platform_device *pdev) 514 { 515 struct iproc_adc_priv *adc_priv; 516 struct iio_dev *indio_dev = NULL; 517 struct device *dev = &pdev->dev; 518 struct clk *adc_clk; 519 int ret; 520 521 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc_priv)); 522 if (!indio_dev) 523 return -ENOMEM; 524 525 adc_priv = iio_priv(indio_dev); 526 527 ret = devm_mutex_init(dev, &adc_priv->mutex); 528 if (ret) 529 return ret; 530 531 init_completion(&adc_priv->completion); 532 533 adc_priv->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 534 "adc-syscon"); 535 if (IS_ERR(adc_priv->regmap)) 536 return dev_err_probe(dev, PTR_ERR(adc_priv->regmap), 537 "failed to get handle for tsc syscon\n"); 538 539 adc_clk = devm_clk_get_enabled(dev, "tsc_clk"); 540 if (IS_ERR(adc_clk)) 541 return dev_err_probe(dev, PTR_ERR(adc_clk), "failed to enable clock\n"); 542 543 adc_priv->irqno = platform_get_irq(pdev, 0); 544 if (adc_priv->irqno < 0) 545 return adc_priv->irqno; 546 547 ret = regmap_clear_bits(adc_priv->regmap, IPROC_REGCTL2, 548 IPROC_ADC_AUXIN_SCAN_ENA); 549 if (ret) 550 return dev_err_probe(dev, ret, "failed to write IPROC_REGCTL2\n"); 551 552 ret = devm_request_threaded_irq(dev, adc_priv->irqno, 553 iproc_adc_interrupt_handler, 554 iproc_adc_interrupt_thread, 555 IRQF_SHARED, "iproc-adc", indio_dev); 556 if (ret) 557 return ret; 558 559 ret = iproc_adc_enable(indio_dev); 560 if (ret) 561 return ret; 562 563 ret = devm_add_action_or_reset(dev, iproc_adc_disable_action, indio_dev); 564 if (ret) 565 return ret; 566 567 indio_dev->name = "iproc-static-adc"; 568 indio_dev->info = &iproc_adc_iio_info; 569 indio_dev->modes = INDIO_DIRECT_MODE; 570 indio_dev->channels = iproc_adc_iio_channels; 571 indio_dev->num_channels = ARRAY_SIZE(iproc_adc_iio_channels); 572 573 return devm_iio_device_register(dev, indio_dev); 574 } 575 576 static const struct of_device_id iproc_adc_of_match[] = { 577 {.compatible = "brcm,iproc-static-adc", }, 578 { } 579 }; 580 MODULE_DEVICE_TABLE(of, iproc_adc_of_match); 581 582 static struct platform_driver iproc_adc_driver = { 583 .probe = iproc_adc_probe, 584 .driver = { 585 .name = "iproc-static-adc", 586 .of_match_table = iproc_adc_of_match, 587 }, 588 }; 589 module_platform_driver(iproc_adc_driver); 590 591 MODULE_DESCRIPTION("Broadcom iProc ADC controller driver"); 592 MODULE_AUTHOR("Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>"); 593 MODULE_LICENSE("GPL v2"); 594