xref: /linux/include/uapi/drm/xe_drm.h (revision 42b16d3ac371a2fac9b6f08fd75f23f34ba3955a)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #ifndef _UAPI_XE_DRM_H_
7 #define _UAPI_XE_DRM_H_
8 
9 #include "drm.h"
10 
11 #if defined(__cplusplus)
12 extern "C" {
13 #endif
14 
15 /*
16  * Please note that modifications to all structs defined here are
17  * subject to backwards-compatibility constraints.
18  * Sections in this file are organized as follows:
19  *   1. IOCTL definition
20  *   2. Extension definition and helper structs
21  *   3. IOCTL's Query structs in the order of the Query's entries.
22  *   4. The rest of IOCTL structs in the order of IOCTL declaration.
23  */
24 
25 /**
26  * DOC: Xe Device Block Diagram
27  *
28  * The diagram below represents a high-level simplification of a discrete
29  * GPU supported by the Xe driver. It shows some device components which
30  * are necessary to understand this API, as well as how their relations
31  * to each other. This diagram does not represent real hardware::
32  *
33  *   ┌──────────────────────────────────────────────────────────────────┐
34  *   │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │
35  *   │ │        ┌───────────────────────┐   ┌─────┐       │ │ ┌─────┐ │ │
36  *   │ │        │         VRAM0         ├───┤ ... │       │ │ │VRAM1│ │ │
37  *   │ │        └───────────┬───────────┘   └─GT1─┘       │ │ └──┬──┘ │ │
38  *   │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │
39  *   │ │ │ ┌─────────────────────┐  ┌─────────────────┐ │ │ │ │     │ │ │
40  *   │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │  │ ┌─────┐ ┌─────┐ │ │ │ │ │     │ │ │
41  *   │ │ │ │ │EU│ │EU│ │EU│ │EU│ │  │ │RCS0 │ │BCS0 │ │ │ │ │ │     │ │ │
42  *   │ │ │ │ └──┘ └──┘ └──┘ └──┘ │  │ └─────┘ └─────┘ │ │ │ │ │     │ │ │
43  *   │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │  │ ┌─────┐ ┌─────┐ │ │ │ │ │     │ │ │
44  *   │ │ │ │ │EU│ │EU│ │EU│ │EU│ │  │ │VCS0 │ │VCS1 │ │ │ │ │ │     │ │ │
45  *   │ │ │ │ └──┘ └──┘ └──┘ └──┘ │  │ └─────┘ └─────┘ │ │ │ │ │     │ │ │
46  *   │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │  │ ┌─────┐ ┌─────┐ │ │ │ │ │     │ │ │
47  *   │ │ │ │ │EU│ │EU│ │EU│ │EU│ │  │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │
48  *   │ │ │ │ └──┘ └──┘ └──┘ └──┘ │  │ └─────┘ └─────┘ │ │ │ │ │     │ │ │
49  *   │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │  │ ┌─────┐ ┌─────┐ │ │ │ │ │     │ │ │
50  *   │ │ │ │ │EU│ │EU│ │EU│ │EU│ │  │ │CCS0 │ │CCS1 │ │ │ │ │ │     │ │ │
51  *   │ │ │ │ └──┘ └──┘ └──┘ └──┘ │  │ └─────┘ └─────┘ │ │ │ │ │     │ │ │
52  *   │ │ │ └─────────DSS─────────┘  │ ┌─────┐ ┌─────┐ │ │ │ │ │     │ │ │
53  *   │ │ │                          │ │CCS2 │ │CCS3 │ │ │ │ │ │     │ │ │
54  *   │ │ │ ┌─────┐ ┌─────┐ ┌─────┐  │ └─────┘ └─────┘ │ │ │ │ │     │ │ │
55  *   │ │ │ │ ... │ │ ... │ │ ... │  │                 │ │ │ │ │     │ │ │
56  *   │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘  └─────Engines─────┘ │ │ │ │     │ │ │
57  *   │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │
58  *   │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │
59  *   └─────────────────────────────Device0───────┬──────────────────────┘
60  *                                               │
61  *                        ───────────────────────┴────────── PCI bus
62  */
63 
64 /**
65  * DOC: Xe uAPI Overview
66  *
67  * This section aims to describe the Xe's IOCTL entries, its structs, and other
68  * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related
69  * entries and usage.
70  *
71  * List of supported IOCTLs:
72  *  - &DRM_IOCTL_XE_DEVICE_QUERY
73  *  - &DRM_IOCTL_XE_GEM_CREATE
74  *  - &DRM_IOCTL_XE_GEM_MMAP_OFFSET
75  *  - &DRM_IOCTL_XE_VM_CREATE
76  *  - &DRM_IOCTL_XE_VM_DESTROY
77  *  - &DRM_IOCTL_XE_VM_BIND
78  *  - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
79  *  - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
80  *  - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
81  *  - &DRM_IOCTL_XE_EXEC
82  *  - &DRM_IOCTL_XE_WAIT_USER_FENCE
83  *  - &DRM_IOCTL_XE_OBSERVATION
84  */
85 
86 /*
87  * xe specific ioctls.
88  *
89  * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
90  * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
91  * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
92  */
93 #define DRM_XE_DEVICE_QUERY		0x00
94 #define DRM_XE_GEM_CREATE		0x01
95 #define DRM_XE_GEM_MMAP_OFFSET		0x02
96 #define DRM_XE_VM_CREATE		0x03
97 #define DRM_XE_VM_DESTROY		0x04
98 #define DRM_XE_VM_BIND			0x05
99 #define DRM_XE_EXEC_QUEUE_CREATE	0x06
100 #define DRM_XE_EXEC_QUEUE_DESTROY	0x07
101 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY	0x08
102 #define DRM_XE_EXEC			0x09
103 #define DRM_XE_WAIT_USER_FENCE		0x0a
104 #define DRM_XE_OBSERVATION		0x0b
105 
106 /* Must be kept compact -- no holes */
107 
108 #define DRM_IOCTL_XE_DEVICE_QUERY		DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)
109 #define DRM_IOCTL_XE_GEM_CREATE			DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create)
110 #define DRM_IOCTL_XE_GEM_MMAP_OFFSET		DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset)
111 #define DRM_IOCTL_XE_VM_CREATE			DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)
112 #define DRM_IOCTL_XE_VM_DESTROY			DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
113 #define DRM_IOCTL_XE_VM_BIND			DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
114 #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE		DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create)
115 #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY		DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy)
116 #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY	DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property)
117 #define DRM_IOCTL_XE_EXEC			DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
118 #define DRM_IOCTL_XE_WAIT_USER_FENCE		DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
119 #define DRM_IOCTL_XE_OBSERVATION		DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param)
120 
121 /**
122  * DOC: Xe IOCTL Extensions
123  *
124  * Before detailing the IOCTLs and its structs, it is important to highlight
125  * that every IOCTL in Xe is extensible.
126  *
127  * Many interfaces need to grow over time. In most cases we can simply
128  * extend the struct and have userspace pass in more data. Another option,
129  * as demonstrated by Vulkan's approach to providing extensions for forward
130  * and backward compatibility, is to use a list of optional structs to
131  * provide those extra details.
132  *
133  * The key advantage to using an extension chain is that it allows us to
134  * redefine the interface more easily than an ever growing struct of
135  * increasing complexity, and for large parts of that interface to be
136  * entirely optional. The downside is more pointer chasing; chasing across
137  * the __user boundary with pointers encapsulated inside u64.
138  *
139  * Example chaining:
140  *
141  * .. code-block:: C
142  *
143  *	struct drm_xe_user_extension ext3 {
144  *		.next_extension = 0, // end
145  *		.name = ...,
146  *	};
147  *	struct drm_xe_user_extension ext2 {
148  *		.next_extension = (uintptr_t)&ext3,
149  *		.name = ...,
150  *	};
151  *	struct drm_xe_user_extension ext1 {
152  *		.next_extension = (uintptr_t)&ext2,
153  *		.name = ...,
154  *	};
155  *
156  * Typically the struct drm_xe_user_extension would be embedded in some uAPI
157  * struct, and in this case we would feed it the head of the chain(i.e ext1),
158  * which would then apply all of the above extensions.
159 */
160 
161 /**
162  * struct drm_xe_user_extension - Base class for defining a chain of extensions
163  */
164 struct drm_xe_user_extension {
165 	/**
166 	 * @next_extension:
167 	 *
168 	 * Pointer to the next struct drm_xe_user_extension, or zero if the end.
169 	 */
170 	__u64 next_extension;
171 
172 	/**
173 	 * @name: Name of the extension.
174 	 *
175 	 * Note that the name here is just some integer.
176 	 *
177 	 * Also note that the name space for this is not global for the whole
178 	 * driver, but rather its scope/meaning is limited to the specific piece
179 	 * of uAPI which has embedded the struct drm_xe_user_extension.
180 	 */
181 	__u32 name;
182 
183 	/**
184 	 * @pad: MBZ
185 	 *
186 	 * All undefined bits must be zero.
187 	 */
188 	__u32 pad;
189 };
190 
191 /**
192  * struct drm_xe_ext_set_property - Generic set property extension
193  *
194  * A generic struct that allows any of the Xe's IOCTL to be extended
195  * with a set_property operation.
196  */
197 struct drm_xe_ext_set_property {
198 	/** @base: base user extension */
199 	struct drm_xe_user_extension base;
200 
201 	/** @property: property to set */
202 	__u32 property;
203 
204 	/** @pad: MBZ */
205 	__u32 pad;
206 
207 	/** @value: property value */
208 	__u64 value;
209 
210 	/** @reserved: Reserved */
211 	__u64 reserved[2];
212 };
213 
214 /**
215  * struct drm_xe_engine_class_instance - instance of an engine class
216  *
217  * It is returned as part of the @drm_xe_engine, but it also is used as
218  * the input of engine selection for both @drm_xe_exec_queue_create and
219  * @drm_xe_query_engine_cycles
220  *
221  * The @engine_class can be:
222  *  - %DRM_XE_ENGINE_CLASS_RENDER
223  *  - %DRM_XE_ENGINE_CLASS_COPY
224  *  - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE
225  *  - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE
226  *  - %DRM_XE_ENGINE_CLASS_COMPUTE
227  *  - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual
228  *    hardware engine class). Used for creating ordered queues of VM
229  *    bind operations.
230  */
231 struct drm_xe_engine_class_instance {
232 #define DRM_XE_ENGINE_CLASS_RENDER		0
233 #define DRM_XE_ENGINE_CLASS_COPY		1
234 #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE	2
235 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE	3
236 #define DRM_XE_ENGINE_CLASS_COMPUTE		4
237 #define DRM_XE_ENGINE_CLASS_VM_BIND		5
238 	/** @engine_class: engine class id */
239 	__u16 engine_class;
240 	/** @engine_instance: engine instance id */
241 	__u16 engine_instance;
242 	/** @gt_id: Unique ID of this GT within the PCI Device */
243 	__u16 gt_id;
244 	/** @pad: MBZ */
245 	__u16 pad;
246 };
247 
248 /**
249  * struct drm_xe_engine - describe hardware engine
250  */
251 struct drm_xe_engine {
252 	/** @instance: The @drm_xe_engine_class_instance */
253 	struct drm_xe_engine_class_instance instance;
254 
255 	/** @reserved: Reserved */
256 	__u64 reserved[3];
257 };
258 
259 /**
260  * struct drm_xe_query_engines - describe engines
261  *
262  * If a query is made with a struct @drm_xe_device_query where .query
263  * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of
264  * struct @drm_xe_query_engines in .data.
265  */
266 struct drm_xe_query_engines {
267 	/** @num_engines: number of engines returned in @engines */
268 	__u32 num_engines;
269 	/** @pad: MBZ */
270 	__u32 pad;
271 	/** @engines: The returned engines for this device */
272 	struct drm_xe_engine engines[];
273 };
274 
275 /**
276  * enum drm_xe_memory_class - Supported memory classes.
277  */
278 enum drm_xe_memory_class {
279 	/** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */
280 	DRM_XE_MEM_REGION_CLASS_SYSMEM = 0,
281 	/**
282 	 * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this
283 	 * represents the memory that is local to the device, which we
284 	 * call VRAM. Not valid on integrated platforms.
285 	 */
286 	DRM_XE_MEM_REGION_CLASS_VRAM
287 };
288 
289 /**
290  * struct drm_xe_mem_region - Describes some region as known to
291  * the driver.
292  */
293 struct drm_xe_mem_region {
294 	/**
295 	 * @mem_class: The memory class describing this region.
296 	 *
297 	 * See enum drm_xe_memory_class for supported values.
298 	 */
299 	__u16 mem_class;
300 	/**
301 	 * @instance: The unique ID for this region, which serves as the
302 	 * index in the placement bitmask used as argument for
303 	 * &DRM_IOCTL_XE_GEM_CREATE
304 	 */
305 	__u16 instance;
306 	/**
307 	 * @min_page_size: Min page-size in bytes for this region.
308 	 *
309 	 * When the kernel allocates memory for this region, the
310 	 * underlying pages will be at least @min_page_size in size.
311 	 * Buffer objects with an allowable placement in this region must be
312 	 * created with a size aligned to this value.
313 	 * GPU virtual address mappings of (parts of) buffer objects that
314 	 * may be placed in this region must also have their GPU virtual
315 	 * address and range aligned to this value.
316 	 * Affected IOCTLS will return %-EINVAL if alignment restrictions are
317 	 * not met.
318 	 */
319 	__u32 min_page_size;
320 	/**
321 	 * @total_size: The usable size in bytes for this region.
322 	 */
323 	__u64 total_size;
324 	/**
325 	 * @used: Estimate of the memory used in bytes for this region.
326 	 *
327 	 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
328 	 * accounting.  Without this the value here will always equal
329 	 * zero.
330 	 */
331 	__u64 used;
332 	/**
333 	 * @cpu_visible_size: How much of this region can be CPU
334 	 * accessed, in bytes.
335 	 *
336 	 * This will always be <= @total_size, and the remainder (if
337 	 * any) will not be CPU accessible. If the CPU accessible part
338 	 * is smaller than @total_size then this is referred to as a
339 	 * small BAR system.
340 	 *
341 	 * On systems without small BAR (full BAR), the probed_size will
342 	 * always equal the @total_size, since all of it will be CPU
343 	 * accessible.
344 	 *
345 	 * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM
346 	 * regions (for other types the value here will always equal
347 	 * zero).
348 	 */
349 	__u64 cpu_visible_size;
350 	/**
351 	 * @cpu_visible_used: Estimate of CPU visible memory used, in
352 	 * bytes.
353 	 *
354 	 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
355 	 * accounting. Without this the value here will always equal
356 	 * zero.  Note this is only currently tracked for
357 	 * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value
358 	 * here will always be zero).
359 	 */
360 	__u64 cpu_visible_used;
361 	/** @reserved: Reserved */
362 	__u64 reserved[6];
363 };
364 
365 /**
366  * struct drm_xe_query_mem_regions - describe memory regions
367  *
368  * If a query is made with a struct drm_xe_device_query where .query
369  * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses
370  * struct drm_xe_query_mem_regions in .data.
371  */
372 struct drm_xe_query_mem_regions {
373 	/** @num_mem_regions: number of memory regions returned in @mem_regions */
374 	__u32 num_mem_regions;
375 	/** @pad: MBZ */
376 	__u32 pad;
377 	/** @mem_regions: The returned memory regions for this device */
378 	struct drm_xe_mem_region mem_regions[];
379 };
380 
381 /**
382  * struct drm_xe_query_config - describe the device configuration
383  *
384  * If a query is made with a struct drm_xe_device_query where .query
385  * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses
386  * struct drm_xe_query_config in .data.
387  *
388  * The index in @info can be:
389  *  - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits)
390  *    and the device revision (next 8 bits)
391  *  - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device
392  *    configuration, see list below
393  *
394  *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device
395  *      has usable VRAM
396  *  - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
397  *    required by this device, typically SZ_4K or SZ_64K
398  *  - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
399  *  - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest
400  *    available exec queue priority
401  */
402 struct drm_xe_query_config {
403 	/** @num_params: number of parameters returned in info */
404 	__u32 num_params;
405 
406 	/** @pad: MBZ */
407 	__u32 pad;
408 
409 #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID	0
410 #define DRM_XE_QUERY_CONFIG_FLAGS			1
411 	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM	(1 << 0)
412 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT		2
413 #define DRM_XE_QUERY_CONFIG_VA_BITS			3
414 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY	4
415 	/** @info: array of elements containing the config info */
416 	__u64 info[];
417 };
418 
419 /**
420  * struct drm_xe_gt - describe an individual GT.
421  *
422  * To be used with drm_xe_query_gt_list, which will return a list with all the
423  * existing GT individual descriptions.
424  * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for
425  * implementing graphics and/or media operations.
426  *
427  * The index in @type can be:
428  *  - %DRM_XE_QUERY_GT_TYPE_MAIN
429  *  - %DRM_XE_QUERY_GT_TYPE_MEDIA
430  */
431 struct drm_xe_gt {
432 #define DRM_XE_QUERY_GT_TYPE_MAIN		0
433 #define DRM_XE_QUERY_GT_TYPE_MEDIA		1
434 	/** @type: GT type: Main or Media */
435 	__u16 type;
436 	/** @tile_id: Tile ID where this GT lives (Information only) */
437 	__u16 tile_id;
438 	/** @gt_id: Unique ID of this GT within the PCI Device */
439 	__u16 gt_id;
440 	/** @pad: MBZ */
441 	__u16 pad[3];
442 	/** @reference_clock: A clock frequency for timestamp */
443 	__u32 reference_clock;
444 	/**
445 	 * @near_mem_regions: Bit mask of instances from
446 	 * drm_xe_query_mem_regions that are nearest to the current engines
447 	 * of this GT.
448 	 * Each index in this mask refers directly to the struct
449 	 * drm_xe_query_mem_regions' instance, no assumptions should
450 	 * be made about order. The type of each region is described
451 	 * by struct drm_xe_query_mem_regions' mem_class.
452 	 */
453 	__u64 near_mem_regions;
454 	/**
455 	 * @far_mem_regions: Bit mask of instances from
456 	 * drm_xe_query_mem_regions that are far from the engines of this GT.
457 	 * In general, they have extra indirections when compared to the
458 	 * @near_mem_regions. For a discrete device this could mean system
459 	 * memory and memory living in a different tile.
460 	 * Each index in this mask refers directly to the struct
461 	 * drm_xe_query_mem_regions' instance, no assumptions should
462 	 * be made about order. The type of each region is described
463 	 * by struct drm_xe_query_mem_regions' mem_class.
464 	 */
465 	__u64 far_mem_regions;
466 	/** @ip_ver_major: Graphics/media IP major version on GMD_ID platforms */
467 	__u16 ip_ver_major;
468 	/** @ip_ver_minor: Graphics/media IP minor version on GMD_ID platforms */
469 	__u16 ip_ver_minor;
470 	/** @ip_ver_rev: Graphics/media IP revision version on GMD_ID platforms */
471 	__u16 ip_ver_rev;
472 	/** @pad2: MBZ */
473 	__u16 pad2;
474 	/** @reserved: Reserved */
475 	__u64 reserved[7];
476 };
477 
478 /**
479  * struct drm_xe_query_gt_list - A list with GT description items.
480  *
481  * If a query is made with a struct drm_xe_device_query where .query
482  * is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct
483  * drm_xe_query_gt_list in .data.
484  */
485 struct drm_xe_query_gt_list {
486 	/** @num_gt: number of GT items returned in gt_list */
487 	__u32 num_gt;
488 	/** @pad: MBZ */
489 	__u32 pad;
490 	/** @gt_list: The GT list returned for this device */
491 	struct drm_xe_gt gt_list[];
492 };
493 
494 /**
495  * struct drm_xe_query_topology_mask - describe the topology mask of a GT
496  *
497  * This is the hardware topology which reflects the internal physical
498  * structure of the GPU.
499  *
500  * If a query is made with a struct drm_xe_device_query where .query
501  * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses
502  * struct drm_xe_query_topology_mask in .data.
503  *
504  * The @type can be:
505  *  - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices
506  *    (DSS) available for geometry operations. For example a query response
507  *    containing the following in mask:
508  *    ``DSS_GEOMETRY    ff ff ff ff 00 00 00 00``
509  *    means 32 DSS are available for geometry.
510  *  - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices
511  *    (DSS) available for compute operations. For example a query response
512  *    containing the following in mask:
513  *    ``DSS_COMPUTE    ff ff ff ff 00 00 00 00``
514  *    means 32 DSS are available for compute.
515  *  - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks
516  *  - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU)
517  *    available per Dual Sub Slices (DSS). For example a query response
518  *    containing the following in mask:
519  *    ``EU_PER_DSS    ff ff 00 00 00 00 00 00``
520  *    means each DSS has 16 SIMD8 EUs. This type may be omitted if device
521  *    doesn't have SIMD8 EUs.
522  *  - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution
523  *    Units (EU) available per Dual Sub Slices (DSS). For example a query
524  *    response containing the following in mask:
525  *    ``SIMD16_EU_PER_DSS    ff ff 00 00 00 00 00 00``
526  *    means each DSS has 16 SIMD16 EUs. This type may be omitted if device
527  *    doesn't have SIMD16 EUs.
528  */
529 struct drm_xe_query_topology_mask {
530 	/** @gt_id: GT ID the mask is associated with */
531 	__u16 gt_id;
532 
533 #define DRM_XE_TOPO_DSS_GEOMETRY	1
534 #define DRM_XE_TOPO_DSS_COMPUTE		2
535 #define DRM_XE_TOPO_L3_BANK		3
536 #define DRM_XE_TOPO_EU_PER_DSS		4
537 #define DRM_XE_TOPO_SIMD16_EU_PER_DSS	5
538 	/** @type: type of mask */
539 	__u16 type;
540 
541 	/** @num_bytes: number of bytes in requested mask */
542 	__u32 num_bytes;
543 
544 	/** @mask: little-endian mask of @num_bytes */
545 	__u8 mask[];
546 };
547 
548 /**
549  * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps
550  *
551  * If a query is made with a struct drm_xe_device_query where .query is equal to
552  * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles
553  * in .data. struct drm_xe_query_engine_cycles is allocated by the user and
554  * .data points to this allocated structure.
555  *
556  * The query returns the engine cycles, which along with GT's @reference_clock,
557  * can be used to calculate the engine timestamp. In addition the
558  * query returns a set of cpu timestamps that indicate when the command
559  * streamer cycle count was captured.
560  */
561 struct drm_xe_query_engine_cycles {
562 	/**
563 	 * @eci: This is input by the user and is the engine for which command
564 	 * streamer cycles is queried.
565 	 */
566 	struct drm_xe_engine_class_instance eci;
567 
568 	/**
569 	 * @clockid: This is input by the user and is the reference clock id for
570 	 * CPU timestamp. For definition, see clock_gettime(2) and
571 	 * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC,
572 	 * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI.
573 	 */
574 	__s32 clockid;
575 
576 	/** @width: Width of the engine cycle counter in bits. */
577 	__u32 width;
578 
579 	/**
580 	 * @engine_cycles: Engine cycles as read from its register
581 	 * at 0x358 offset.
582 	 */
583 	__u64 engine_cycles;
584 
585 	/**
586 	 * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before
587 	 * reading the engine_cycles register using the reference clockid set by the
588 	 * user.
589 	 */
590 	__u64 cpu_timestamp;
591 
592 	/**
593 	 * @cpu_delta: Time delta in ns captured around reading the lower dword
594 	 * of the engine_cycles register.
595 	 */
596 	__u64 cpu_delta;
597 };
598 
599 /**
600  * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version
601  *
602  * Given a uc_type this will return the branch, major, minor and patch version
603  * of the micro-controller firmware.
604  */
605 struct drm_xe_query_uc_fw_version {
606 	/** @uc_type: The micro-controller type to query firmware version */
607 #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0
608 #define XE_QUERY_UC_TYPE_HUC 1
609 	__u16 uc_type;
610 
611 	/** @pad: MBZ */
612 	__u16 pad;
613 
614 	/** @branch_ver: branch uc fw version */
615 	__u32 branch_ver;
616 	/** @major_ver: major uc fw version */
617 	__u32 major_ver;
618 	/** @minor_ver: minor uc fw version */
619 	__u32 minor_ver;
620 	/** @patch_ver: patch uc fw version */
621 	__u32 patch_ver;
622 
623 	/** @pad2: MBZ */
624 	__u32 pad2;
625 
626 	/** @reserved: Reserved */
627 	__u64 reserved;
628 };
629 
630 /**
631  * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main
632  * structure to query device information
633  *
634  * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_*
635  * and sets the value in the query member. This determines the type of
636  * the structure provided by the driver in data, among struct drm_xe_query_*.
637  *
638  * The @query can be:
639  *  - %DRM_XE_DEVICE_QUERY_ENGINES
640  *  - %DRM_XE_DEVICE_QUERY_MEM_REGIONS
641  *  - %DRM_XE_DEVICE_QUERY_CONFIG
642  *  - %DRM_XE_DEVICE_QUERY_GT_LIST
643  *  - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware
644  *    configuration of the device such as information on slices, memory,
645  *    caches, and so on. It is provided as a table of key / value
646  *    attributes.
647  *  - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY
648  *  - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES
649  *
650  * If size is set to 0, the driver fills it with the required size for
651  * the requested type of data to query. If size is equal to the required
652  * size, the queried information is copied into data. If size is set to
653  * a value different from 0 and different from the required size, the
654  * IOCTL call returns -EINVAL.
655  *
656  * For example the following code snippet allows retrieving and printing
657  * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:
658  *
659  * .. code-block:: C
660  *
661  *     struct drm_xe_query_engines *engines;
662  *     struct drm_xe_device_query query = {
663  *         .extensions = 0,
664  *         .query = DRM_XE_DEVICE_QUERY_ENGINES,
665  *         .size = 0,
666  *         .data = 0,
667  *     };
668  *     ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
669  *     engines = malloc(query.size);
670  *     query.data = (uintptr_t)engines;
671  *     ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
672  *     for (int i = 0; i < engines->num_engines; i++) {
673  *         printf("Engine %d: %s\n", i,
674  *             engines->engines[i].instance.engine_class ==
675  *                 DRM_XE_ENGINE_CLASS_RENDER ? "RENDER":
676  *             engines->engines[i].instance.engine_class ==
677  *                 DRM_XE_ENGINE_CLASS_COPY ? "COPY":
678  *             engines->engines[i].instance.engine_class ==
679  *                 DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE":
680  *             engines->engines[i].instance.engine_class ==
681  *                 DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE":
682  *             engines->engines[i].instance.engine_class ==
683  *                 DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE":
684  *             "UNKNOWN");
685  *     }
686  *     free(engines);
687  */
688 struct drm_xe_device_query {
689 	/** @extensions: Pointer to the first extension struct, if any */
690 	__u64 extensions;
691 
692 #define DRM_XE_DEVICE_QUERY_ENGINES		0
693 #define DRM_XE_DEVICE_QUERY_MEM_REGIONS		1
694 #define DRM_XE_DEVICE_QUERY_CONFIG		2
695 #define DRM_XE_DEVICE_QUERY_GT_LIST		3
696 #define DRM_XE_DEVICE_QUERY_HWCONFIG		4
697 #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY		5
698 #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES	6
699 #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION	7
700 #define DRM_XE_DEVICE_QUERY_OA_UNITS		8
701 	/** @query: The type of data to query */
702 	__u32 query;
703 
704 	/** @size: Size of the queried data */
705 	__u32 size;
706 
707 	/** @data: Queried data is placed here */
708 	__u64 data;
709 
710 	/** @reserved: Reserved */
711 	__u64 reserved[2];
712 };
713 
714 /**
715  * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for
716  * gem creation
717  *
718  * The @flags can be:
719  *  - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING
720  *  - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
721  *  - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
722  *    possible placement, ensure that the corresponding VRAM allocation
723  *    will always use the CPU accessible part of VRAM. This is important
724  *    for small-bar systems (on full-bar systems this gets turned into a
725  *    noop).
726  *    Note1: System memory can be used as an extra placement if the kernel
727  *    should spill the allocation to system memory, if space can't be made
728  *    available in the CPU accessible part of VRAM (giving the same
729  *    behaviour as the i915 interface, see
730  *    I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS).
731  *    Note2: For clear-color CCS surfaces the kernel needs to read the
732  *    clear-color value stored in the buffer, and on discrete platforms we
733  *    need to use VRAM for display surfaces, therefore the kernel requires
734  *    setting this flag for such objects, otherwise an error is thrown on
735  *    small-bar systems.
736  *
737  * @cpu_caching supports the following values:
738  *  - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
739  *    caching. On iGPU this can't be used for scanout surfaces. Currently
740  *    not allowed for objects placed in VRAM.
741  *  - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This
742  *    is uncached. Scanout surfaces should likely use this. All objects
743  *    that can be placed in VRAM must use this.
744  */
745 struct drm_xe_gem_create {
746 	/** @extensions: Pointer to the first extension struct, if any */
747 	__u64 extensions;
748 
749 	/**
750 	 * @size: Size of the object to be created, must match region
751 	 * (system or vram) minimum alignment (&min_page_size).
752 	 */
753 	__u64 size;
754 
755 	/**
756 	 * @placement: A mask of memory instances of where BO can be placed.
757 	 * Each index in this mask refers directly to the struct
758 	 * drm_xe_query_mem_regions' instance, no assumptions should
759 	 * be made about order. The type of each region is described
760 	 * by struct drm_xe_query_mem_regions' mem_class.
761 	 */
762 	__u32 placement;
763 
764 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING		(1 << 0)
765 #define DRM_XE_GEM_CREATE_FLAG_SCANOUT			(1 << 1)
766 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM	(1 << 2)
767 	/**
768 	 * @flags: Flags, currently a mask of memory instances of where BO can
769 	 * be placed
770 	 */
771 	__u32 flags;
772 
773 	/**
774 	 * @vm_id: Attached VM, if any
775 	 *
776 	 * If a VM is specified, this BO must:
777 	 *
778 	 *  1. Only ever be bound to that VM.
779 	 *  2. Cannot be exported as a PRIME fd.
780 	 */
781 	__u32 vm_id;
782 
783 	/**
784 	 * @handle: Returned handle for the object.
785 	 *
786 	 * Object handles are nonzero.
787 	 */
788 	__u32 handle;
789 
790 #define DRM_XE_GEM_CPU_CACHING_WB                      1
791 #define DRM_XE_GEM_CPU_CACHING_WC                      2
792 	/**
793 	 * @cpu_caching: The CPU caching mode to select for this object. If
794 	 * mmaping the object the mode selected here will also be used. The
795 	 * exception is when mapping system memory (including data evicted
796 	 * to system) on discrete GPUs. The caching mode selected will
797 	 * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency
798 	 * between GPU- and CPU is guaranteed. The caching mode of
799 	 * existing CPU-mappings will be updated transparently to
800 	 * user-space clients.
801 	 */
802 	__u16 cpu_caching;
803 	/** @pad: MBZ */
804 	__u16 pad[3];
805 
806 	/** @reserved: Reserved */
807 	__u64 reserved[2];
808 };
809 
810 /**
811  * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET
812  */
813 struct drm_xe_gem_mmap_offset {
814 	/** @extensions: Pointer to the first extension struct, if any */
815 	__u64 extensions;
816 
817 	/** @handle: Handle for the object being mapped. */
818 	__u32 handle;
819 
820 	/** @flags: Must be zero */
821 	__u32 flags;
822 
823 	/** @offset: The fake offset to use for subsequent mmap call */
824 	__u64 offset;
825 
826 	/** @reserved: Reserved */
827 	__u64 reserved[2];
828 };
829 
830 /**
831  * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE
832  *
833  * The @flags can be:
834  *  - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE
835  *  - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts
836  *    exec submissions to its exec_queues that don't have an upper time
837  *    limit on the job execution time. But exec submissions to these
838  *    don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ,
839  *    DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF,
840  *    used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL.
841  *    LR VMs can be created in recoverable page-fault mode using
842  *    DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it.
843  *    If that flag is omitted, the UMD can not rely on the slightly
844  *    different per-VM overcommit semantics that are enabled by
845  *    DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may
846  *    still enable recoverable pagefaults if supported by the device.
847  *  - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also
848  *    DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on
849  *    demand when accessed, and also allows per-VM overcommit of memory.
850  *    The xe driver internally uses recoverable pagefaults to implement
851  *    this.
852  */
853 struct drm_xe_vm_create {
854 	/** @extensions: Pointer to the first extension struct, if any */
855 	__u64 extensions;
856 
857 #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE	(1 << 0)
858 #define DRM_XE_VM_CREATE_FLAG_LR_MODE	        (1 << 1)
859 #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE	(1 << 2)
860 	/** @flags: Flags */
861 	__u32 flags;
862 
863 	/** @vm_id: Returned VM ID */
864 	__u32 vm_id;
865 
866 	/** @reserved: Reserved */
867 	__u64 reserved[2];
868 };
869 
870 /**
871  * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY
872  */
873 struct drm_xe_vm_destroy {
874 	/** @vm_id: VM ID */
875 	__u32 vm_id;
876 
877 	/** @pad: MBZ */
878 	__u32 pad;
879 
880 	/** @reserved: Reserved */
881 	__u64 reserved[2];
882 };
883 
884 /**
885  * struct drm_xe_vm_bind_op - run bind operations
886  *
887  * The @op can be:
888  *  - %DRM_XE_VM_BIND_OP_MAP
889  *  - %DRM_XE_VM_BIND_OP_UNMAP
890  *  - %DRM_XE_VM_BIND_OP_MAP_USERPTR
891  *  - %DRM_XE_VM_BIND_OP_UNMAP_ALL
892  *  - %DRM_XE_VM_BIND_OP_PREFETCH
893  *
894  * and the @flags can be:
895  *  - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only
896  *    to ensure write protection
897  *  - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the
898  *    MAP operation immediately rather than deferring the MAP to the page
899  *    fault handler. This is implied on a non-faulting VM as there is no
900  *    fault handler to defer to.
901  *  - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page
902  *    tables are setup with a special bit which indicates writes are
903  *    dropped and all reads return zero. In the future, the NULL flags
904  *    will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
905  *    handle MBZ, and the BO offset MBZ. This flag is intended to
906  *    implement VK sparse bindings.
907  */
908 struct drm_xe_vm_bind_op {
909 	/** @extensions: Pointer to the first extension struct, if any */
910 	__u64 extensions;
911 
912 	/**
913 	 * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP
914 	 */
915 	__u32 obj;
916 
917 	/**
918 	 * @pat_index: The platform defined @pat_index to use for this mapping.
919 	 * The index basically maps to some predefined memory attributes,
920 	 * including things like caching, coherency, compression etc.  The exact
921 	 * meaning of the pat_index is platform specific and defined in the
922 	 * Bspec and PRMs.  When the KMD sets up the binding the index here is
923 	 * encoded into the ppGTT PTE.
924 	 *
925 	 * For coherency the @pat_index needs to be at least 1way coherent when
926 	 * drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD
927 	 * will extract the coherency mode from the @pat_index and reject if
928 	 * there is a mismatch (see note below for pre-MTL platforms).
929 	 *
930 	 * Note: On pre-MTL platforms there is only a caching mode and no
931 	 * explicit coherency mode, but on such hardware there is always a
932 	 * shared-LLC (or is dgpu) so all GT memory accesses are coherent with
933 	 * CPU caches even with the caching mode set as uncached.  It's only the
934 	 * display engine that is incoherent (on dgpu it must be in VRAM which
935 	 * is always mapped as WC on the CPU). However to keep the uapi somewhat
936 	 * consistent with newer platforms the KMD groups the different cache
937 	 * levels into the following coherency buckets on all pre-MTL platforms:
938 	 *
939 	 *	ppGTT UC -> COH_NONE
940 	 *	ppGTT WC -> COH_NONE
941 	 *	ppGTT WT -> COH_NONE
942 	 *	ppGTT WB -> COH_AT_LEAST_1WAY
943 	 *
944 	 * In practice UC/WC/WT should only ever used for scanout surfaces on
945 	 * such platforms (or perhaps in general for dma-buf if shared with
946 	 * another device) since it is only the display engine that is actually
947 	 * incoherent.  Everything else should typically use WB given that we
948 	 * have a shared-LLC.  On MTL+ this completely changes and the HW
949 	 * defines the coherency mode as part of the @pat_index, where
950 	 * incoherent GT access is possible.
951 	 *
952 	 * Note: For userptr and externally imported dma-buf the kernel expects
953 	 * either 1WAY or 2WAY for the @pat_index.
954 	 *
955 	 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions
956 	 * on the @pat_index. For such mappings there is no actual memory being
957 	 * mapped (the address in the PTE is invalid), so the various PAT memory
958 	 * attributes likely do not apply.  Simply leaving as zero is one
959 	 * option (still a valid pat_index).
960 	 */
961 	__u16 pat_index;
962 
963 	/** @pad: MBZ */
964 	__u16 pad;
965 
966 	union {
967 		/**
968 		 * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE,
969 		 * ignored for unbind
970 		 */
971 		__u64 obj_offset;
972 
973 		/** @userptr: user pointer to bind on */
974 		__u64 userptr;
975 	};
976 
977 	/**
978 	 * @range: Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL
979 	 */
980 	__u64 range;
981 
982 	/** @addr: Address to operate on, MBZ for UNMAP_ALL */
983 	__u64 addr;
984 
985 #define DRM_XE_VM_BIND_OP_MAP		0x0
986 #define DRM_XE_VM_BIND_OP_UNMAP		0x1
987 #define DRM_XE_VM_BIND_OP_MAP_USERPTR	0x2
988 #define DRM_XE_VM_BIND_OP_UNMAP_ALL	0x3
989 #define DRM_XE_VM_BIND_OP_PREFETCH	0x4
990 	/** @op: Bind operation to perform */
991 	__u32 op;
992 
993 #define DRM_XE_VM_BIND_FLAG_READONLY	(1 << 0)
994 #define DRM_XE_VM_BIND_FLAG_IMMEDIATE	(1 << 1)
995 #define DRM_XE_VM_BIND_FLAG_NULL	(1 << 2)
996 #define DRM_XE_VM_BIND_FLAG_DUMPABLE	(1 << 3)
997 	/** @flags: Bind flags */
998 	__u32 flags;
999 
1000 	/**
1001 	 * @prefetch_mem_region_instance: Memory region to prefetch VMA to.
1002 	 * It is a region instance, not a mask.
1003 	 * To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation.
1004 	 */
1005 	__u32 prefetch_mem_region_instance;
1006 
1007 	/** @pad2: MBZ */
1008 	__u32 pad2;
1009 
1010 	/** @reserved: Reserved */
1011 	__u64 reserved[3];
1012 };
1013 
1014 /**
1015  * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND
1016  *
1017  * Below is an example of a minimal use of @drm_xe_vm_bind to
1018  * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to
1019  * illustrate `userptr`. It can be synchronized by using the example
1020  * provided for @drm_xe_sync.
1021  *
1022  * .. code-block:: C
1023  *
1024  *     data = aligned_alloc(ALIGNMENT, BO_SIZE);
1025  *     struct drm_xe_vm_bind bind = {
1026  *         .vm_id = vm,
1027  *         .num_binds = 1,
1028  *         .bind.obj = 0,
1029  *         .bind.obj_offset = to_user_pointer(data),
1030  *         .bind.range = BO_SIZE,
1031  *         .bind.addr = BIND_ADDRESS,
1032  *         .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR,
1033  *         .bind.flags = 0,
1034  *         .num_syncs = 1,
1035  *         .syncs = &sync,
1036  *         .exec_queue_id = 0,
1037  *     };
1038  *     ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind);
1039  *
1040  */
1041 struct drm_xe_vm_bind {
1042 	/** @extensions: Pointer to the first extension struct, if any */
1043 	__u64 extensions;
1044 
1045 	/** @vm_id: The ID of the VM to bind to */
1046 	__u32 vm_id;
1047 
1048 	/**
1049 	 * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND
1050 	 * and exec queue must have same vm_id. If zero, the default VM bind engine
1051 	 * is used.
1052 	 */
1053 	__u32 exec_queue_id;
1054 
1055 	/** @pad: MBZ */
1056 	__u32 pad;
1057 
1058 	/** @num_binds: number of binds in this IOCTL */
1059 	__u32 num_binds;
1060 
1061 	union {
1062 		/** @bind: used if num_binds == 1 */
1063 		struct drm_xe_vm_bind_op bind;
1064 
1065 		/**
1066 		 * @vector_of_binds: userptr to array of struct
1067 		 * drm_xe_vm_bind_op if num_binds > 1
1068 		 */
1069 		__u64 vector_of_binds;
1070 	};
1071 
1072 	/** @pad2: MBZ */
1073 	__u32 pad2;
1074 
1075 	/** @num_syncs: amount of syncs to wait on */
1076 	__u32 num_syncs;
1077 
1078 	/** @syncs: pointer to struct drm_xe_sync array */
1079 	__u64 syncs;
1080 
1081 	/** @reserved: Reserved */
1082 	__u64 reserved[2];
1083 };
1084 
1085 /**
1086  * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
1087  *
1088  * The example below shows how to use @drm_xe_exec_queue_create to create
1089  * a simple exec_queue (no parallel submission) of class
1090  * &DRM_XE_ENGINE_CLASS_RENDER.
1091  *
1092  * .. code-block:: C
1093  *
1094  *     struct drm_xe_engine_class_instance instance = {
1095  *         .engine_class = DRM_XE_ENGINE_CLASS_RENDER,
1096  *     };
1097  *     struct drm_xe_exec_queue_create exec_queue_create = {
1098  *          .extensions = 0,
1099  *          .vm_id = vm,
1100  *          .num_bb_per_exec = 1,
1101  *          .num_eng_per_bb = 1,
1102  *          .instances = to_user_pointer(&instance),
1103  *     };
1104  *     ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);
1105  *
1106  */
1107 struct drm_xe_exec_queue_create {
1108 #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY		0
1109 #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY		0
1110 #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE		1
1111 
1112 	/** @extensions: Pointer to the first extension struct, if any */
1113 	__u64 extensions;
1114 
1115 	/** @width: submission width (number BB per exec) for this exec queue */
1116 	__u16 width;
1117 
1118 	/** @num_placements: number of valid placements for this exec queue */
1119 	__u16 num_placements;
1120 
1121 	/** @vm_id: VM to use for this exec queue */
1122 	__u32 vm_id;
1123 
1124 	/** @flags: MBZ */
1125 	__u32 flags;
1126 
1127 	/** @exec_queue_id: Returned exec queue ID */
1128 	__u32 exec_queue_id;
1129 
1130 	/**
1131 	 * @instances: user pointer to a 2-d array of struct
1132 	 * drm_xe_engine_class_instance
1133 	 *
1134 	 * length = width (i) * num_placements (j)
1135 	 * index = j + i * width
1136 	 */
1137 	__u64 instances;
1138 
1139 	/** @reserved: Reserved */
1140 	__u64 reserved[2];
1141 };
1142 
1143 /**
1144  * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
1145  */
1146 struct drm_xe_exec_queue_destroy {
1147 	/** @exec_queue_id: Exec queue ID */
1148 	__u32 exec_queue_id;
1149 
1150 	/** @pad: MBZ */
1151 	__u32 pad;
1152 
1153 	/** @reserved: Reserved */
1154 	__u64 reserved[2];
1155 };
1156 
1157 /**
1158  * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
1159  *
1160  * The @property can be:
1161  *  - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN
1162  */
1163 struct drm_xe_exec_queue_get_property {
1164 	/** @extensions: Pointer to the first extension struct, if any */
1165 	__u64 extensions;
1166 
1167 	/** @exec_queue_id: Exec queue ID */
1168 	__u32 exec_queue_id;
1169 
1170 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN	0
1171 	/** @property: property to get */
1172 	__u32 property;
1173 
1174 	/** @value: property value */
1175 	__u64 value;
1176 
1177 	/** @reserved: Reserved */
1178 	__u64 reserved[2];
1179 };
1180 
1181 /**
1182  * struct drm_xe_sync - sync object
1183  *
1184  * The @type can be:
1185  *  - %DRM_XE_SYNC_TYPE_SYNCOBJ
1186  *  - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ
1187  *  - %DRM_XE_SYNC_TYPE_USER_FENCE
1188  *
1189  * and the @flags can be:
1190  *  - %DRM_XE_SYNC_FLAG_SIGNAL
1191  *
1192  * A minimal use of @drm_xe_sync looks like this:
1193  *
1194  * .. code-block:: C
1195  *
1196  *     struct drm_xe_sync sync = {
1197  *         .flags = DRM_XE_SYNC_FLAG_SIGNAL,
1198  *         .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
1199  *     };
1200  *     struct drm_syncobj_create syncobj_create = { 0 };
1201  *     ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create);
1202  *     sync.handle = syncobj_create.handle;
1203  *         ...
1204  *         use of &sync in drm_xe_exec or drm_xe_vm_bind
1205  *         ...
1206  *     struct drm_syncobj_wait wait = {
1207  *         .handles = &sync.handle,
1208  *         .timeout_nsec = INT64_MAX,
1209  *         .count_handles = 1,
1210  *         .flags = 0,
1211  *         .first_signaled = 0,
1212  *         .pad = 0,
1213  *     };
1214  *     ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);
1215  */
1216 struct drm_xe_sync {
1217 	/** @extensions: Pointer to the first extension struct, if any */
1218 	__u64 extensions;
1219 
1220 #define DRM_XE_SYNC_TYPE_SYNCOBJ		0x0
1221 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ	0x1
1222 #define DRM_XE_SYNC_TYPE_USER_FENCE		0x2
1223 	/** @type: Type of the this sync object */
1224 	__u32 type;
1225 
1226 #define DRM_XE_SYNC_FLAG_SIGNAL	(1 << 0)
1227 	/** @flags: Sync Flags */
1228 	__u32 flags;
1229 
1230 	union {
1231 		/** @handle: Handle for the object */
1232 		__u32 handle;
1233 
1234 		/**
1235 		 * @addr: Address of user fence. When sync is passed in via exec
1236 		 * IOCTL this is a GPU address in the VM. When sync passed in via
1237 		 * VM bind IOCTL this is a user pointer. In either case, it is
1238 		 * the users responsibility that this address is present and
1239 		 * mapped when the user fence is signalled. Must be qword
1240 		 * aligned.
1241 		 */
1242 		__u64 addr;
1243 	};
1244 
1245 	/**
1246 	 * @timeline_value: Input for the timeline sync object. Needs to be
1247 	 * different than 0 when used with %DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ.
1248 	 */
1249 	__u64 timeline_value;
1250 
1251 	/** @reserved: Reserved */
1252 	__u64 reserved[2];
1253 };
1254 
1255 /**
1256  * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC
1257  *
1258  * This is an example to use @drm_xe_exec for execution of the object
1259  * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue
1260  * (see example in @drm_xe_exec_queue_create). It can be synchronized
1261  * by using the example provided for @drm_xe_sync.
1262  *
1263  * .. code-block:: C
1264  *
1265  *     struct drm_xe_exec exec = {
1266  *         .exec_queue_id = exec_queue,
1267  *         .syncs = &sync,
1268  *         .num_syncs = 1,
1269  *         .address = BIND_ADDRESS,
1270  *         .num_batch_buffer = 1,
1271  *     };
1272  *     ioctl(fd, DRM_IOCTL_XE_EXEC, &exec);
1273  *
1274  */
1275 struct drm_xe_exec {
1276 	/** @extensions: Pointer to the first extension struct, if any */
1277 	__u64 extensions;
1278 
1279 	/** @exec_queue_id: Exec queue ID for the batch buffer */
1280 	__u32 exec_queue_id;
1281 
1282 	/** @num_syncs: Amount of struct drm_xe_sync in array. */
1283 	__u32 num_syncs;
1284 
1285 	/** @syncs: Pointer to struct drm_xe_sync array. */
1286 	__u64 syncs;
1287 
1288 	/**
1289 	 * @address: address of batch buffer if num_batch_buffer == 1 or an
1290 	 * array of batch buffer addresses
1291 	 */
1292 	__u64 address;
1293 
1294 	/**
1295 	 * @num_batch_buffer: number of batch buffer in this exec, must match
1296 	 * the width of the engine
1297 	 */
1298 	__u16 num_batch_buffer;
1299 
1300 	/** @pad: MBZ */
1301 	__u16 pad[3];
1302 
1303 	/** @reserved: Reserved */
1304 	__u64 reserved[2];
1305 };
1306 
1307 /**
1308  * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE
1309  *
1310  * Wait on user fence, XE will wake-up on every HW engine interrupt in the
1311  * instances list and check if user fence is complete::
1312  *
1313  *	(*addr & MASK) OP (VALUE & MASK)
1314  *
1315  * Returns to user on user fence completion or timeout.
1316  *
1317  * The @op can be:
1318  *  - %DRM_XE_UFENCE_WAIT_OP_EQ
1319  *  - %DRM_XE_UFENCE_WAIT_OP_NEQ
1320  *  - %DRM_XE_UFENCE_WAIT_OP_GT
1321  *  - %DRM_XE_UFENCE_WAIT_OP_GTE
1322  *  - %DRM_XE_UFENCE_WAIT_OP_LT
1323  *  - %DRM_XE_UFENCE_WAIT_OP_LTE
1324  *
1325  * and the @flags can be:
1326  *  - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME
1327  *  - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP
1328  *
1329  * The @mask values can be for example:
1330  *  - 0xffu for u8
1331  *  - 0xffffu for u16
1332  *  - 0xffffffffu for u32
1333  *  - 0xffffffffffffffffu for u64
1334  */
1335 struct drm_xe_wait_user_fence {
1336 	/** @extensions: Pointer to the first extension struct, if any */
1337 	__u64 extensions;
1338 
1339 	/**
1340 	 * @addr: user pointer address to wait on, must qword aligned
1341 	 */
1342 	__u64 addr;
1343 
1344 #define DRM_XE_UFENCE_WAIT_OP_EQ	0x0
1345 #define DRM_XE_UFENCE_WAIT_OP_NEQ	0x1
1346 #define DRM_XE_UFENCE_WAIT_OP_GT	0x2
1347 #define DRM_XE_UFENCE_WAIT_OP_GTE	0x3
1348 #define DRM_XE_UFENCE_WAIT_OP_LT	0x4
1349 #define DRM_XE_UFENCE_WAIT_OP_LTE	0x5
1350 	/** @op: wait operation (type of comparison) */
1351 	__u16 op;
1352 
1353 #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME	(1 << 0)
1354 	/** @flags: wait flags */
1355 	__u16 flags;
1356 
1357 	/** @pad: MBZ */
1358 	__u32 pad;
1359 
1360 	/** @value: compare value */
1361 	__u64 value;
1362 
1363 	/** @mask: comparison mask */
1364 	__u64 mask;
1365 
1366 	/**
1367 	 * @timeout: how long to wait before bailing, value in nanoseconds.
1368 	 * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout)
1369 	 * it contains timeout expressed in nanoseconds to wait (fence will
1370 	 * expire at now() + timeout).
1371 	 * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait
1372 	 * will end at timeout (uses system MONOTONIC_CLOCK).
1373 	 * Passing negative timeout leads to neverending wait.
1374 	 *
1375 	 * On relative timeout this value is updated with timeout left
1376 	 * (for restarting the call in case of signal delivery).
1377 	 * On absolute timeout this value stays intact (restarted call still
1378 	 * expire at the same point of time).
1379 	 */
1380 	__s64 timeout;
1381 
1382 	/** @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl */
1383 	__u32 exec_queue_id;
1384 
1385 	/** @pad2: MBZ */
1386 	__u32 pad2;
1387 
1388 	/** @reserved: Reserved */
1389 	__u64 reserved[2];
1390 };
1391 
1392 /**
1393  * enum drm_xe_observation_type - Observation stream types
1394  */
1395 enum drm_xe_observation_type {
1396 	/** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */
1397 	DRM_XE_OBSERVATION_TYPE_OA,
1398 };
1399 
1400 /**
1401  * enum drm_xe_observation_op - Observation stream ops
1402  */
1403 enum drm_xe_observation_op {
1404 	/** @DRM_XE_OBSERVATION_OP_STREAM_OPEN: Open an observation stream */
1405 	DRM_XE_OBSERVATION_OP_STREAM_OPEN,
1406 
1407 	/** @DRM_XE_OBSERVATION_OP_ADD_CONFIG: Add observation stream config */
1408 	DRM_XE_OBSERVATION_OP_ADD_CONFIG,
1409 
1410 	/** @DRM_XE_OBSERVATION_OP_REMOVE_CONFIG: Remove observation stream config */
1411 	DRM_XE_OBSERVATION_OP_REMOVE_CONFIG,
1412 };
1413 
1414 /**
1415  * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION
1416  *
1417  * The observation layer enables multiplexing observation streams of
1418  * multiple types. The actual params for a particular stream operation are
1419  * supplied via the @param pointer (use __copy_from_user to get these
1420  * params).
1421  */
1422 struct drm_xe_observation_param {
1423 	/** @extensions: Pointer to the first extension struct, if any */
1424 	__u64 extensions;
1425 	/** @observation_type: observation stream type, of enum @drm_xe_observation_type */
1426 	__u64 observation_type;
1427 	/** @observation_op: observation stream op, of enum @drm_xe_observation_op */
1428 	__u64 observation_op;
1429 	/** @param: Pointer to actual stream params */
1430 	__u64 param;
1431 };
1432 
1433 /**
1434  * enum drm_xe_observation_ioctls - Observation stream fd ioctl's
1435  *
1436  * Information exchanged between userspace and kernel for observation fd
1437  * ioctl's is stream type specific
1438  */
1439 enum drm_xe_observation_ioctls {
1440 	/** @DRM_XE_OBSERVATION_IOCTL_ENABLE: Enable data capture for an observation stream */
1441 	DRM_XE_OBSERVATION_IOCTL_ENABLE = _IO('i', 0x0),
1442 
1443 	/** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for a observation stream */
1444 	DRM_XE_OBSERVATION_IOCTL_DISABLE = _IO('i', 0x1),
1445 
1446 	/** @DRM_XE_OBSERVATION_IOCTL_CONFIG: Change observation stream configuration */
1447 	DRM_XE_OBSERVATION_IOCTL_CONFIG = _IO('i', 0x2),
1448 
1449 	/** @DRM_XE_OBSERVATION_IOCTL_STATUS: Return observation stream status */
1450 	DRM_XE_OBSERVATION_IOCTL_STATUS = _IO('i', 0x3),
1451 
1452 	/** @DRM_XE_OBSERVATION_IOCTL_INFO: Return observation stream info */
1453 	DRM_XE_OBSERVATION_IOCTL_INFO = _IO('i', 0x4),
1454 };
1455 
1456 /**
1457  * enum drm_xe_oa_unit_type - OA unit types
1458  */
1459 enum drm_xe_oa_unit_type {
1460 	/**
1461 	 * @DRM_XE_OA_UNIT_TYPE_OAG: OAG OA unit. OAR/OAC are considered
1462 	 * sub-types of OAG. For OAR/OAC, use OAG.
1463 	 */
1464 	DRM_XE_OA_UNIT_TYPE_OAG,
1465 
1466 	/** @DRM_XE_OA_UNIT_TYPE_OAM: OAM OA unit */
1467 	DRM_XE_OA_UNIT_TYPE_OAM,
1468 };
1469 
1470 /**
1471  * struct drm_xe_oa_unit - describe OA unit
1472  */
1473 struct drm_xe_oa_unit {
1474 	/** @extensions: Pointer to the first extension struct, if any */
1475 	__u64 extensions;
1476 
1477 	/** @oa_unit_id: OA unit ID */
1478 	__u32 oa_unit_id;
1479 
1480 	/** @oa_unit_type: OA unit type of @drm_xe_oa_unit_type */
1481 	__u32 oa_unit_type;
1482 
1483 	/** @capabilities: OA capabilities bit-mask */
1484 	__u64 capabilities;
1485 #define DRM_XE_OA_CAPS_BASE		(1 << 0)
1486 
1487 	/** @oa_timestamp_freq: OA timestamp freq */
1488 	__u64 oa_timestamp_freq;
1489 
1490 	/** @reserved: MBZ */
1491 	__u64 reserved[4];
1492 
1493 	/** @num_engines: number of engines in @eci array */
1494 	__u64 num_engines;
1495 
1496 	/** @eci: engines attached to this OA unit */
1497 	struct drm_xe_engine_class_instance eci[];
1498 };
1499 
1500 /**
1501  * struct drm_xe_query_oa_units - describe OA units
1502  *
1503  * If a query is made with a struct drm_xe_device_query where .query
1504  * is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct
1505  * drm_xe_query_oa_units in .data.
1506  *
1507  * OA unit properties for all OA units can be accessed using a code block
1508  * such as the one below:
1509  *
1510  * .. code-block:: C
1511  *
1512  *	struct drm_xe_query_oa_units *qoa;
1513  *	struct drm_xe_oa_unit *oau;
1514  *	u8 *poau;
1515  *
1516  *	// malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then:
1517  *	poau = (u8 *)&qoa->oa_units[0];
1518  *	for (int i = 0; i < qoa->num_oa_units; i++) {
1519  *		oau = (struct drm_xe_oa_unit *)poau;
1520  *		// Access 'struct drm_xe_oa_unit' fields here
1521  *		poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]);
1522  *	}
1523  */
1524 struct drm_xe_query_oa_units {
1525 	/** @extensions: Pointer to the first extension struct, if any */
1526 	__u64 extensions;
1527 	/** @num_oa_units: number of OA units returned in oau[] */
1528 	__u32 num_oa_units;
1529 	/** @pad: MBZ */
1530 	__u32 pad;
1531 	/**
1532 	 * @oa_units: struct @drm_xe_oa_unit array returned for this device.
1533 	 * Written below as a u64 array to avoid problems with nested flexible
1534 	 * arrays with some compilers
1535 	 */
1536 	__u64 oa_units[];
1537 };
1538 
1539 /**
1540  * enum drm_xe_oa_format_type - OA format types as specified in PRM/Bspec
1541  * 52198/60942
1542  */
1543 enum drm_xe_oa_format_type {
1544 	/** @DRM_XE_OA_FMT_TYPE_OAG: OAG report format */
1545 	DRM_XE_OA_FMT_TYPE_OAG,
1546 	/** @DRM_XE_OA_FMT_TYPE_OAR: OAR report format */
1547 	DRM_XE_OA_FMT_TYPE_OAR,
1548 	/** @DRM_XE_OA_FMT_TYPE_OAM: OAM report format */
1549 	DRM_XE_OA_FMT_TYPE_OAM,
1550 	/** @DRM_XE_OA_FMT_TYPE_OAC: OAC report format */
1551 	DRM_XE_OA_FMT_TYPE_OAC,
1552 	/** @DRM_XE_OA_FMT_TYPE_OAM_MPEC: OAM SAMEDIA or OAM MPEC report format */
1553 	DRM_XE_OA_FMT_TYPE_OAM_MPEC,
1554 	/** @DRM_XE_OA_FMT_TYPE_PEC: PEC report format */
1555 	DRM_XE_OA_FMT_TYPE_PEC,
1556 };
1557 
1558 /**
1559  * enum drm_xe_oa_property_id - OA stream property id's
1560  *
1561  * Stream params are specified as a chain of @drm_xe_ext_set_property
1562  * struct's, with @property values from enum @drm_xe_oa_property_id and
1563  * @drm_xe_user_extension base.name set to @DRM_XE_OA_EXTENSION_SET_PROPERTY.
1564  * @param field in struct @drm_xe_observation_param points to the first
1565  * @drm_xe_ext_set_property struct.
1566  *
1567  * Exactly the same mechanism is also used for stream reconfiguration using the
1568  * @DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a
1569  * subset of properties below can be specified for stream reconfiguration.
1570  */
1571 enum drm_xe_oa_property_id {
1572 #define DRM_XE_OA_EXTENSION_SET_PROPERTY	0
1573 	/**
1574 	 * @DRM_XE_OA_PROPERTY_OA_UNIT_ID: ID of the OA unit on which to open
1575 	 * the OA stream, see @oa_unit_id in 'struct
1576 	 * drm_xe_query_oa_units'. Defaults to 0 if not provided.
1577 	 */
1578 	DRM_XE_OA_PROPERTY_OA_UNIT_ID = 1,
1579 
1580 	/**
1581 	 * @DRM_XE_OA_PROPERTY_SAMPLE_OA: A value of 1 requests inclusion of raw
1582 	 * OA unit reports or stream samples in a global buffer attached to an
1583 	 * OA unit.
1584 	 */
1585 	DRM_XE_OA_PROPERTY_SAMPLE_OA,
1586 
1587 	/**
1588 	 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET: OA metrics defining contents of OA
1589 	 * reports, previously added via @DRM_XE_OBSERVATION_OP_ADD_CONFIG.
1590 	 */
1591 	DRM_XE_OA_PROPERTY_OA_METRIC_SET,
1592 
1593 	/** @DRM_XE_OA_PROPERTY_OA_FORMAT: OA counter report format */
1594 	DRM_XE_OA_PROPERTY_OA_FORMAT,
1595 	/*
1596 	 * OA_FORMAT's are specified the same way as in PRM/Bspec 52198/60942,
1597 	 * in terms of the following quantities: a. enum @drm_xe_oa_format_type
1598 	 * b. Counter select c. Counter size and d. BC report. Also refer to the
1599 	 * oa_formats array in drivers/gpu/drm/xe/xe_oa.c.
1600 	 */
1601 #define DRM_XE_OA_FORMAT_MASK_FMT_TYPE		(0xffu << 0)
1602 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL	(0xffu << 8)
1603 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE	(0xffu << 16)
1604 #define DRM_XE_OA_FORMAT_MASK_BC_REPORT		(0xffu << 24)
1605 
1606 	/**
1607 	 * @DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT: Requests periodic OA unit
1608 	 * sampling with sampling frequency proportional to 2^(period_exponent + 1)
1609 	 */
1610 	DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT,
1611 
1612 	/**
1613 	 * @DRM_XE_OA_PROPERTY_OA_DISABLED: A value of 1 will open the OA
1614 	 * stream in a DISABLED state (see @DRM_XE_OBSERVATION_IOCTL_ENABLE).
1615 	 */
1616 	DRM_XE_OA_PROPERTY_OA_DISABLED,
1617 
1618 	/**
1619 	 * @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID: Open the stream for a specific
1620 	 * @exec_queue_id. OA queries can be executed on this exec queue.
1621 	 */
1622 	DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID,
1623 
1624 	/**
1625 	 * @DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE: Optional engine instance to
1626 	 * pass along with @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0.
1627 	 */
1628 	DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE,
1629 
1630 	/**
1631 	 * @DRM_XE_OA_PROPERTY_NO_PREEMPT: Allow preemption and timeslicing
1632 	 * to be disabled for the stream exec queue.
1633 	 */
1634 	DRM_XE_OA_PROPERTY_NO_PREEMPT,
1635 };
1636 
1637 /**
1638  * struct drm_xe_oa_config - OA metric configuration
1639  *
1640  * Multiple OA configs can be added using @DRM_XE_OBSERVATION_OP_ADD_CONFIG. A
1641  * particular config can be specified when opening an OA stream using
1642  * @DRM_XE_OA_PROPERTY_OA_METRIC_SET property.
1643  */
1644 struct drm_xe_oa_config {
1645 	/** @extensions: Pointer to the first extension struct, if any */
1646 	__u64 extensions;
1647 
1648 	/** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */
1649 	char uuid[36];
1650 
1651 	/** @n_regs: Number of regs in @regs_ptr */
1652 	__u32 n_regs;
1653 
1654 	/**
1655 	 * @regs_ptr: Pointer to (register address, value) pairs for OA config
1656 	 * registers. Expected length of buffer is: (2 * sizeof(u32) * @n_regs).
1657 	 */
1658 	__u64 regs_ptr;
1659 };
1660 
1661 /**
1662  * struct drm_xe_oa_stream_status - OA stream status returned from
1663  * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can
1664  * call the ioctl to query stream status in response to EIO errno from
1665  * observation fd read().
1666  */
1667 struct drm_xe_oa_stream_status {
1668 	/** @extensions: Pointer to the first extension struct, if any */
1669 	__u64 extensions;
1670 
1671 	/** @oa_status: OA stream status (see Bspec 46717/61226) */
1672 	__u64 oa_status;
1673 #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL		(1 << 3)
1674 #define DRM_XE_OASTATUS_COUNTER_OVERFLOW	(1 << 2)
1675 #define DRM_XE_OASTATUS_BUFFER_OVERFLOW		(1 << 1)
1676 #define DRM_XE_OASTATUS_REPORT_LOST		(1 << 0)
1677 
1678 	/** @reserved: reserved for future use */
1679 	__u64 reserved[3];
1680 };
1681 
1682 /**
1683  * struct drm_xe_oa_stream_info - OA stream info returned from
1684  * @DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl
1685  */
1686 struct drm_xe_oa_stream_info {
1687 	/** @extensions: Pointer to the first extension struct, if any */
1688 	__u64 extensions;
1689 
1690 	/** @oa_buf_size: OA buffer size */
1691 	__u64 oa_buf_size;
1692 
1693 	/** @reserved: reserved for future use */
1694 	__u64 reserved[3];
1695 };
1696 
1697 #if defined(__cplusplus)
1698 }
1699 #endif
1700 
1701 #endif /* _UAPI_XE_DRM_H_ */
1702