1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 */
5 #include <linux/module.h>
6 #include <linux/kernel.h>
7 #include <linux/slab.h>
8 #include <linux/pci.h>
9 #include <linux/gpio/driver.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12
13 #define IOH_EDGE_FALLING 0
14 #define IOH_EDGE_RISING BIT(0)
15 #define IOH_LEVEL_L BIT(1)
16 #define IOH_LEVEL_H (BIT(0) | BIT(1))
17 #define IOH_EDGE_BOTH BIT(2)
18 #define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
19
20 #define IOH_IRQ_BASE 0
21
22 struct ioh_reg_comn {
23 u32 ien;
24 u32 istatus;
25 u32 idisp;
26 u32 iclr;
27 u32 imask;
28 u32 imaskclr;
29 u32 po;
30 u32 pi;
31 u32 pm;
32 u32 im_0;
33 u32 im_1;
34 u32 reserved;
35 };
36
37 struct ioh_regs {
38 struct ioh_reg_comn regs[8];
39 u32 reserve1[16];
40 u32 ioh_sel_reg[4];
41 u32 reserve2[11];
42 u32 srst;
43 };
44
45 /**
46 * struct ioh_gpio_reg_data - The register store data.
47 * @ien_reg: To store contents of interrupt enable register.
48 * @imask_reg: To store contents of interrupt mask regist
49 * @po_reg: To store contents of PO register.
50 * @pm_reg: To store contents of PM register.
51 * @im0_reg: To store contents of interrupt mode regist0
52 * @im1_reg: To store contents of interrupt mode regist1
53 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
54 */
55 struct ioh_gpio_reg_data {
56 u32 ien_reg;
57 u32 imask_reg;
58 u32 po_reg;
59 u32 pm_reg;
60 u32 im0_reg;
61 u32 im1_reg;
62 u32 use_sel_reg;
63 };
64
65 /**
66 * struct ioh_gpio - GPIO private data structure.
67 * @base: PCI base address of Memory mapped I/O register.
68 * @reg: Memory mapped IOH GPIO register list.
69 * @dev: Pointer to device structure.
70 * @gpio: Data for GPIO infrastructure.
71 * @ioh_gpio_reg: Memory mapped Register data is saved here
72 * when suspend.
73 * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
74 * @ch: Indicate GPIO channel
75 * @irq_base: Save base of IRQ number for interrupt
76 * @spinlock: Shared register access lock
77 */
78 struct ioh_gpio {
79 void __iomem *base;
80 struct ioh_regs __iomem *reg;
81 struct device *dev;
82 struct gpio_chip gpio;
83 struct ioh_gpio_reg_data ioh_gpio_reg;
84 u32 gpio_use_sel;
85 int ch;
86 int irq_base;
87 raw_spinlock_t *spinlock;
88 };
89
90 struct ioh_gpio_device {
91 raw_spinlock_t spinlock;
92 struct ioh_gpio chip[8];
93 };
94
95 static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
96
ioh_gpio_set(struct gpio_chip * gpio,unsigned int nr,int val)97 static int ioh_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
98 {
99 u32 reg_val;
100 struct ioh_gpio *chip = gpiochip_get_data(gpio);
101 unsigned long flags;
102
103 raw_spin_lock_irqsave(chip->spinlock, flags);
104 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
105 if (val)
106 reg_val |= BIT(nr);
107 else
108 reg_val &= ~BIT(nr);
109
110 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
111 raw_spin_unlock_irqrestore(chip->spinlock, flags);
112
113 return 0;
114 }
115
ioh_gpio_get(struct gpio_chip * gpio,unsigned nr)116 static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
117 {
118 struct ioh_gpio *chip = gpiochip_get_data(gpio);
119
120 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & BIT(nr));
121 }
122
ioh_gpio_direction_output(struct gpio_chip * gpio,unsigned nr,int val)123 static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
124 int val)
125 {
126 struct ioh_gpio *chip = gpiochip_get_data(gpio);
127 u32 pm;
128 u32 reg_val;
129 unsigned long flags;
130
131 raw_spin_lock_irqsave(chip->spinlock, flags);
132 pm = ioread32(&chip->reg->regs[chip->ch].pm);
133 pm &= BIT(num_ports[chip->ch]) - 1;
134 pm |= BIT(nr);
135 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
136
137 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
138 if (val)
139 reg_val |= BIT(nr);
140 else
141 reg_val &= ~BIT(nr);
142 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
143
144 raw_spin_unlock_irqrestore(chip->spinlock, flags);
145
146 return 0;
147 }
148
ioh_gpio_direction_input(struct gpio_chip * gpio,unsigned nr)149 static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
150 {
151 struct ioh_gpio *chip = gpiochip_get_data(gpio);
152 u32 pm;
153 unsigned long flags;
154
155 raw_spin_lock_irqsave(chip->spinlock, flags);
156 pm = ioread32(&chip->reg->regs[chip->ch].pm);
157 pm &= BIT(num_ports[chip->ch]) - 1;
158 pm &= ~BIT(nr);
159 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
160 raw_spin_unlock_irqrestore(chip->spinlock, flags);
161
162 return 0;
163 }
164
165 /*
166 * Save register configuration and disable interrupts.
167 */
ioh_gpio_save_reg_conf(struct ioh_gpio * chip)168 static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
169 {
170 int i;
171
172 for (i = 0; i < 8; i ++, chip++) {
173 chip->ioh_gpio_reg.po_reg =
174 ioread32(&chip->reg->regs[chip->ch].po);
175 chip->ioh_gpio_reg.pm_reg =
176 ioread32(&chip->reg->regs[chip->ch].pm);
177 chip->ioh_gpio_reg.ien_reg =
178 ioread32(&chip->reg->regs[chip->ch].ien);
179 chip->ioh_gpio_reg.imask_reg =
180 ioread32(&chip->reg->regs[chip->ch].imask);
181 chip->ioh_gpio_reg.im0_reg =
182 ioread32(&chip->reg->regs[chip->ch].im_0);
183 chip->ioh_gpio_reg.im1_reg =
184 ioread32(&chip->reg->regs[chip->ch].im_1);
185 if (i < 4)
186 chip->ioh_gpio_reg.use_sel_reg =
187 ioread32(&chip->reg->ioh_sel_reg[i]);
188 }
189 }
190
191 /*
192 * This function restores the register configuration of the GPIO device.
193 */
ioh_gpio_restore_reg_conf(struct ioh_gpio * chip)194 static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
195 {
196 int i;
197
198 for (i = 0; i < 8; i ++, chip++) {
199 iowrite32(chip->ioh_gpio_reg.po_reg,
200 &chip->reg->regs[chip->ch].po);
201 iowrite32(chip->ioh_gpio_reg.pm_reg,
202 &chip->reg->regs[chip->ch].pm);
203 iowrite32(chip->ioh_gpio_reg.ien_reg,
204 &chip->reg->regs[chip->ch].ien);
205 iowrite32(chip->ioh_gpio_reg.imask_reg,
206 &chip->reg->regs[chip->ch].imask);
207 iowrite32(chip->ioh_gpio_reg.im0_reg,
208 &chip->reg->regs[chip->ch].im_0);
209 iowrite32(chip->ioh_gpio_reg.im1_reg,
210 &chip->reg->regs[chip->ch].im_1);
211 if (i < 4)
212 iowrite32(chip->ioh_gpio_reg.use_sel_reg,
213 &chip->reg->ioh_sel_reg[i]);
214 }
215 }
216
ioh_gpio_to_irq(struct gpio_chip * gpio,unsigned offset)217 static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
218 {
219 struct ioh_gpio *chip = gpiochip_get_data(gpio);
220 return chip->irq_base + offset;
221 }
222
ioh_gpio_setup(struct ioh_gpio * chip,int num_port)223 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
224 {
225 struct gpio_chip *gpio = &chip->gpio;
226
227 gpio->label = dev_name(chip->dev);
228 gpio->owner = THIS_MODULE;
229 gpio->direction_input = ioh_gpio_direction_input;
230 gpio->get = ioh_gpio_get;
231 gpio->direction_output = ioh_gpio_direction_output;
232 gpio->set = ioh_gpio_set;
233 gpio->dbg_show = NULL;
234 gpio->base = -1;
235 gpio->ngpio = num_port;
236 gpio->can_sleep = false;
237 gpio->to_irq = ioh_gpio_to_irq;
238 }
239
ioh_irq_type(struct irq_data * d,unsigned int type)240 static int ioh_irq_type(struct irq_data *d, unsigned int type)
241 {
242 u32 im;
243 void __iomem *im_reg;
244 u32 ien;
245 u32 im_pos;
246 int ch;
247 unsigned long flags;
248 u32 val;
249 int irq = d->irq;
250 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
251 struct ioh_gpio *chip = gc->private;
252
253 ch = irq - chip->irq_base;
254 if (irq <= chip->irq_base + 7) {
255 im_reg = &chip->reg->regs[chip->ch].im_0;
256 im_pos = ch;
257 } else {
258 im_reg = &chip->reg->regs[chip->ch].im_1;
259 im_pos = ch - 8;
260 }
261 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
262 __func__, irq, type, ch, im_pos, type);
263
264 raw_spin_lock_irqsave(chip->spinlock, flags);
265
266 switch (type) {
267 case IRQ_TYPE_EDGE_RISING:
268 val = IOH_EDGE_RISING;
269 break;
270 case IRQ_TYPE_EDGE_FALLING:
271 val = IOH_EDGE_FALLING;
272 break;
273 case IRQ_TYPE_EDGE_BOTH:
274 val = IOH_EDGE_BOTH;
275 break;
276 case IRQ_TYPE_LEVEL_HIGH:
277 val = IOH_LEVEL_H;
278 break;
279 case IRQ_TYPE_LEVEL_LOW:
280 val = IOH_LEVEL_L;
281 break;
282 case IRQ_TYPE_PROBE:
283 goto end;
284 default:
285 dev_warn(chip->dev, "%s: unknown type(%dd)",
286 __func__, type);
287 goto end;
288 }
289
290 /* Set interrupt mode */
291 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
292 iowrite32(im | (val << (im_pos * 4)), im_reg);
293
294 /* iclr */
295 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
296
297 /* IMASKCLR */
298 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
299
300 /* Enable interrupt */
301 ien = ioread32(&chip->reg->regs[chip->ch].ien);
302 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
303 end:
304 raw_spin_unlock_irqrestore(chip->spinlock, flags);
305
306 return 0;
307 }
308
ioh_irq_unmask(struct irq_data * d)309 static void ioh_irq_unmask(struct irq_data *d)
310 {
311 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
312 struct ioh_gpio *chip = gc->private;
313
314 iowrite32(BIT(d->irq - chip->irq_base),
315 &chip->reg->regs[chip->ch].imaskclr);
316 }
317
ioh_irq_mask(struct irq_data * d)318 static void ioh_irq_mask(struct irq_data *d)
319 {
320 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
321 struct ioh_gpio *chip = gc->private;
322
323 iowrite32(BIT(d->irq - chip->irq_base),
324 &chip->reg->regs[chip->ch].imask);
325 }
326
ioh_irq_disable(struct irq_data * d)327 static void ioh_irq_disable(struct irq_data *d)
328 {
329 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
330 struct ioh_gpio *chip = gc->private;
331 unsigned long flags;
332 u32 ien;
333
334 raw_spin_lock_irqsave(chip->spinlock, flags);
335 ien = ioread32(&chip->reg->regs[chip->ch].ien);
336 ien &= ~BIT(d->irq - chip->irq_base);
337 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
338 raw_spin_unlock_irqrestore(chip->spinlock, flags);
339 }
340
ioh_irq_enable(struct irq_data * d)341 static void ioh_irq_enable(struct irq_data *d)
342 {
343 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
344 struct ioh_gpio *chip = gc->private;
345 unsigned long flags;
346 u32 ien;
347
348 raw_spin_lock_irqsave(chip->spinlock, flags);
349 ien = ioread32(&chip->reg->regs[chip->ch].ien);
350 ien |= BIT(d->irq - chip->irq_base);
351 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
352 raw_spin_unlock_irqrestore(chip->spinlock, flags);
353 }
354
ioh_gpio_handler(int irq,void * dev_id)355 static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
356 {
357 struct ioh_gpio *chip = dev_id;
358 u32 reg_val;
359 int i, j;
360 int ret = IRQ_NONE;
361
362 for (i = 0; i < 8; i++, chip++) {
363 reg_val = ioread32(&chip->reg->regs[i].istatus);
364 for (j = 0; j < num_ports[i]; j++) {
365 if (reg_val & BIT(j)) {
366 dev_dbg(chip->dev,
367 "%s:[%d]:irq=%d status=0x%x\n",
368 __func__, j, irq, reg_val);
369 iowrite32(BIT(j),
370 &chip->reg->regs[chip->ch].iclr);
371 generic_handle_irq(chip->irq_base + j);
372 ret = IRQ_HANDLED;
373 }
374 }
375 }
376 return ret;
377 }
378
ioh_gpio_alloc_generic_chip(struct ioh_gpio * chip,unsigned int irq_start,unsigned int num)379 static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
380 unsigned int irq_start,
381 unsigned int num)
382 {
383 struct irq_chip_generic *gc;
384 struct irq_chip_type *ct;
385 int rv;
386
387 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
388 chip->base, handle_simple_irq);
389 if (!gc)
390 return -ENOMEM;
391
392 gc->private = chip;
393 ct = gc->chip_types;
394
395 ct->chip.irq_mask = ioh_irq_mask;
396 ct->chip.irq_unmask = ioh_irq_unmask;
397 ct->chip.irq_set_type = ioh_irq_type;
398 ct->chip.irq_disable = ioh_irq_disable;
399 ct->chip.irq_enable = ioh_irq_enable;
400
401 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
402 IRQ_GC_INIT_MASK_CACHE,
403 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
404
405 return rv;
406 }
407
ioh_gpio_probe(struct pci_dev * pdev,const struct pci_device_id * id)408 static int ioh_gpio_probe(struct pci_dev *pdev,
409 const struct pci_device_id *id)
410 {
411 struct device *dev = &pdev->dev;
412 int ret;
413 int i, j;
414 struct ioh_gpio *chip;
415 struct ioh_gpio_device *priv;
416 void __iomem *base;
417 int irq_base;
418
419 ret = pcim_enable_device(pdev);
420 if (ret) {
421 dev_err(dev, "%s : pcim_enable_device failed", __func__);
422 return ret;
423 }
424
425 ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
426 if (ret) {
427 dev_err(dev, "pcim_iomap_regions failed-%d", ret);
428 return ret;
429 }
430
431 base = pcim_iomap_table(pdev)[1];
432 if (!base) {
433 dev_err(dev, "%s : pcim_iomap_table failed", __func__);
434 return -ENOMEM;
435 }
436
437 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
438 if (!priv)
439 return -ENOMEM;
440
441 raw_spin_lock_init(&priv->spinlock);
442 chip = priv->chip;
443 for (i = 0; i < 8; i++, chip++) {
444 chip->dev = dev;
445 chip->base = base;
446 chip->reg = chip->base;
447 chip->ch = i;
448 chip->spinlock = &priv->spinlock;
449 ioh_gpio_setup(chip, num_ports[i]);
450 ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
451 if (ret) {
452 dev_err(dev, "IOH gpio: Failed to register GPIO\n");
453 return ret;
454 }
455 }
456
457 chip = priv->chip;
458 for (j = 0; j < 8; j++, chip++) {
459 irq_base = devm_irq_alloc_descs(dev, -1, IOH_IRQ_BASE,
460 num_ports[j], NUMA_NO_NODE);
461 if (irq_base < 0) {
462 dev_warn(dev,
463 "ml_ioh_gpio: Failed to get IRQ base num\n");
464 return irq_base;
465 }
466 chip->irq_base = irq_base;
467
468 ret = ioh_gpio_alloc_generic_chip(chip,
469 irq_base, num_ports[j]);
470 if (ret)
471 return ret;
472 }
473
474 chip = priv->chip;
475 ret = devm_request_irq(dev, pdev->irq, ioh_gpio_handler,
476 IRQF_SHARED, KBUILD_MODNAME, chip);
477 if (ret != 0) {
478 dev_err(dev, "%s request_irq failed\n", __func__);
479 return ret;
480 }
481
482 pci_set_drvdata(pdev, priv);
483
484 return 0;
485 }
486
ioh_gpio_suspend(struct device * dev)487 static int ioh_gpio_suspend(struct device *dev)
488 {
489 struct ioh_gpio_device *priv = dev_get_drvdata(dev);
490 unsigned long flags;
491
492 raw_spin_lock_irqsave(&priv->spinlock, flags);
493 ioh_gpio_save_reg_conf(priv->chip);
494 raw_spin_unlock_irqrestore(&priv->spinlock, flags);
495
496 return 0;
497 }
498
ioh_gpio_resume(struct device * dev)499 static int ioh_gpio_resume(struct device *dev)
500 {
501 struct ioh_gpio_device *priv = dev_get_drvdata(dev);
502 unsigned long flags;
503
504 raw_spin_lock_irqsave(&priv->spinlock, flags);
505 iowrite32(0x01, &priv->chip->reg->srst);
506 iowrite32(0x00, &priv->chip->reg->srst);
507 ioh_gpio_restore_reg_conf(priv->chip);
508 raw_spin_unlock_irqrestore(&priv->spinlock, flags);
509
510 return 0;
511 }
512
513 static DEFINE_SIMPLE_DEV_PM_OPS(ioh_gpio_pm_ops, ioh_gpio_suspend, ioh_gpio_resume);
514
515 static const struct pci_device_id ioh_gpio_pcidev_id[] = {
516 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
517 { 0, }
518 };
519 MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
520
521 static struct pci_driver ioh_gpio_driver = {
522 .name = "ml_ioh_gpio",
523 .id_table = ioh_gpio_pcidev_id,
524 .probe = ioh_gpio_probe,
525 .driver = {
526 .pm = pm_sleep_ptr(&ioh_gpio_pm_ops),
527 },
528 };
529
530 module_pci_driver(ioh_gpio_driver);
531
532 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
533 MODULE_LICENSE("GPL");
534