1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIO driver for Marvell SoCs
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * Andrew Lunn <andrew@lunn.ch>
9 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
10 *
11 * This driver is a fairly straightforward GPIO driver for the
12 * complete family of Marvell EBU SoC platforms (Orion, Dove,
13 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
14 * driver is the different register layout that exists between the
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
16 * platforms (MV78200 from the Discovery family and the Armada
17 * XP). Therefore, this driver handles three variants of the GPIO
18 * block:
19 * - the basic variant, called "orion-gpio", with the simplest
20 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
23 * turns the edge mask and level mask registers into CPU0 edge
24 * mask/level mask registers, and adds CPU1 edge mask/level mask
25 * registers.
26 * - the armadaxp variant for Armada XP systems. This variant keeps
27 * the normal cause/edge mask/level mask registers when the global
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
29 * registers n a separate memory area for the per-CPU GPIO
30 * interrupts.
31 */
32
33 #include <linux/bitops.h>
34 #include <linux/clk.h>
35 #include <linux/err.h>
36 #include <linux/gpio/driver.h>
37 #include <linux/gpio/consumer.h>
38 #include <linux/gpio/machine.h>
39 #include <linux/init.h>
40 #include <linux/interrupt.h>
41 #include <linux/io.h>
42 #include <linux/irq.h>
43 #include <linux/irqchip/chained_irq.h>
44 #include <linux/irqdomain.h>
45 #include <linux/mfd/syscon.h>
46 #include <linux/of.h>
47 #include <linux/pinctrl/consumer.h>
48 #include <linux/platform_device.h>
49 #include <linux/property.h>
50 #include <linux/pwm.h>
51 #include <linux/regmap.h>
52 #include <linux/slab.h>
53 #include <linux/string_choices.h>
54
55 /*
56 * GPIO unit register offsets.
57 */
58 #define GPIO_OUT_OFF 0x0000
59 #define GPIO_IO_CONF_OFF 0x0004
60 #define GPIO_BLINK_EN_OFF 0x0008
61 #define GPIO_IN_POL_OFF 0x000c
62 #define GPIO_DATA_IN_OFF 0x0010
63 #define GPIO_EDGE_CAUSE_OFF 0x0014
64 #define GPIO_EDGE_MASK_OFF 0x0018
65 #define GPIO_LEVEL_MASK_OFF 0x001c
66 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
67
68 /*
69 * PWM register offsets.
70 */
71 #define PWM_BLINK_ON_DURATION_OFF 0x0
72 #define PWM_BLINK_OFF_DURATION_OFF 0x4
73 #define PWM_BLINK_COUNTER_B_OFF 0x8
74
75 /* Armada 8k variant gpios register offsets */
76 #define AP80X_GPIO0_OFF_A8K 0x1040
77 #define CP11X_GPIO0_OFF_A8K 0x100
78 #define CP11X_GPIO1_OFF_A8K 0x140
79
80 /* The MV78200 has per-CPU registers for edge mask and level mask */
81 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
82 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
83
84 /*
85 * The Armada XP has per-CPU registers for interrupt cause, interrupt
86 * mask and interrupt level mask. Those are in percpu_regs range.
87 */
88 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
89 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
90 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
91
92 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
93 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
94 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
95 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
96
97 #define MVEBU_MAX_GPIO_PER_BANK 32
98
99 struct mvebu_pwm {
100 struct regmap *regs;
101 u32 offset;
102 unsigned long clk_rate;
103 struct gpio_desc *gpiod;
104 spinlock_t lock;
105 struct mvebu_gpio_chip *mvchip;
106
107 /* Used to preserve GPIO/PWM registers across suspend/resume */
108 u32 blink_select;
109 u32 blink_on_duration;
110 u32 blink_off_duration;
111 };
112
113 struct mvebu_gpio_chip {
114 struct gpio_chip chip;
115 struct regmap *regs;
116 u32 offset;
117 struct regmap *percpu_regs;
118 int bank_irq[4];
119 struct irq_domain *domain;
120 int soc_variant;
121
122 /* Used for PWM support */
123 struct clk *clk;
124 struct mvebu_pwm *mvpwm;
125
126 /* Used to preserve GPIO registers across suspend/resume */
127 u32 out_reg;
128 u32 io_conf_reg;
129 u32 blink_en_reg;
130 u32 in_pol_reg;
131 u32 edge_mask_regs[4];
132 u32 level_mask_regs[4];
133 };
134
135 /*
136 * Functions returning addresses of individual registers for a given
137 * GPIO controller.
138 */
139
mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)140 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
141 struct regmap **map, unsigned int *offset)
142 {
143 int cpu;
144
145 switch (mvchip->soc_variant) {
146 case MVEBU_GPIO_SOC_VARIANT_ORION:
147 case MVEBU_GPIO_SOC_VARIANT_MV78200:
148 case MVEBU_GPIO_SOC_VARIANT_A8K:
149 *map = mvchip->regs;
150 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
151 break;
152 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
153 cpu = smp_processor_id();
154 *map = mvchip->percpu_regs;
155 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
156 break;
157 default:
158 BUG();
159 }
160 }
161
162 static u32
mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip * mvchip)163 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
164 {
165 struct regmap *map;
166 unsigned int offset;
167 u32 val;
168
169 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
170 regmap_read(map, offset, &val);
171
172 return val;
173 }
174
175 static void
mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip * mvchip,u32 val)176 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
177 {
178 struct regmap *map;
179 unsigned int offset;
180
181 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
182 regmap_write(map, offset, val);
183 }
184
185 static inline void
mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)186 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
187 struct regmap **map, unsigned int *offset)
188 {
189 int cpu;
190
191 switch (mvchip->soc_variant) {
192 case MVEBU_GPIO_SOC_VARIANT_ORION:
193 case MVEBU_GPIO_SOC_VARIANT_A8K:
194 *map = mvchip->regs;
195 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
196 break;
197 case MVEBU_GPIO_SOC_VARIANT_MV78200:
198 cpu = smp_processor_id();
199 *map = mvchip->regs;
200 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
201 break;
202 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
203 cpu = smp_processor_id();
204 *map = mvchip->percpu_regs;
205 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
206 break;
207 default:
208 BUG();
209 }
210 }
211
212 static u32
mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip * mvchip)213 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
214 {
215 struct regmap *map;
216 unsigned int offset;
217 u32 val;
218
219 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
220 regmap_read(map, offset, &val);
221
222 return val;
223 }
224
225 static void
mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip * mvchip,u32 val)226 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
227 {
228 struct regmap *map;
229 unsigned int offset;
230
231 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
232 regmap_write(map, offset, val);
233 }
234
235 static void
mvebu_gpioreg_level_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)236 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
237 struct regmap **map, unsigned int *offset)
238 {
239 int cpu;
240
241 switch (mvchip->soc_variant) {
242 case MVEBU_GPIO_SOC_VARIANT_ORION:
243 case MVEBU_GPIO_SOC_VARIANT_A8K:
244 *map = mvchip->regs;
245 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
246 break;
247 case MVEBU_GPIO_SOC_VARIANT_MV78200:
248 cpu = smp_processor_id();
249 *map = mvchip->regs;
250 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
251 break;
252 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
253 cpu = smp_processor_id();
254 *map = mvchip->percpu_regs;
255 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
256 break;
257 default:
258 BUG();
259 }
260 }
261
262 static u32
mvebu_gpio_read_level_mask(struct mvebu_gpio_chip * mvchip)263 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
264 {
265 struct regmap *map;
266 unsigned int offset;
267 u32 val;
268
269 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
270 regmap_read(map, offset, &val);
271
272 return val;
273 }
274
275 static void
mvebu_gpio_write_level_mask(struct mvebu_gpio_chip * mvchip,u32 val)276 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
277 {
278 struct regmap *map;
279 unsigned int offset;
280
281 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
282 regmap_write(map, offset, val);
283 }
284
285 /*
286 * Functions returning offsets of individual registers for a given
287 * PWM controller.
288 */
mvebu_pwmreg_blink_on_duration(struct mvebu_pwm * mvpwm)289 static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
290 {
291 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF;
292 }
293
mvebu_pwmreg_blink_off_duration(struct mvebu_pwm * mvpwm)294 static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
295 {
296 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF;
297 }
298
299 /*
300 * Functions implementing the gpio_chip methods
301 */
mvebu_gpio_set(struct gpio_chip * chip,unsigned int pin,int value)302 static int mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
303 {
304 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
305
306 return regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
307 BIT(pin), value ? BIT(pin) : 0);
308 }
309
mvebu_gpio_get(struct gpio_chip * chip,unsigned int pin)310 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
311 {
312 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
313 u32 u;
314
315 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
316
317 if (u & BIT(pin)) {
318 u32 data_in, in_pol;
319
320 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
321 &data_in);
322 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
323 &in_pol);
324 u = data_in ^ in_pol;
325 } else {
326 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
327 }
328
329 return (u >> pin) & 1;
330 }
331
mvebu_gpio_blink(struct gpio_chip * chip,unsigned int pin,int value)332 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
333 int value)
334 {
335 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
336
337 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
338 BIT(pin), value ? BIT(pin) : 0);
339 }
340
mvebu_gpio_direction_input(struct gpio_chip * chip,unsigned int pin)341 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
342 {
343 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
344 int ret;
345
346 /*
347 * Check with the pinctrl driver whether this pin is usable as
348 * an input GPIO
349 */
350 ret = pinctrl_gpio_direction_input(chip, pin);
351 if (ret)
352 return ret;
353
354 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
355 BIT(pin), BIT(pin));
356
357 return 0;
358 }
359
mvebu_gpio_direction_output(struct gpio_chip * chip,unsigned int pin,int value)360 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
361 int value)
362 {
363 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
364 int ret;
365
366 /*
367 * Check with the pinctrl driver whether this pin is usable as
368 * an output GPIO
369 */
370 ret = pinctrl_gpio_direction_output(chip, pin);
371 if (ret)
372 return ret;
373
374 mvebu_gpio_blink(chip, pin, 0);
375 mvebu_gpio_set(chip, pin, value);
376
377 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
378 BIT(pin), 0);
379
380 return 0;
381 }
382
mvebu_gpio_get_direction(struct gpio_chip * chip,unsigned int pin)383 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
384 {
385 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
386 u32 u;
387
388 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
389
390 if (u & BIT(pin))
391 return GPIO_LINE_DIRECTION_IN;
392
393 return GPIO_LINE_DIRECTION_OUT;
394 }
395
mvebu_gpio_to_irq(struct gpio_chip * chip,unsigned int pin)396 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
397 {
398 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
399
400 return irq_create_mapping(mvchip->domain, pin);
401 }
402
403 /*
404 * Functions implementing the irq_chip methods
405 */
mvebu_gpio_irq_ack(struct irq_data * d)406 static void mvebu_gpio_irq_ack(struct irq_data *d)
407 {
408 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
409 struct mvebu_gpio_chip *mvchip = gc->private;
410 u32 mask = d->mask;
411
412 guard(raw_spinlock)(&gc->lock);
413 mvebu_gpio_write_edge_cause(mvchip, ~mask);
414 }
415
mvebu_gpio_edge_irq_mask(struct irq_data * d)416 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
417 {
418 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
419 struct mvebu_gpio_chip *mvchip = gc->private;
420 struct irq_chip_type *ct = irq_data_get_chip_type(d);
421 u32 mask = d->mask;
422
423 guard(raw_spinlock)(&gc->lock);
424 ct->mask_cache_priv &= ~mask;
425 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
426 }
427
mvebu_gpio_edge_irq_unmask(struct irq_data * d)428 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
429 {
430 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
431 struct mvebu_gpio_chip *mvchip = gc->private;
432 struct irq_chip_type *ct = irq_data_get_chip_type(d);
433 u32 mask = d->mask;
434
435 guard(raw_spinlock)(&gc->lock);
436 mvebu_gpio_write_edge_cause(mvchip, ~mask);
437 ct->mask_cache_priv |= mask;
438 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
439 }
440
mvebu_gpio_level_irq_mask(struct irq_data * d)441 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
442 {
443 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
444 struct mvebu_gpio_chip *mvchip = gc->private;
445 struct irq_chip_type *ct = irq_data_get_chip_type(d);
446 u32 mask = d->mask;
447
448 guard(raw_spinlock)(&gc->lock);
449 ct->mask_cache_priv &= ~mask;
450 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
451 }
452
mvebu_gpio_level_irq_unmask(struct irq_data * d)453 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
454 {
455 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
456 struct mvebu_gpio_chip *mvchip = gc->private;
457 struct irq_chip_type *ct = irq_data_get_chip_type(d);
458 u32 mask = d->mask;
459
460 guard(raw_spinlock)(&gc->lock);
461 ct->mask_cache_priv |= mask;
462 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
463 }
464
465 /*****************************************************************************
466 * MVEBU GPIO IRQ
467 *
468 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
469 * value of the line or the opposite value.
470 *
471 * Level IRQ handlers: DATA_IN is used directly as cause register.
472 * Interrupt are masked by LEVEL_MASK registers.
473 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
474 * Interrupt are masked by EDGE_MASK registers.
475 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
476 * the polarity to catch the next line transaction.
477 * This is a race condition that might not perfectly
478 * work on some use cases.
479 *
480 * Every eight GPIO lines are grouped (OR'ed) before going up to main
481 * cause register.
482 *
483 * EDGE cause mask
484 * data-in /--------| |-----| |----\
485 * -----| |----- ---- to main cause reg
486 * X \----------------| |----/
487 * polarity LEVEL mask
488 *
489 ****************************************************************************/
490
mvebu_gpio_irq_set_type(struct irq_data * d,unsigned int type)491 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
492 {
493 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
494 struct irq_chip_type *ct = irq_data_get_chip_type(d);
495 struct mvebu_gpio_chip *mvchip = gc->private;
496 int pin;
497 u32 u;
498
499 pin = d->hwirq;
500
501 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
502 if ((u & BIT(pin)) == 0)
503 return -EINVAL;
504
505 type &= IRQ_TYPE_SENSE_MASK;
506 if (type == IRQ_TYPE_NONE)
507 return -EINVAL;
508
509 /* Check if we need to change chip and handler */
510 if (!(ct->type & type))
511 if (irq_setup_alt_chip(d, type))
512 return -EINVAL;
513
514 /*
515 * Configure interrupt polarity.
516 */
517 switch (type) {
518 case IRQ_TYPE_EDGE_RISING:
519 case IRQ_TYPE_LEVEL_HIGH:
520 regmap_update_bits(mvchip->regs,
521 GPIO_IN_POL_OFF + mvchip->offset,
522 BIT(pin), 0);
523 break;
524 case IRQ_TYPE_EDGE_FALLING:
525 case IRQ_TYPE_LEVEL_LOW:
526 regmap_update_bits(mvchip->regs,
527 GPIO_IN_POL_OFF + mvchip->offset,
528 BIT(pin), BIT(pin));
529 break;
530 case IRQ_TYPE_EDGE_BOTH: {
531 u32 data_in, in_pol, val;
532
533 regmap_read(mvchip->regs,
534 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
535 regmap_read(mvchip->regs,
536 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
537
538 /*
539 * set initial polarity based on current input level
540 */
541 if ((data_in ^ in_pol) & BIT(pin))
542 val = BIT(pin); /* falling */
543 else
544 val = 0; /* raising */
545
546 regmap_update_bits(mvchip->regs,
547 GPIO_IN_POL_OFF + mvchip->offset,
548 BIT(pin), val);
549 break;
550 }
551 }
552 return 0;
553 }
554
mvebu_gpio_irq_handler(struct irq_desc * desc)555 static void mvebu_gpio_irq_handler(struct irq_desc *desc)
556 {
557 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
558 struct irq_chip *chip = irq_desc_get_chip(desc);
559 u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
560 int i;
561
562 if (mvchip == NULL)
563 return;
564
565 chained_irq_enter(chip, desc);
566
567 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
568 level_mask = mvebu_gpio_read_level_mask(mvchip);
569 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
570 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
571
572 cause = (data_in & level_mask) | (edge_cause & edge_mask);
573
574 for (i = 0; i < mvchip->chip.ngpio; i++) {
575 int irq;
576
577 if (!(cause & BIT(i)))
578 continue;
579
580 irq = irq_find_mapping(mvchip->domain, i);
581 type = irq_get_trigger_type(irq);
582 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
583 /* Swap polarity (race with GPIO line) */
584 u32 polarity;
585
586 regmap_read(mvchip->regs,
587 GPIO_IN_POL_OFF + mvchip->offset,
588 &polarity);
589 polarity ^= BIT(i);
590 regmap_write(mvchip->regs,
591 GPIO_IN_POL_OFF + mvchip->offset,
592 polarity);
593 }
594
595 generic_handle_irq(irq);
596 }
597
598 chained_irq_exit(chip, desc);
599 }
600
601 static const struct regmap_config mvebu_gpio_regmap_config = {
602 .reg_bits = 32,
603 .reg_stride = 4,
604 .val_bits = 32,
605 };
606
607 /*
608 * Forward wake-up configuration to the parent bank IRQ.
609 * @d: interrupt data
610 * @enable: enable as wake-up if non-zero
611 *
612 * Return: 0 on success, or a negative error code.
613 */
mvebu_gpio_set_wake_irq(struct irq_data * d,unsigned int enable)614 static int mvebu_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
615 {
616 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
617 struct mvebu_gpio_chip *mvchip = gc->private;
618 int bank;
619 int irq;
620
621 bank = d->hwirq / 8;
622 if (bank >= ARRAY_SIZE(mvchip->bank_irq))
623 return -EINVAL;
624
625 irq = mvchip->bank_irq[bank];
626 if (irq <= 0)
627 return -EINVAL;
628
629 if (enable)
630 return enable_irq_wake(irq);
631
632 return disable_irq_wake(irq);
633 }
634
635 /*
636 * Functions implementing the pwm_chip methods
637 */
to_mvebu_pwm(struct pwm_chip * chip)638 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
639 {
640 return pwmchip_get_drvdata(chip);
641 }
642
mvebu_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)643 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
644 {
645 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
646 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
647 struct gpio_desc *desc;
648 unsigned long flags;
649 int ret = 0;
650
651 spin_lock_irqsave(&mvpwm->lock, flags);
652
653 if (mvpwm->gpiod) {
654 ret = -EBUSY;
655 } else {
656 desc = gpiochip_request_own_desc(&mvchip->chip,
657 pwm->hwpwm, "mvebu-pwm",
658 GPIO_ACTIVE_HIGH,
659 GPIOD_OUT_LOW);
660 if (IS_ERR(desc)) {
661 ret = PTR_ERR(desc);
662 goto out;
663 }
664
665 mvpwm->gpiod = desc;
666 }
667 out:
668 spin_unlock_irqrestore(&mvpwm->lock, flags);
669 return ret;
670 }
671
mvebu_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)672 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
673 {
674 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
675 unsigned long flags;
676
677 spin_lock_irqsave(&mvpwm->lock, flags);
678 gpiochip_free_own_desc(mvpwm->gpiod);
679 mvpwm->gpiod = NULL;
680 spin_unlock_irqrestore(&mvpwm->lock, flags);
681 }
682
mvebu_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)683 static int mvebu_pwm_get_state(struct pwm_chip *chip,
684 struct pwm_device *pwm,
685 struct pwm_state *state)
686 {
687
688 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
689 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
690 unsigned long long val;
691 unsigned long flags;
692 u32 u;
693
694 spin_lock_irqsave(&mvpwm->lock, flags);
695
696 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
697 /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */
698 if (u > 0)
699 val = u;
700 else
701 val = UINT_MAX + 1ULL;
702 state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC,
703 mvpwm->clk_rate);
704
705 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
706 /* period = on + off duration */
707 if (u > 0)
708 val += u;
709 else
710 val += UINT_MAX + 1ULL;
711 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
712
713 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
714 if (u)
715 state->enabled = true;
716 else
717 state->enabled = false;
718
719 spin_unlock_irqrestore(&mvpwm->lock, flags);
720
721 return 0;
722 }
723
mvebu_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)724 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
725 const struct pwm_state *state)
726 {
727 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
728 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
729 unsigned long long val;
730 unsigned long flags;
731 unsigned int on, off;
732
733 if (state->polarity != PWM_POLARITY_NORMAL)
734 return -EINVAL;
735
736 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
737 do_div(val, NSEC_PER_SEC);
738 if (val > UINT_MAX + 1ULL)
739 return -EINVAL;
740 /*
741 * Zero on/off values don't work as expected. Experimentation shows
742 * that zero value is treated as 2^32. This behavior is not documented.
743 */
744 if (val == UINT_MAX + 1ULL)
745 on = 0;
746 else if (val)
747 on = val;
748 else
749 on = 1;
750
751 val = (unsigned long long) mvpwm->clk_rate * state->period;
752 do_div(val, NSEC_PER_SEC);
753 val -= on;
754 if (val > UINT_MAX + 1ULL)
755 return -EINVAL;
756 if (val == UINT_MAX + 1ULL)
757 off = 0;
758 else if (val)
759 off = val;
760 else
761 off = 1;
762
763 spin_lock_irqsave(&mvpwm->lock, flags);
764
765 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on);
766 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off);
767 if (state->enabled)
768 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
769 else
770 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
771
772 spin_unlock_irqrestore(&mvpwm->lock, flags);
773
774 return 0;
775 }
776
777 static const struct pwm_ops mvebu_pwm_ops = {
778 .request = mvebu_pwm_request,
779 .free = mvebu_pwm_free,
780 .get_state = mvebu_pwm_get_state,
781 .apply = mvebu_pwm_apply,
782 };
783
mvebu_pwm_suspend(struct mvebu_gpio_chip * mvchip)784 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
785 {
786 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
787
788 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
789 &mvpwm->blink_select);
790 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
791 &mvpwm->blink_on_duration);
792 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
793 &mvpwm->blink_off_duration);
794 }
795
mvebu_pwm_resume(struct mvebu_gpio_chip * mvchip)796 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
797 {
798 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
799
800 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
801 mvpwm->blink_select);
802 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
803 mvpwm->blink_on_duration);
804 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
805 mvpwm->blink_off_duration);
806 }
807
mvebu_pwm_probe(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip,int id)808 static int mvebu_pwm_probe(struct platform_device *pdev,
809 struct mvebu_gpio_chip *mvchip,
810 int id)
811 {
812 struct device *dev = &pdev->dev;
813 struct mvebu_pwm *mvpwm;
814 struct pwm_chip *chip;
815 void __iomem *base;
816 u32 offset;
817 u32 set;
818
819 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
820 int ret = device_property_read_u32(dev, "marvell,pwm-offset",
821 &offset);
822 if (ret < 0)
823 return 0;
824 } else {
825 /*
826 * There are only two sets of PWM configuration registers for
827 * all the GPIO lines on those SoCs which this driver reserves
828 * for the first two GPIO chips. So if the resource is missing
829 * we can't treat it as an error.
830 */
831 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
832 return 0;
833 offset = 0;
834 }
835
836 if (IS_ERR(mvchip->clk))
837 return PTR_ERR(mvchip->clk);
838
839 chip = devm_pwmchip_alloc(dev, mvchip->chip.ngpio, sizeof(*mvpwm));
840 if (IS_ERR(chip))
841 return PTR_ERR(chip);
842 mvpwm = to_mvebu_pwm(chip);
843
844 mvchip->mvpwm = mvpwm;
845 mvpwm->mvchip = mvchip;
846 mvpwm->offset = offset;
847
848 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
849 mvpwm->regs = mvchip->regs;
850
851 switch (mvchip->offset) {
852 case AP80X_GPIO0_OFF_A8K:
853 case CP11X_GPIO0_OFF_A8K:
854 /* Blink counter A */
855 set = 0;
856 break;
857 case CP11X_GPIO1_OFF_A8K:
858 /* Blink counter B */
859 set = U32_MAX;
860 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF;
861 break;
862 default:
863 return -EINVAL;
864 }
865 } else {
866 base = devm_platform_ioremap_resource_byname(pdev, "pwm");
867 if (IS_ERR(base))
868 return PTR_ERR(base);
869
870 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
871 &mvebu_gpio_regmap_config);
872 if (IS_ERR(mvpwm->regs))
873 return PTR_ERR(mvpwm->regs);
874
875 /*
876 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
877 * with id 1. Don't allow further GPIO chips to be used for PWM.
878 */
879 if (id == 0)
880 set = 0;
881 else if (id == 1)
882 set = U32_MAX;
883 else
884 return -EINVAL;
885 }
886
887 regmap_write(mvchip->regs,
888 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
889
890 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
891 if (!mvpwm->clk_rate) {
892 dev_err(dev, "failed to get clock rate\n");
893 return -EINVAL;
894 }
895
896 chip->ops = &mvebu_pwm_ops;
897
898 spin_lock_init(&mvpwm->lock);
899
900 return devm_pwmchip_add(dev, chip);
901 }
902
903 #ifdef CONFIG_DEBUG_FS
904 #include <linux/seq_file.h>
905
mvebu_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)906 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
907 {
908 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
909 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
910 const char *label;
911 int i;
912
913 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
914 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
915 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
916 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
917 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
918 cause = mvebu_gpio_read_edge_cause(mvchip);
919 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
920 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
921
922 for_each_requested_gpio(chip, i, label) {
923 u32 msk;
924 bool is_out;
925
926 msk = BIT(i);
927 is_out = !(io_conf & msk);
928
929 seq_printf(s, " gpio-%-3d (%-20.20s)", i, label);
930
931 if (is_out) {
932 seq_printf(s, " out %s %s\n",
933 str_hi_lo(out & msk),
934 blink & msk ? "(blink )" : "");
935 continue;
936 }
937
938 seq_printf(s, " in %s (act %s) - IRQ",
939 str_hi_lo((data_in ^ in_pol) & msk),
940 str_lo_hi(in_pol & msk));
941 if (!((edg_msk | lvl_msk) & msk)) {
942 seq_puts(s, " disabled\n");
943 continue;
944 }
945 if (edg_msk & msk)
946 seq_puts(s, " edge ");
947 if (lvl_msk & msk)
948 seq_puts(s, " level");
949 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
950 }
951 }
952 #else
953 #define mvebu_gpio_dbg_show NULL
954 #endif
955
956 static const struct of_device_id mvebu_gpio_of_match[] = {
957 {
958 .compatible = "marvell,orion-gpio",
959 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
960 },
961 {
962 .compatible = "marvell,mv78200-gpio",
963 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
964 },
965 {
966 .compatible = "marvell,armadaxp-gpio",
967 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
968 },
969 {
970 .compatible = "marvell,armada-370-gpio",
971 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
972 },
973 {
974 .compatible = "marvell,armada-8k-gpio",
975 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
976 },
977 {
978 /* sentinel */
979 },
980 };
981
mvebu_gpio_suspend(struct platform_device * pdev,pm_message_t state)982 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
983 {
984 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
985 int i;
986
987 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
988 &mvchip->out_reg);
989 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
990 &mvchip->io_conf_reg);
991 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
992 &mvchip->blink_en_reg);
993 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
994 &mvchip->in_pol_reg);
995
996 switch (mvchip->soc_variant) {
997 case MVEBU_GPIO_SOC_VARIANT_ORION:
998 case MVEBU_GPIO_SOC_VARIANT_A8K:
999 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
1000 &mvchip->edge_mask_regs[0]);
1001 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
1002 &mvchip->level_mask_regs[0]);
1003 break;
1004 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1005 for (i = 0; i < 2; i++) {
1006 regmap_read(mvchip->regs,
1007 GPIO_EDGE_MASK_MV78200_OFF(i),
1008 &mvchip->edge_mask_regs[i]);
1009 regmap_read(mvchip->regs,
1010 GPIO_LEVEL_MASK_MV78200_OFF(i),
1011 &mvchip->level_mask_regs[i]);
1012 }
1013 break;
1014 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1015 for (i = 0; i < 4; i++) {
1016 regmap_read(mvchip->regs,
1017 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1018 &mvchip->edge_mask_regs[i]);
1019 regmap_read(mvchip->regs,
1020 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1021 &mvchip->level_mask_regs[i]);
1022 }
1023 break;
1024 default:
1025 BUG();
1026 }
1027
1028 if (IS_REACHABLE(CONFIG_PWM) && mvchip->mvpwm)
1029 mvebu_pwm_suspend(mvchip);
1030
1031 return 0;
1032 }
1033
mvebu_gpio_resume(struct platform_device * pdev)1034 static int mvebu_gpio_resume(struct platform_device *pdev)
1035 {
1036 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
1037 u32 edge_cache = ~0U, level_cache = ~0U;
1038 unsigned long flags;
1039 int i;
1040
1041 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
1042 mvchip->out_reg);
1043 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
1044 mvchip->io_conf_reg);
1045 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
1046 mvchip->blink_en_reg);
1047 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
1048 mvchip->in_pol_reg);
1049
1050 /*
1051 * genirq skips mask_irq() for a line it already considers masked, so
1052 * unmasking one behind its back leaves an asserted level line that
1053 * nobody masks. Restore only bits the irqchip cache still has set.
1054 *
1055 * Snapshot the caches under the raw spinlock, but release it before
1056 * the regmap writes below: regmap_write() takes a sleepable lock on
1057 * PREEMPT_RT.
1058 */
1059 if (mvchip->domain) {
1060 struct irq_chip_generic *gc;
1061
1062 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1063 raw_spin_lock_irqsave(&gc->lock, flags);
1064 level_cache = gc->chip_types[0].mask_cache_priv;
1065 edge_cache = gc->chip_types[1].mask_cache_priv;
1066 raw_spin_unlock_irqrestore(&gc->lock, flags);
1067 }
1068
1069 switch (mvchip->soc_variant) {
1070 case MVEBU_GPIO_SOC_VARIANT_ORION:
1071 case MVEBU_GPIO_SOC_VARIANT_A8K:
1072 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
1073 mvchip->edge_mask_regs[0] & edge_cache);
1074 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
1075 mvchip->level_mask_regs[0] & level_cache);
1076 break;
1077 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1078 for (i = 0; i < 2; i++) {
1079 regmap_write(mvchip->regs,
1080 GPIO_EDGE_MASK_MV78200_OFF(i),
1081 mvchip->edge_mask_regs[i] & edge_cache);
1082 regmap_write(mvchip->regs,
1083 GPIO_LEVEL_MASK_MV78200_OFF(i),
1084 mvchip->level_mask_regs[i] & level_cache);
1085 }
1086 break;
1087 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1088 for (i = 0; i < 4; i++) {
1089 regmap_write(mvchip->regs,
1090 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1091 mvchip->edge_mask_regs[i] & edge_cache);
1092 regmap_write(mvchip->regs,
1093 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1094 mvchip->level_mask_regs[i] & level_cache);
1095 }
1096 break;
1097 default:
1098 BUG();
1099 }
1100
1101 if (IS_REACHABLE(CONFIG_PWM) && mvchip->mvpwm)
1102 mvebu_pwm_resume(mvchip);
1103
1104 return 0;
1105 }
1106
mvebu_gpio_probe_raw(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1107 static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1108 struct mvebu_gpio_chip *mvchip)
1109 {
1110 void __iomem *base;
1111
1112 base = devm_platform_ioremap_resource(pdev, 0);
1113 if (IS_ERR(base))
1114 return PTR_ERR(base);
1115
1116 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1117 &mvebu_gpio_regmap_config);
1118 if (IS_ERR(mvchip->regs))
1119 return PTR_ERR(mvchip->regs);
1120
1121 /*
1122 * For the legacy SoCs, the regmap directly maps to the GPIO
1123 * registers, so no offset is needed.
1124 */
1125 mvchip->offset = 0;
1126
1127 /*
1128 * The Armada XP has a second range of registers for the
1129 * per-CPU registers
1130 */
1131 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1132 base = devm_platform_ioremap_resource(pdev, 1);
1133 if (IS_ERR(base))
1134 return PTR_ERR(base);
1135
1136 mvchip->percpu_regs =
1137 devm_regmap_init_mmio(&pdev->dev, base,
1138 &mvebu_gpio_regmap_config);
1139 if (IS_ERR(mvchip->percpu_regs))
1140 return PTR_ERR(mvchip->percpu_regs);
1141 }
1142
1143 return 0;
1144 }
1145
mvebu_gpio_probe_syscon(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1146 static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1147 struct mvebu_gpio_chip *mvchip)
1148 {
1149 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1150 if (IS_ERR(mvchip->regs))
1151 return PTR_ERR(mvchip->regs);
1152
1153 if (device_property_read_u32(&pdev->dev, "offset", &mvchip->offset))
1154 return -EINVAL;
1155
1156 return 0;
1157 }
1158
mvebu_gpio_remove_irq_domain(void * data)1159 static void mvebu_gpio_remove_irq_domain(void *data)
1160 {
1161 struct irq_domain *domain = data;
1162
1163 irq_domain_remove_generic_chips(domain);
1164 irq_domain_remove(domain);
1165 }
1166
mvebu_gpio_probe(struct platform_device * pdev)1167 static int mvebu_gpio_probe(struct platform_device *pdev)
1168 {
1169 struct mvebu_gpio_chip *mvchip;
1170 struct device_node *np = pdev->dev.of_node;
1171 struct irq_chip_generic *gc;
1172 struct irq_chip_type *ct;
1173 unsigned int ngpios;
1174 bool have_irqs;
1175 int soc_variant;
1176 int i, cpu, id;
1177 int err;
1178
1179 soc_variant = (unsigned long)device_get_match_data(&pdev->dev);
1180
1181 /* Some gpio controllers do not provide irq support */
1182 err = platform_irq_count(pdev);
1183 if (err < 0)
1184 return err;
1185
1186 have_irqs = err != 0;
1187
1188 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1189 GFP_KERNEL);
1190 if (!mvchip)
1191 return -ENOMEM;
1192
1193 platform_set_drvdata(pdev, mvchip);
1194
1195 if (device_property_read_u32(&pdev->dev, "ngpios", &ngpios)) {
1196 dev_err(&pdev->dev, "Missing ngpios OF property\n");
1197 return -ENODEV;
1198 }
1199
1200 id = of_alias_get_id(pdev->dev.of_node, "gpio");
1201 if (id < 0) {
1202 dev_err(&pdev->dev, "Couldn't get OF id\n");
1203 return id;
1204 }
1205
1206 mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1207 /* Not all SoCs require a clock.*/
1208 if (!IS_ERR(mvchip->clk))
1209 clk_prepare_enable(mvchip->clk);
1210
1211 mvchip->soc_variant = soc_variant;
1212 mvchip->chip.label = dev_name(&pdev->dev);
1213 mvchip->chip.parent = &pdev->dev;
1214 mvchip->chip.request = gpiochip_generic_request;
1215 mvchip->chip.free = gpiochip_generic_free;
1216 mvchip->chip.get_direction = mvebu_gpio_get_direction;
1217 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1218 mvchip->chip.get = mvebu_gpio_get;
1219 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1220 mvchip->chip.set = mvebu_gpio_set;
1221 if (have_irqs)
1222 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1223 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1224 mvchip->chip.ngpio = ngpios;
1225 mvchip->chip.can_sleep = false;
1226 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1227
1228 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1229 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1230 else
1231 err = mvebu_gpio_probe_raw(pdev, mvchip);
1232
1233 if (err)
1234 return err;
1235
1236 /*
1237 * Mask and clear GPIO interrupts.
1238 */
1239 switch (soc_variant) {
1240 case MVEBU_GPIO_SOC_VARIANT_ORION:
1241 case MVEBU_GPIO_SOC_VARIANT_A8K:
1242 regmap_write(mvchip->regs,
1243 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1244 regmap_write(mvchip->regs,
1245 GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1246 regmap_write(mvchip->regs,
1247 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1248 break;
1249 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1250 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1251 for (cpu = 0; cpu < 2; cpu++) {
1252 regmap_write(mvchip->regs,
1253 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1254 regmap_write(mvchip->regs,
1255 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1256 }
1257 break;
1258 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1259 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1260 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1261 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1262 for (cpu = 0; cpu < 4; cpu++) {
1263 regmap_write(mvchip->percpu_regs,
1264 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1265 regmap_write(mvchip->percpu_regs,
1266 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1267 regmap_write(mvchip->percpu_regs,
1268 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1269 }
1270 break;
1271 default:
1272 BUG();
1273 }
1274
1275 err = devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1276 if (err)
1277 return dev_err_probe(&pdev->dev, err,
1278 "failed to register gpiochip\n");
1279
1280 /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1281 if (IS_REACHABLE(CONFIG_PWM)) {
1282 err = mvebu_pwm_probe(pdev, mvchip, id);
1283 if (err)
1284 return err;
1285 }
1286
1287 /* Some gpio controllers do not provide irq support */
1288 if (!have_irqs)
1289 return 0;
1290
1291 mvchip->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), ngpios,
1292 &irq_generic_chip_ops, NULL);
1293 if (!mvchip->domain) {
1294 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1295 mvchip->chip.label);
1296 return -ENODEV;
1297 }
1298
1299 err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain,
1300 mvchip->domain);
1301 if (err)
1302 return err;
1303
1304 err = irq_alloc_domain_generic_chips(
1305 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1306 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, IRQ_GC_INIT_NESTED_LOCK);
1307 if (err) {
1308 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1309 mvchip->chip.label);
1310 return err;
1311 }
1312
1313 /*
1314 * NOTE: The common accessors cannot be used because of the percpu
1315 * access to the mask registers
1316 */
1317 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1318 gc->private = mvchip;
1319 ct = &gc->chip_types[0];
1320 ct->type = IRQ_TYPE_LEVEL_MASK;
1321 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1322 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1323 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1324 ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
1325 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
1326 ct->chip.name = mvchip->chip.label;
1327
1328 ct = &gc->chip_types[1];
1329 ct->type = IRQ_TYPE_EDGE_BOTH;
1330 ct->chip.irq_ack = mvebu_gpio_irq_ack;
1331 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1332 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1333 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1334 ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
1335 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
1336 ct->handler = handle_edge_irq;
1337 ct->chip.name = mvchip->chip.label;
1338
1339 /*
1340 * Setup the interrupt handlers. Each chip can have up to 4
1341 * interrupt handlers, with each handler dealing with 8 GPIO
1342 * pins.
1343 */
1344 for (i = 0; i < ARRAY_SIZE(mvchip->bank_irq); i++) {
1345 int irq = platform_get_irq_optional(pdev, i);
1346
1347 if (irq < 0)
1348 continue;
1349 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1350 mvchip);
1351 mvchip->bank_irq[i] = irq;
1352 }
1353
1354 return 0;
1355 }
1356
1357 static struct platform_driver mvebu_gpio_driver = {
1358 .driver = {
1359 .name = "mvebu-gpio",
1360 .of_match_table = mvebu_gpio_of_match,
1361 },
1362 .probe = mvebu_gpio_probe,
1363 .suspend = mvebu_gpio_suspend,
1364 .resume = mvebu_gpio_resume,
1365 };
1366 builtin_platform_driver(mvebu_gpio_driver);
1367