xref: /linux/drivers/pinctrl/qcom/pinctrl-msm.h (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2013, Sony Mobile Communications AB.
4  */
5 #ifndef __PINCTRL_MSM_H__
6 #define __PINCTRL_MSM_H__
7 
8 #include <linux/pm.h>
9 #include <linux/types.h>
10 
11 #include <linux/pinctrl/pinctrl.h>
12 
13 struct platform_device;
14 
15 struct pinctrl_pin_desc;
16 
17 #define APQ_PIN_FUNCTION(fname)					\
18 	[APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname,		\
19 					fname##_groups,		\
20 					ARRAY_SIZE(fname##_groups))
21 
22 #define IPQ_PIN_FUNCTION(fname)					\
23 	[IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname,		\
24 					fname##_groups,		\
25 					ARRAY_SIZE(fname##_groups))
26 
27 #define MSM_PIN_FUNCTION(fname) 				\
28 	[msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname,		\
29 					fname##_groups,		\
30 					ARRAY_SIZE(fname##_groups))
31 
32 #define QCA_PIN_FUNCTION(fname)					\
33 	[qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname,		\
34 					fname##_groups,		\
35 					ARRAY_SIZE(fname##_groups))
36 
37 /**
38  * struct msm_pingroup - Qualcomm pingroup definition
39  * @grp:                  Generic data of the pin group (name and pins)
40  * @funcs:                A list of pinmux functions that can be selected for
41  *                        this group. The index of the selected function is used
42  *                        for programming the function selector.
43  *                        Entries should be indices into the groups list of the
44  *                        struct msm_pinctrl_soc_data.
45  * @ctl_reg:              Offset of the register holding control bits for this group.
46  * @io_reg:               Offset of the register holding input/output bits for this group.
47  * @intr_cfg_reg:         Offset of the register holding interrupt configuration bits.
48  * @intr_status_reg:      Offset of the register holding the status bits for this group.
49  * @intr_target_reg:      Offset of the register specifying routing of the interrupts
50  *                        from this group.
51  * @mux_bit:              Offset in @ctl_reg for the pinmux function selection.
52  * @pull_bit:             Offset in @ctl_reg for the bias configuration.
53  * @drv_bit:              Offset in @ctl_reg for the drive strength configuration.
54  * @od_bit:               Offset in @ctl_reg for controlling open drain.
55  * @oe_bit:               Offset in @ctl_reg for controlling output enable.
56  * @in_bit:               Offset in @io_reg for the input bit value.
57  * @out_bit:              Offset in @io_reg for the output bit value.
58  * @intr_enable_bit:      Offset in @intr_cfg_reg for enabling the interrupt for this group.
59  * @intr_status_bit:      Offset in @intr_status_reg for reading and acking the interrupt
60  *                        status.
61  * @intr_wakeup_present_bit: Offset in @intr_target_reg specifying the GPIO can generate
62  *			  wakeup events.
63  * @intr_wakeup_enable_bit: Offset in @intr_target_reg to enable wakeup events for the GPIO.
64  * @intr_target_bit:      Offset in @intr_target_reg for configuring the interrupt routing.
65  * @intr_target_width:    Number of bits used for specifying interrupt routing target.
66  * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
67  *                        this gpio should get routed to the KPSS processor.
68  * @intr_raw_status_bit:  Offset in @intr_cfg_reg for the raw status bit.
69  * @intr_polarity_bit:    Offset in @intr_cfg_reg for specifying polarity of the interrupt.
70  * @intr_detection_bit:   Offset in @intr_cfg_reg for specifying interrupt type.
71  * @intr_detection_width: Number of bits used for specifying interrupt type,
72  *                        Should be 2 for SoCs that can detect both edges in hardware,
73  *                        otherwise 1.
74  */
75 struct msm_pingroup {
76 	struct pingroup grp;
77 
78 	unsigned *funcs;
79 	unsigned nfuncs;
80 
81 	u32 ctl_reg;
82 	u32 io_reg;
83 	u32 intr_cfg_reg;
84 	u32 intr_status_reg;
85 	u32 intr_target_reg;
86 
87 	unsigned int tile:2;
88 
89 	unsigned mux_bit:5;
90 
91 	unsigned pull_bit:5;
92 	unsigned drv_bit:5;
93 	unsigned i2c_pull_bit:5;
94 
95 	unsigned od_bit:5;
96 	unsigned egpio_enable:5;
97 	unsigned egpio_present:5;
98 	unsigned oe_bit:5;
99 	unsigned in_bit:5;
100 	unsigned out_bit:5;
101 
102 	unsigned intr_enable_bit:5;
103 	unsigned intr_status_bit:5;
104 	unsigned intr_ack_high:1;
105 
106 	unsigned intr_wakeup_present_bit:5;
107 	unsigned intr_wakeup_enable_bit:5;
108 	unsigned intr_target_bit:5;
109 	unsigned intr_target_width:5;
110 	unsigned intr_target_kpss_val:5;
111 	unsigned intr_raw_status_bit:5;
112 	unsigned intr_polarity_bit:5;
113 	unsigned intr_detection_bit:5;
114 	unsigned intr_detection_width:5;
115 };
116 
117 /**
118  * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
119  * @gpio:          The GPIOs that are wakeup capable
120  * @wakeirq:       The interrupt at the always-on interrupt controller
121  */
122 struct msm_gpio_wakeirq_map {
123 	unsigned int gpio;
124 	unsigned int wakeirq;
125 };
126 
127 /**
128  * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
129  * @pins:	    An array describing all pins the pin controller affects.
130  * @npins:	    The number of entries in @pins.
131  * @functions:	    An array describing all mux functions the SoC supports.
132  * @nfunctions:	    The number of entries in @functions.
133  * @groups:	    An array describing all pin groups the pin SoC supports.
134  * @ngroups:	    The numbmer of entries in @groups.
135  * @ngpio:	    The number of pingroups the driver should expose as GPIOs.
136  * @pull_no_keeper: The SoC does not support keeper bias.
137  * @wakeirq_map:    The map of wakeup capable GPIOs and the pin at PDC/MPM
138  * @nwakeirq_map:   The number of entries in @wakeirq_map
139  * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need
140  *                            to be aware that their parent can't handle dual
141  *                            edge interrupts.
142  * @gpio_func: Which function number is GPIO (usually 0).
143  * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in
144  *              hardware this is a mux 1-level above the TLMM, we'll treat
145  *              it as if this is just another mux state of the TLMM. Since
146  *              it doesn't really map to hardware, we'll allocate a virtual
147  *              function number for eGPIO and any time we see that function
148  *              number used we'll treat it as a request to mux away from
149  *              our TLMM towards another owner.
150  */
151 struct msm_pinctrl_soc_data {
152 	const struct pinctrl_pin_desc *pins;
153 	unsigned npins;
154 	const struct pinfunction *functions;
155 	unsigned nfunctions;
156 	const struct msm_pingroup *groups;
157 	unsigned ngroups;
158 	unsigned ngpios;
159 	bool pull_no_keeper;
160 	const char *const *tiles;
161 	unsigned int ntiles;
162 	const int *reserved_gpios;
163 	const struct msm_gpio_wakeirq_map *wakeirq_map;
164 	unsigned int nwakeirq_map;
165 	bool wakeirq_dual_edge_errata;
166 	unsigned int gpio_func;
167 	unsigned int egpio_func;
168 };
169 
170 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
171 
172 int msm_pinctrl_probe(struct platform_device *pdev,
173 		      const struct msm_pinctrl_soc_data *soc_data);
174 void msm_pinctrl_remove(struct platform_device *pdev);
175 
176 #endif
177