1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // es8326.c -- es8326 ALSA SoC audio driver
4 // Copyright Everest Semiconductor Co., Ltd
5 //
6 // Authors: David Yang <yangxiaohua@everest-semi.com>
7 //
8
9 #include <linux/cleanup.h>
10 #include <linux/clk.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <sound/jack.h>
16 #include <sound/pcm_params.h>
17 #include <sound/soc.h>
18 #include <sound/soc-dapm.h>
19 #include <sound/tlv.h>
20 #include "es8326.h"
21
22 struct es8326_priv {
23 struct clk *mclk;
24 struct i2c_client *i2c;
25 struct regmap *regmap;
26 struct snd_soc_component *component;
27 struct delayed_work jack_detect_work;
28 struct delayed_work button_press_work;
29 struct delayed_work capture_pop_work;
30 struct snd_soc_jack *jack;
31 int irq;
32 /* The lock protects the situation that an irq is generated
33 * while enabling or disabling or during an irq.
34 */
35 struct mutex lock;
36 u8 jack_pol;
37 u8 interrupt_src;
38 u8 interrupt_clk;
39 u8 hpl_vol;
40 u8 hpr_vol;
41 bool jd_inverted;
42 unsigned int sysclk;
43
44 bool calibrated;
45 int version;
46 int hp;
47 int jack_remove_retry;
48 };
49
es8326_crosstalk1_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)50 static int es8326_crosstalk1_get(struct snd_kcontrol *kcontrol,
51 struct snd_ctl_elem_value *ucontrol)
52 {
53 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
54 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
55 unsigned int crosstalk_h, crosstalk_l;
56 unsigned int crosstalk;
57
58 regmap_read(es8326->regmap, ES8326_DAC_RAMPRATE, &crosstalk_h);
59 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l);
60 crosstalk_h &= 0x20;
61 crosstalk_l &= 0xf0;
62 crosstalk = crosstalk_h >> 1 | crosstalk_l >> 4;
63 ucontrol->value.integer.value[0] = crosstalk;
64
65 return 0;
66 }
67
es8326_crosstalk1_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)68 static int es8326_crosstalk1_set(struct snd_kcontrol *kcontrol,
69 struct snd_ctl_elem_value *ucontrol)
70 {
71 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
72 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
73 unsigned int crosstalk_h, crosstalk_l;
74 unsigned int crosstalk;
75
76 crosstalk = ucontrol->value.integer.value[0];
77 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l);
78 crosstalk_h = (crosstalk & 0x10) << 1;
79 crosstalk_l &= 0x0f;
80 crosstalk_l |= (crosstalk & 0x0f) << 4;
81 regmap_update_bits(es8326->regmap, ES8326_DAC_RAMPRATE,
82 0x20, crosstalk_h);
83 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l);
84
85 return 0;
86 }
87
es8326_crosstalk2_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)88 static int es8326_crosstalk2_get(struct snd_kcontrol *kcontrol,
89 struct snd_ctl_elem_value *ucontrol)
90 {
91 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
92 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
93 unsigned int crosstalk_h, crosstalk_l;
94 unsigned int crosstalk;
95
96 regmap_read(es8326->regmap, ES8326_DAC_RAMPRATE, &crosstalk_h);
97 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l);
98 crosstalk_h &= 0x10;
99 crosstalk_l &= 0x0f;
100 crosstalk = crosstalk_h | crosstalk_l;
101 ucontrol->value.integer.value[0] = crosstalk;
102
103 return 0;
104 }
105
es8326_crosstalk2_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)106 static int es8326_crosstalk2_set(struct snd_kcontrol *kcontrol,
107 struct snd_ctl_elem_value *ucontrol)
108 {
109 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
110 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
111 unsigned int crosstalk_h, crosstalk_l;
112 unsigned int crosstalk;
113
114 crosstalk = ucontrol->value.integer.value[0];
115 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l);
116 crosstalk_h = crosstalk & 0x10;
117 crosstalk_l &= 0xf0;
118 crosstalk_l |= crosstalk & 0x0f;
119 regmap_update_bits(es8326->regmap, ES8326_DAC_RAMPRATE,
120 0x10, crosstalk_h);
121 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l);
122
123 return 0;
124 }
125
es8326_hplvol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)126 static int es8326_hplvol_get(struct snd_kcontrol *kcontrol,
127 struct snd_ctl_elem_value *ucontrol)
128 {
129 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
130 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
131
132 ucontrol->value.integer.value[0] = es8326->hpl_vol;
133
134 return 0;
135 }
136
es8326_hplvol_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)137 static int es8326_hplvol_set(struct snd_kcontrol *kcontrol,
138 struct snd_ctl_elem_value *ucontrol)
139 {
140 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
141 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
142 unsigned int hp_vol;
143
144 hp_vol = ucontrol->value.integer.value[0];
145 if (hp_vol > 5)
146 return -EINVAL;
147 if (es8326->hpl_vol != hp_vol) {
148 es8326->hpl_vol = hp_vol;
149 if (hp_vol >= 3)
150 hp_vol++;
151 regmap_update_bits(es8326->regmap, ES8326_HP_VOL,
152 0x70, (hp_vol << 4));
153 return 1;
154 }
155
156 return 0;
157 }
158
es8326_hprvol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)159 static int es8326_hprvol_get(struct snd_kcontrol *kcontrol,
160 struct snd_ctl_elem_value *ucontrol)
161 {
162 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
163 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
164
165 ucontrol->value.integer.value[0] = es8326->hpr_vol;
166
167 return 0;
168 }
169
es8326_hprvol_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)170 static int es8326_hprvol_set(struct snd_kcontrol *kcontrol,
171 struct snd_ctl_elem_value *ucontrol)
172 {
173 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
174 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
175 unsigned int hp_vol;
176
177 hp_vol = ucontrol->value.integer.value[0];
178 if (hp_vol > 5)
179 return -EINVAL;
180 if (es8326->hpr_vol != hp_vol) {
181 es8326->hpr_vol = hp_vol;
182 if (hp_vol >= 3)
183 hp_vol++;
184 regmap_update_bits(es8326->regmap, ES8326_HP_VOL,
185 0x07, hp_vol);
186 return 1;
187 }
188
189 return 0;
190 }
191
192 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9550, 50, 0);
193 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9550, 50, 0);
194 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_analog_pga_tlv, 0, 300, 0);
195 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_pga_tlv, 0, 600, 0);
196 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(softramp_rate, 0, 100, 0);
197 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_target_tlv, -3200, 200, 0);
198 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_recovery_tlv, -125, 250, 0);
199 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dre_gain_tlv, -9550, 400, 0);
200 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dre_gate_tlv, -9600, 600, 0);
201
202 static const char *const winsize[] = {
203 "0.25db/2 LRCK",
204 "0.25db/4 LRCK",
205 "0.25db/8 LRCK",
206 "0.25db/16 LRCK",
207 "0.25db/32 LRCK",
208 "0.25db/64 LRCK",
209 "0.25db/128 LRCK",
210 "0.25db/256 LRCK",
211 "0.25db/512 LRCK",
212 "0.25db/1024 LRCK",
213 "0.25db/2048 LRCK",
214 "0.25db/4096 LRCK",
215 "0.25db/8192 LRCK",
216 "0.25db/16384 LRCK",
217 "0.25db/32768 LRCK",
218 "0.25db/65536 LRCK",
219 };
220
221 static const char *const dacpol_txt[] = {
222 "Normal", "R Invert", "L Invert", "L + R Invert" };
223
224 static const char *const hp_spkvol_switch[] = {
225 "HPVOL: HPL+HPL, SPKVOL: HPL+HPL",
226 "HPVOL: HPL+HPR, SPKVOL: HPL+HPR",
227 "HPVOL: HPL+HPL, SPKVOL: SPKL+SPKR",
228 "HPVOL: HPL+HPR, SPKVOL: SPKL+SPKR",
229 };
230
231 static const struct soc_enum dacpol =
232 SOC_ENUM_SINGLE(ES8326_DAC_DSM, 4, 4, dacpol_txt);
233 static const struct soc_enum dre_winsize =
234 SOC_ENUM_SINGLE(ES8326_ADC_DRE, 0, 16, winsize);
235 static const struct soc_enum alc_winsize =
236 SOC_ENUM_SINGLE(ES8326_ADC_RAMPRATE, 4, 16, winsize);
237 static const struct soc_enum drc_winsize =
238 SOC_ENUM_SINGLE(ES8326_DRC_WINSIZE, 4, 16, winsize);
239 static const struct soc_enum hpvol_spkvol_switch =
240 SOC_ENUM_SINGLE(ES8326_HP_MISC, 6, 4, hp_spkvol_switch);
241
242 static const struct snd_kcontrol_new es8326_snd_controls[] = {
243 SOC_SINGLE_TLV("DAC Playback Volume", ES8326_DACL_VOL, 0, 0xbf, 0, dac_vol_tlv),
244 SOC_ENUM("Playback Polarity", dacpol),
245 SOC_SINGLE_TLV("DAC Ramp Rate", ES8326_DAC_RAMPRATE, 0, 0x0f, 0, softramp_rate),
246 SOC_SINGLE_TLV("DRC Recovery Level", ES8326_DRC_RECOVERY, 0, 4, 0, drc_recovery_tlv),
247 SOC_ENUM("DRC Winsize", drc_winsize),
248 SOC_SINGLE_TLV("DRC Target Level", ES8326_DRC_WINSIZE, 0, 0x0f, 0, drc_target_tlv),
249
250 SOC_DOUBLE_R_TLV("ADC Capture Volume", ES8326_ADC1_VOL, ES8326_ADC2_VOL, 0, 0xff, 0,
251 adc_vol_tlv),
252 SOC_DOUBLE_TLV("ADC PGA Volume", ES8326_ADC_SCALE, 4, 0, 5, 0, adc_pga_tlv),
253 SOC_SINGLE_TLV("ADC PGA Gain Volume", ES8326_PGAGAIN, 0, 10, 0, adc_analog_pga_tlv),
254 SOC_SINGLE("ADC PGA SE Switch", ES8326_PGAGAIN, 7, 1, 0),
255 SOC_SINGLE_TLV("ADC Ramp Rate", ES8326_ADC_RAMPRATE, 0, 0x0f, 0, softramp_rate),
256 SOC_SINGLE("ADC4 DRE Switch", ES8326_ADC_DRE, 4, 1, 0),
257 SOC_SINGLE("ADC3 DRE Switch", ES8326_ADC_DRE, 5, 1, 0),
258 SOC_SINGLE("ADC2 DRE Switch", ES8326_ADC_DRE, 6, 1, 0),
259 SOC_SINGLE("ADC1 DRE Switch", ES8326_ADC_DRE, 7, 1, 0),
260 SOC_ENUM("DRE Winsize", dre_winsize),
261 SOC_SINGLE("DRE Gain Switch", ES8326_ADC_DRE_GAIN, 5, 1, 0),
262 SOC_SINGLE_TLV("DRE Gain Volume", ES8326_ADC_DRE_GAIN,
263 0, 0x1F, 0, dre_gain_tlv),
264 SOC_SINGLE_TLV("DRE Gate Volume", ES8326_ADC_DRE_GATE,
265 4, 0x07, 0, dre_gate_tlv),
266 SOC_SINGLE("ALC Capture Switch", ES8326_ALC_RECOVERY, 3, 1, 0),
267 SOC_SINGLE_TLV("ALC Capture Recovery Level", ES8326_ALC_LEVEL,
268 0, 4, 0, drc_recovery_tlv),
269 SOC_ENUM("ALC Capture Winsize", alc_winsize),
270 SOC_SINGLE_TLV("ALC Capture Target Level", ES8326_ALC_LEVEL,
271 0, 0x0f, 0, drc_target_tlv),
272
273 SOC_SINGLE_EXT("CROSSTALK1", SND_SOC_NOPM, 0, 31, 0,
274 es8326_crosstalk1_get, es8326_crosstalk1_set),
275 SOC_SINGLE_EXT("CROSSTALK2", SND_SOC_NOPM, 0, 31, 0,
276 es8326_crosstalk2_get, es8326_crosstalk2_set),
277 SOC_SINGLE_EXT("HPL Volume", SND_SOC_NOPM, 0, 5, 0,
278 es8326_hplvol_get, es8326_hplvol_set),
279 SOC_SINGLE_EXT("HPR Volume", SND_SOC_NOPM, 0, 5, 0,
280 es8326_hprvol_get, es8326_hprvol_set),
281
282 SOC_SINGLE_TLV("HPL Playback Volume", ES8326_DACL_VOL, 0, 0xbf, 0, dac_vol_tlv),
283 SOC_SINGLE_TLV("HPR Playback Volume", ES8326_DACR_VOL, 0, 0xbf, 0, dac_vol_tlv),
284 SOC_SINGLE_TLV("SPKL Playback Volume", ES8326_SPKL_VOL, 0, 0xbf, 0, dac_vol_tlv),
285 SOC_SINGLE_TLV("SPKR Playback Volume", ES8326_SPKR_VOL, 0, 0xbf, 0, dac_vol_tlv),
286
287 SOC_ENUM("HPVol SPKVol Switch", hpvol_spkvol_switch),
288 };
289
290 static const struct snd_soc_dapm_widget es8326_dapm_widgets[] = {
291 SND_SOC_DAPM_INPUT("MIC1"),
292 SND_SOC_DAPM_INPUT("MIC2"),
293 SND_SOC_DAPM_INPUT("MIC3"),
294 SND_SOC_DAPM_INPUT("MIC4"),
295
296 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
297 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
298
299 /* Digital Interface */
300 SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 0, SND_SOC_NOPM, 0, 0),
301 SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0, SND_SOC_NOPM, 0, 0),
302
303 /* Analog Power Supply*/
304 SND_SOC_DAPM_DAC("Right DAC", NULL, ES8326_ANA_PDN, 0, 1),
305 SND_SOC_DAPM_DAC("Left DAC", NULL, ES8326_ANA_PDN, 1, 1),
306 SND_SOC_DAPM_SUPPLY("MICBIAS1", ES8326_ANA_MICBIAS, 2, 0, NULL, 0),
307 SND_SOC_DAPM_SUPPLY("MICBIAS2", ES8326_ANA_MICBIAS, 3, 0, NULL, 0),
308
309 SND_SOC_DAPM_PGA("LHPMIX", ES8326_DAC2HPMIX, 7, 0, NULL, 0),
310 SND_SOC_DAPM_PGA("RHPMIX", ES8326_DAC2HPMIX, 3, 0, NULL, 0),
311
312 SND_SOC_DAPM_OUTPUT("HPOL"),
313 SND_SOC_DAPM_OUTPUT("HPOR"),
314 };
315
316 static const struct snd_soc_dapm_route es8326_dapm_routes[] = {
317 {"ADC L", NULL, "MIC1"},
318 {"ADC R", NULL, "MIC2"},
319 {"ADC L", NULL, "MIC3"},
320 {"ADC R", NULL, "MIC4"},
321
322 {"I2S OUT", NULL, "ADC L"},
323 {"I2S OUT", NULL, "ADC R"},
324
325 {"Right DAC", NULL, "I2S IN"},
326 {"Left DAC", NULL, "I2S IN"},
327
328 {"LHPMIX", NULL, "Left DAC"},
329 {"RHPMIX", NULL, "Right DAC"},
330
331 {"HPOL", NULL, "LHPMIX"},
332 {"HPOR", NULL, "RHPMIX"},
333 };
334
es8326_volatile_register(struct device * dev,unsigned int reg)335 static bool es8326_volatile_register(struct device *dev, unsigned int reg)
336 {
337 switch (reg) {
338 case ES8326_HPL_OFFSET_INI:
339 case ES8326_HPR_OFFSET_INI:
340 case ES8326_HPDET_STA:
341 case ES8326_CTIA_OMTP_STA:
342 case ES8326_CSM_MUTE_STA:
343 return true;
344 default:
345 return false;
346 }
347 }
348
es8326_writeable_register(struct device * dev,unsigned int reg)349 static bool es8326_writeable_register(struct device *dev, unsigned int reg)
350 {
351 switch (reg) {
352 case ES8326_BIAS_SW1:
353 case ES8326_BIAS_SW2:
354 case ES8326_BIAS_SW3:
355 case ES8326_BIAS_SW4:
356 case ES8326_ADC_HPFS1:
357 case ES8326_ADC_HPFS2:
358 return false;
359 default:
360 return true;
361 }
362 }
363
364 static const struct regmap_config es8326_regmap_config = {
365 .reg_bits = 8,
366 .val_bits = 8,
367 .max_register = 0xff,
368 .use_single_read = true,
369 .use_single_write = true,
370 .volatile_reg = es8326_volatile_register,
371 .writeable_reg = es8326_writeable_register,
372 .cache_type = REGCACHE_RBTREE,
373 };
374
375 struct _coeff_div {
376 u16 fs;
377 u32 rate;
378 u32 mclk;
379 u8 reg4;
380 u8 reg5;
381 u8 reg6;
382 u8 reg7;
383 u8 reg8;
384 u8 reg9;
385 u8 rega;
386 u8 regb;
387 };
388
389 /* codec hifi mclk clock divider coefficients */
390 /* {ratio, LRCK, MCLK, REG04, REG05, REG06, REG07, REG08, REG09, REG10, REG11} */
391 static const struct _coeff_div coeff_div_v0[] = {
392 {64, 8000, 512000, 0x60, 0x01, 0x0F, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
393 {64, 16000, 1024000, 0x20, 0x00, 0x33, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
394 {64, 44100, 2822400, 0xE0, 0x00, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
395 {64, 48000, 3072000, 0xE0, 0x00, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
396 {128, 8000, 1024000, 0x60, 0x00, 0x33, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
397 {128, 16000, 2048000, 0x20, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
398 {128, 44100, 5644800, 0xE0, 0x01, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
399 {128, 48000, 6144000, 0xE0, 0x01, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
400
401 {192, 32000, 6144000, 0xE0, 0x02, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
402 {256, 8000, 2048000, 0x60, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
403 {256, 16000, 4096000, 0x20, 0x01, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
404 {256, 44100, 11289600, 0xE0, 0x00, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
405 {256, 48000, 12288000, 0xE0, 0x00, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
406 {384, 32000, 12288000, 0xE0, 0x05, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
407 {400, 48000, 19200000, 0xE9, 0x04, 0x0F, 0x6d, 0x4A, 0x0A, 0x1F, 0x1F},
408
409 {500, 48000, 24000000, 0xF8, 0x04, 0x3F, 0x6D, 0x4A, 0x0A, 0x1F, 0x1F},
410 {512, 8000, 4096000, 0x60, 0x01, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
411 {512, 16000, 8192000, 0x20, 0x00, 0x30, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
412 {512, 44100, 22579200, 0xE0, 0x00, 0x00, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
413 {512, 48000, 24576000, 0xE0, 0x00, 0x00, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
414 {768, 32000, 24576000, 0xE0, 0x02, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F},
415 {1024, 8000, 8192000, 0x60, 0x00, 0x30, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
416 {1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
417 };
418
419 static const struct _coeff_div coeff_div_v3[] = {
420 {32, 8000, 256000, 0x60, 0x00, 0x0F, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
421 {32, 16000, 512000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x3F},
422 {32, 44100, 1411200, 0x00, 0x00, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F},
423 {32, 48000, 1536000, 0x00, 0x00, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F},
424 {36, 8000, 288000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x23, 0x47},
425 {36, 16000, 576000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x23, 0x47},
426 {48, 8000, 384000, 0x60, 0x02, 0x1F, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
427 {48, 16000, 768000, 0x20, 0x02, 0x0F, 0x75, 0x8A, 0x1B, 0x1F, 0x3F},
428 {48, 48000, 2304000, 0x00, 0x02, 0x0D, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F},
429
430 {64, 8000, 512000, 0x60, 0x00, 0x35, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
431 {64, 16000, 1024000, 0x20, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x3F},
432 {64, 44100, 2822400, 0xE0, 0x00, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
433 {64, 48000, 3072000, 0xE0, 0x00, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
434 {72, 8000, 576000, 0x20, 0x00, 0x13, 0x35, 0x8A, 0x1B, 0x23, 0x47},
435 {72, 16000, 1152000, 0x20, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x23, 0x47},
436 {96, 8000, 768000, 0x60, 0x02, 0x1D, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
437 {96, 16000, 1536000, 0x20, 0x02, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x3F},
438 {100, 48000, 4800000, 0x04, 0x04, 0x3F, 0x6D, 0xB8, 0x08, 0x4f, 0x1f},
439 {125, 48000, 6000000, 0x04, 0x04, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27},
440
441 {128, 8000, 1024000, 0x60, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
442 {128, 16000, 2048000, 0x20, 0x00, 0x31, 0x35, 0x08, 0x19, 0x1F, 0x3F},
443 {128, 44100, 5644800, 0xE0, 0x00, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F},
444 {128, 48000, 6144000, 0xE0, 0x00, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F},
445 {144, 8000, 1152000, 0x20, 0x00, 0x03, 0x35, 0x8A, 0x1B, 0x23, 0x47},
446 {144, 16000, 2304000, 0x20, 0x00, 0x11, 0x35, 0x8A, 0x1B, 0x23, 0x47},
447 {192, 8000, 1536000, 0x60, 0x02, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
448 {192, 32000, 6144000, 0xE0, 0x02, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
449 {192, 16000, 3072000, 0x20, 0x02, 0x05, 0x75, 0xCA, 0x1B, 0x1F, 0x3F},
450
451 {200, 48000, 9600000, 0x04, 0x04, 0x0F, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
452 {250, 48000, 12000000, 0x04, 0x04, 0x0F, 0x2D, 0xCA, 0x0A, 0x27, 0x27},
453 {256, 8000, 2048000, 0x60, 0x00, 0x31, 0x35, 0x08, 0x19, 0x1F, 0x7F},
454 {256, 16000, 4096000, 0x20, 0x00, 0x01, 0x35, 0x08, 0x19, 0x1F, 0x3F},
455 {256, 44100, 11289600, 0xE0, 0x01, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F},
456 {256, 48000, 12288000, 0xE0, 0x01, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F},
457 {288, 8000, 2304000, 0x20, 0x00, 0x01, 0x35, 0x8A, 0x1B, 0x23, 0x47},
458 {384, 8000, 3072000, 0x60, 0x02, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x7F},
459 {384, 16000, 6144000, 0x20, 0x02, 0x03, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
460 {384, 32000, 12288000, 0xE0, 0x02, 0x01, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
461 {384, 48000, 18432000, 0x00, 0x02, 0x01, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F},
462
463 {400, 48000, 19200000, 0xE4, 0x04, 0x35, 0x6d, 0xCA, 0x0A, 0x1F, 0x1F},
464 {500, 48000, 24000000, 0xF8, 0x04, 0x3F, 0x6D, 0xCA, 0x0A, 0x1F, 0x1F},
465 {512, 8000, 4096000, 0x60, 0x00, 0x01, 0x08, 0x19, 0x1B, 0x1F, 0x7F},
466 {512, 16000, 8192000, 0x20, 0x00, 0x30, 0x35, 0x08, 0x19, 0x1F, 0x3F},
467 {512, 44100, 22579200, 0xE0, 0x00, 0x00, 0x2D, 0x48, 0x08, 0x1F, 0x1F},
468 {512, 48000, 24576000, 0xE0, 0x00, 0x00, 0x2D, 0x48, 0x08, 0x1F, 0x1F},
469 {768, 8000, 6144000, 0x60, 0x02, 0x11, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
470 {768, 16000, 12288000, 0x20, 0x02, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
471 {768, 32000, 24576000, 0xE0, 0x02, 0x30, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F},
472 {800, 48000, 38400000, 0x00, 0x18, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F},
473
474 {1024, 8000, 8192000, 0x60, 0x00, 0x30, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
475 {1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
476 {1152, 16000, 18432000, 0x20, 0x08, 0x11, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
477 {1536, 8000, 12288000, 0x60, 0x02, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
478 {1536, 16000, 24576000, 0x20, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x3F},
479 {1625, 8000, 13000000, 0x0C, 0x18, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27},
480 {1625, 16000, 26000000, 0x0C, 0x18, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27},
481 {2048, 8000, 16384000, 0x60, 0x00, 0x00, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
482 {2304, 8000, 18432000, 0x40, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x5F},
483 {3072, 8000, 24576000, 0x60, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x7F},
484 {3250, 8000, 26000000, 0x0C, 0x18, 0x0F, 0x2D, 0x8A, 0x0A, 0x27, 0x27},
485 };
486
get_coeff(int mclk,int rate,int array,const struct _coeff_div * coeff_div)487 static inline int get_coeff(int mclk, int rate, int array,
488 const struct _coeff_div *coeff_div)
489 {
490 int i;
491
492 for (i = 0; i < array; i++) {
493 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
494 return i;
495 }
496
497 return -EINVAL;
498 }
499
es8326_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)500 static int es8326_set_dai_sysclk(struct snd_soc_dai *codec_dai,
501 int clk_id, unsigned int freq, int dir)
502 {
503 struct snd_soc_component *codec = codec_dai->component;
504 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec);
505
506 es8326->sysclk = freq;
507
508 return 0;
509 }
510
es8326_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)511 static int es8326_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
512 {
513 struct snd_soc_component *component = codec_dai->component;
514 u8 iface = 0;
515
516 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
517 case SND_SOC_DAIFMT_CBC_CFP:
518 snd_soc_component_update_bits(component, ES8326_RESET,
519 ES8326_MASTER_MODE_EN, ES8326_MASTER_MODE_EN);
520 break;
521 case SND_SOC_DAIFMT_CBC_CFC:
522 break;
523 default:
524 return -EINVAL;
525 }
526
527 /* interface format */
528 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
529 case SND_SOC_DAIFMT_I2S:
530 break;
531 case SND_SOC_DAIFMT_RIGHT_J:
532 dev_err(component->dev, "Codec driver does not support right justified\n");
533 return -EINVAL;
534 case SND_SOC_DAIFMT_LEFT_J:
535 iface |= ES8326_DAIFMT_LEFT_J;
536 break;
537 case SND_SOC_DAIFMT_DSP_A:
538 iface |= ES8326_DAIFMT_DSP_A;
539 break;
540 case SND_SOC_DAIFMT_DSP_B:
541 iface |= ES8326_DAIFMT_DSP_B;
542 break;
543 default:
544 return -EINVAL;
545 }
546
547 snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DAIFMT_MASK, iface);
548
549 return 0;
550 }
551
es8326_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)552 static int es8326_pcm_hw_params(struct snd_pcm_substream *substream,
553 struct snd_pcm_hw_params *params,
554 struct snd_soc_dai *dai)
555 {
556 struct snd_soc_component *component = dai->component;
557 const struct _coeff_div *coeff_div;
558 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
559 u8 srate = 0;
560 int coeff, array;
561
562 if (es8326->version == 0) {
563 coeff_div = coeff_div_v0;
564 array = ARRAY_SIZE(coeff_div_v0);
565 } else {
566 coeff_div = coeff_div_v3;
567 array = ARRAY_SIZE(coeff_div_v3);
568 }
569 coeff = get_coeff(es8326->sysclk, params_rate(params), array, coeff_div);
570 /* bit size */
571 switch (params_format(params)) {
572 case SNDRV_PCM_FORMAT_S16_LE:
573 srate |= ES8326_S16_LE;
574 break;
575 case SNDRV_PCM_FORMAT_S20_3LE:
576 srate |= ES8326_S20_3_LE;
577 break;
578 case SNDRV_PCM_FORMAT_S18_3LE:
579 srate |= ES8326_S18_LE;
580 break;
581 case SNDRV_PCM_FORMAT_S24_LE:
582 srate |= ES8326_S24_LE;
583 break;
584 case SNDRV_PCM_FORMAT_S32_LE:
585 srate |= ES8326_S32_LE;
586 break;
587 default:
588 return -EINVAL;
589 }
590
591 /* set iface & srate */
592 snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DATA_LEN_MASK, srate);
593
594 if (coeff >= 0) {
595 regmap_write(es8326->regmap, ES8326_CLK_DIV1,
596 coeff_div[coeff].reg4);
597 regmap_write(es8326->regmap, ES8326_CLK_DIV2,
598 coeff_div[coeff].reg5);
599 regmap_write(es8326->regmap, ES8326_CLK_DLL,
600 coeff_div[coeff].reg6);
601 regmap_write(es8326->regmap, ES8326_CLK_MUX,
602 coeff_div[coeff].reg7);
603 regmap_write(es8326->regmap, ES8326_CLK_ADC_SEL,
604 coeff_div[coeff].reg8);
605 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL,
606 coeff_div[coeff].reg9);
607 regmap_write(es8326->regmap, ES8326_CLK_ADC_OSR,
608 coeff_div[coeff].rega);
609 regmap_write(es8326->regmap, ES8326_CLK_DAC_OSR,
610 coeff_div[coeff].regb);
611 } else {
612 dev_warn(component->dev, "Clock coefficients do not match");
613 }
614
615 return 0;
616 }
617
es8326_mute(struct snd_soc_dai * dai,int mute,int direction)618 static int es8326_mute(struct snd_soc_dai *dai, int mute, int direction)
619 {
620 struct snd_soc_component *component = dai->component;
621 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
622 unsigned int offset_l, offset_r;
623
624 if (mute) {
625 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
626 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
627 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE,
628 ES8326_MUTE_MASK, ES8326_MUTE);
629 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF,
630 0x30, 0x00);
631 } else {
632 cancel_delayed_work_sync(&es8326->capture_pop_work);
633 regmap_update_bits(es8326->regmap, ES8326_ADC_MUTE,
634 0x0F, 0x0F);
635 if (es8326->version > ES8326_VERSION_B) {
636 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40);
637 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x30);
638 }
639 }
640 } else {
641 if (!es8326->calibrated) {
642 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_FORCE_CAL);
643 msleep(30);
644 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
645 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l);
646 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r);
647 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c);
648 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l);
649 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r);
650 es8326->calibrated = true;
651 }
652 regmap_update_bits(es8326->regmap, ES8326_CLK_INV, 0xc0, 0x00);
653 regmap_update_bits(es8326->regmap, ES8326_CLK_MUX, 0x80, 0x00);
654 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
655 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x01);
656 usleep_range(1000, 5000);
657 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x00);
658 usleep_range(1000, 5000);
659 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x30, 0x20);
660 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x30, 0x30);
661 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1);
662 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_ON);
663 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE,
664 ES8326_MUTE_MASK, ~(ES8326_MUTE));
665 } else {
666 msleep(300);
667 if (es8326->version > ES8326_VERSION_B) {
668 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x70);
669 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x00);
670 }
671
672 queue_delayed_work(system_dfl_wq, &es8326->capture_pop_work,
673 msecs_to_jiffies(40));
674 }
675 }
676 return 0;
677 }
678
es8326_set_bias_level(struct snd_soc_component * codec,enum snd_soc_bias_level level)679 static int es8326_set_bias_level(struct snd_soc_component *codec,
680 enum snd_soc_bias_level level)
681 {
682 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec);
683 int ret;
684
685 switch (level) {
686 case SND_SOC_BIAS_ON:
687 ret = clk_prepare_enable(es8326->mclk);
688 if (ret)
689 return ret;
690
691 regmap_update_bits(es8326->regmap, ES8326_RESET, 0x02, 0x02);
692 usleep_range(5000, 10000);
693 regmap_write(es8326->regmap, ES8326_INTOUT_IO, es8326->interrupt_clk);
694 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO,
695 (ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT));
696 regmap_write(es8326->regmap, ES8326_PGA_PDN, 0x40);
697 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00);
698 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x20);
699 regmap_update_bits(es8326->regmap, ES8326_RESET, 0x02, 0x00);
700 if (es8326->version > ES8326_VERSION_B) {
701 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40);
702 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x30);
703 }
704 break;
705 case SND_SOC_BIAS_PREPARE:
706 break;
707 case SND_SOC_BIAS_STANDBY:
708 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b);
709 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x00);
710 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, ES8326_IO_INPUT);
711 if (es8326->version > ES8326_VERSION_B) {
712 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40);
713 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x10);
714 }
715 regmap_update_bits(es8326->regmap, ES8326_CLK_INV, 0xc0, 0xc0);
716 regmap_update_bits(es8326->regmap, ES8326_CLK_MUX, 0x80, 0x80);
717 break;
718 case SND_SOC_BIAS_OFF:
719 clk_disable_unprepare(es8326->mclk);
720 break;
721 }
722
723 return 0;
724 }
725
726 #define es8326_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
727 SNDRV_PCM_FMTBIT_S24_LE)
728
729 static const struct snd_soc_dai_ops es8326_ops = {
730 .hw_params = es8326_pcm_hw_params,
731 .set_fmt = es8326_set_dai_fmt,
732 .set_sysclk = es8326_set_dai_sysclk,
733 .mute_stream = es8326_mute,
734 .no_capture_mute = 0,
735 };
736
737 static struct snd_soc_dai_driver es8326_dai = {
738 .name = "ES8326 HiFi",
739 .playback = {
740 .stream_name = "Playback",
741 .channels_min = 1,
742 .channels_max = 2,
743 .rates = SNDRV_PCM_RATE_8000_48000,
744 .formats = es8326_FORMATS,
745 },
746 .capture = {
747 .stream_name = "Capture",
748 .channels_min = 1,
749 .channels_max = 2,
750 .rates = SNDRV_PCM_RATE_8000_48000,
751 .formats = es8326_FORMATS,
752 },
753 .ops = &es8326_ops,
754 .symmetric_rate = 1,
755 };
756
es8326_enable_micbias(struct snd_soc_component * component)757 static void es8326_enable_micbias(struct snd_soc_component *component)
758 {
759 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
760
761 snd_soc_dapm_mutex_lock(dapm);
762 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS1");
763 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS2");
764 snd_soc_dapm_sync_unlocked(dapm);
765 snd_soc_dapm_mutex_unlock(dapm);
766 }
767
es8326_disable_micbias(struct snd_soc_component * component)768 static void es8326_disable_micbias(struct snd_soc_component *component)
769 {
770 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
771
772 snd_soc_dapm_mutex_lock(dapm);
773 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS1");
774 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS2");
775 snd_soc_dapm_sync_unlocked(dapm);
776 snd_soc_dapm_mutex_unlock(dapm);
777 }
778
es8326_capture_pop_handler(struct work_struct * work)779 static void es8326_capture_pop_handler(struct work_struct *work)
780 {
781 struct es8326_priv *es8326 =
782 container_of(work, struct es8326_priv, capture_pop_work.work);
783
784 regmap_update_bits(es8326->regmap, ES8326_ADC_MUTE,
785 0x0F, 0x00);
786 }
787
788 /*
789 * For button detection, set the following in soundcard
790 * snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
791 * snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
792 * snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
793 */
es8326_jack_button_handler(struct work_struct * work)794 static void es8326_jack_button_handler(struct work_struct *work)
795 {
796 struct es8326_priv *es8326 =
797 container_of(work, struct es8326_priv, button_press_work.work);
798 struct snd_soc_component *comp = es8326->component;
799 unsigned int iface;
800 static int button_to_report, press_count;
801 static int prev_button, cur_button;
802
803 if (!(es8326->jack->status & SND_JACK_HEADSET)) /* Jack unplugged */
804 return;
805
806 guard(mutex)(&es8326->lock);
807 iface = snd_soc_component_read(comp, ES8326_HPDET_STA);
808 switch (iface) {
809 case 0x93:
810 /* pause button detected */
811 cur_button = SND_JACK_BTN_0;
812 break;
813 case 0x6f:
814 case 0x4b:
815 /* button volume up */
816 if ((iface == 0x6f) && (es8326->version > ES8326_VERSION_B))
817 cur_button = SND_JACK_BTN_0;
818 else
819 cur_button = SND_JACK_BTN_1;
820 break;
821 case 0x27:
822 /* button volume down */
823 cur_button = SND_JACK_BTN_2;
824 break;
825 case 0x1e:
826 case 0xe2:
827 /* button released or not pressed */
828 cur_button = 0;
829 break;
830 default:
831 break;
832 }
833
834 if ((prev_button == cur_button) && (cur_button != 0)) {
835 press_count++;
836 if (press_count > 3) {
837 /* report a press every 120ms */
838 snd_soc_jack_report(es8326->jack, cur_button,
839 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2);
840 press_count = 0;
841 }
842 button_to_report = cur_button;
843 queue_delayed_work(system_dfl_wq, &es8326->button_press_work,
844 msecs_to_jiffies(35));
845 } else if (prev_button != cur_button) {
846 /* mismatch, detect again */
847 prev_button = cur_button;
848 queue_delayed_work(system_dfl_wq, &es8326->button_press_work,
849 msecs_to_jiffies(35));
850 } else {
851 /* released or no pressed */
852 if (button_to_report != 0) {
853 snd_soc_jack_report(es8326->jack, button_to_report,
854 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2);
855 snd_soc_jack_report(es8326->jack, 0,
856 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2);
857 button_to_report = 0;
858 }
859 es8326_disable_micbias(es8326->component);
860 }
861 }
862
es8326_jack_detect_handler(struct work_struct * work)863 static void es8326_jack_detect_handler(struct work_struct *work)
864 {
865 struct es8326_priv *es8326 =
866 container_of(work, struct es8326_priv, jack_detect_work.work);
867 struct snd_soc_component *comp = es8326->component;
868 unsigned int iface;
869
870 guard(mutex)(&es8326->lock);
871 iface = snd_soc_component_read(comp, ES8326_HPDET_STA);
872 dev_dbg(comp->dev, "gpio flag %#04x", iface);
873
874 if ((es8326->jack_remove_retry == 1) && (es8326->version < ES8326_VERSION_B)) {
875 if (iface & ES8326_HPINSERT_FLAG)
876 es8326->jack_remove_retry = 2;
877 else
878 es8326->jack_remove_retry = 0;
879
880 dev_dbg(comp->dev, "remove event check, set HPJACK_POL normal, cnt = %d\n",
881 es8326->jack_remove_retry);
882 /*
883 * Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event
884 */
885 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE,
886 ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ?
887 ~es8326->jack_pol : es8326->jack_pol));
888 return;
889 }
890
891 if ((iface & ES8326_HPINSERT_FLAG) == 0) {
892 /* Jack unplugged or spurious IRQ */
893 dev_dbg(comp->dev, "No headset detected\n");
894 es8326_disable_micbias(es8326->component);
895 if (es8326->jack->status & SND_JACK_HEADPHONE) {
896 dev_dbg(comp->dev, "Report hp remove event\n");
897 snd_soc_jack_report(es8326->jack, 0,
898 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2);
899 snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET);
900 /* mute adc when mic path switch */
901 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x44);
902 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x66);
903 }
904 es8326->hp = 0;
905 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01);
906 regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x0a);
907 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x0f, 0x03);
908 regmap_write(es8326->regmap, ES8326_INT_SOURCE, ES8326_INT_SRC_PIN9);
909 /*
910 * Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event
911 */
912 if ((es8326->jack_remove_retry == 0) && (es8326->version < ES8326_VERSION_B)) {
913 es8326->jack_remove_retry = 1;
914 dev_dbg(comp->dev, "remove event check, invert HPJACK_POL, cnt = %d\n",
915 es8326->jack_remove_retry);
916 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE,
917 ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ?
918 es8326->jack_pol : ~es8326->jack_pol));
919
920 } else {
921 es8326->jack_remove_retry = 0;
922 }
923 } else if ((iface & ES8326_HPINSERT_FLAG) == ES8326_HPINSERT_FLAG) {
924 es8326->jack_remove_retry = 0;
925 if (es8326->hp == 0) {
926 dev_dbg(comp->dev, "First insert, start OMTP/CTIA type check\n");
927 /*
928 * set auto-check mode, then restart jack_detect_work after 400ms.
929 * Don't report jack status.
930 */
931 regmap_write(es8326->regmap, ES8326_INT_SOURCE, 0x00);
932 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01);
933 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x10, 0x00);
934 usleep_range(50000, 70000);
935 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00);
936 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x10, 0x10);
937 usleep_range(50000, 70000);
938 regmap_write(es8326->regmap, ES8326_INT_SOURCE,
939 (ES8326_INT_SRC_PIN9 | ES8326_INT_SRC_BUTTON));
940 regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x1f);
941 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x0f, 0x0d);
942 queue_delayed_work(system_dfl_wq, &es8326->jack_detect_work,
943 msecs_to_jiffies(400));
944 es8326->hp = 1;
945 return;
946 }
947 if (es8326->jack->status & SND_JACK_HEADSET) {
948 /* detect button */
949 dev_dbg(comp->dev, "button pressed\n");
950 regmap_write(es8326->regmap, ES8326_INT_SOURCE,
951 (ES8326_INT_SRC_PIN9 | ES8326_INT_SRC_BUTTON));
952 es8326_enable_micbias(es8326->component);
953 queue_delayed_work(system_dfl_wq, &es8326->button_press_work, 10);
954 return;
955 }
956 if ((iface & ES8326_HPBUTTON_FLAG) == 0x01) {
957 dev_dbg(comp->dev, "Headphone detected\n");
958 snd_soc_jack_report(es8326->jack,
959 SND_JACK_HEADPHONE, SND_JACK_HEADSET);
960 } else {
961 dev_dbg(comp->dev, "Headset detected\n");
962 snd_soc_jack_report(es8326->jack,
963 SND_JACK_HEADSET, SND_JACK_HEADSET);
964 regmap_update_bits(es8326->regmap, ES8326_PGA_PDN,
965 0x08, 0x08);
966 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x00);
967 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x00);
968 regmap_update_bits(es8326->regmap, ES8326_PGA_PDN,
969 0x08, 0x00);
970 usleep_range(10000, 15000);
971 }
972 }
973 }
974
es8326_irq(int irq,void * dev_id)975 static irqreturn_t es8326_irq(int irq, void *dev_id)
976 {
977 struct es8326_priv *es8326 = dev_id;
978
979 if (!es8326->jack)
980 goto out;
981
982 if (es8326->jack->status & SND_JACK_HEADSET)
983 queue_delayed_work(system_dfl_wq, &es8326->jack_detect_work,
984 msecs_to_jiffies(10));
985 else
986 queue_delayed_work(system_dfl_wq, &es8326->jack_detect_work,
987 msecs_to_jiffies(300));
988
989 out:
990 return IRQ_HANDLED;
991 }
992
es8326_calibrate(struct snd_soc_component * component)993 static int es8326_calibrate(struct snd_soc_component *component)
994 {
995 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
996 unsigned int reg;
997 unsigned int offset_l, offset_r;
998
999 regmap_read(es8326->regmap, ES8326_CHIP_VERSION, ®);
1000 es8326->version = reg;
1001
1002 if ((es8326->version >= ES8326_VERSION_B) && (es8326->calibrated == false)) {
1003 dev_dbg(component->dev, "ES8326_VERSION_B, calibrating\n");
1004 regmap_write(es8326->regmap, ES8326_CLK_INV, 0xc0);
1005 regmap_write(es8326->regmap, ES8326_CLK_DIV1, 0x03);
1006 regmap_write(es8326->regmap, ES8326_CLK_DLL, 0x30);
1007 regmap_write(es8326->regmap, ES8326_CLK_MUX, 0xed);
1008 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL, 0x08);
1009 regmap_write(es8326->regmap, ES8326_CLK_TRI, 0xc1);
1010 regmap_write(es8326->regmap, ES8326_DAC_MUTE, 0x03);
1011 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7f);
1012 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x23);
1013 regmap_write(es8326->regmap, ES8326_DAC2HPMIX, 0x88);
1014 usleep_range(15000, 20000);
1015 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c);
1016 usleep_range(15000, 20000);
1017 regmap_write(es8326->regmap, ES8326_RESET, 0xc0);
1018 usleep_range(15000, 20000);
1019
1020 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, ES8326_HP_OFF);
1021 regmap_read(es8326->regmap, ES8326_CSM_MUTE_STA, ®);
1022 if ((reg & 0xf0) != 0x40)
1023 msleep(50);
1024
1025 regmap_write(es8326->regmap, ES8326_HP_CAL, 0xd4);
1026 msleep(200);
1027 regmap_write(es8326->regmap, ES8326_HP_CAL, 0x4d);
1028 msleep(200);
1029 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
1030 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l);
1031 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r);
1032 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c);
1033 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l);
1034 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r);
1035 regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00);
1036
1037 es8326->calibrated = true;
1038 }
1039
1040 return 0;
1041 }
1042
es8326_init(struct snd_soc_component * component)1043 static void es8326_init(struct snd_soc_component *component)
1044 {
1045 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
1046
1047 regmap_write(es8326->regmap, ES8326_RESET, 0x1f);
1048 regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x3E);
1049 regmap_write(es8326->regmap, ES8326_ANA_LP, 0xf0);
1050 usleep_range(10000, 15000);
1051 regmap_write(es8326->regmap, ES8326_HPJACK_TIMER, 0xd9);
1052 regmap_write(es8326->regmap, ES8326_ANA_MICBIAS, 0xd8);
1053 /* set headphone default type and detect pin */
1054 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x83);
1055 regmap_write(es8326->regmap, ES8326_CLK_RESAMPLE, 0x05);
1056
1057 /* set internal oscillator as clock source of headpone cp */
1058 regmap_write(es8326->regmap, ES8326_CLK_DIV_CPC, 0x89);
1059 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_ON);
1060 /* clock manager reset release */
1061 regmap_write(es8326->regmap, ES8326_RESET, 0x17);
1062 /* set headphone detection as half scan mode */
1063 regmap_write(es8326->regmap, ES8326_HP_MISC, 0x3d);
1064 regmap_write(es8326->regmap, ES8326_PULLUP_CTL, 0x00);
1065
1066 /* enable headphone driver */
1067 regmap_write(es8326->regmap, ES8326_HP_VOL, 0xc4);
1068 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa7);
1069 usleep_range(2000, 5000);
1070 regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0x23);
1071 regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0x33);
1072 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1);
1073
1074 regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00);
1075 regmap_write(es8326->regmap, ES8326_CLK_VMIDS1, 0xc4);
1076 regmap_write(es8326->regmap, ES8326_CLK_VMIDS2, 0x81);
1077 regmap_write(es8326->regmap, ES8326_CLK_CAL_TIME, 0x00);
1078 /* calibrate for B version */
1079 es8326_calibrate(component);
1080 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, 0xaa);
1081 regmap_write(es8326->regmap, ES8326_DAC_RAMPRATE, 0x00);
1082 /* turn off headphone out */
1083 regmap_write(es8326->regmap, ES8326_HP_CAL, 0x00);
1084 /* set ADC and DAC in low power mode */
1085 regmap_write(es8326->regmap, ES8326_ANA_LP, 0xf0);
1086
1087 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7F);
1088 /* select vdda as micbias source */
1089 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x03);
1090 /* set dac dsmclip = 1 */
1091 regmap_write(es8326->regmap, ES8326_DAC_DSM, 0x08);
1092 regmap_write(es8326->regmap, ES8326_DAC_VPPSCALE, 0x15);
1093
1094 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x80 |
1095 ((es8326->version >= ES8326_VERSION_B) ?
1096 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol) :
1097 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol | 0x04)));
1098 usleep_range(5000, 10000);
1099 es8326_enable_micbias(es8326->component);
1100 usleep_range(50000, 70000);
1101 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00);
1102 regmap_write(es8326->regmap, ES8326_INTOUT_IO,
1103 es8326->interrupt_clk);
1104 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, ES8326_IO_INPUT);
1105 regmap_write(es8326->regmap, ES8326_SDINOUT23_IO, ES8326_IO_INPUT);
1106
1107 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00);
1108 regmap_write(es8326->regmap, ES8326_RESET, ES8326_CSM_ON);
1109 regmap_update_bits(es8326->regmap, ES8326_PGAGAIN, ES8326_MIC_SEL_MASK,
1110 ES8326_MIC1_SEL);
1111
1112 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, ES8326_MUTE_MASK,
1113 ES8326_MUTE);
1114
1115 regmap_write(es8326->regmap, ES8326_ADC_MUTE, 0x0f);
1116 regmap_write(es8326->regmap, ES8326_CLK_DIV_LRCK, 0xff);
1117 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x44);
1118 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x66);
1119 es8326_disable_micbias(es8326->component);
1120 if (es8326->version > ES8326_VERSION_B) {
1121 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x73, 0x10);
1122 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40);
1123 }
1124
1125 msleep(200);
1126 regmap_write(es8326->regmap, ES8326_INT_SOURCE, ES8326_INT_SRC_PIN9);
1127 }
1128
es8326_resume(struct snd_soc_component * component)1129 static int es8326_resume(struct snd_soc_component *component)
1130 {
1131 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
1132 unsigned int reg;
1133
1134 regcache_cache_only(es8326->regmap, false);
1135 regcache_cache_bypass(es8326->regmap, true);
1136 regmap_read(es8326->regmap, ES8326_CLK_RESAMPLE, ®);
1137 regcache_cache_bypass(es8326->regmap, false);
1138 /* reset internal clock state */
1139 if (reg == 0x05)
1140 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_ON);
1141 else
1142 es8326_init(component);
1143
1144 regcache_sync(es8326->regmap);
1145
1146 es8326_irq(es8326->irq, es8326);
1147 return 0;
1148 }
1149
es8326_suspend(struct snd_soc_component * component)1150 static int es8326_suspend(struct snd_soc_component *component)
1151 {
1152 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
1153
1154 cancel_delayed_work_sync(&es8326->jack_detect_work);
1155 cancel_delayed_work_sync(&es8326->capture_pop_work);
1156 es8326_disable_micbias(component);
1157 es8326->calibrated = false;
1158 regmap_write(es8326->regmap, ES8326_CLK_MUX, 0x2d);
1159 regmap_write(es8326->regmap, ES8326_DAC2HPMIX, 0x00);
1160 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b);
1161 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_OFF);
1162 regcache_cache_only(es8326->regmap, true);
1163
1164 /* reset register value to default */
1165 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01);
1166 usleep_range(1000, 3000);
1167 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00);
1168
1169 regcache_mark_dirty(es8326->regmap);
1170 return 0;
1171 }
1172
es8326_probe(struct snd_soc_component * component)1173 static int es8326_probe(struct snd_soc_component *component)
1174 {
1175 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
1176 int ret;
1177
1178 es8326->component = component;
1179 es8326->jd_inverted = device_property_read_bool(component->dev,
1180 "everest,jack-detect-inverted");
1181
1182 ret = device_property_read_u8(component->dev, "everest,jack-pol", &es8326->jack_pol);
1183 if (ret != 0) {
1184 dev_dbg(component->dev, "jack-pol return %d", ret);
1185 es8326->jack_pol = ES8326_HP_TYPE_AUTO;
1186 }
1187 dev_dbg(component->dev, "jack-pol %x", es8326->jack_pol);
1188
1189 ret = device_property_read_u8(component->dev, "everest,interrupt-src",
1190 &es8326->interrupt_src);
1191 if (ret != 0) {
1192 dev_dbg(component->dev, "interrupt-src return %d", ret);
1193 es8326->interrupt_src = ES8326_HP_DET_SRC_PIN9;
1194 }
1195 dev_dbg(component->dev, "interrupt-src %x", es8326->interrupt_src);
1196
1197 ret = device_property_read_u8(component->dev, "everest,interrupt-clk",
1198 &es8326->interrupt_clk);
1199 if (ret != 0) {
1200 dev_dbg(component->dev, "interrupt-clk return %d", ret);
1201 es8326->interrupt_clk = 0x00;
1202 }
1203 dev_dbg(component->dev, "interrupt-clk %x", es8326->interrupt_clk);
1204
1205 es8326_init(component);
1206 return 0;
1207 }
1208
es8326_enable_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * jack)1209 static void es8326_enable_jack_detect(struct snd_soc_component *component,
1210 struct snd_soc_jack *jack)
1211 {
1212 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
1213
1214 scoped_guard(mutex, &es8326->lock) {
1215 if (es8326->jd_inverted)
1216 snd_soc_component_update_bits(component, ES8326_HPDET_TYPE,
1217 ES8326_HP_DET_JACK_POL, ~es8326->jack_pol);
1218 es8326->jack = jack;
1219 }
1220 es8326_irq(es8326->irq, es8326);
1221 }
1222
es8326_disable_jack_detect(struct snd_soc_component * component)1223 static void es8326_disable_jack_detect(struct snd_soc_component *component)
1224 {
1225 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
1226
1227 dev_dbg(component->dev, "Enter into %s\n", __func__);
1228 if (!es8326->jack)
1229 return; /* Already disabled (or never enabled) */
1230 cancel_delayed_work_sync(&es8326->jack_detect_work);
1231
1232 guard(mutex)(&es8326->lock);
1233 if (es8326->jack->status & SND_JACK_MICROPHONE) {
1234 es8326_disable_micbias(component);
1235 snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET);
1236 }
1237 es8326->jack = NULL;
1238 }
1239
es8326_set_jack(struct snd_soc_component * component,struct snd_soc_jack * jack,void * data)1240 static int es8326_set_jack(struct snd_soc_component *component,
1241 struct snd_soc_jack *jack, void *data)
1242 {
1243 if (jack)
1244 es8326_enable_jack_detect(component, jack);
1245 else
1246 es8326_disable_jack_detect(component);
1247
1248 return 0;
1249 }
1250
es8326_remove(struct snd_soc_component * component)1251 static void es8326_remove(struct snd_soc_component *component)
1252 {
1253 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
1254
1255 es8326_disable_jack_detect(component);
1256 es8326_set_bias_level(component, SND_SOC_BIAS_OFF);
1257 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01);
1258 usleep_range(1000, 3000);
1259 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00);
1260 }
1261
1262 static const struct snd_soc_component_driver soc_component_dev_es8326 = {
1263 .probe = es8326_probe,
1264 .remove = es8326_remove,
1265 .resume = es8326_resume,
1266 .suspend = es8326_suspend,
1267 .set_bias_level = es8326_set_bias_level,
1268 .set_jack = es8326_set_jack,
1269 .dapm_widgets = es8326_dapm_widgets,
1270 .num_dapm_widgets = ARRAY_SIZE(es8326_dapm_widgets),
1271 .dapm_routes = es8326_dapm_routes,
1272 .num_dapm_routes = ARRAY_SIZE(es8326_dapm_routes),
1273 .controls = es8326_snd_controls,
1274 .num_controls = ARRAY_SIZE(es8326_snd_controls),
1275 .use_pmdown_time = 1,
1276 .endianness = 1,
1277 };
1278
es8326_i2c_probe(struct i2c_client * i2c)1279 static int es8326_i2c_probe(struct i2c_client *i2c)
1280 {
1281 struct es8326_priv *es8326;
1282 int ret;
1283
1284 es8326 = devm_kzalloc(&i2c->dev, sizeof(struct es8326_priv), GFP_KERNEL);
1285 if (!es8326)
1286 return -ENOMEM;
1287
1288 i2c_set_clientdata(i2c, es8326);
1289 es8326->i2c = i2c;
1290 mutex_init(&es8326->lock);
1291 es8326->regmap = devm_regmap_init_i2c(i2c, &es8326_regmap_config);
1292 if (IS_ERR(es8326->regmap)) {
1293 ret = PTR_ERR(es8326->regmap);
1294 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
1295 return ret;
1296 }
1297
1298 es8326->irq = i2c->irq;
1299 es8326->jack_remove_retry = 0;
1300 es8326->hp = 0;
1301 es8326->hpl_vol = 0x03;
1302 es8326->hpr_vol = 0x03;
1303 INIT_DELAYED_WORK(&es8326->jack_detect_work,
1304 es8326_jack_detect_handler);
1305 INIT_DELAYED_WORK(&es8326->button_press_work,
1306 es8326_jack_button_handler);
1307 INIT_DELAYED_WORK(&es8326->capture_pop_work,
1308 es8326_capture_pop_handler);
1309 /* ES8316 is level-based while ES8326 is edge-based */
1310 ret = devm_request_threaded_irq(&i2c->dev, es8326->irq, NULL, es8326_irq,
1311 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1312 "es8326", es8326);
1313 if (ret) {
1314 dev_warn(&i2c->dev, "Failed to request IRQ: %d: %d\n",
1315 es8326->irq, ret);
1316 es8326->irq = -ENXIO;
1317 }
1318
1319 es8326->mclk = devm_clk_get_optional(&i2c->dev, "mclk");
1320 if (IS_ERR(es8326->mclk)) {
1321 dev_err(&i2c->dev, "unable to get mclk\n");
1322 return PTR_ERR(es8326->mclk);
1323 }
1324 if (!es8326->mclk)
1325 dev_warn(&i2c->dev, "assuming static mclk\n");
1326
1327 ret = clk_prepare_enable(es8326->mclk);
1328 if (ret) {
1329 dev_err(&i2c->dev, "unable to enable mclk\n");
1330 return ret;
1331 }
1332 return devm_snd_soc_register_component(&i2c->dev,
1333 &soc_component_dev_es8326,
1334 &es8326_dai, 1);
1335 }
1336
1337
es8326_i2c_shutdown(struct i2c_client * i2c)1338 static void es8326_i2c_shutdown(struct i2c_client *i2c)
1339 {
1340 struct snd_soc_component *component;
1341 struct es8326_priv *es8326;
1342
1343 es8326 = i2c_get_clientdata(i2c);
1344 component = es8326->component;
1345 dev_dbg(component->dev, "Enter into %s\n", __func__);
1346 cancel_delayed_work_sync(&es8326->jack_detect_work);
1347 cancel_delayed_work_sync(&es8326->button_press_work);
1348
1349 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01);
1350 usleep_range(1000, 3000);
1351 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00);
1352
1353 }
1354
es8326_i2c_remove(struct i2c_client * i2c)1355 static void es8326_i2c_remove(struct i2c_client *i2c)
1356 {
1357 es8326_i2c_shutdown(i2c);
1358 }
1359
1360 static const struct i2c_device_id es8326_i2c_id[] = {
1361 { .name = "es8326" },
1362 { }
1363 };
1364 MODULE_DEVICE_TABLE(i2c, es8326_i2c_id);
1365
1366 #ifdef CONFIG_OF
1367 static const struct of_device_id es8326_of_match[] = {
1368 { .compatible = "everest,es8326", },
1369 {}
1370 };
1371 MODULE_DEVICE_TABLE(of, es8326_of_match);
1372 #endif
1373
1374 #ifdef CONFIG_ACPI
1375 static const struct acpi_device_id es8326_acpi_match[] = {
1376 {"ESSX8326", 0},
1377 {},
1378 };
1379 MODULE_DEVICE_TABLE(acpi, es8326_acpi_match);
1380 #endif
1381
1382 static struct i2c_driver es8326_i2c_driver = {
1383 .driver = {
1384 .name = "es8326",
1385 .acpi_match_table = ACPI_PTR(es8326_acpi_match),
1386 .of_match_table = of_match_ptr(es8326_of_match),
1387 },
1388 .probe = es8326_i2c_probe,
1389 .shutdown = es8326_i2c_shutdown,
1390 .remove = es8326_i2c_remove,
1391 .id_table = es8326_i2c_id,
1392 };
1393 module_i2c_driver(es8326_i2c_driver);
1394
1395 MODULE_DESCRIPTION("ASoC es8326 driver");
1396 MODULE_AUTHOR("David Yang <yangxiaohua@everest-semi.com>");
1397 MODULE_LICENSE("GPL");
1398