1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019 Nuvoton Technology corporation.
3
4 #include <linux/clk.h>
5 #include <linux/device.h>
6 #include <linux/mfd/syscon.h>
7 #include <linux/io.h>
8 #include <linux/iio/iio.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/property.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/spinlock.h>
17 #include <linux/uaccess.h>
18 #include <linux/reset.h>
19
20 struct npcm_adc_info {
21 u32 data_mask;
22 u32 internal_vref;
23 u32 res_bits;
24 };
25
26 struct npcm_adc {
27 bool int_status;
28 u32 adc_sample_hz;
29 struct device *dev;
30 void __iomem *regs;
31 struct clk *adc_clk;
32 wait_queue_head_t wq;
33 struct regulator *vref;
34 struct reset_control *reset;
35 /*
36 * Lock to protect the device state during a potential concurrent
37 * read access from userspace. Reading a raw value requires a sequence
38 * of register writes, then a wait for a event and finally a register
39 * read, during which userspace could issue another read request.
40 * This lock protects a read access from occurring before another one
41 * has finished.
42 */
43 struct mutex lock;
44 const struct npcm_adc_info *data;
45 };
46
47 /* ADC registers */
48 #define NPCM_ADCCON 0x00
49 #define NPCM_ADCDATA 0x04
50
51 /* ADCCON Register Bits */
52 #define NPCM_ADCCON_ADC_INT_EN BIT(21)
53 #define NPCM_ADCCON_REFSEL BIT(19)
54 #define NPCM_ADCCON_ADC_INT_ST BIT(18)
55 #define NPCM_ADCCON_ADC_EN BIT(17)
56 #define NPCM_ADCCON_ADC_RST BIT(16)
57 #define NPCM_ADCCON_ADC_CONV BIT(13)
58
59 #define NPCM_ADCCON_CH_MASK GENMASK(27, 24)
60 #define NPCM_ADCCON_CH(x) ((x) << 24)
61 #define NPCM_ADCCON_DIV_SHIFT 1
62 #define NPCM_ADCCON_DIV_MASK GENMASK(8, 1)
63
64 #define NPCM_ADC_ENABLE (NPCM_ADCCON_ADC_EN | NPCM_ADCCON_ADC_INT_EN)
65
66 /* ADC General Definition */
67 static const struct npcm_adc_info npxm7xx_adc_info = {
68 .data_mask = GENMASK(9, 0),
69 .internal_vref = 2048,
70 .res_bits = 10,
71 };
72
73 static const struct npcm_adc_info npxm8xx_adc_info = {
74 .data_mask = GENMASK(11, 0),
75 .internal_vref = 1229,
76 .res_bits = 12,
77 };
78
79 #define NPCM_ADC_CHAN(ch) { \
80 .type = IIO_VOLTAGE, \
81 .indexed = 1, \
82 .channel = ch, \
83 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
84 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
85 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
86 }
87
88 static const struct iio_chan_spec npcm_adc_iio_channels[] = {
89 NPCM_ADC_CHAN(0),
90 NPCM_ADC_CHAN(1),
91 NPCM_ADC_CHAN(2),
92 NPCM_ADC_CHAN(3),
93 NPCM_ADC_CHAN(4),
94 NPCM_ADC_CHAN(5),
95 NPCM_ADC_CHAN(6),
96 NPCM_ADC_CHAN(7),
97 };
98
npcm_adc_isr(int irq,void * data)99 static irqreturn_t npcm_adc_isr(int irq, void *data)
100 {
101 u32 regtemp;
102 struct iio_dev *indio_dev = data;
103 struct npcm_adc *info = iio_priv(indio_dev);
104
105 regtemp = ioread32(info->regs + NPCM_ADCCON);
106 if (regtemp & NPCM_ADCCON_ADC_INT_ST) {
107 iowrite32(regtemp, info->regs + NPCM_ADCCON);
108 wake_up_interruptible(&info->wq);
109 info->int_status = true;
110 }
111
112 return IRQ_HANDLED;
113 }
114
npcm_adc_read(struct npcm_adc * info,int * val,u8 channel)115 static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel)
116 {
117 int ret;
118 u32 regtemp;
119
120 /* Select ADC channel */
121 regtemp = ioread32(info->regs + NPCM_ADCCON);
122 regtemp &= ~NPCM_ADCCON_CH_MASK;
123 info->int_status = false;
124 iowrite32(regtemp | NPCM_ADCCON_CH(channel) |
125 NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
126
127 ret = wait_event_interruptible_timeout(info->wq, info->int_status,
128 msecs_to_jiffies(10));
129 if (ret == 0) {
130 regtemp = ioread32(info->regs + NPCM_ADCCON);
131 if (regtemp & NPCM_ADCCON_ADC_CONV) {
132 /* if conversion failed - reset ADC module */
133 reset_control_assert(info->reset);
134 msleep(100);
135 reset_control_deassert(info->reset);
136 msleep(100);
137
138 /* Enable ADC and start conversion module */
139 iowrite32(NPCM_ADC_ENABLE | NPCM_ADCCON_ADC_CONV,
140 info->regs + NPCM_ADCCON);
141 dev_err(info->dev, "RESET ADC Complete\n");
142 }
143 return -ETIMEDOUT;
144 }
145 if (ret < 0)
146 return ret;
147
148 *val = ioread32(info->regs + NPCM_ADCDATA);
149 *val &= info->data->data_mask;
150
151 return 0;
152 }
153
npcm_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)154 static int npcm_adc_read_raw(struct iio_dev *indio_dev,
155 struct iio_chan_spec const *chan, int *val,
156 int *val2, long mask)
157 {
158 int ret;
159 int vref_uv;
160 struct npcm_adc *info = iio_priv(indio_dev);
161
162 switch (mask) {
163 case IIO_CHAN_INFO_RAW:
164 mutex_lock(&info->lock);
165 ret = npcm_adc_read(info, val, chan->channel);
166 mutex_unlock(&info->lock);
167 if (ret) {
168 dev_err(info->dev, "NPCM ADC read failed\n");
169 return ret;
170 }
171 return IIO_VAL_INT;
172 case IIO_CHAN_INFO_SCALE:
173 if (!IS_ERR(info->vref)) {
174 vref_uv = regulator_get_voltage(info->vref);
175 *val = vref_uv / 1000;
176 } else {
177 *val = info->data->internal_vref;
178 }
179 *val2 = info->data->res_bits;
180 return IIO_VAL_FRACTIONAL_LOG2;
181 case IIO_CHAN_INFO_SAMP_FREQ:
182 *val = info->adc_sample_hz;
183 return IIO_VAL_INT;
184 default:
185 return -EINVAL;
186 }
187
188 return 0;
189 }
190
191 static const struct iio_info npcm_adc_iio_info = {
192 .read_raw = &npcm_adc_read_raw,
193 };
194
195 static const struct of_device_id npcm_adc_match[] = {
196 { .compatible = "nuvoton,npcm750-adc", .data = &npxm7xx_adc_info},
197 { .compatible = "nuvoton,npcm845-adc", .data = &npxm8xx_adc_info},
198 { }
199 };
200 MODULE_DEVICE_TABLE(of, npcm_adc_match);
201
npcm_adc_probe(struct platform_device * pdev)202 static int npcm_adc_probe(struct platform_device *pdev)
203 {
204 int ret;
205 int irq;
206 u32 div;
207 u32 reg_con;
208 struct npcm_adc *info;
209 struct iio_dev *indio_dev;
210 struct device *dev = &pdev->dev;
211
212 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
213 if (!indio_dev)
214 return -ENOMEM;
215 info = iio_priv(indio_dev);
216
217 info->data = device_get_match_data(dev);
218 if (!info->data)
219 return -EINVAL;
220
221 mutex_init(&info->lock);
222
223 info->dev = &pdev->dev;
224
225 info->regs = devm_platform_ioremap_resource(pdev, 0);
226 if (IS_ERR(info->regs))
227 return PTR_ERR(info->regs);
228
229 info->reset = devm_reset_control_get(&pdev->dev, NULL);
230 if (IS_ERR(info->reset))
231 return PTR_ERR(info->reset);
232
233 info->adc_clk = devm_clk_get_enabled(&pdev->dev, NULL);
234 if (IS_ERR(info->adc_clk)) {
235 dev_warn(&pdev->dev, "ADC clock failed: can't read clk\n");
236 return PTR_ERR(info->adc_clk);
237 }
238
239 /* calculate ADC clock sample rate */
240 reg_con = ioread32(info->regs + NPCM_ADCCON);
241 div = reg_con & NPCM_ADCCON_DIV_MASK;
242 div = div >> NPCM_ADCCON_DIV_SHIFT;
243 info->adc_sample_hz = clk_get_rate(info->adc_clk) / ((div + 1) * 2);
244
245 irq = platform_get_irq(pdev, 0);
246 if (irq < 0)
247 return irq;
248
249 ret = devm_request_irq(&pdev->dev, irq, npcm_adc_isr, 0,
250 "NPCM_ADC", indio_dev);
251 if (ret < 0)
252 return ret;
253
254 reg_con = ioread32(info->regs + NPCM_ADCCON);
255 info->vref = devm_regulator_get_optional(&pdev->dev, "vref");
256 if (!IS_ERR(info->vref)) {
257 ret = regulator_enable(info->vref);
258 if (ret) {
259 dev_err(&pdev->dev, "Can't enable ADC reference voltage\n");
260 return ret;
261 }
262
263 iowrite32(reg_con & ~NPCM_ADCCON_REFSEL,
264 info->regs + NPCM_ADCCON);
265 } else {
266 /*
267 * Any error which is not ENODEV indicates the regulator
268 * has been specified and so is a failure case.
269 */
270 if (PTR_ERR(info->vref) != -ENODEV)
271 return PTR_ERR(info->vref);
272
273 /* Use internal reference */
274 iowrite32(reg_con | NPCM_ADCCON_REFSEL,
275 info->regs + NPCM_ADCCON);
276 }
277
278 init_waitqueue_head(&info->wq);
279
280 reg_con = ioread32(info->regs + NPCM_ADCCON);
281 reg_con |= NPCM_ADC_ENABLE;
282
283 /* Enable the ADC Module */
284 iowrite32(reg_con, info->regs + NPCM_ADCCON);
285
286 /* Start ADC conversion */
287 iowrite32(reg_con | NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
288
289 platform_set_drvdata(pdev, indio_dev);
290 indio_dev->name = dev_name(&pdev->dev);
291 indio_dev->info = &npcm_adc_iio_info;
292 indio_dev->modes = INDIO_DIRECT_MODE;
293 indio_dev->channels = npcm_adc_iio_channels;
294 indio_dev->num_channels = ARRAY_SIZE(npcm_adc_iio_channels);
295
296 ret = iio_device_register(indio_dev);
297 if (ret) {
298 dev_err(&pdev->dev, "Couldn't register the device.\n");
299 goto err_iio_register;
300 }
301
302 pr_info("NPCM ADC driver probed\n");
303
304 return 0;
305
306 err_iio_register:
307 iowrite32(reg_con & ~NPCM_ADCCON_ADC_EN, info->regs + NPCM_ADCCON);
308 if (!IS_ERR(info->vref))
309 regulator_disable(info->vref);
310
311 return ret;
312 }
313
npcm_adc_remove(struct platform_device * pdev)314 static void npcm_adc_remove(struct platform_device *pdev)
315 {
316 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
317 struct npcm_adc *info = iio_priv(indio_dev);
318 u32 regtemp;
319
320 iio_device_unregister(indio_dev);
321
322 regtemp = ioread32(info->regs + NPCM_ADCCON);
323 iowrite32(regtemp & ~NPCM_ADCCON_ADC_EN, info->regs + NPCM_ADCCON);
324 if (!IS_ERR(info->vref))
325 regulator_disable(info->vref);
326 }
327
328 static struct platform_driver npcm_adc_driver = {
329 .probe = npcm_adc_probe,
330 .remove = npcm_adc_remove,
331 .driver = {
332 .name = "npcm_adc",
333 .of_match_table = npcm_adc_match,
334 },
335 };
336
337 module_platform_driver(npcm_adc_driver);
338
339 MODULE_DESCRIPTION("Nuvoton NPCM ADC Driver");
340 MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
341 MODULE_LICENSE("GPL v2");
342