1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DEVICE_H
34 #define MLX5_DEVICE_H
35
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
39 #include <linux/bitfield.h>
40
41 #if defined(__LITTLE_ENDIAN)
42 #define MLX5_SET_HOST_ENDIANNESS 0
43 #elif defined(__BIG_ENDIAN)
44 #define MLX5_SET_HOST_ENDIANNESS 0x80
45 #else
46 #error Host endianness not defined
47 #endif
48
49 /* helper macros */
50 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
51 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
52 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
53 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
54 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
55 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
56 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
57 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
58 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
59 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
60 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
61 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
62 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
63
64 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
65 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
66 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
67 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
68 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
69 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
70 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
71 #define MLX5_ADDR_OF(typ, p, fld) ((void *)((u8 *)(p) + MLX5_BYTE_OFF(typ, fld)))
72
73 /* insert a value to a struct */
74 #define MLX5_SET(typ, p, fld, v) do { \
75 u32 _v = v; \
76 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
77 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
78 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
79 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
80 << __mlx5_dw_bit_off(typ, fld))); \
81 } while (0)
82
83 #define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
84 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
85 MLX5_SET(typ, p, fld[idx], v); \
86 } while (0)
87
88 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
89 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
90 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
91 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
92 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
93 << __mlx5_dw_bit_off(typ, fld))); \
94 } while (0)
95
96 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
97 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
98 __mlx5_mask(typ, fld))
99
100 #define MLX5_GET_PR(typ, p, fld) ({ \
101 u32 ___t = MLX5_GET(typ, p, fld); \
102 pr_debug(#fld " = 0x%x\n", ___t); \
103 ___t; \
104 })
105
106 #define __MLX5_SET64(typ, p, fld, v) do { \
107 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
108 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
109 } while (0)
110
111 #define MLX5_SET64(typ, p, fld, v) do { \
112 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
113 __MLX5_SET64(typ, p, fld, v); \
114 } while (0)
115
116 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
117 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
118 __MLX5_SET64(typ, p, fld[idx], v); \
119 } while (0)
120
121 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
122
123 #define MLX5_GET64_PR(typ, p, fld) ({ \
124 u64 ___t = MLX5_GET64(typ, p, fld); \
125 pr_debug(#fld " = 0x%llx\n", ___t); \
126 ___t; \
127 })
128
129 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
130 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
131 __mlx5_mask16(typ, fld))
132
133 #define MLX5_SET16(typ, p, fld, v) do { \
134 u16 _v = v; \
135 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
136 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
137 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
138 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
139 << __mlx5_16_bit_off(typ, fld))); \
140 } while (0)
141
142 /* Big endian getters */
143 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
144 __mlx5_64_off(typ, fld)))
145
146 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
147 type_t tmp; \
148 switch (sizeof(tmp)) { \
149 case sizeof(u8): \
150 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
151 break; \
152 case sizeof(u16): \
153 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
154 break; \
155 case sizeof(u32): \
156 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
157 break; \
158 case sizeof(u64): \
159 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
160 break; \
161 } \
162 tmp; \
163 })
164
165 enum mlx5_inline_modes {
166 MLX5_INLINE_MODE_NONE,
167 MLX5_INLINE_MODE_L2,
168 MLX5_INLINE_MODE_IP,
169 MLX5_INLINE_MODE_TCP_UDP,
170 };
171
172 enum {
173 MLX5_MAX_COMMANDS = 32,
174 MLX5_CMD_DATA_BLOCK_SIZE = 512,
175 MLX5_PCI_CMD_XPORT = 7,
176 MLX5_MKEY_BSF_OCTO_SIZE = 4,
177 MLX5_MAX_PSVS = 4,
178 };
179
180 enum {
181 MLX5_EXTENDED_UD_AV = 0x80000000,
182 };
183
184 enum {
185 MLX5_CQ_STATE_ARMED = 9,
186 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
187 MLX5_CQ_STATE_FIRED = 0xa,
188 };
189
190 enum {
191 MLX5_STAT_RATE_OFFSET = 5,
192 };
193
194 enum {
195 MLX5_INLINE_SEG = 0x80000000,
196 };
197
198 enum {
199 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
200 };
201
202 enum {
203 MLX5_MIN_PKEY_TABLE_SIZE = 128,
204 MLX5_MAX_LOG_PKEY_TABLE = 5,
205 };
206
207 enum {
208 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
209 };
210
211 enum {
212 MLX5_PFAULT_SUBTYPE_WQE = 0,
213 MLX5_PFAULT_SUBTYPE_RDMA = 1,
214 MLX5_PFAULT_SUBTYPE_MEMORY = 2,
215 };
216
217 enum wqe_page_fault_type {
218 MLX5_WQE_PF_TYPE_RMP = 0,
219 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
220 MLX5_WQE_PF_TYPE_RESP = 2,
221 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
222 };
223
224 enum {
225 MLX5_PERM_LOCAL_READ = 1 << 2,
226 MLX5_PERM_LOCAL_WRITE = 1 << 3,
227 MLX5_PERM_REMOTE_READ = 1 << 4,
228 MLX5_PERM_REMOTE_WRITE = 1 << 5,
229 MLX5_PERM_ATOMIC = 1 << 6,
230 MLX5_PERM_UMR_EN = 1 << 7,
231 };
232
233 enum {
234 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
235 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
236 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
237 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
238 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
239 };
240
241 enum {
242 MLX5_EN_RD = (u64)1,
243 MLX5_EN_WR = (u64)2
244 };
245
246 enum {
247 MLX5_ADAPTER_PAGE_SHIFT = 12,
248 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
249 };
250
251 enum {
252 MLX5_BFREGS_PER_UAR = 4,
253 MLX5_MAX_UARS = 1 << 8,
254 MLX5_NON_FP_BFREGS_PER_UAR = 2,
255 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
256 MLX5_NON_FP_BFREGS_PER_UAR,
257 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
258 MLX5_NON_FP_BFREGS_PER_UAR,
259 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
260 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
261 MLX5_MIN_DYN_BFREGS = 512,
262 MLX5_MAX_DYN_BFREGS = 1024,
263 };
264
265 enum {
266 MLX5_MKEY_MASK_LEN = 1ull << 0,
267 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
268 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
269 MLX5_MKEY_MASK_PD = 1ull << 7,
270 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
271 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
272 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
273 MLX5_MKEY_MASK_KEY = 1ull << 13,
274 MLX5_MKEY_MASK_QPN = 1ull << 14,
275 MLX5_MKEY_MASK_LR = 1ull << 17,
276 MLX5_MKEY_MASK_LW = 1ull << 18,
277 MLX5_MKEY_MASK_RR = 1ull << 19,
278 MLX5_MKEY_MASK_RW = 1ull << 20,
279 MLX5_MKEY_MASK_A = 1ull << 21,
280 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
281 MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25,
282 MLX5_MKEY_MASK_FREE = 1ull << 29,
283 MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47,
284 };
285
286 enum {
287 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
288
289 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
290 MLX5_UMR_CHECK_FREE = (2 << 5),
291
292 MLX5_UMR_INLINE = (1 << 7),
293 };
294
295 #define MLX5_UMR_FLEX_ALIGNMENT 0x40
296 #define MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_mtt))
297 #define MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_klm))
298 #define MLX5_UMR_KSM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_ksm))
299
300 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
301
302 enum {
303 MLX5_EVENT_QUEUE_TYPE_QP = 0,
304 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
305 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
306 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
307 };
308
309 /* mlx5 components can subscribe to any one of these events via
310 * mlx5_eq_notifier_register API.
311 */
312 enum mlx5_event {
313 /* Special value to subscribe to any event */
314 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
315 /* HW events enum start: comp events are not subscribable */
316 MLX5_EVENT_TYPE_COMP = 0x0,
317 /* HW Async events enum start: subscribable events */
318 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
319 MLX5_EVENT_TYPE_COMM_EST = 0x02,
320 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
321 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
322 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
323
324 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
325 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
326 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
327 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
328 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
329 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
330 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
331
332 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
333 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
334 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
335 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
336 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
337 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18,
338 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
339 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
340 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24,
341 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
342
343 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
344 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
345
346 MLX5_EVENT_TYPE_CMD = 0x0a,
347 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
348
349 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
350 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
351
352 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
353 MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf,
354
355 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
356 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
357
358 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
359 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
360
361 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
362
363 MLX5_EVENT_TYPE_MAX = 0x100,
364 };
365
366 enum mlx5_driver_event {
367 MLX5_DRIVER_EVENT_TYPE_TRAP = 0,
368 MLX5_DRIVER_EVENT_UPLINK_NETDEV,
369 MLX5_DRIVER_EVENT_MACSEC_SA_ADDED,
370 MLX5_DRIVER_EVENT_MACSEC_SA_DELETED,
371 MLX5_DRIVER_EVENT_SF_PEER_DEVLINK,
372 MLX5_DRIVER_EVENT_AFFILIATION_DONE,
373 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED,
374 MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE,
375 };
376
377 enum {
378 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
379 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
380 MLX5_TRACER_SUBTYPE_STRINGS_DB_UPDATE = 0x2,
381 };
382
383 enum {
384 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
385 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
386 MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7,
387 MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8,
388 };
389
390 enum {
391 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
392 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
393 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
394 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
395 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
396 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
397 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
398 };
399
400 enum {
401 MLX5_ROCE_VERSION_1 = 0,
402 MLX5_ROCE_VERSION_2 = 2,
403 };
404
405 enum {
406 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
407 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
408 };
409
410 enum {
411 MLX5_ROCE_L3_TYPE_IPV4 = 0,
412 MLX5_ROCE_L3_TYPE_IPV6 = 1,
413 };
414
415 enum {
416 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
417 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
418 };
419
420 enum {
421 MLX5_OPCODE_NOP = 0x00,
422 MLX5_OPCODE_SEND_INVAL = 0x01,
423 MLX5_OPCODE_RDMA_WRITE = 0x08,
424 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
425 MLX5_OPCODE_SEND = 0x0a,
426 MLX5_OPCODE_SEND_IMM = 0x0b,
427 MLX5_OPCODE_LSO = 0x0e,
428 MLX5_OPCODE_RDMA_READ = 0x10,
429 MLX5_OPCODE_ATOMIC_CS = 0x11,
430 MLX5_OPCODE_ATOMIC_FA = 0x12,
431 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
432 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
433 MLX5_OPCODE_BIND_MW = 0x18,
434 MLX5_OPCODE_CONFIG_CMD = 0x1f,
435 MLX5_OPCODE_ENHANCED_MPSW = 0x29,
436
437 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
438 MLX5_RECV_OPCODE_SEND = 0x01,
439 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
440 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
441
442 MLX5_CQE_OPCODE_ERROR = 0x1e,
443 MLX5_CQE_OPCODE_RESIZE = 0x16,
444
445 MLX5_OPCODE_SET_PSV = 0x20,
446 MLX5_OPCODE_GET_PSV = 0x21,
447 MLX5_OPCODE_CHECK_PSV = 0x22,
448 MLX5_OPCODE_DUMP = 0x23,
449 MLX5_OPCODE_RGET_PSV = 0x26,
450 MLX5_OPCODE_RCHECK_PSV = 0x27,
451
452 MLX5_OPCODE_UMR = 0x25,
453
454 MLX5_OPCODE_FLOW_TBL_ACCESS = 0x2c,
455
456 MLX5_OPCODE_ACCESS_ASO = 0x2d,
457 };
458
459 enum {
460 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1,
461 MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2,
462 };
463
464 enum {
465 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1,
466 MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2,
467 };
468
469 struct mlx5_wqe_tls_static_params_seg {
470 u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)];
471 };
472
473 struct mlx5_wqe_tls_progress_params_seg {
474 __be32 tis_tir_num;
475 u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)];
476 };
477
478 enum {
479 MLX5_SET_PORT_RESET_QKEY = 0,
480 MLX5_SET_PORT_GUID0 = 16,
481 MLX5_SET_PORT_NODE_GUID = 17,
482 MLX5_SET_PORT_SYS_GUID = 18,
483 MLX5_SET_PORT_GID_TABLE = 19,
484 MLX5_SET_PORT_PKEY_TABLE = 20,
485 };
486
487 enum {
488 MLX5_BW_NO_LIMIT = 0,
489 MLX5_100_MBPS_UNIT = 3,
490 MLX5_GBPS_UNIT = 4,
491 };
492
493 enum {
494 MLX5_MAX_PAGE_SHIFT = 31
495 };
496
497 enum {
498 /*
499 * Max wqe size for rdma read is 512 bytes, so this
500 * limits our max_sge_rd as the wqe needs to fit:
501 * - ctrl segment (16 bytes)
502 * - rdma segment (16 bytes)
503 * - scatter elements (16 bytes each)
504 */
505 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
506 };
507
508 enum mlx5_odp_transport_cap_bits {
509 MLX5_ODP_SUPPORT_SEND = 1 << 31,
510 MLX5_ODP_SUPPORT_RECV = 1 << 30,
511 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
512 MLX5_ODP_SUPPORT_READ = 1 << 28,
513 };
514
515 struct mlx5_odp_caps {
516 char reserved[0x10];
517 struct {
518 __be32 rc_odp_caps;
519 __be32 uc_odp_caps;
520 __be32 ud_odp_caps;
521 } per_transport_caps;
522 char reserved2[0xe4];
523 };
524
525 struct mlx5_cmd_layout {
526 u8 type;
527 u8 rsvd0[3];
528 __be32 inlen;
529 __be64 in_ptr;
530 __be32 in[4];
531 __be32 out[4];
532 __be64 out_ptr;
533 __be32 outlen;
534 u8 token;
535 u8 sig;
536 u8 rsvd1;
537 u8 status_own;
538 };
539
540 enum mlx5_rfr_severity_bit_offsets {
541 MLX5_CRR_BIT_OFFSET = 0x6,
542 MLX5_RFR_BIT_OFFSET = 0x7,
543 };
544
545 struct health_buffer {
546 __be32 assert_var[6];
547 __be32 rsvd0[2];
548 __be32 assert_exit_ptr;
549 __be32 assert_callra;
550 __be32 rsvd1[1];
551 __be32 time;
552 __be32 fw_ver;
553 __be32 hw_id;
554 u8 rfr_severity;
555 u8 rsvd2[3];
556 u8 irisc_index;
557 u8 synd;
558 __be16 ext_synd;
559 };
560
561 enum mlx5_initializing_bit_offsets {
562 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
563 };
564
565 enum mlx5_cmd_addr_l_sz_offset {
566 MLX5_NIC_IFC_OFFSET = 8,
567 };
568
569 struct mlx5_init_seg {
570 __be32 fw_rev;
571 __be32 cmdif_rev_fw_sub;
572 __be32 rsvd0[2];
573 __be32 cmdq_addr_h;
574 __be32 cmdq_addr_l_sz;
575 __be32 cmd_dbell;
576 __be32 rsvd1[120];
577 __be32 initializing;
578 struct health_buffer health;
579 __be32 rsvd2[878];
580 __be32 cmd_exec_to;
581 __be32 cmd_q_init_to;
582 __be32 internal_timer_h;
583 __be32 internal_timer_l;
584 __be32 rsvd3[2];
585 __be32 health_counter;
586 __be32 rsvd4[11];
587 __be32 real_time_h;
588 __be32 real_time_l;
589 __be32 rsvd5[1006];
590 __be64 ieee1588_clk;
591 __be32 ieee1588_clk_type;
592 __be32 clr_intx;
593 };
594
595 struct mlx5_eqe_comp {
596 __be32 reserved[6];
597 __be32 cqn;
598 };
599
600 struct mlx5_eqe_qp_srq {
601 __be32 reserved1[5];
602 u8 type;
603 u8 reserved2[3];
604 __be32 qp_srq_n;
605 };
606
607 struct mlx5_eqe_cq_err {
608 __be32 cqn;
609 u8 reserved1[7];
610 u8 syndrome;
611 };
612
613 struct mlx5_eqe_xrq_err {
614 __be32 reserved1[5];
615 __be32 type_xrqn;
616 __be32 reserved2;
617 };
618
619 struct mlx5_eqe_port_state {
620 u8 reserved0[8];
621 u8 port;
622 };
623
624 struct mlx5_eqe_gpio {
625 __be32 reserved0[2];
626 __be64 gpio_event;
627 };
628
629 struct mlx5_eqe_congestion {
630 u8 type;
631 u8 rsvd0;
632 u8 congestion_level;
633 };
634
635 struct mlx5_eqe_stall_vl {
636 u8 rsvd0[3];
637 u8 port_vl;
638 };
639
640 struct mlx5_eqe_cmd {
641 __be32 vector;
642 __be32 rsvd[6];
643 };
644
645 struct mlx5_eqe_page_req {
646 __be16 ec_function;
647 __be16 func_id;
648 __be32 num_pages;
649 __be32 rsvd1[5];
650 };
651
652 #define MEMORY_SCHEME_PAGE_FAULT_GRANULARITY 4096
653 struct mlx5_eqe_page_fault {
654 union {
655 struct {
656 __be32 bytes_committed;
657 u16 reserved1;
658 __be16 wqe_index;
659 u16 reserved2;
660 __be16 packet_length;
661 __be32 token;
662 u8 reserved4[8];
663 __be32 pftype_wq;
664 } __packed wqe;
665 struct {
666 __be32 bytes_committed;
667 __be32 r_key;
668 u16 reserved1;
669 __be16 packet_length;
670 __be32 rdma_op_len;
671 __be64 rdma_va;
672 __be32 pftype_token;
673 } __packed rdma;
674 struct {
675 u8 flags;
676 u8 reserved1;
677 __be16 post_demand_fault_pages;
678 __be16 pre_demand_fault_pages;
679 __be16 token47_32;
680 __be32 token31_0;
681 /*
682 * FW changed from specifying the fault size in byte
683 * count to 4k pages granularity. The size specified
684 * in pages uses bits 31:12, to keep backward
685 * compatibility.
686 */
687 __be32 demand_fault_pages;
688 __be32 mkey;
689 __be64 va;
690 } __packed memory;
691 } __packed;
692 } __packed;
693
694 struct mlx5_eqe_vport_change {
695 u8 rsvd0[2];
696 __be16 vport_num;
697 __be32 rsvd1[6];
698 } __packed;
699
700 struct mlx5_eqe_port_module {
701 u8 reserved_at_0[1];
702 u8 module;
703 u8 reserved_at_2[1];
704 u8 module_status;
705 u8 reserved_at_4[2];
706 u8 error_type;
707 } __packed;
708
709 struct mlx5_eqe_pps {
710 u8 rsvd0[3];
711 u8 pin;
712 u8 rsvd1[4];
713 union {
714 struct {
715 __be32 time_sec;
716 __be32 time_nsec;
717 };
718 struct {
719 __be64 time_stamp;
720 };
721 };
722 u8 rsvd2[12];
723 } __packed;
724
725 struct mlx5_eqe_dct {
726 __be32 reserved[6];
727 __be32 dctn;
728 };
729
730 struct mlx5_eqe_temp_warning {
731 __be64 sensor_warning_msb;
732 __be64 sensor_warning_lsb;
733 } __packed;
734
735 struct mlx5_eqe_obj_change {
736 u8 rsvd0[2];
737 __be16 obj_type;
738 __be32 obj_id;
739 } __packed;
740
741 #define SYNC_RST_STATE_MASK 0xf
742
743 enum sync_rst_state_type {
744 MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0,
745 MLX5_SYNC_RST_STATE_RESET_NOW = 0x1,
746 MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2,
747 MLX5_SYNC_RST_STATE_RESET_UNLOAD = 0x3,
748 };
749
750 struct mlx5_eqe_sync_fw_update {
751 u8 reserved_at_0[3];
752 u8 sync_rst_state;
753 };
754
755 struct mlx5_eqe_vhca_state {
756 __be16 ec_function;
757 __be16 function_id;
758 } __packed;
759
760 union ev_data {
761 __be32 raw[7];
762 struct mlx5_eqe_cmd cmd;
763 struct mlx5_eqe_comp comp;
764 struct mlx5_eqe_qp_srq qp_srq;
765 struct mlx5_eqe_cq_err cq_err;
766 struct mlx5_eqe_port_state port;
767 struct mlx5_eqe_gpio gpio;
768 struct mlx5_eqe_congestion cong;
769 struct mlx5_eqe_stall_vl stall_vl;
770 struct mlx5_eqe_page_req req_pages;
771 struct mlx5_eqe_page_fault page_fault;
772 struct mlx5_eqe_vport_change vport_change;
773 struct mlx5_eqe_port_module port_module;
774 struct mlx5_eqe_pps pps;
775 struct mlx5_eqe_dct dct;
776 struct mlx5_eqe_temp_warning temp_warning;
777 struct mlx5_eqe_xrq_err xrq_err;
778 struct mlx5_eqe_sync_fw_update sync_fw_update;
779 struct mlx5_eqe_vhca_state vhca_state;
780 struct mlx5_eqe_obj_change obj_change;
781 } __packed;
782
783 struct mlx5_eqe {
784 u8 rsvd0;
785 u8 type;
786 u8 rsvd1;
787 u8 sub_type;
788 __be32 rsvd2[7];
789 union ev_data data;
790 __be16 rsvd3;
791 u8 signature;
792 u8 owner;
793 } __packed;
794
795 struct mlx5_cmd_prot_block {
796 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
797 u8 rsvd0[48];
798 __be64 next;
799 __be32 block_num;
800 u8 rsvd1;
801 u8 token;
802 u8 ctrl_sig;
803 u8 sig;
804 };
805
806 enum {
807 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
808 };
809
810 struct mlx5_err_cqe {
811 u8 rsvd0[32];
812 __be32 srqn;
813 u8 rsvd1[18];
814 u8 vendor_err_synd;
815 u8 syndrome;
816 __be32 s_wqe_opcode_qpn;
817 __be16 wqe_counter;
818 u8 signature;
819 u8 op_own;
820 };
821
822 struct mlx5_cqe64 {
823 u8 tls_outer_l3_tunneled;
824 u8 rsvd0;
825 __be16 wqe_id;
826 union {
827 struct {
828 u8 tcppsh_abort_dupack;
829 u8 min_ttl;
830 __be16 tcp_win;
831 __be32 ack_seq_num;
832 } lro;
833 struct {
834 u8 reserved0:1;
835 u8 match:1;
836 u8 flush:1;
837 u8 reserved3:5;
838 u8 header_size;
839 __be16 header_entry_index;
840 __be32 data_offset;
841 } shampo;
842 };
843 __be32 rss_hash_result;
844 u8 rss_hash_type;
845 u8 ml_path;
846 u8 rsvd20[2];
847 __be16 check_sum;
848 __be16 slid;
849 __be32 flags_rqpn;
850 u8 hds_ip_ext;
851 u8 l4_l3_hdr_type;
852 __be16 vlan_info;
853 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
854 union {
855 __be32 immediate;
856 __be32 inval_rkey;
857 __be32 pkey;
858 __be32 ft_metadata;
859 };
860 u8 rsvd40[4];
861 __be32 byte_cnt;
862 __be32 timestamp_h;
863 __be32 timestamp_l;
864 __be32 sop_drop_qpn;
865 __be16 wqe_counter;
866 union {
867 u8 signature;
868 u8 validity_iteration_count;
869 };
870 u8 op_own;
871 };
872
873 struct mlx5_mini_cqe8 {
874 union {
875 __be32 rx_hash_result;
876 struct {
877 __be16 checksum;
878 __be16 stridx;
879 };
880 struct {
881 __be16 wqe_counter;
882 u8 s_wqe_opcode;
883 u8 reserved;
884 } s_wqe_info;
885 };
886 __be32 byte_cnt;
887 };
888
889 enum {
890 MLX5_NO_INLINE_DATA,
891 MLX5_INLINE_DATA32_SEG,
892 MLX5_INLINE_DATA64_SEG,
893 MLX5_COMPRESSED,
894 };
895
896 enum {
897 MLX5_CQE_FORMAT_CSUM = 0x1,
898 MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3,
899 };
900
901 enum {
902 MLX5_CQE_COMPRESS_LAYOUT_BASIC = 0,
903 MLX5_CQE_COMPRESS_LAYOUT_ENHANCED = 1,
904 };
905
906 #define MLX5_MINI_CQE_ARRAY_SIZE 8
907
mlx5_get_cqe_format(struct mlx5_cqe64 * cqe)908 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
909 {
910 return (cqe->op_own >> 2) & 0x3;
911 }
912
get_cqe_opcode(struct mlx5_cqe64 * cqe)913 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
914 {
915 return cqe->op_own >> 4;
916 }
917
get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 * cqe)918 static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe)
919 {
920 /* num_of_mini_cqes is zero based */
921 return get_cqe_opcode(cqe) + 1;
922 }
923
get_cqe_lro_tcppsh(struct mlx5_cqe64 * cqe)924 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
925 {
926 return (cqe->lro.tcppsh_abort_dupack >> 6) & 1;
927 }
928
get_cqe_l4_hdr_type(struct mlx5_cqe64 * cqe)929 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
930 {
931 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
932 }
933
cqe_is_tunneled(struct mlx5_cqe64 * cqe)934 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
935 {
936 return cqe->tls_outer_l3_tunneled & 0x1;
937 }
938
get_cqe_tls_offload(struct mlx5_cqe64 * cqe)939 static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe)
940 {
941 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3;
942 }
943
cqe_has_vlan(const struct mlx5_cqe64 * cqe)944 static inline bool cqe_has_vlan(const struct mlx5_cqe64 *cqe)
945 {
946 return cqe->l4_l3_hdr_type & 0x1;
947 }
948
get_cqe_ts(struct mlx5_cqe64 * cqe)949 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
950 {
951 u32 hi, lo;
952
953 hi = be32_to_cpu(cqe->timestamp_h);
954 lo = be32_to_cpu(cqe->timestamp_l);
955
956 return (u64)lo | ((u64)hi << 32);
957 }
958
get_cqe_flow_tag(struct mlx5_cqe64 * cqe)959 static inline u16 get_cqe_flow_tag(struct mlx5_cqe64 *cqe)
960 {
961 return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF;
962 }
963
964 #define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE 3
965 #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE 9
966 #define MLX5_MPWQE_LOG_NUM_STRIDES_MAX 16
967 #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE 6
968 #define MLX5_MPWQE_LOG_STRIDE_SZ_MAX 13
969
970 struct mpwrq_cqe_bc {
971 __be16 filler_consumed_strides;
972 __be16 byte_cnt;
973 };
974
mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 * cqe)975 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
976 {
977 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
978
979 return be16_to_cpu(bc->byte_cnt);
980 }
981
mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc * bc)982 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
983 {
984 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
985 }
986
mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 * cqe)987 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
988 {
989 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
990
991 return mpwrq_get_cqe_bc_consumed_strides(bc);
992 }
993
mpwrq_is_filler_cqe(struct mlx5_cqe64 * cqe)994 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
995 {
996 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
997
998 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
999 }
1000
mpwrq_get_cqe_stride_index(struct mlx5_cqe64 * cqe)1001 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
1002 {
1003 return be16_to_cpu(cqe->wqe_counter);
1004 }
1005
1006 enum {
1007 CQE_L4_HDR_TYPE_NONE = 0x0,
1008 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
1009 CQE_L4_HDR_TYPE_UDP = 0x2,
1010 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
1011 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
1012 };
1013
1014 enum {
1015 CQE_RSS_HTYPE_IP = GENMASK(3, 2),
1016 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
1017 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
1018 */
1019 CQE_RSS_IP_NONE = 0x0,
1020 CQE_RSS_IPV4 = 0x1,
1021 CQE_RSS_IPV6 = 0x2,
1022 CQE_RSS_RESERVED = 0x3,
1023
1024 CQE_RSS_HTYPE_L4 = GENMASK(7, 6),
1025 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
1026 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
1027 */
1028 CQE_RSS_L4_NONE = 0x0,
1029 CQE_RSS_L4_TCP = 0x1,
1030 CQE_RSS_L4_UDP = 0x2,
1031 CQE_RSS_L4_IPSEC = 0x3,
1032 };
1033
1034 enum {
1035 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
1036 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
1037 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
1038 };
1039
1040 enum {
1041 CQE_L2_OK = 1 << 0,
1042 CQE_L3_OK = 1 << 1,
1043 CQE_L4_OK = 1 << 2,
1044 };
1045
1046 enum {
1047 CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0,
1048 CQE_TLS_OFFLOAD_DECRYPTED = 0x1,
1049 CQE_TLS_OFFLOAD_RESYNC = 0x2,
1050 CQE_TLS_OFFLOAD_ERROR = 0x3,
1051 };
1052
1053 struct mlx5_sig_err_cqe {
1054 u8 rsvd0[16];
1055 __be32 expected_trans_sig;
1056 __be32 actual_trans_sig;
1057 __be32 expected_reftag;
1058 __be32 actual_reftag;
1059 __be16 syndrome;
1060 u8 rsvd22[2];
1061 __be32 mkey;
1062 __be64 err_offset;
1063 u8 rsvd30[8];
1064 __be32 qpn;
1065 u8 rsvd38[2];
1066 u8 signature;
1067 u8 op_own;
1068 };
1069
1070 struct mlx5_wqe_srq_next_seg {
1071 u8 rsvd0[2];
1072 __be16 next_wqe_index;
1073 u8 signature;
1074 u8 rsvd1[11];
1075 };
1076
1077 union mlx5_ext_cqe {
1078 struct ib_grh grh;
1079 u8 inl[64];
1080 };
1081
1082 struct mlx5_cqe128 {
1083 union mlx5_ext_cqe inl_grh;
1084 struct mlx5_cqe64 cqe64;
1085 };
1086
1087 enum {
1088 MLX5_MKEY_STATUS_FREE = 1 << 6,
1089 };
1090
1091 enum {
1092 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
1093 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
1094 MLX5_MKEY_BSF_EN = 1 << 30,
1095 };
1096
1097 struct mlx5_mkey_seg {
1098 /* This is a two bit field occupying bits 31-30.
1099 * bit 31 is always 0,
1100 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have translation
1101 */
1102 u8 status;
1103 u8 pcie_control;
1104 u8 flags;
1105 u8 version;
1106 __be32 qpn_mkey7_0;
1107 u8 rsvd1[4];
1108 __be32 flags_pd;
1109 __be64 start_addr;
1110 __be64 len;
1111 __be32 bsfs_octo_size;
1112 u8 rsvd2[16];
1113 __be32 xlt_oct_size;
1114 u8 rsvd3[3];
1115 u8 log2_page_size;
1116 u8 rsvd4[4];
1117 };
1118
1119 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1120
1121 enum {
1122 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1123 };
1124
1125 enum {
1126 VPORT_STATE_DOWN = 0x0,
1127 VPORT_STATE_UP = 0x1,
1128 };
1129
1130 enum {
1131 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0,
1132 MLX5_VPORT_ADMIN_STATE_UP = 0x1,
1133 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2,
1134 };
1135
1136 enum {
1137 MLX5_VPORT_CVLAN_INSERT_WHEN_NO_CVLAN = 0x1,
1138 MLX5_VPORT_CVLAN_INSERT_ALWAYS = 0x3,
1139 };
1140
1141 enum {
1142 MLX5_L3_PROT_TYPE_IPV4 = 0,
1143 MLX5_L3_PROT_TYPE_IPV6 = 1,
1144 };
1145
1146 enum {
1147 MLX5_L4_PROT_TYPE_TCP = 0,
1148 MLX5_L4_PROT_TYPE_UDP = 1,
1149 };
1150
1151 enum {
1152 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1153 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1154 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1155 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1156 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1157 };
1158
1159 enum {
1160 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1161 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1162 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1163 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3,
1164 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4,
1165 MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5,
1166 MLX5_MATCH_MISC_PARAMETERS_5 = 1 << 6,
1167 };
1168
1169 enum {
1170 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1171 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1172 };
1173
1174 enum {
1175 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1176 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1177 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1178 };
1179
1180 enum mlx5_list_type {
1181 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1182 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1183 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1184 };
1185
1186 enum {
1187 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1188 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1189 };
1190
1191 enum mlx5_wol_mode {
1192 MLX5_WOL_DISABLE = 0,
1193 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1194 MLX5_WOL_MAGIC = 1 << 2,
1195 MLX5_WOL_ARP = 1 << 3,
1196 MLX5_WOL_BROADCAST = 1 << 4,
1197 MLX5_WOL_MULTICAST = 1 << 5,
1198 MLX5_WOL_UNICAST = 1 << 6,
1199 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1200 };
1201
1202 enum mlx5_mpls_supported_fields {
1203 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1204 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
1205 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1206 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
1207 };
1208
1209 enum mlx5_flex_parser_protos {
1210 MLX5_FLEX_PROTO_GENEVE = 1 << 3,
1211 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
1212 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
1213 MLX5_FLEX_PROTO_ICMP = 1 << 8,
1214 MLX5_FLEX_PROTO_ICMPV6 = 1 << 9,
1215 };
1216
1217 /* MLX5 DEV CAPs */
1218
1219 /* TODO: EAT.ME */
1220 enum mlx5_cap_mode {
1221 HCA_CAP_OPMOD_GET_MAX = 0,
1222 HCA_CAP_OPMOD_GET_CUR = 1,
1223 };
1224
1225 /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate
1226 * capability memory.
1227 */
1228 enum mlx5_cap_type {
1229 MLX5_CAP_GENERAL = 0,
1230 MLX5_CAP_ETHERNET_OFFLOADS,
1231 MLX5_CAP_ODP,
1232 MLX5_CAP_ATOMIC,
1233 MLX5_CAP_ROCE,
1234 MLX5_CAP_IPOIB_OFFLOADS,
1235 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1236 MLX5_CAP_FLOW_TABLE,
1237 MLX5_CAP_ESWITCH_FLOW_TABLE,
1238 MLX5_CAP_ESWITCH,
1239 MLX5_CAP_QOS = 0xc,
1240 MLX5_CAP_DEBUG,
1241 MLX5_CAP_RESERVED_14,
1242 MLX5_CAP_DEV_MEM,
1243 MLX5_CAP_RESERVED_16,
1244 MLX5_CAP_TLS,
1245 MLX5_CAP_VDPA_EMULATION = 0x13,
1246 MLX5_CAP_DEV_EVENT = 0x14,
1247 MLX5_CAP_IPSEC,
1248 MLX5_CAP_CRYPTO = 0x1a,
1249 MLX5_CAP_SHAMPO = 0x1d,
1250 MLX5_CAP_MACSEC = 0x1f,
1251 MLX5_CAP_GENERAL_2 = 0x20,
1252 MLX5_CAP_PORT_SELECTION = 0x25,
1253 MLX5_CAP_ADV_VIRTUALIZATION = 0x26,
1254 MLX5_CAP_ADV_RDMA = 0x28,
1255 /* NUM OF CAP Types */
1256 MLX5_CAP_NUM
1257 };
1258
1259 enum mlx5_pcam_reg_groups {
1260 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1261 };
1262
1263 enum mlx5_pcam_feature_groups {
1264 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1265 };
1266
1267 enum mlx5_mcam_reg_groups {
1268 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1269 MLX5_MCAM_REGS_0x9100_0x917F = 0x2,
1270 MLX5_MCAM_REGS_0x9180_0x91FF = 0x3,
1271 MLX5_MCAM_REGS_NUM = 0x4,
1272 };
1273
1274 enum mlx5_mcam_feature_groups {
1275 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1276 };
1277
1278 enum mlx5_qcam_reg_groups {
1279 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1280 };
1281
1282 enum mlx5_qcam_feature_groups {
1283 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1284 };
1285
1286 /* GET Dev Caps macros */
1287 #define MLX5_CAP_GEN(mdev, cap) \
1288 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1289
1290 #define MLX5_CAP_GEN_64(mdev, cap) \
1291 MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1292
1293 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1294 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1295
1296 #define MLX5_CAP_GEN_2(mdev, cap) \
1297 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1298
1299 #define MLX5_CAP_GEN_2_64(mdev, cap) \
1300 MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1301
1302 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \
1303 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1304
1305 #define MLX5_CAP_ETH(mdev, cap) \
1306 MLX5_GET(per_protocol_networking_offload_caps,\
1307 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1308
1309 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1310 MLX5_GET(per_protocol_networking_offload_caps,\
1311 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1312
1313 #define MLX5_CAP_ROCE(mdev, cap) \
1314 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1315
1316 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1317 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1318
1319 #define MLX5_CAP_ATOMIC(mdev, cap) \
1320 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1321
1322 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1323 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1324
1325 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1326 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1327
1328 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \
1329 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1330
1331 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1332 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1333
1334 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1335 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1336
1337 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1338 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1339
1340 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1341 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1342
1343 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \
1344 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1345
1346 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \
1347 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1348
1349 #define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(mdev, cap) \
1350 MLX5_CAP_ADV_RDMA(mdev, rdma_transport_rx_flow_table_properties.cap)
1351
1352 #define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(mdev, cap) \
1353 MLX5_CAP_ADV_RDMA(mdev, rdma_transport_tx_flow_table_properties.cap)
1354
1355 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1356 MLX5_GET(flow_table_eswitch_cap, \
1357 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1358
1359 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1360 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1361
1362 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1363 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1364
1365 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1366 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1367
1368 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \
1369 MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1370
1371 #define MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(mdev, cap) \
1372 MLX5_CAP_FLOWTABLE(mdev, ft_field_support_2_nic_receive.cap)
1373
1374 #define MLX5_CAP_ESW(mdev, cap) \
1375 MLX5_GET(e_switch_cap, \
1376 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1377
1378 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
1379 MLX5_GET64(flow_table_eswitch_cap, \
1380 (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1381
1382 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \
1383 MLX5_GET(port_selection_cap, \
1384 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1385
1386 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \
1387 MLX5_GET(port_selection_cap, \
1388 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1389
1390 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \
1391 MLX5_GET(adv_virtualization_cap, \
1392 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1393
1394 #define MLX5_CAP_ADV_RDMA(mdev, cap) \
1395 MLX5_GET(adv_rdma_cap, \
1396 mdev->caps.hca[MLX5_CAP_ADV_RDMA]->cur, cap)
1397
1398 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \
1399 MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1400
1401 #define MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(mdev, cap) \
1402 MLX5_CAP_PORT_SELECTION(mdev, ft_field_support_2_port_selection.cap)
1403
1404 #define MLX5_CAP_ODP(mdev, cap)\
1405 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1406
1407 #define MLX5_CAP_ODP_SCHEME(mdev, cap) \
1408 (MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1409 mem_page_fault) ? \
1410 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1411 memory_page_fault_scheme_cap.cap) : \
1412 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1413 transport_page_fault_scheme_cap.cap))
1414
1415 #define MLX5_CAP_ODP_MAX(mdev, cap)\
1416 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1417
1418 #define MLX5_CAP_QOS(mdev, cap)\
1419 MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1420
1421 #define MLX5_CAP_DEBUG(mdev, cap)\
1422 MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1423
1424 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1425 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1426
1427 #define MLX5_CAP_PCAM_REG(mdev, reg) \
1428 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1429
1430 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1431 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
1432 mng_access_reg_cap_mask.access_regs.reg)
1433
1434 #define MLX5_CAP_MCAM_REG2(mdev, reg) \
1435 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
1436 mng_access_reg_cap_mask.access_regs2.reg)
1437
1438 #define MLX5_CAP_MCAM_REG3(mdev, reg) \
1439 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9180_0x91FF], \
1440 mng_access_reg_cap_mask.access_regs3.reg)
1441
1442 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1443 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1444
1445 #define MLX5_CAP_QCAM_REG(mdev, fld) \
1446 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1447
1448 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1449 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1450
1451 #define MLX5_CAP_FPGA(mdev, cap) \
1452 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1453
1454 #define MLX5_CAP64_FPGA(mdev, cap) \
1455 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1456
1457 #define MLX5_CAP_DEV_MEM(mdev, cap)\
1458 MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1459
1460 #define MLX5_CAP64_DEV_MEM(mdev, cap)\
1461 MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1462
1463 #define MLX5_CAP_TLS(mdev, cap) \
1464 MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1465
1466 #define MLX5_CAP_DEV_EVENT(mdev, cap)\
1467 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1468
1469 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\
1470 MLX5_GET(virtio_emulation_cap, \
1471 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1472
1473 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\
1474 MLX5_GET64(virtio_emulation_cap, \
1475 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1476
1477 #define MLX5_CAP_IPSEC(mdev, cap)\
1478 MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1479
1480 #define MLX5_CAP_CRYPTO(mdev, cap)\
1481 MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1482
1483 #define MLX5_CAP_MACSEC(mdev, cap)\
1484 MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
1485
1486 #define MLX5_CAP_SHAMPO(mdev, cap) \
1487 MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap)
1488
1489 enum {
1490 MLX5_CMD_STAT_OK = 0x0,
1491 MLX5_CMD_STAT_INT_ERR = 0x1,
1492 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1493 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1494 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1495 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1496 MLX5_CMD_STAT_RES_BUSY = 0x6,
1497 MLX5_CMD_STAT_NOT_READY = 0x7,
1498 MLX5_CMD_STAT_LIM_ERR = 0x8,
1499 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1500 MLX5_CMD_STAT_IX_ERR = 0xa,
1501 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1502 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1503 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1504 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1505 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1506 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1507 };
1508
1509 enum {
1510 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1511 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1512 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1513 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1514 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1515 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1516 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1517 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1518 MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13,
1519 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1520 MLX5_PHYSICAL_LAYER_RECOVERY_GROUP = 0x1a,
1521 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1522 MLX5_INFINIBAND_EXTENDED_PORT_COUNTERS_GROUP = 0x21,
1523 };
1524
1525 enum {
1526 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1527 };
1528
mlx5_to_sw_pkey_sz(int pkey_sz)1529 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1530 {
1531 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1532 return 0;
1533 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1534 }
1535
1536 #define MLX5_RDMA_RX_NUM_COUNTERS_PRIOS 2
1537 #define MLX5_RDMA_TX_NUM_COUNTERS_PRIOS 1
1538 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1539 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1540 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1541 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1542 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1543 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1544
1545 #endif /* MLX5_DEVICE_H */
1546