1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include <linux/dma-fence.h> 7 #include <linux/dma-resv.h> 8 9 #include <drm/drm_blend.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_modeset_helper.h> 12 13 #include "i915_drv.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_bo.h" 16 #include "intel_display.h" 17 #include "intel_display_types.h" 18 #include "intel_dpt.h" 19 #include "intel_fb.h" 20 #include "intel_fb_bo.h" 21 #include "intel_frontbuffer.h" 22 23 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a)) 24 25 /* 26 * From the Sky Lake PRM: 27 * "The Color Control Surface (CCS) contains the compression status of 28 * the cache-line pairs. The compression state of the cache-line pair 29 * is specified by 2 bits in the CCS. Each CCS cache-line represents 30 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled 31 * cache-line-pairs. CCS is always Y tiled." 32 * 33 * Since cache line pairs refers to horizontally adjacent cache lines, 34 * each cache line in the CCS corresponds to an area of 32x16 cache 35 * lines on the main surface. Since each pixel is 4 bytes, this gives 36 * us a ratio of one byte in the CCS for each 8x16 pixels in the 37 * main surface. 38 */ 39 static const struct drm_format_info skl_ccs_formats[] = { 40 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 41 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 42 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 43 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 44 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 45 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 46 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 47 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 48 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 49 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 50 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 51 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 52 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 53 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 54 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 55 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 56 }; 57 58 /* 59 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the 60 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles 61 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of 62 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in 63 * the main surface. 64 */ 65 static const struct drm_format_info gen12_ccs_formats[] = { 66 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 67 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 68 .hsub = 1, .vsub = 1, }, 69 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 70 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 71 .hsub = 1, .vsub = 1, }, 72 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 73 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 74 .hsub = 1, .vsub = 1, .has_alpha = true }, 75 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 76 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 77 .hsub = 1, .vsub = 1, .has_alpha = true }, 78 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 79 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 80 .hsub = 1, .vsub = 1, }, 81 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 82 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 83 .hsub = 1, .vsub = 1, }, 84 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 85 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 86 .hsub = 1, .vsub = 1, .has_alpha = true }, 87 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 88 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 89 .hsub = 1, .vsub = 1, .has_alpha = true }, 90 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2, 91 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 92 .hsub = 1, .vsub = 1, }, 93 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2, 94 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 95 .hsub = 1, .vsub = 1, }, 96 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2, 97 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 98 .hsub = 1, .vsub = 1, .has_alpha = true }, 99 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2, 100 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 101 .hsub = 1, .vsub = 1, .has_alpha = true }, 102 { .format = DRM_FORMAT_YUYV, .num_planes = 2, 103 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 104 .hsub = 2, .vsub = 1, .is_yuv = true }, 105 { .format = DRM_FORMAT_YVYU, .num_planes = 2, 106 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 107 .hsub = 2, .vsub = 1, .is_yuv = true }, 108 { .format = DRM_FORMAT_UYVY, .num_planes = 2, 109 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 110 .hsub = 2, .vsub = 1, .is_yuv = true }, 111 { .format = DRM_FORMAT_VYUY, .num_planes = 2, 112 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 113 .hsub = 2, .vsub = 1, .is_yuv = true }, 114 { .format = DRM_FORMAT_XYUV8888, .num_planes = 2, 115 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 116 .hsub = 1, .vsub = 1, .is_yuv = true }, 117 { .format = DRM_FORMAT_NV12, .num_planes = 4, 118 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 }, 119 .hsub = 2, .vsub = 2, .is_yuv = true }, 120 { .format = DRM_FORMAT_P010, .num_planes = 4, 121 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 122 .hsub = 2, .vsub = 2, .is_yuv = true }, 123 { .format = DRM_FORMAT_P012, .num_planes = 4, 124 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 125 .hsub = 2, .vsub = 2, .is_yuv = true }, 126 { .format = DRM_FORMAT_P016, .num_planes = 4, 127 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 128 .hsub = 2, .vsub = 2, .is_yuv = true }, 129 }; 130 131 /* 132 * Same as gen12_ccs_formats[] above, but with additional surface used 133 * to pass Clear Color information in plane 2 with 64 bits of data. 134 */ 135 static const struct drm_format_info gen12_ccs_cc_formats[] = { 136 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, 137 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 138 .hsub = 1, .vsub = 1, }, 139 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, 140 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 141 .hsub = 1, .vsub = 1, }, 142 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, 143 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 144 .hsub = 1, .vsub = 1, .has_alpha = true }, 145 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, 146 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 147 .hsub = 1, .vsub = 1, .has_alpha = true }, 148 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3, 149 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 150 .hsub = 1, .vsub = 1, }, 151 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3, 152 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 153 .hsub = 1, .vsub = 1, }, 154 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3, 155 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 156 .hsub = 1, .vsub = 1, .has_alpha = true }, 157 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3, 158 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 159 .hsub = 1, .vsub = 1, .has_alpha = true }, 160 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 3, 161 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 162 .hsub = 1, .vsub = 1, }, 163 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 3, 164 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 165 .hsub = 1, .vsub = 1, }, 166 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 3, 167 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 168 .hsub = 1, .vsub = 1, .has_alpha = true }, 169 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 3, 170 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 171 .hsub = 1, .vsub = 1, .has_alpha = true }, 172 }; 173 174 static const struct drm_format_info gen12_flat_ccs_cc_formats[] = { 175 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 176 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 177 .hsub = 1, .vsub = 1, }, 178 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 179 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 180 .hsub = 1, .vsub = 1, }, 181 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 182 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 183 .hsub = 1, .vsub = 1, .has_alpha = true }, 184 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 185 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 186 .hsub = 1, .vsub = 1, .has_alpha = true }, 187 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 188 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 189 .hsub = 1, .vsub = 1, }, 190 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 191 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 192 .hsub = 1, .vsub = 1, }, 193 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 194 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 195 .hsub = 1, .vsub = 1, .has_alpha = true }, 196 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 197 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 198 .hsub = 1, .vsub = 1, .has_alpha = true }, 199 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2, 200 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 201 .hsub = 1, .vsub = 1, }, 202 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2, 203 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 204 .hsub = 1, .vsub = 1, }, 205 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2, 206 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 207 .hsub = 1, .vsub = 1, .has_alpha = true }, 208 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2, 209 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 210 .hsub = 1, .vsub = 1, .has_alpha = true }, 211 }; 212 213 struct intel_modifier_desc { 214 u64 modifier; 215 struct { 216 u8 from; 217 u8 until; 218 } display_ver; 219 #define DISPLAY_VER_ALL { 0, -1 } 220 221 const struct drm_format_info *formats; 222 int format_count; 223 #define FORMAT_OVERRIDE(format_list) \ 224 .formats = format_list, \ 225 .format_count = ARRAY_SIZE(format_list) 226 227 u8 plane_caps; 228 229 struct { 230 u8 cc_planes:3; 231 u8 packed_aux_planes:4; 232 u8 planar_aux_planes:4; 233 } ccs; 234 }; 235 236 #define INTEL_PLANE_CAP_CCS_MASK (INTEL_PLANE_CAP_CCS_RC | \ 237 INTEL_PLANE_CAP_CCS_RC_CC | \ 238 INTEL_PLANE_CAP_CCS_MC) 239 #define INTEL_PLANE_CAP_TILING_MASK (INTEL_PLANE_CAP_TILING_X | \ 240 INTEL_PLANE_CAP_TILING_Y | \ 241 INTEL_PLANE_CAP_TILING_Yf | \ 242 INTEL_PLANE_CAP_TILING_4) 243 #define INTEL_PLANE_CAP_TILING_NONE 0 244 245 static const struct intel_modifier_desc intel_modifiers[] = { 246 { 247 .modifier = I915_FORMAT_MOD_4_TILED_LNL_CCS, 248 .display_ver = { 20, -1 }, 249 .plane_caps = INTEL_PLANE_CAP_TILING_4, 250 }, { 251 .modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS, 252 .display_ver = { 14, -1 }, 253 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS, 254 }, { 255 .modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS, 256 .display_ver = { 14, 14 }, 257 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC, 258 259 .ccs.packed_aux_planes = BIT(1), 260 .ccs.planar_aux_planes = BIT(2) | BIT(3), 261 262 FORMAT_OVERRIDE(gen12_ccs_formats), 263 }, { 264 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, 265 .display_ver = { 14, 14 }, 266 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC, 267 268 .ccs.packed_aux_planes = BIT(1), 269 270 FORMAT_OVERRIDE(gen12_ccs_formats), 271 }, { 272 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC, 273 .display_ver = { 14, 14 }, 274 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC, 275 276 .ccs.cc_planes = BIT(2), 277 .ccs.packed_aux_planes = BIT(1), 278 279 FORMAT_OVERRIDE(gen12_ccs_cc_formats), 280 }, { 281 .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS, 282 .display_ver = { 13, 13 }, 283 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC, 284 }, { 285 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC, 286 .display_ver = { 13, 13 }, 287 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC, 288 289 .ccs.cc_planes = BIT(1), 290 291 FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats), 292 }, { 293 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, 294 .display_ver = { 13, 13 }, 295 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC, 296 }, { 297 .modifier = I915_FORMAT_MOD_4_TILED, 298 .display_ver = { 13, -1 }, 299 .plane_caps = INTEL_PLANE_CAP_TILING_4, 300 }, { 301 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, 302 .display_ver = { 12, 13 }, 303 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC, 304 305 .ccs.packed_aux_planes = BIT(1), 306 .ccs.planar_aux_planes = BIT(2) | BIT(3), 307 308 FORMAT_OVERRIDE(gen12_ccs_formats), 309 }, { 310 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, 311 .display_ver = { 12, 13 }, 312 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC, 313 314 .ccs.packed_aux_planes = BIT(1), 315 316 FORMAT_OVERRIDE(gen12_ccs_formats), 317 }, { 318 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, 319 .display_ver = { 12, 13 }, 320 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC_CC, 321 322 .ccs.cc_planes = BIT(2), 323 .ccs.packed_aux_planes = BIT(1), 324 325 FORMAT_OVERRIDE(gen12_ccs_cc_formats), 326 }, { 327 .modifier = I915_FORMAT_MOD_Yf_TILED_CCS, 328 .display_ver = { 9, 11 }, 329 .plane_caps = INTEL_PLANE_CAP_TILING_Yf | INTEL_PLANE_CAP_CCS_RC, 330 331 .ccs.packed_aux_planes = BIT(1), 332 333 FORMAT_OVERRIDE(skl_ccs_formats), 334 }, { 335 .modifier = I915_FORMAT_MOD_Y_TILED_CCS, 336 .display_ver = { 9, 11 }, 337 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC, 338 339 .ccs.packed_aux_planes = BIT(1), 340 341 FORMAT_OVERRIDE(skl_ccs_formats), 342 }, { 343 .modifier = I915_FORMAT_MOD_Yf_TILED, 344 .display_ver = { 9, 11 }, 345 .plane_caps = INTEL_PLANE_CAP_TILING_Yf, 346 }, { 347 .modifier = I915_FORMAT_MOD_Y_TILED, 348 .display_ver = { 9, 13 }, 349 .plane_caps = INTEL_PLANE_CAP_TILING_Y, 350 }, { 351 .modifier = I915_FORMAT_MOD_X_TILED, 352 .display_ver = { 0, 29 }, 353 .plane_caps = INTEL_PLANE_CAP_TILING_X, 354 }, { 355 .modifier = DRM_FORMAT_MOD_LINEAR, 356 .display_ver = DISPLAY_VER_ALL, 357 }, 358 }; 359 360 static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier) 361 { 362 int i; 363 364 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) 365 if (intel_modifiers[i].modifier == modifier) 366 return &intel_modifiers[i]; 367 368 return NULL; 369 } 370 371 static const struct intel_modifier_desc *lookup_modifier(u64 modifier) 372 { 373 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); 374 375 if (WARN_ON(!md)) 376 return &intel_modifiers[0]; 377 378 return md; 379 } 380 381 static const struct drm_format_info * 382 lookup_format_info(const struct drm_format_info formats[], 383 int num_formats, u32 format) 384 { 385 int i; 386 387 for (i = 0; i < num_formats; i++) { 388 if (formats[i].format == format) 389 return &formats[i]; 390 } 391 392 return NULL; 393 } 394 395 unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) 396 { 397 const struct intel_modifier_desc *md; 398 u8 tiling_caps; 399 400 md = lookup_modifier_or_null(fb_modifier); 401 if (!md) 402 return I915_TILING_NONE; 403 404 tiling_caps = lookup_modifier_or_null(fb_modifier)->plane_caps & 405 INTEL_PLANE_CAP_TILING_MASK; 406 407 switch (tiling_caps) { 408 case INTEL_PLANE_CAP_TILING_Y: 409 return I915_TILING_Y; 410 case INTEL_PLANE_CAP_TILING_X: 411 return I915_TILING_X; 412 case INTEL_PLANE_CAP_TILING_4: 413 case INTEL_PLANE_CAP_TILING_Yf: 414 case INTEL_PLANE_CAP_TILING_NONE: 415 return I915_TILING_NONE; 416 default: 417 MISSING_CASE(tiling_caps); 418 return I915_TILING_NONE; 419 } 420 } 421 422 /** 423 * intel_fb_get_format_info: Get a modifier specific format information 424 * @cmd: FB add command structure 425 * 426 * Returns: 427 * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0], 428 * or %NULL if the modifier doesn't override the format. 429 */ 430 const struct drm_format_info * 431 intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd) 432 { 433 const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]); 434 435 if (!md || !md->formats) 436 return NULL; 437 438 return lookup_format_info(md->formats, md->format_count, cmd->pixel_format); 439 } 440 441 static bool plane_caps_contain_any(u8 caps, u8 mask) 442 { 443 return caps & mask; 444 } 445 446 static bool plane_caps_contain_all(u8 caps, u8 mask) 447 { 448 return (caps & mask) == mask; 449 } 450 451 /** 452 * intel_fb_is_tiled_modifier: Check if a modifier is a tiled modifier type 453 * @modifier: Modifier to check 454 * 455 * Returns: 456 * Returns %true if @modifier is a tiled modifier. 457 */ 458 bool intel_fb_is_tiled_modifier(u64 modifier) 459 { 460 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 461 INTEL_PLANE_CAP_TILING_MASK); 462 } 463 464 /** 465 * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type 466 * @modifier: Modifier to check 467 * 468 * Returns: 469 * Returns %true if @modifier is a render, render with color clear or 470 * media compression modifier. 471 */ 472 bool intel_fb_is_ccs_modifier(u64 modifier) 473 { 474 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 475 INTEL_PLANE_CAP_CCS_MASK); 476 } 477 478 /** 479 * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type 480 * @modifier: Modifier to check 481 * 482 * Returns: 483 * Returns %true if @modifier is a render with color clear modifier. 484 */ 485 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier) 486 { 487 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 488 INTEL_PLANE_CAP_CCS_RC_CC); 489 } 490 491 /** 492 * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type 493 * @modifier: Modifier to check 494 * 495 * Returns: 496 * Returns %true if @modifier is a media compression modifier. 497 */ 498 bool intel_fb_is_mc_ccs_modifier(u64 modifier) 499 { 500 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 501 INTEL_PLANE_CAP_CCS_MC); 502 } 503 504 /** 505 * intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement. 506 * @modifier: Modifier to check 507 * 508 * Returns: 509 * Returns %true if @modifier requires 64k aligned physical pages. 510 */ 511 bool intel_fb_needs_64k_phys(u64 modifier) 512 { 513 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); 514 515 if (!md) 516 return false; 517 518 return plane_caps_contain_any(md->plane_caps, 519 INTEL_PLANE_CAP_NEED64K_PHYS); 520 } 521 522 /** 523 * intel_fb_is_tile4_modifier: Check if a modifier is a tile4 modifier type 524 * @modifier: Modifier to check 525 * 526 * Returns: 527 * Returns %true if @modifier is a tile4 modifier. 528 */ 529 bool intel_fb_is_tile4_modifier(u64 modifier) 530 { 531 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 532 INTEL_PLANE_CAP_TILING_4); 533 } 534 535 static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md, 536 u8 display_ver_from, u8 display_ver_until) 537 { 538 return md->display_ver.from <= display_ver_until && 539 display_ver_from <= md->display_ver.until; 540 } 541 542 static bool plane_has_modifier(struct intel_display *display, 543 u8 plane_caps, 544 const struct intel_modifier_desc *md) 545 { 546 struct drm_i915_private *i915 = to_i915(display->drm); 547 548 if (!IS_DISPLAY_VER(display, md->display_ver.from, md->display_ver.until)) 549 return false; 550 551 if (!plane_caps_contain_all(plane_caps, md->plane_caps)) 552 return false; 553 554 /* 555 * Separate AuxCCS and Flat CCS modifiers to be run only on platforms 556 * where supported. 557 */ 558 if (intel_fb_is_ccs_modifier(md->modifier) && 559 HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes) 560 return false; 561 562 if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS && 563 (GRAPHICS_VER(i915) < 20 || !IS_DGFX(i915))) 564 return false; 565 566 if (md->modifier == I915_FORMAT_MOD_4_TILED_LNL_CCS && 567 (GRAPHICS_VER(i915) < 20 || IS_DGFX(i915))) 568 return false; 569 570 return true; 571 } 572 573 /** 574 * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities 575 * @display: display instance 576 * @plane_caps: capabilities for the plane the modifiers are queried for 577 * 578 * Returns: 579 * Returns the list of modifiers allowed by the @display platform and @plane_caps. 580 * The caller must free the returned buffer. 581 */ 582 u64 *intel_fb_plane_get_modifiers(struct intel_display *display, 583 u8 plane_caps) 584 { 585 u64 *list, *p; 586 int count = 1; /* +1 for invalid modifier terminator */ 587 int i; 588 589 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { 590 if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) 591 count++; 592 } 593 594 list = kmalloc_array(count, sizeof(*list), GFP_KERNEL); 595 if (drm_WARN_ON(display->drm, !list)) 596 return NULL; 597 598 p = list; 599 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { 600 if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) 601 *p++ = intel_modifiers[i].modifier; 602 } 603 *p++ = DRM_FORMAT_MOD_INVALID; 604 605 return list; 606 } 607 608 /** 609 * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane 610 * @plane: Plane to check the modifier support for 611 * @modifier: The modifier to check the support for 612 * 613 * Returns: 614 * %true if the @modifier is supported on @plane. 615 */ 616 bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier) 617 { 618 int i; 619 620 for (i = 0; i < plane->base.modifier_count; i++) 621 if (plane->base.modifiers[i] == modifier) 622 return true; 623 624 return false; 625 } 626 627 static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md, 628 const struct drm_format_info *info) 629 { 630 if (!info->is_yuv) 631 return false; 632 633 if (hweight8(md->ccs.planar_aux_planes) == 2) 634 return info->num_planes == 4; 635 else 636 return info->num_planes == 2; 637 } 638 639 /** 640 * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar 641 * @info: format to check 642 * @modifier: modifier used with the format 643 * 644 * Returns: 645 * %true if @info / @modifier is YUV semiplanar. 646 */ 647 bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, 648 u64 modifier) 649 { 650 return format_is_yuv_semiplanar(lookup_modifier(modifier), info); 651 } 652 653 static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md, 654 const struct drm_format_info *format) 655 { 656 if (format_is_yuv_semiplanar(md, format)) 657 return md->ccs.planar_aux_planes; 658 else 659 return md->ccs.packed_aux_planes; 660 } 661 662 /** 663 * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane 664 * @fb: Framebuffer 665 * @color_plane: color plane index to check 666 * 667 * Returns: 668 * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane. 669 */ 670 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) 671 { 672 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 673 674 return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane); 675 } 676 677 /** 678 * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane 679 * @fb: Framebuffer 680 * @color_plane: color plane index to check 681 * 682 * Returns: 683 * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane. 684 */ 685 static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) 686 { 687 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 688 689 return check_modifier_display_ver_range(md, 12, 14) && 690 ccs_aux_plane_mask(md, fb->format) & BIT(color_plane); 691 } 692 693 /** 694 * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer 695 * @fb: Framebuffer 696 * 697 * Returns: 698 * Returns the index of the color clear plane for @fb, or -1 if @fb is not a 699 * framebuffer using a render compression/color clear modifier. 700 */ 701 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb) 702 { 703 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 704 705 if (!md->ccs.cc_planes) 706 return -1; 707 708 drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1); 709 710 return ilog2((int)md->ccs.cc_planes); 711 } 712 713 static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane) 714 { 715 return intel_fb_rc_ccs_cc_plane(fb) == color_plane; 716 } 717 718 bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) 719 { 720 return fb->modifier == DRM_FORMAT_MOD_LINEAR || 721 intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) || 722 is_gen12_ccs_cc_plane(fb, color_plane); 723 } 724 725 int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) 726 { 727 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) || 728 (main_plane && main_plane >= fb->format->num_planes / 2)); 729 730 return fb->format->num_planes / 2 + main_plane; 731 } 732 733 int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane) 734 { 735 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) || 736 ccs_plane < fb->format->num_planes / 2); 737 738 if (is_gen12_ccs_cc_plane(fb, ccs_plane)) 739 return 0; 740 741 return ccs_plane - fb->format->num_planes / 2; 742 } 743 744 static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_plane) 745 { 746 int main_plane = skl_ccs_to_main_plane(&fb->base, ccs_plane); 747 unsigned int main_stride = fb->base.pitches[main_plane]; 748 unsigned int main_tile_width = intel_tile_width_bytes(&fb->base, main_plane); 749 750 return DIV_ROUND_UP(main_stride, 4 * main_tile_width) * 64; 751 } 752 753 int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) 754 { 755 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 756 struct intel_display *display = to_intel_display(fb->dev); 757 758 if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes) 759 return main_to_ccs_plane(fb, main_plane); 760 else if (DISPLAY_VER(display) < 11 && 761 format_is_yuv_semiplanar(md, fb->format)) 762 return 1; 763 else 764 return 0; 765 } 766 767 unsigned int intel_tile_size(struct intel_display *display) 768 { 769 return DISPLAY_VER(display) == 2 ? 2048 : 4096; 770 } 771 772 unsigned int 773 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) 774 { 775 struct intel_display *display = to_intel_display(fb->dev); 776 struct drm_i915_private *i915 = to_i915(display->drm); 777 unsigned int cpp = fb->format->cpp[color_plane]; 778 779 switch (fb->modifier) { 780 case DRM_FORMAT_MOD_LINEAR: 781 return intel_tile_size(display); 782 case I915_FORMAT_MOD_X_TILED: 783 if (DISPLAY_VER(display) == 2) 784 return 128; 785 else 786 return 512; 787 case I915_FORMAT_MOD_4_TILED_BMG_CCS: 788 case I915_FORMAT_MOD_4_TILED_LNL_CCS: 789 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 790 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 791 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 792 case I915_FORMAT_MOD_4_TILED: 793 /* 794 * Each 4K tile consists of 64B(8*8) subtiles, with 795 * same shape as Y Tile(i.e 4*16B OWords) 796 */ 797 return 128; 798 case I915_FORMAT_MOD_Y_TILED_CCS: 799 if (intel_fb_is_ccs_aux_plane(fb, color_plane)) 800 return 128; 801 fallthrough; 802 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 803 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 804 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 805 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 806 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 807 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 808 if (intel_fb_is_ccs_aux_plane(fb, color_plane) || 809 is_gen12_ccs_cc_plane(fb, color_plane)) 810 return 64; 811 fallthrough; 812 case I915_FORMAT_MOD_Y_TILED: 813 if (DISPLAY_VER(display) == 2 || HAS_128_BYTE_Y_TILING(i915)) 814 return 128; 815 else 816 return 512; 817 case I915_FORMAT_MOD_Yf_TILED_CCS: 818 if (intel_fb_is_ccs_aux_plane(fb, color_plane)) 819 return 128; 820 fallthrough; 821 case I915_FORMAT_MOD_Yf_TILED: 822 switch (cpp) { 823 case 1: 824 return 64; 825 case 2: 826 case 4: 827 return 128; 828 case 8: 829 case 16: 830 return 256; 831 default: 832 MISSING_CASE(cpp); 833 return cpp; 834 } 835 break; 836 default: 837 MISSING_CASE(fb->modifier); 838 return cpp; 839 } 840 } 841 842 unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane) 843 { 844 struct intel_display *display = to_intel_display(fb->dev); 845 846 return intel_tile_size(display) / 847 intel_tile_width_bytes(fb, color_plane); 848 } 849 850 /* 851 * Return the tile dimensions in pixel units, based on the (2 or 4 kbyte) GTT 852 * page tile size. 853 */ 854 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane, 855 unsigned int *tile_width, 856 unsigned int *tile_height) 857 { 858 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane); 859 unsigned int cpp = fb->format->cpp[color_plane]; 860 861 *tile_width = tile_width_bytes / cpp; 862 *tile_height = intel_tile_height(fb, color_plane); 863 } 864 865 /* 866 * Return the tile dimensions in pixel units, based on the tile block size. 867 * The block covers the full GTT page sized tile on all tiled surfaces and 868 * it's a 64 byte portion of the tile on TGL+ CCS surfaces. 869 */ 870 static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_plane, 871 unsigned int *tile_width, 872 unsigned int *tile_height) 873 { 874 intel_tile_dims(fb, color_plane, tile_width, tile_height); 875 876 if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) 877 *tile_height = 1; 878 } 879 880 unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane) 881 { 882 unsigned int tile_width, tile_height; 883 884 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 885 886 return fb->pitches[color_plane] * tile_height; 887 } 888 889 unsigned int 890 intel_fb_align_height(const struct drm_framebuffer *fb, 891 int color_plane, unsigned int height) 892 { 893 unsigned int tile_height = intel_tile_height(fb, color_plane); 894 895 return ALIGN(height, tile_height); 896 } 897 898 bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier) 899 { 900 return HAS_DPT(display) && modifier != DRM_FORMAT_MOD_LINEAR; 901 } 902 903 bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) 904 { 905 struct intel_display *display = to_intel_display(fb->dev); 906 907 return display->params.enable_dpt && 908 intel_fb_modifier_uses_dpt(display, fb->modifier); 909 } 910 911 void intel_fb_plane_get_subsampling(int *hsub, int *vsub, 912 const struct drm_framebuffer *fb, 913 int color_plane) 914 { 915 int main_plane; 916 917 if (color_plane == 0) { 918 *hsub = 1; 919 *vsub = 1; 920 921 return; 922 } 923 924 /* 925 * TODO: Deduct the subsampling from the char block for all CCS 926 * formats and planes. 927 */ 928 if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) { 929 *hsub = fb->format->hsub; 930 *vsub = fb->format->vsub; 931 932 return; 933 } 934 935 main_plane = skl_ccs_to_main_plane(fb, color_plane); 936 *hsub = drm_format_info_block_width(fb->format, color_plane) / 937 drm_format_info_block_width(fb->format, main_plane); 938 939 /* 940 * The min stride check in the core framebuffer_check() function 941 * assumes that format->hsub applies to every plane except for the 942 * first plane. That's incorrect for the CCS AUX plane of the first 943 * plane, but for the above check to pass we must define the block 944 * width with that subsampling applied to it. Adjust the width here 945 * accordingly, so we can calculate the actual subsampling factor. 946 */ 947 if (main_plane == 0) 948 *hsub *= fb->format->hsub; 949 950 *vsub = 32; 951 } 952 953 static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h) 954 { 955 int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ? 956 skl_ccs_to_main_plane(&fb->base, color_plane) : 0; 957 unsigned int main_width = fb->base.width; 958 unsigned int main_height = fb->base.height; 959 int main_hsub, main_vsub; 960 int hsub, vsub; 961 962 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane); 963 intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane); 964 965 *w = DIV_ROUND_UP(main_width, main_hsub * hsub); 966 *h = DIV_ROUND_UP(main_height, main_vsub * vsub); 967 } 968 969 static u32 intel_adjust_tile_offset(int *x, int *y, 970 unsigned int tile_width, 971 unsigned int tile_height, 972 unsigned int tile_size, 973 unsigned int pitch_tiles, 974 u32 old_offset, 975 u32 new_offset) 976 { 977 unsigned int pitch_pixels = pitch_tiles * tile_width; 978 unsigned int tiles; 979 980 WARN_ON(old_offset & (tile_size - 1)); 981 WARN_ON(new_offset & (tile_size - 1)); 982 WARN_ON(new_offset > old_offset); 983 984 tiles = (old_offset - new_offset) / tile_size; 985 986 *y += tiles / pitch_tiles * tile_height; 987 *x += tiles % pitch_tiles * tile_width; 988 989 /* minimize x in case it got needlessly big */ 990 *y += *x / pitch_pixels * tile_height; 991 *x %= pitch_pixels; 992 993 return new_offset; 994 } 995 996 static u32 intel_adjust_linear_offset(int *x, int *y, 997 unsigned int cpp, 998 unsigned int pitch, 999 u32 old_offset, 1000 u32 new_offset) 1001 { 1002 old_offset += *y * pitch + *x * cpp; 1003 1004 *y = (old_offset - new_offset) / pitch; 1005 *x = ((old_offset - new_offset) - *y * pitch) / cpp; 1006 1007 return new_offset; 1008 } 1009 1010 static u32 intel_adjust_aligned_offset(int *x, int *y, 1011 const struct drm_framebuffer *fb, 1012 int color_plane, 1013 unsigned int rotation, 1014 unsigned int pitch, 1015 u32 old_offset, u32 new_offset) 1016 { 1017 struct intel_display *display = to_intel_display(fb->dev); 1018 unsigned int cpp = fb->format->cpp[color_plane]; 1019 1020 drm_WARN_ON(display->drm, new_offset > old_offset); 1021 1022 if (!is_surface_linear(fb, color_plane)) { 1023 unsigned int tile_size, tile_width, tile_height; 1024 unsigned int pitch_tiles; 1025 1026 tile_size = intel_tile_size(display); 1027 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 1028 1029 if (drm_rotation_90_or_270(rotation)) { 1030 pitch_tiles = pitch / tile_height; 1031 swap(tile_width, tile_height); 1032 } else { 1033 pitch_tiles = pitch / (tile_width * cpp); 1034 } 1035 1036 intel_adjust_tile_offset(x, y, tile_width, tile_height, 1037 tile_size, pitch_tiles, 1038 old_offset, new_offset); 1039 } else { 1040 intel_adjust_linear_offset(x, y, cpp, pitch, 1041 old_offset, new_offset); 1042 } 1043 1044 return new_offset; 1045 } 1046 1047 /* 1048 * Adjust the tile offset by moving the difference into 1049 * the x/y offsets. 1050 */ 1051 u32 intel_plane_adjust_aligned_offset(int *x, int *y, 1052 const struct intel_plane_state *plane_state, 1053 int color_plane, 1054 u32 old_offset, u32 new_offset) 1055 { 1056 return intel_adjust_aligned_offset(x, y, plane_state->hw.fb, color_plane, 1057 plane_state->hw.rotation, 1058 plane_state->view.color_plane[color_plane].mapping_stride, 1059 old_offset, new_offset); 1060 } 1061 1062 /* 1063 * Computes the aligned offset to the base tile and adjusts 1064 * x, y. bytes per pixel is assumed to be a power-of-two. 1065 * 1066 * In the 90/270 rotated case, x and y are assumed 1067 * to be already rotated to match the rotated GTT view, and 1068 * pitch is the tile_height aligned framebuffer height. 1069 * 1070 * This function is used when computing the derived information 1071 * under intel_framebuffer, so using any of that information 1072 * here is not allowed. Anything under drm_framebuffer can be 1073 * used. This is why the user has to pass in the pitch since it 1074 * is specified in the rotated orientation. 1075 */ 1076 static u32 intel_compute_aligned_offset(struct intel_display *display, 1077 int *x, int *y, 1078 const struct drm_framebuffer *fb, 1079 int color_plane, 1080 unsigned int pitch, 1081 unsigned int rotation, 1082 unsigned int alignment) 1083 { 1084 unsigned int cpp = fb->format->cpp[color_plane]; 1085 u32 offset, offset_aligned; 1086 1087 if (!is_surface_linear(fb, color_plane)) { 1088 unsigned int tile_size, tile_width, tile_height; 1089 unsigned int tile_rows, tiles, pitch_tiles; 1090 1091 tile_size = intel_tile_size(display); 1092 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 1093 1094 if (drm_rotation_90_or_270(rotation)) { 1095 pitch_tiles = pitch / tile_height; 1096 swap(tile_width, tile_height); 1097 } else { 1098 pitch_tiles = pitch / (tile_width * cpp); 1099 } 1100 1101 tile_rows = *y / tile_height; 1102 *y %= tile_height; 1103 1104 tiles = *x / tile_width; 1105 *x %= tile_width; 1106 1107 offset = (tile_rows * pitch_tiles + tiles) * tile_size; 1108 1109 offset_aligned = offset; 1110 if (alignment) 1111 offset_aligned = rounddown(offset_aligned, alignment); 1112 1113 intel_adjust_tile_offset(x, y, tile_width, tile_height, 1114 tile_size, pitch_tiles, 1115 offset, offset_aligned); 1116 } else { 1117 offset = *y * pitch + *x * cpp; 1118 offset_aligned = offset; 1119 if (alignment) { 1120 offset_aligned = rounddown(offset_aligned, alignment); 1121 *y = (offset % alignment) / pitch; 1122 *x = ((offset % alignment) - *y * pitch) / cpp; 1123 } else { 1124 *y = *x = 0; 1125 } 1126 } 1127 1128 return offset_aligned; 1129 } 1130 1131 u32 intel_plane_compute_aligned_offset(int *x, int *y, 1132 const struct intel_plane_state *plane_state, 1133 int color_plane) 1134 { 1135 struct intel_display *display = to_intel_display(plane_state); 1136 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1137 const struct drm_framebuffer *fb = plane_state->hw.fb; 1138 unsigned int rotation = plane_state->hw.rotation; 1139 unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride; 1140 unsigned int alignment = plane->min_alignment(plane, fb, color_plane); 1141 1142 return intel_compute_aligned_offset(display, x, y, fb, color_plane, 1143 pitch, rotation, alignment); 1144 } 1145 1146 /* Convert the fb->offset[] into x/y offsets */ 1147 static int intel_fb_offset_to_xy(int *x, int *y, 1148 const struct drm_framebuffer *fb, 1149 int color_plane) 1150 { 1151 struct intel_display *display = to_intel_display(fb->dev); 1152 unsigned int height, alignment, unused; 1153 1154 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) 1155 alignment = intel_tile_size(display); 1156 else 1157 alignment = 0; 1158 1159 if (alignment != 0 && fb->offsets[color_plane] % alignment) { 1160 drm_dbg_kms(display->drm, 1161 "Misaligned offset 0x%08x for color plane %d\n", 1162 fb->offsets[color_plane], color_plane); 1163 return -EINVAL; 1164 } 1165 1166 height = drm_format_info_plane_height(fb->format, fb->height, color_plane); 1167 height = ALIGN(height, intel_tile_height(fb, color_plane)); 1168 1169 /* Catch potential overflows early */ 1170 if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]), 1171 fb->offsets[color_plane], &unused)) { 1172 drm_dbg_kms(display->drm, 1173 "Bad offset 0x%08x or pitch %d for color plane %d\n", 1174 fb->offsets[color_plane], fb->pitches[color_plane], 1175 color_plane); 1176 return -ERANGE; 1177 } 1178 1179 *x = 0; 1180 *y = 0; 1181 1182 intel_adjust_aligned_offset(x, y, 1183 fb, color_plane, DRM_MODE_ROTATE_0, 1184 fb->pitches[color_plane], 1185 fb->offsets[color_plane], 0); 1186 1187 return 0; 1188 } 1189 1190 static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y) 1191 { 1192 struct intel_display *display = to_intel_display(fb->dev); 1193 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1194 int main_plane; 1195 int hsub, vsub; 1196 int tile_width, tile_height; 1197 int ccs_x, ccs_y; 1198 int main_x, main_y; 1199 1200 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) 1201 return 0; 1202 1203 /* 1204 * While all the tile dimensions are based on a 2k or 4k GTT page size 1205 * here the main and CCS coordinates must match only within a (64 byte 1206 * on TGL+) block inside the tile. 1207 */ 1208 intel_tile_block_dims(fb, ccs_plane, &tile_width, &tile_height); 1209 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1210 1211 tile_width *= hsub; 1212 tile_height *= vsub; 1213 1214 ccs_x = (x * hsub) % tile_width; 1215 ccs_y = (y * vsub) % tile_height; 1216 1217 main_plane = skl_ccs_to_main_plane(fb, ccs_plane); 1218 main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width; 1219 main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height; 1220 1221 /* 1222 * CCS doesn't have its own x/y offset register, so the intra CCS tile 1223 * x/y offsets must match between CCS and the main surface. 1224 */ 1225 if (main_x != ccs_x || main_y != ccs_y) { 1226 drm_dbg_kms(display->drm, 1227 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", 1228 main_x, main_y, ccs_x, ccs_y, 1229 intel_fb->normal_view.color_plane[main_plane].x, 1230 intel_fb->normal_view.color_plane[main_plane].y, 1231 x, y); 1232 return -EINVAL; 1233 } 1234 1235 return 0; 1236 } 1237 1238 static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) 1239 { 1240 struct intel_display *display = to_intel_display(plane_state); 1241 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1242 const struct drm_framebuffer *fb = plane_state->hw.fb; 1243 int i; 1244 1245 /* We don't want to deal with remapping with cursors */ 1246 if (plane->id == PLANE_CURSOR) 1247 return false; 1248 1249 /* 1250 * The display engine limits already match/exceed the 1251 * render engine limits, so not much point in remapping. 1252 * Would also need to deal with the fence POT alignment 1253 * and gen2 2KiB GTT tile size. 1254 */ 1255 if (DISPLAY_VER(display) < 4) 1256 return false; 1257 1258 /* 1259 * The new CCS hash mode isn't compatible with remapping as 1260 * the virtual address of the pages affects the compressed data. 1261 */ 1262 if (intel_fb_is_ccs_modifier(fb->modifier)) 1263 return false; 1264 1265 /* Linear needs a page aligned stride for remapping */ 1266 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) { 1267 unsigned int alignment = intel_tile_size(display) - 1; 1268 1269 for (i = 0; i < fb->format->num_planes; i++) { 1270 if (fb->pitches[i] & alignment) 1271 return false; 1272 } 1273 } 1274 1275 return true; 1276 } 1277 1278 bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) 1279 { 1280 struct intel_display *display = to_intel_display(fb->base.dev); 1281 1282 return (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) && 1283 intel_fb_uses_dpt(&fb->base); 1284 } 1285 1286 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 1287 { 1288 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1289 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1290 1291 return DISPLAY_VER(dev_priv) < 4 || 1292 (plane->fbc && !plane_state->no_fbc_reason && 1293 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 1294 } 1295 1296 static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation) 1297 { 1298 if (drm_rotation_90_or_270(rotation)) 1299 return fb->rotated_view.color_plane[color_plane].mapping_stride; 1300 else if (intel_fb_needs_pot_stride_remap(fb)) 1301 return fb->remapped_view.color_plane[color_plane].mapping_stride; 1302 else 1303 return fb->normal_view.color_plane[color_plane].mapping_stride; 1304 } 1305 1306 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) 1307 { 1308 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1309 const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); 1310 unsigned int rotation = plane_state->hw.rotation; 1311 u32 stride, max_stride; 1312 1313 /* 1314 * No remapping for invisible planes since we don't have 1315 * an actual source viewport to remap. 1316 */ 1317 if (!plane_state->uapi.visible) 1318 return false; 1319 1320 if (!intel_plane_can_remap(plane_state)) 1321 return false; 1322 1323 /* 1324 * FIXME: aux plane limits on gen9+ are 1325 * unclear in Bspec, for now no checking. 1326 */ 1327 stride = intel_fb_pitch(fb, 0, rotation); 1328 max_stride = plane->max_stride(plane, fb->base.format->format, 1329 fb->base.modifier, rotation); 1330 1331 return stride > max_stride; 1332 } 1333 1334 static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane, 1335 int plane_width, int *x, int *y) 1336 { 1337 struct intel_display *display = to_intel_display(fb->base.dev); 1338 struct drm_gem_object *obj = intel_fb_bo(&fb->base); 1339 int ret; 1340 1341 ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane); 1342 if (ret) { 1343 drm_dbg_kms(display->drm, 1344 "bad fb plane %d offset: 0x%x\n", 1345 color_plane, fb->base.offsets[color_plane]); 1346 return ret; 1347 } 1348 1349 ret = intel_fb_check_ccs_xy(&fb->base, color_plane, *x, *y); 1350 if (ret) 1351 return ret; 1352 1353 /* 1354 * The fence (if used) is aligned to the start of the object 1355 * so having the framebuffer wrap around across the edge of the 1356 * fenced region doesn't really work. We have no API to configure 1357 * the fence start offset within the object (nor could we probably 1358 * on gen2/3). So it's just easier if we just require that the 1359 * fb layout agrees with the fence layout. We already check that the 1360 * fb stride matches the fence stride elsewhere. 1361 */ 1362 if (color_plane == 0 && intel_bo_is_tiled(obj) && 1363 (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) { 1364 drm_dbg_kms(display->drm, 1365 "bad fb plane %d offset: 0x%x\n", 1366 color_plane, fb->base.offsets[color_plane]); 1367 return -EINVAL; 1368 } 1369 1370 return 0; 1371 } 1372 1373 static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y) 1374 { 1375 struct intel_display *display = to_intel_display(fb->base.dev); 1376 unsigned int tile_size = intel_tile_size(display); 1377 u32 offset; 1378 1379 offset = intel_compute_aligned_offset(display, x, y, &fb->base, color_plane, 1380 fb->base.pitches[color_plane], 1381 DRM_MODE_ROTATE_0, 1382 tile_size); 1383 1384 return offset / tile_size; 1385 } 1386 1387 struct fb_plane_view_dims { 1388 unsigned int width, height; 1389 unsigned int tile_width, tile_height; 1390 }; 1391 1392 static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane, 1393 unsigned int width, unsigned int height, 1394 struct fb_plane_view_dims *dims) 1395 { 1396 dims->width = width; 1397 dims->height = height; 1398 1399 intel_tile_dims(&fb->base, color_plane, &dims->tile_width, &dims->tile_height); 1400 } 1401 1402 static unsigned int 1403 plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane, 1404 const struct fb_plane_view_dims *dims) 1405 { 1406 return DIV_ROUND_UP(fb->base.pitches[color_plane], 1407 dims->tile_width * fb->base.format->cpp[color_plane]); 1408 } 1409 1410 static unsigned int 1411 plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane, 1412 unsigned int pitch_tiles) 1413 { 1414 if (intel_fb_needs_pot_stride_remap(fb)) { 1415 /* 1416 * ADL_P, the only platform needing a POT stride has a minimum 1417 * of 8 main surface tiles. 1418 */ 1419 return roundup_pow_of_two(max(pitch_tiles, 8u)); 1420 } else { 1421 return pitch_tiles; 1422 } 1423 } 1424 1425 static unsigned int 1426 plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane, 1427 unsigned int tile_width, 1428 unsigned int src_stride_tiles, unsigned int dst_stride_tiles) 1429 { 1430 struct intel_display *display = to_intel_display(fb->base.dev); 1431 unsigned int stride_tiles; 1432 1433 if ((display->platform.alderlake_p || DISPLAY_VER(display) >= 14) && 1434 src_stride_tiles < dst_stride_tiles) 1435 stride_tiles = src_stride_tiles; 1436 else 1437 stride_tiles = dst_stride_tiles; 1438 1439 return stride_tiles * tile_width * fb->base.format->cpp[color_plane]; 1440 } 1441 1442 static unsigned int 1443 plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane, 1444 const struct fb_plane_view_dims *dims, 1445 int x) 1446 { 1447 return DIV_ROUND_UP(x + dims->width, dims->tile_width); 1448 } 1449 1450 static unsigned int 1451 plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane, 1452 const struct fb_plane_view_dims *dims, 1453 int y) 1454 { 1455 return DIV_ROUND_UP(y + dims->height, dims->tile_height); 1456 } 1457 1458 static unsigned int 1459 plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane, 1460 const struct fb_plane_view_dims *dims, 1461 int x, int y) 1462 { 1463 struct intel_display *display = to_intel_display(fb->base.dev); 1464 unsigned int size; 1465 1466 size = (y + dims->height) * fb->base.pitches[color_plane] + 1467 x * fb->base.format->cpp[color_plane]; 1468 1469 return DIV_ROUND_UP(size, intel_tile_size(display)); 1470 } 1471 1472 #define assign_chk_ovf(display, var, val) ({ \ 1473 drm_WARN_ON((display)->drm, overflows_type(val, var)); \ 1474 (var) = (val); \ 1475 }) 1476 1477 #define assign_bfld_chk_ovf(display, var, val) ({ \ 1478 (var) = (val); \ 1479 drm_WARN_ON((display)->drm, (var) != (val)); \ 1480 (var); \ 1481 }) 1482 1483 static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane, 1484 const struct fb_plane_view_dims *dims, 1485 u32 obj_offset, u32 gtt_offset, int x, int y, 1486 struct intel_fb_view *view) 1487 { 1488 struct intel_display *display = to_intel_display(fb->base.dev); 1489 struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane]; 1490 struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane]; 1491 unsigned int tile_width = dims->tile_width; 1492 unsigned int tile_height = dims->tile_height; 1493 unsigned int tile_size = intel_tile_size(display); 1494 struct drm_rect r; 1495 u32 size = 0; 1496 1497 assign_bfld_chk_ovf(display, remap_info->offset, obj_offset); 1498 1499 if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) { 1500 remap_info->linear = 1; 1501 1502 assign_chk_ovf(display, remap_info->size, 1503 plane_view_linear_tiles(fb, color_plane, dims, x, y)); 1504 } else { 1505 remap_info->linear = 0; 1506 1507 assign_chk_ovf(display, remap_info->src_stride, 1508 plane_view_src_stride_tiles(fb, color_plane, dims)); 1509 assign_chk_ovf(display, remap_info->width, 1510 plane_view_width_tiles(fb, color_plane, dims, x)); 1511 assign_chk_ovf(display, remap_info->height, 1512 plane_view_height_tiles(fb, color_plane, dims, y)); 1513 } 1514 1515 if (view->gtt.type == I915_GTT_VIEW_ROTATED) { 1516 drm_WARN_ON(display->drm, remap_info->linear); 1517 check_array_bounds(display, view->gtt.rotated.plane, color_plane); 1518 1519 assign_chk_ovf(display, remap_info->dst_stride, 1520 plane_view_dst_stride_tiles(fb, color_plane, remap_info->height)); 1521 1522 /* rotate the x/y offsets to match the GTT view */ 1523 drm_rect_init(&r, x, y, dims->width, dims->height); 1524 drm_rect_rotate(&r, 1525 remap_info->width * tile_width, 1526 remap_info->height * tile_height, 1527 DRM_MODE_ROTATE_270); 1528 1529 color_plane_info->x = r.x1; 1530 color_plane_info->y = r.y1; 1531 1532 color_plane_info->mapping_stride = remap_info->dst_stride * tile_height; 1533 color_plane_info->scanout_stride = color_plane_info->mapping_stride; 1534 1535 size += remap_info->dst_stride * remap_info->width; 1536 1537 /* rotate the tile dimensions to match the GTT view */ 1538 swap(tile_width, tile_height); 1539 } else { 1540 drm_WARN_ON(display->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED); 1541 1542 check_array_bounds(display, view->gtt.remapped.plane, color_plane); 1543 1544 if (view->gtt.remapped.plane_alignment) { 1545 u32 aligned_offset = ALIGN(gtt_offset, 1546 view->gtt.remapped.plane_alignment); 1547 1548 size += aligned_offset - gtt_offset; 1549 gtt_offset = aligned_offset; 1550 } 1551 1552 color_plane_info->x = x; 1553 color_plane_info->y = y; 1554 1555 if (remap_info->linear) { 1556 color_plane_info->mapping_stride = fb->base.pitches[color_plane]; 1557 color_plane_info->scanout_stride = color_plane_info->mapping_stride; 1558 1559 size += remap_info->size; 1560 } else { 1561 unsigned int dst_stride; 1562 1563 /* 1564 * The hardware automagically calculates the CCS AUX surface 1565 * stride from the main surface stride so can't really remap a 1566 * smaller subset (unless we'd remap in whole AUX page units). 1567 */ 1568 if (intel_fb_needs_pot_stride_remap(fb) && 1569 intel_fb_is_ccs_modifier(fb->base.modifier)) 1570 dst_stride = remap_info->src_stride; 1571 else 1572 dst_stride = remap_info->width; 1573 1574 dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride); 1575 1576 assign_chk_ovf(display, remap_info->dst_stride, dst_stride); 1577 color_plane_info->mapping_stride = dst_stride * 1578 tile_width * 1579 fb->base.format->cpp[color_plane]; 1580 color_plane_info->scanout_stride = 1581 plane_view_scanout_stride(fb, color_plane, tile_width, 1582 remap_info->src_stride, 1583 dst_stride); 1584 1585 size += dst_stride * remap_info->height; 1586 } 1587 } 1588 1589 /* 1590 * We only keep the x/y offsets, so push all of the gtt offset into 1591 * the x/y offsets. x,y will hold the first pixel of the framebuffer 1592 * plane from the start of the remapped/rotated gtt mapping. 1593 */ 1594 if (remap_info->linear) 1595 intel_adjust_linear_offset(&color_plane_info->x, &color_plane_info->y, 1596 fb->base.format->cpp[color_plane], 1597 color_plane_info->mapping_stride, 1598 gtt_offset * tile_size, 0); 1599 else 1600 intel_adjust_tile_offset(&color_plane_info->x, &color_plane_info->y, 1601 tile_width, tile_height, 1602 tile_size, remap_info->dst_stride, 1603 gtt_offset * tile_size, 0); 1604 1605 return size; 1606 } 1607 1608 #undef assign_chk_ovf 1609 1610 /* Return number of tiles @color_plane needs. */ 1611 static unsigned int 1612 calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane, 1613 const struct fb_plane_view_dims *dims, 1614 int x, int y) 1615 { 1616 unsigned int tiles; 1617 1618 if (is_surface_linear(&fb->base, color_plane)) { 1619 tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y); 1620 } else { 1621 tiles = plane_view_src_stride_tiles(fb, color_plane, dims) * 1622 plane_view_height_tiles(fb, color_plane, dims, y); 1623 /* 1624 * If the plane isn't horizontally tile aligned, 1625 * we need one more tile. 1626 */ 1627 if (x != 0) 1628 tiles++; 1629 } 1630 1631 return tiles; 1632 } 1633 1634 static void intel_fb_view_init(struct intel_display *display, 1635 struct intel_fb_view *view, 1636 enum i915_gtt_view_type view_type) 1637 { 1638 memset(view, 0, sizeof(*view)); 1639 view->gtt.type = view_type; 1640 1641 if (view_type == I915_GTT_VIEW_REMAPPED && 1642 (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) 1643 view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE; 1644 } 1645 1646 bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) 1647 { 1648 struct intel_display *display = to_intel_display(fb->base.dev); 1649 1650 if (DISPLAY_VER(display) >= 13) 1651 return false; 1652 1653 return fb->base.modifier == I915_FORMAT_MOD_Y_TILED || 1654 fb->base.modifier == I915_FORMAT_MOD_Yf_TILED; 1655 } 1656 1657 static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) 1658 { 1659 struct intel_display *display = to_intel_display(fb->dev); 1660 struct intel_plane *plane; 1661 unsigned int min_alignment = 0; 1662 1663 for_each_intel_plane(display->drm, plane) { 1664 unsigned int plane_min_alignment; 1665 1666 if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) 1667 continue; 1668 1669 plane_min_alignment = plane->min_alignment(plane, fb, 0); 1670 1671 drm_WARN_ON(display->drm, plane_min_alignment && 1672 !is_power_of_2(plane_min_alignment)); 1673 1674 if (intel_plane_needs_physical(plane)) 1675 continue; 1676 1677 min_alignment = max(min_alignment, plane_min_alignment); 1678 } 1679 1680 return min_alignment; 1681 } 1682 1683 static unsigned int intel_fb_vtd_guard(const struct drm_framebuffer *fb) 1684 { 1685 struct intel_display *display = to_intel_display(fb->dev); 1686 struct intel_plane *plane; 1687 unsigned int vtd_guard = 0; 1688 1689 for_each_intel_plane(display->drm, plane) { 1690 if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) 1691 continue; 1692 1693 vtd_guard = max_t(unsigned int, vtd_guard, plane->vtd_guard); 1694 } 1695 1696 return vtd_guard; 1697 } 1698 1699 int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb) 1700 { 1701 struct drm_gem_object *obj = intel_fb_bo(&fb->base); 1702 u32 gtt_offset_rotated = 0; 1703 u32 gtt_offset_remapped = 0; 1704 unsigned int max_size = 0; 1705 int i, num_planes = fb->base.format->num_planes; 1706 unsigned int tile_size = intel_tile_size(display); 1707 1708 intel_fb_view_init(display, &fb->normal_view, I915_GTT_VIEW_NORMAL); 1709 1710 drm_WARN_ON(display->drm, 1711 intel_fb_supports_90_270_rotation(fb) && 1712 intel_fb_needs_pot_stride_remap(fb)); 1713 1714 if (intel_fb_supports_90_270_rotation(fb)) 1715 intel_fb_view_init(display, &fb->rotated_view, I915_GTT_VIEW_ROTATED); 1716 if (intel_fb_needs_pot_stride_remap(fb)) 1717 intel_fb_view_init(display, &fb->remapped_view, I915_GTT_VIEW_REMAPPED); 1718 1719 for (i = 0; i < num_planes; i++) { 1720 struct fb_plane_view_dims view_dims; 1721 unsigned int width, height; 1722 unsigned int size; 1723 u32 offset; 1724 int x, y; 1725 int ret; 1726 1727 /* 1728 * Plane 2 of Render Compression with Clear Color fb modifier 1729 * is consumed by the driver and not passed to DE. Skip the 1730 * arithmetic related to alignment and offset calculation. 1731 */ 1732 if (is_gen12_ccs_cc_plane(&fb->base, i)) { 1733 unsigned int end; 1734 1735 if (!IS_ALIGNED(fb->base.offsets[i], 64)) { 1736 drm_dbg_kms(display->drm, 1737 "fb misaligned clear color plane %d offset (0x%x)\n", 1738 i, fb->base.offsets[i]); 1739 return -EINVAL; 1740 } 1741 1742 if (check_add_overflow(fb->base.offsets[i], 64, &end)) { 1743 drm_dbg_kms(display->drm, 1744 "fb bad clear color plane %d offset (0x%x)\n", 1745 i, fb->base.offsets[i]); 1746 return -EINVAL; 1747 } 1748 1749 max_size = max(max_size, DIV_ROUND_UP(end, tile_size)); 1750 continue; 1751 } 1752 1753 intel_fb_plane_dims(fb, i, &width, &height); 1754 1755 ret = convert_plane_offset_to_xy(fb, i, width, &x, &y); 1756 if (ret) 1757 return ret; 1758 1759 init_plane_view_dims(fb, i, width, height, &view_dims); 1760 1761 /* 1762 * First pixel of the framebuffer from 1763 * the start of the normal gtt mapping. 1764 */ 1765 fb->normal_view.color_plane[i].x = x; 1766 fb->normal_view.color_plane[i].y = y; 1767 fb->normal_view.color_plane[i].mapping_stride = fb->base.pitches[i]; 1768 fb->normal_view.color_plane[i].scanout_stride = 1769 fb->normal_view.color_plane[i].mapping_stride; 1770 1771 offset = calc_plane_aligned_offset(fb, i, &x, &y); 1772 1773 if (intel_fb_supports_90_270_rotation(fb)) 1774 gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims, 1775 offset, gtt_offset_rotated, x, y, 1776 &fb->rotated_view); 1777 1778 if (intel_fb_needs_pot_stride_remap(fb)) 1779 gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims, 1780 offset, gtt_offset_remapped, x, y, 1781 &fb->remapped_view); 1782 1783 size = calc_plane_normal_size(fb, i, &view_dims, x, y); 1784 /* how many tiles in total needed in the bo */ 1785 max_size = max(max_size, offset + size); 1786 } 1787 1788 if (mul_u32_u32(max_size, tile_size) > obj->size) { 1789 drm_dbg_kms(display->drm, 1790 "fb too big for bo (need %llu bytes, have %zu bytes)\n", 1791 mul_u32_u32(max_size, tile_size), obj->size); 1792 return -EINVAL; 1793 } 1794 1795 fb->min_alignment = intel_fb_min_alignment(&fb->base); 1796 fb->vtd_guard = intel_fb_vtd_guard(&fb->base); 1797 1798 return 0; 1799 } 1800 1801 unsigned int intel_fb_view_vtd_guard(const struct drm_framebuffer *fb, 1802 const struct intel_fb_view *view, 1803 unsigned int rotation) 1804 { 1805 unsigned int vtd_guard; 1806 int color_plane; 1807 1808 vtd_guard = to_intel_framebuffer(fb)->vtd_guard; 1809 if (!vtd_guard) 1810 return 0; 1811 1812 for (color_plane = 0; color_plane < fb->format->num_planes; color_plane++) { 1813 unsigned int stride, tile; 1814 1815 if (intel_fb_is_ccs_aux_plane(fb, color_plane) || 1816 is_gen12_ccs_cc_plane(fb, color_plane)) 1817 continue; 1818 1819 stride = view->color_plane[color_plane].mapping_stride; 1820 1821 if (drm_rotation_90_or_270(rotation)) 1822 tile = intel_tile_height(fb, color_plane); 1823 else 1824 tile = intel_tile_width_bytes(fb, color_plane); 1825 1826 vtd_guard = max(vtd_guard, DIV_ROUND_UP(stride, tile)); 1827 } 1828 1829 return vtd_guard; 1830 } 1831 1832 static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) 1833 { 1834 struct intel_display *display = to_intel_display(plane_state); 1835 struct drm_framebuffer *fb = plane_state->hw.fb; 1836 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1837 unsigned int rotation = plane_state->hw.rotation; 1838 int i, num_planes = fb->format->num_planes; 1839 unsigned int src_x, src_y; 1840 unsigned int src_w, src_h; 1841 u32 gtt_offset = 0; 1842 1843 intel_fb_view_init(display, &plane_state->view, 1844 drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED : 1845 I915_GTT_VIEW_REMAPPED); 1846 1847 src_x = plane_state->uapi.src.x1 >> 16; 1848 src_y = plane_state->uapi.src.y1 >> 16; 1849 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1850 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1851 1852 drm_WARN_ON(display->drm, intel_fb_is_ccs_modifier(fb->modifier)); 1853 1854 /* Make src coordinates relative to the viewport */ 1855 drm_rect_translate(&plane_state->uapi.src, 1856 -(src_x << 16), -(src_y << 16)); 1857 1858 /* Rotate src coordinates to match rotated GTT view */ 1859 if (drm_rotation_90_or_270(rotation)) 1860 drm_rect_rotate(&plane_state->uapi.src, 1861 src_w << 16, src_h << 16, 1862 DRM_MODE_ROTATE_270); 1863 1864 for (i = 0; i < num_planes; i++) { 1865 unsigned int hsub = i ? fb->format->hsub : 1; 1866 unsigned int vsub = i ? fb->format->vsub : 1; 1867 struct fb_plane_view_dims view_dims; 1868 unsigned int width, height; 1869 unsigned int x, y; 1870 u32 offset; 1871 1872 x = src_x / hsub; 1873 y = src_y / vsub; 1874 width = src_w / hsub; 1875 height = src_h / vsub; 1876 1877 init_plane_view_dims(intel_fb, i, width, height, &view_dims); 1878 1879 /* 1880 * First pixel of the src viewport from the 1881 * start of the normal gtt mapping. 1882 */ 1883 x += intel_fb->normal_view.color_plane[i].x; 1884 y += intel_fb->normal_view.color_plane[i].y; 1885 1886 offset = calc_plane_aligned_offset(intel_fb, i, &x, &y); 1887 1888 gtt_offset += calc_plane_remap_info(intel_fb, i, &view_dims, 1889 offset, gtt_offset, x, y, 1890 &plane_state->view); 1891 } 1892 } 1893 1894 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 1895 { 1896 unsigned int size = 0; 1897 int i; 1898 1899 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 1900 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 1901 1902 return size; 1903 } 1904 1905 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 1906 { 1907 unsigned int size = 0; 1908 int i; 1909 1910 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 1911 unsigned int plane_size; 1912 1913 if (rem_info->plane[i].linear) 1914 plane_size = rem_info->plane[i].size; 1915 else 1916 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 1917 1918 if (plane_size == 0) 1919 continue; 1920 1921 if (rem_info->plane_alignment) 1922 size = ALIGN(size, rem_info->plane_alignment); 1923 1924 size += plane_size; 1925 } 1926 1927 return size; 1928 } 1929 1930 void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation, 1931 struct intel_fb_view *view) 1932 { 1933 if (drm_rotation_90_or_270(rotation)) 1934 *view = fb->rotated_view; 1935 else if (intel_fb_needs_pot_stride_remap(fb)) 1936 *view = fb->remapped_view; 1937 else 1938 *view = fb->normal_view; 1939 } 1940 1941 /* 1942 * Convert the x/y offsets into a linear offset. 1943 * Only valid with 0/180 degree rotation, which is fine since linear 1944 * offset is only used with linear buffers on pre-hsw and tiled buffers 1945 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 1946 */ 1947 u32 intel_fb_xy_to_linear(int x, int y, 1948 const struct intel_plane_state *plane_state, 1949 int color_plane) 1950 { 1951 const struct drm_framebuffer *fb = plane_state->hw.fb; 1952 unsigned int cpp = fb->format->cpp[color_plane]; 1953 unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride; 1954 1955 return y * pitch + x * cpp; 1956 } 1957 1958 /* 1959 * Add the x/y offsets derived from fb->offsets[] to the user 1960 * specified plane src x/y offsets. The resulting x/y offsets 1961 * specify the start of scanout from the beginning of the gtt mapping. 1962 */ 1963 void intel_add_fb_offsets(int *x, int *y, 1964 const struct intel_plane_state *plane_state, 1965 int color_plane) 1966 1967 { 1968 *x += plane_state->view.color_plane[color_plane].x; 1969 *y += plane_state->view.color_plane[color_plane].y; 1970 } 1971 1972 static 1973 u32 intel_fb_max_stride(struct intel_display *display, 1974 u32 pixel_format, u64 modifier) 1975 { 1976 /* 1977 * Arbitrary limit for gen4+ chosen to match the 1978 * render engine max stride. 1979 * 1980 * The new CCS hash mode makes remapping impossible 1981 */ 1982 if (DISPLAY_VER(display) < 4 || intel_fb_is_ccs_modifier(modifier) || 1983 intel_fb_modifier_uses_dpt(display, modifier)) 1984 return intel_plane_fb_max_stride(display->drm, pixel_format, modifier); 1985 else if (DISPLAY_VER(display) >= 7) 1986 return 256 * 1024; 1987 else 1988 return 128 * 1024; 1989 } 1990 1991 static unsigned int 1992 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) 1993 { 1994 struct intel_display *display = to_intel_display(fb->dev); 1995 unsigned int tile_width; 1996 1997 if (is_surface_linear(fb, color_plane)) { 1998 unsigned int max_stride = intel_plane_fb_max_stride(display->drm, 1999 fb->format->format, 2000 fb->modifier); 2001 2002 /* 2003 * To make remapping with linear generally feasible 2004 * we need the stride to be page aligned. 2005 */ 2006 if (fb->pitches[color_plane] > max_stride && 2007 !intel_fb_is_ccs_modifier(fb->modifier)) 2008 return intel_tile_size(display); 2009 else 2010 return 64; 2011 } 2012 2013 tile_width = intel_tile_width_bytes(fb, color_plane); 2014 if (intel_fb_is_ccs_modifier(fb->modifier)) { 2015 /* 2016 * On TGL the surface stride must be 4 tile aligned, mapped by 2017 * one 64 byte cacheline on the CCS AUX surface. 2018 */ 2019 if (DISPLAY_VER(display) >= 12) 2020 tile_width *= 4; 2021 /* 2022 * Display WA #0531: skl,bxt,kbl,glk 2023 * 2024 * Render decompression and plane width > 3840 2025 * combined with horizontal panning requires the 2026 * plane stride to be a multiple of 4. We'll just 2027 * require the entire fb to accommodate that to avoid 2028 * potential runtime errors at plane configuration time. 2029 */ 2030 else if ((DISPLAY_VER(display) == 9 || display->platform.geminilake) && 2031 color_plane == 0 && fb->width > 3840) 2032 tile_width *= 4; 2033 } 2034 return tile_width; 2035 } 2036 2037 static int intel_plane_check_stride(const struct intel_plane_state *plane_state) 2038 { 2039 struct intel_display *display = to_intel_display(plane_state); 2040 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2041 const struct drm_framebuffer *fb = plane_state->hw.fb; 2042 unsigned int rotation = plane_state->hw.rotation; 2043 u32 stride, max_stride; 2044 2045 /* 2046 * We ignore stride for all invisible planes that 2047 * can be remapped. Otherwise we could end up 2048 * with a false positive when the remapping didn't 2049 * kick in due the plane being invisible. 2050 */ 2051 if (intel_plane_can_remap(plane_state) && 2052 !plane_state->uapi.visible) 2053 return 0; 2054 2055 /* FIXME other color planes? */ 2056 stride = plane_state->view.color_plane[0].mapping_stride; 2057 max_stride = plane->max_stride(plane, fb->format->format, 2058 fb->modifier, rotation); 2059 2060 if (stride > max_stride) { 2061 drm_dbg_kms(display->drm, 2062 "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n", 2063 fb->base.id, stride, 2064 plane->base.base.id, plane->base.name, max_stride); 2065 return -EINVAL; 2066 } 2067 2068 return 0; 2069 } 2070 2071 int intel_plane_compute_gtt(struct intel_plane_state *plane_state) 2072 { 2073 const struct intel_framebuffer *fb = 2074 to_intel_framebuffer(plane_state->hw.fb); 2075 unsigned int rotation = plane_state->hw.rotation; 2076 2077 if (!fb) 2078 return 0; 2079 2080 if (intel_plane_needs_remap(plane_state)) { 2081 intel_plane_remap_gtt(plane_state); 2082 2083 /* 2084 * Sometimes even remapping can't overcome 2085 * the stride limitations :( Can happen with 2086 * big plane sizes and suitably misaligned 2087 * offsets. 2088 */ 2089 return intel_plane_check_stride(plane_state); 2090 } 2091 2092 intel_fb_fill_view(fb, rotation, &plane_state->view); 2093 2094 /* Rotate src coordinates to match rotated GTT view */ 2095 if (drm_rotation_90_or_270(rotation)) 2096 drm_rect_rotate(&plane_state->uapi.src, 2097 fb->base.width << 16, fb->base.height << 16, 2098 DRM_MODE_ROTATE_270); 2099 2100 return intel_plane_check_stride(plane_state); 2101 } 2102 2103 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 2104 { 2105 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 2106 2107 drm_framebuffer_cleanup(fb); 2108 2109 if (intel_fb_uses_dpt(fb)) 2110 intel_dpt_destroy(intel_fb->dpt_vm); 2111 2112 intel_frontbuffer_put(intel_fb->frontbuffer); 2113 2114 intel_fb_bo_framebuffer_fini(intel_fb_bo(fb)); 2115 2116 kfree(intel_fb); 2117 } 2118 2119 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, 2120 struct drm_file *file, 2121 unsigned int *handle) 2122 { 2123 struct drm_gem_object *obj = intel_fb_bo(fb); 2124 struct intel_display *display = to_intel_display(obj->dev); 2125 2126 if (intel_bo_is_userptr(obj)) { 2127 drm_dbg(display->drm, 2128 "attempting to use a userptr for a framebuffer, denied\n"); 2129 return -EINVAL; 2130 } 2131 2132 return drm_gem_handle_create(file, obj, handle); 2133 } 2134 2135 struct frontbuffer_fence_cb { 2136 struct dma_fence_cb base; 2137 struct intel_frontbuffer *front; 2138 }; 2139 2140 static void intel_user_framebuffer_fence_wake(struct dma_fence *dma, 2141 struct dma_fence_cb *data) 2142 { 2143 struct frontbuffer_fence_cb *cb = container_of(data, typeof(*cb), base); 2144 2145 intel_frontbuffer_queue_flush(cb->front); 2146 kfree(cb); 2147 dma_fence_put(dma); 2148 } 2149 2150 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, 2151 struct drm_file *file, 2152 unsigned int flags, unsigned int color, 2153 struct drm_clip_rect *clips, 2154 unsigned int num_clips) 2155 { 2156 struct drm_gem_object *obj = intel_fb_bo(fb); 2157 struct intel_frontbuffer *front = to_intel_frontbuffer(fb); 2158 struct dma_fence *fence; 2159 struct frontbuffer_fence_cb *cb; 2160 int ret = 0; 2161 2162 if (!atomic_read(&front->bits)) 2163 return 0; 2164 2165 if (dma_resv_test_signaled(obj->resv, dma_resv_usage_rw(false))) 2166 goto flush; 2167 2168 ret = dma_resv_get_singleton(obj->resv, dma_resv_usage_rw(false), 2169 &fence); 2170 if (ret || !fence) 2171 goto flush; 2172 2173 cb = kmalloc(sizeof(*cb), GFP_KERNEL); 2174 if (!cb) { 2175 dma_fence_put(fence); 2176 ret = -ENOMEM; 2177 goto flush; 2178 } 2179 2180 cb->front = front; 2181 2182 intel_frontbuffer_invalidate(front, ORIGIN_DIRTYFB); 2183 2184 ret = dma_fence_add_callback(fence, &cb->base, 2185 intel_user_framebuffer_fence_wake); 2186 if (ret) { 2187 intel_user_framebuffer_fence_wake(fence, &cb->base); 2188 if (ret == -ENOENT) 2189 ret = 0; 2190 } 2191 2192 return ret; 2193 2194 flush: 2195 intel_bo_flush_if_display(obj); 2196 intel_frontbuffer_flush(front, ORIGIN_DIRTYFB); 2197 return ret; 2198 } 2199 2200 static const struct drm_framebuffer_funcs intel_fb_funcs = { 2201 .destroy = intel_user_framebuffer_destroy, 2202 .create_handle = intel_user_framebuffer_create_handle, 2203 .dirty = intel_user_framebuffer_dirty, 2204 }; 2205 2206 int intel_framebuffer_init(struct intel_framebuffer *intel_fb, 2207 struct drm_gem_object *obj, 2208 struct drm_mode_fb_cmd2 *mode_cmd) 2209 { 2210 struct intel_display *display = to_intel_display(obj->dev); 2211 struct drm_framebuffer *fb = &intel_fb->base; 2212 u32 max_stride; 2213 int ret = -EINVAL; 2214 int i; 2215 2216 ret = intel_fb_bo_framebuffer_init(fb, obj, mode_cmd); 2217 if (ret) 2218 return ret; 2219 2220 intel_fb->frontbuffer = intel_frontbuffer_get(obj); 2221 if (!intel_fb->frontbuffer) { 2222 ret = -ENOMEM; 2223 goto err; 2224 } 2225 2226 ret = -EINVAL; 2227 if (!drm_any_plane_has_format(display->drm, 2228 mode_cmd->pixel_format, 2229 mode_cmd->modifier[0])) { 2230 drm_dbg_kms(display->drm, 2231 "unsupported pixel format %p4cc / modifier 0x%llx\n", 2232 &mode_cmd->pixel_format, mode_cmd->modifier[0]); 2233 goto err_frontbuffer_put; 2234 } 2235 2236 max_stride = intel_fb_max_stride(display, mode_cmd->pixel_format, 2237 mode_cmd->modifier[0]); 2238 if (mode_cmd->pitches[0] > max_stride) { 2239 drm_dbg_kms(display->drm, 2240 "%s pitch (%u) must be at most %d\n", 2241 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? 2242 "tiled" : "linear", 2243 mode_cmd->pitches[0], max_stride); 2244 goto err_frontbuffer_put; 2245 } 2246 2247 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ 2248 if (mode_cmd->offsets[0] != 0) { 2249 drm_dbg_kms(display->drm, 2250 "plane 0 offset (0x%08x) must be 0\n", 2251 mode_cmd->offsets[0]); 2252 goto err_frontbuffer_put; 2253 } 2254 2255 drm_helper_mode_fill_fb_struct(display->drm, fb, mode_cmd); 2256 2257 for (i = 0; i < fb->format->num_planes; i++) { 2258 unsigned int stride_alignment; 2259 2260 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { 2261 drm_dbg_kms(display->drm, "bad plane %d handle\n", i); 2262 goto err_frontbuffer_put; 2263 } 2264 2265 stride_alignment = intel_fb_stride_alignment(fb, i); 2266 if (fb->pitches[i] & (stride_alignment - 1)) { 2267 drm_dbg_kms(display->drm, 2268 "plane %d pitch (%d) must be at least %u byte aligned\n", 2269 i, fb->pitches[i], stride_alignment); 2270 goto err_frontbuffer_put; 2271 } 2272 2273 if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) { 2274 unsigned int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i); 2275 2276 if (fb->pitches[i] != ccs_aux_stride) { 2277 drm_dbg_kms(display->drm, 2278 "ccs aux plane %d pitch (%d) must be %d\n", 2279 i, fb->pitches[i], ccs_aux_stride); 2280 goto err_frontbuffer_put; 2281 } 2282 } 2283 2284 fb->obj[i] = obj; 2285 } 2286 2287 ret = intel_fill_fb_info(display, intel_fb); 2288 if (ret) 2289 goto err_frontbuffer_put; 2290 2291 if (intel_fb_uses_dpt(fb)) { 2292 struct i915_address_space *vm; 2293 2294 vm = intel_dpt_create(intel_fb); 2295 if (IS_ERR(vm)) { 2296 drm_dbg_kms(display->drm, "failed to create DPT\n"); 2297 ret = PTR_ERR(vm); 2298 goto err_frontbuffer_put; 2299 } 2300 2301 intel_fb->dpt_vm = vm; 2302 } 2303 2304 ret = drm_framebuffer_init(display->drm, fb, &intel_fb_funcs); 2305 if (ret) { 2306 drm_err(display->drm, "framebuffer init failed %d\n", ret); 2307 goto err_free_dpt; 2308 } 2309 2310 return 0; 2311 2312 err_free_dpt: 2313 if (intel_fb_uses_dpt(fb)) 2314 intel_dpt_destroy(intel_fb->dpt_vm); 2315 err_frontbuffer_put: 2316 intel_frontbuffer_put(intel_fb->frontbuffer); 2317 err: 2318 intel_fb_bo_framebuffer_fini(obj); 2319 return ret; 2320 } 2321 2322 struct drm_framebuffer * 2323 intel_user_framebuffer_create(struct drm_device *dev, 2324 struct drm_file *filp, 2325 const struct drm_mode_fb_cmd2 *user_mode_cmd) 2326 { 2327 struct drm_framebuffer *fb; 2328 struct drm_gem_object *obj; 2329 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; 2330 2331 obj = intel_fb_bo_lookup_valid_bo(dev, filp, &mode_cmd); 2332 if (IS_ERR(obj)) 2333 return ERR_CAST(obj); 2334 2335 fb = intel_framebuffer_create(obj, &mode_cmd); 2336 drm_gem_object_put(obj); 2337 2338 return fb; 2339 } 2340 2341 struct drm_framebuffer * 2342 intel_framebuffer_create(struct drm_gem_object *obj, 2343 struct drm_mode_fb_cmd2 *mode_cmd) 2344 { 2345 struct intel_framebuffer *intel_fb; 2346 int ret; 2347 2348 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 2349 if (!intel_fb) 2350 return ERR_PTR(-ENOMEM); 2351 2352 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); 2353 if (ret) 2354 goto err; 2355 2356 return &intel_fb->base; 2357 2358 err: 2359 kfree(intel_fb); 2360 return ERR_PTR(ret); 2361 } 2362 2363 struct drm_gem_object *intel_fb_bo(const struct drm_framebuffer *fb) 2364 { 2365 return fb ? fb->obj[0] : NULL; 2366 } 2367