1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Quadrature Encoder Peripheral driver 4 * 5 * Copyright (C) 2019-2021 Intel Corporation 6 * 7 * Author: Felipe Balbi (Intel) 8 * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com> 9 * Author: Raymond Tan <raymond.tan@intel.com> 10 */ 11 #include <linux/counter.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/pci.h> 16 #include <linux/pm_runtime.h> 17 18 #define INTEL_QEPCON 0x00 19 #define INTEL_QEPFLT 0x04 20 #define INTEL_QEPCOUNT 0x08 21 #define INTEL_QEPMAX 0x0c 22 #define INTEL_QEPWDT 0x10 23 #define INTEL_QEPCAPDIV 0x14 24 #define INTEL_QEPCNTR 0x18 25 #define INTEL_QEPCAPBUF 0x1c 26 #define INTEL_QEPINT_STAT 0x20 27 #define INTEL_QEPINT_MASK 0x24 28 29 /* QEPCON */ 30 #define INTEL_QEPCON_EN BIT(0) 31 #define INTEL_QEPCON_FLT_EN BIT(1) 32 #define INTEL_QEPCON_EDGE_A BIT(2) 33 #define INTEL_QEPCON_EDGE_B BIT(3) 34 #define INTEL_QEPCON_EDGE_INDX BIT(4) 35 #define INTEL_QEPCON_SWPAB BIT(5) 36 #define INTEL_QEPCON_OP_MODE BIT(6) 37 #define INTEL_QEPCON_PH_ERR BIT(7) 38 #define INTEL_QEPCON_COUNT_RST_MODE BIT(8) 39 #define INTEL_QEPCON_INDX_GATING_MASK GENMASK(10, 9) 40 #define INTEL_QEPCON_INDX_GATING(n) (((n) & 3) << 9) 41 #define INTEL_QEPCON_INDX_PAL_PBL INTEL_QEPCON_INDX_GATING(0) 42 #define INTEL_QEPCON_INDX_PAL_PBH INTEL_QEPCON_INDX_GATING(1) 43 #define INTEL_QEPCON_INDX_PAH_PBL INTEL_QEPCON_INDX_GATING(2) 44 #define INTEL_QEPCON_INDX_PAH_PBH INTEL_QEPCON_INDX_GATING(3) 45 #define INTEL_QEPCON_CAP_MODE BIT(11) 46 #define INTEL_QEPCON_FIFO_THRE_MASK GENMASK(14, 12) 47 #define INTEL_QEPCON_FIFO_THRE(n) ((((n) - 1) & 7) << 12) 48 #define INTEL_QEPCON_FIFO_EMPTY BIT(15) 49 50 /* QEPFLT */ 51 #define INTEL_QEPFLT_MAX_COUNT(n) ((n) & 0x1fffff) 52 53 /* QEPINT */ 54 #define INTEL_QEPINT_FIFOCRIT BIT(5) 55 #define INTEL_QEPINT_FIFOENTRY BIT(4) 56 #define INTEL_QEPINT_QEPDIR BIT(3) 57 #define INTEL_QEPINT_QEPRST_UP BIT(2) 58 #define INTEL_QEPINT_QEPRST_DOWN BIT(1) 59 #define INTEL_QEPINT_WDT BIT(0) 60 61 #define INTEL_QEPINT_MASK_ALL GENMASK(5, 0) 62 63 #define INTEL_QEP_CLK_PERIOD_NS 10 64 65 struct intel_qep { 66 struct mutex lock; 67 struct device *dev; 68 void __iomem *regs; 69 bool enabled; 70 /* Context save registers */ 71 u32 qepcon; 72 u32 qepflt; 73 u32 qepmax; 74 }; 75 76 static inline u32 intel_qep_readl(struct intel_qep *qep, u32 offset) 77 { 78 return readl(qep->regs + offset); 79 } 80 81 static inline void intel_qep_writel(struct intel_qep *qep, 82 u32 offset, u32 value) 83 { 84 writel(value, qep->regs + offset); 85 } 86 87 static void intel_qep_init(struct intel_qep *qep) 88 { 89 u32 reg; 90 91 reg = intel_qep_readl(qep, INTEL_QEPCON); 92 reg &= ~INTEL_QEPCON_EN; 93 intel_qep_writel(qep, INTEL_QEPCON, reg); 94 qep->enabled = false; 95 /* 96 * Make sure peripheral is disabled by flushing the write with 97 * a dummy read 98 */ 99 reg = intel_qep_readl(qep, INTEL_QEPCON); 100 101 reg &= ~(INTEL_QEPCON_OP_MODE | INTEL_QEPCON_FLT_EN); 102 reg |= INTEL_QEPCON_EDGE_A | INTEL_QEPCON_EDGE_B | 103 INTEL_QEPCON_EDGE_INDX | INTEL_QEPCON_COUNT_RST_MODE; 104 intel_qep_writel(qep, INTEL_QEPCON, reg); 105 intel_qep_writel(qep, INTEL_QEPINT_MASK, INTEL_QEPINT_MASK_ALL); 106 } 107 108 static int intel_qep_count_read(struct counter_device *counter, 109 struct counter_count *count, u64 *val) 110 { 111 struct intel_qep *const qep = counter_priv(counter); 112 113 pm_runtime_get_sync(qep->dev); 114 *val = intel_qep_readl(qep, INTEL_QEPCOUNT); 115 pm_runtime_put(qep->dev); 116 117 return 0; 118 } 119 120 static const enum counter_function intel_qep_count_functions[] = { 121 COUNTER_FUNCTION_QUADRATURE_X4, 122 }; 123 124 static int intel_qep_function_read(struct counter_device *counter, 125 struct counter_count *count, 126 enum counter_function *function) 127 { 128 *function = COUNTER_FUNCTION_QUADRATURE_X4; 129 130 return 0; 131 } 132 133 static const enum counter_synapse_action intel_qep_synapse_actions[] = { 134 COUNTER_SYNAPSE_ACTION_BOTH_EDGES, 135 }; 136 137 static int intel_qep_action_read(struct counter_device *counter, 138 struct counter_count *count, 139 struct counter_synapse *synapse, 140 enum counter_synapse_action *action) 141 { 142 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 143 return 0; 144 } 145 146 static const struct counter_ops intel_qep_counter_ops = { 147 .count_read = intel_qep_count_read, 148 .function_read = intel_qep_function_read, 149 .action_read = intel_qep_action_read, 150 }; 151 152 #define INTEL_QEP_SIGNAL(_id, _name) { \ 153 .id = (_id), \ 154 .name = (_name), \ 155 } 156 157 static struct counter_signal intel_qep_signals[] = { 158 INTEL_QEP_SIGNAL(0, "Phase A"), 159 INTEL_QEP_SIGNAL(1, "Phase B"), 160 INTEL_QEP_SIGNAL(2, "Index"), 161 }; 162 163 #define INTEL_QEP_SYNAPSE(_signal_id) { \ 164 .actions_list = intel_qep_synapse_actions, \ 165 .num_actions = ARRAY_SIZE(intel_qep_synapse_actions), \ 166 .signal = &intel_qep_signals[(_signal_id)], \ 167 } 168 169 static struct counter_synapse intel_qep_count_synapses[] = { 170 INTEL_QEP_SYNAPSE(0), 171 INTEL_QEP_SYNAPSE(1), 172 INTEL_QEP_SYNAPSE(2), 173 }; 174 175 static int intel_qep_ceiling_read(struct counter_device *counter, 176 struct counter_count *count, u64 *ceiling) 177 { 178 struct intel_qep *qep = counter_priv(counter); 179 180 pm_runtime_get_sync(qep->dev); 181 *ceiling = intel_qep_readl(qep, INTEL_QEPMAX); 182 pm_runtime_put(qep->dev); 183 184 return 0; 185 } 186 187 static int intel_qep_ceiling_write(struct counter_device *counter, 188 struct counter_count *count, u64 max) 189 { 190 struct intel_qep *qep = counter_priv(counter); 191 192 /* Intel QEP ceiling configuration only supports 32-bit values */ 193 if (max != (u32)max) 194 return -ERANGE; 195 196 guard(mutex)(&qep->lock); 197 198 if (qep->enabled) 199 return -EBUSY; 200 201 pm_runtime_get_sync(qep->dev); 202 intel_qep_writel(qep, INTEL_QEPMAX, max); 203 pm_runtime_put(qep->dev); 204 205 return 0; 206 } 207 208 static int intel_qep_enable_read(struct counter_device *counter, 209 struct counter_count *count, u8 *enable) 210 { 211 struct intel_qep *qep = counter_priv(counter); 212 213 *enable = qep->enabled; 214 215 return 0; 216 } 217 218 static int intel_qep_enable_write(struct counter_device *counter, 219 struct counter_count *count, u8 val) 220 { 221 struct intel_qep *qep = counter_priv(counter); 222 u32 reg; 223 bool changed; 224 225 guard(mutex)(&qep->lock); 226 227 changed = val ^ qep->enabled; 228 if (!changed) 229 return 0; 230 231 pm_runtime_get_sync(qep->dev); 232 reg = intel_qep_readl(qep, INTEL_QEPCON); 233 if (val) { 234 /* Enable peripheral and keep runtime PM always on */ 235 reg |= INTEL_QEPCON_EN; 236 pm_runtime_get_noresume(qep->dev); 237 } else { 238 /* Let runtime PM be idle and disable peripheral */ 239 pm_runtime_put_noidle(qep->dev); 240 reg &= ~INTEL_QEPCON_EN; 241 } 242 intel_qep_writel(qep, INTEL_QEPCON, reg); 243 pm_runtime_put(qep->dev); 244 qep->enabled = val; 245 246 return 0; 247 } 248 249 static int intel_qep_spike_filter_ns_read(struct counter_device *counter, 250 struct counter_count *count, 251 u64 *length) 252 { 253 struct intel_qep *qep = counter_priv(counter); 254 u32 reg; 255 256 pm_runtime_get_sync(qep->dev); 257 reg = intel_qep_readl(qep, INTEL_QEPCON); 258 if (!(reg & INTEL_QEPCON_FLT_EN)) { 259 pm_runtime_put(qep->dev); 260 return 0; 261 } 262 reg = INTEL_QEPFLT_MAX_COUNT(intel_qep_readl(qep, INTEL_QEPFLT)); 263 pm_runtime_put(qep->dev); 264 265 *length = (reg + 2) * INTEL_QEP_CLK_PERIOD_NS; 266 267 return 0; 268 } 269 270 static int intel_qep_spike_filter_ns_write(struct counter_device *counter, 271 struct counter_count *count, 272 u64 length) 273 { 274 struct intel_qep *qep = counter_priv(counter); 275 u32 reg; 276 bool enable; 277 278 /* 279 * Spike filter length is (MAX_COUNT + 2) clock periods. 280 * Disable filter when userspace writes 0, enable for valid 281 * nanoseconds values and error out otherwise. 282 */ 283 do_div(length, INTEL_QEP_CLK_PERIOD_NS); 284 if (length == 0) { 285 enable = false; 286 length = 0; 287 } else if (length >= 2) { 288 enable = true; 289 length -= 2; 290 } else { 291 return -EINVAL; 292 } 293 294 if (length > INTEL_QEPFLT_MAX_COUNT(length)) 295 return -ERANGE; 296 297 guard(mutex)(&qep->lock); 298 299 if (qep->enabled) 300 return -EBUSY; 301 302 pm_runtime_get_sync(qep->dev); 303 reg = intel_qep_readl(qep, INTEL_QEPCON); 304 if (enable) 305 reg |= INTEL_QEPCON_FLT_EN; 306 else 307 reg &= ~INTEL_QEPCON_FLT_EN; 308 intel_qep_writel(qep, INTEL_QEPFLT, length); 309 intel_qep_writel(qep, INTEL_QEPCON, reg); 310 pm_runtime_put(qep->dev); 311 312 return 0; 313 } 314 315 static int intel_qep_preset_enable_read(struct counter_device *counter, 316 struct counter_count *count, 317 u8 *preset_enable) 318 { 319 struct intel_qep *qep = counter_priv(counter); 320 u32 reg; 321 322 pm_runtime_get_sync(qep->dev); 323 reg = intel_qep_readl(qep, INTEL_QEPCON); 324 pm_runtime_put(qep->dev); 325 326 *preset_enable = !(reg & INTEL_QEPCON_COUNT_RST_MODE); 327 328 return 0; 329 } 330 331 static int intel_qep_preset_enable_write(struct counter_device *counter, 332 struct counter_count *count, u8 val) 333 { 334 struct intel_qep *qep = counter_priv(counter); 335 u32 reg; 336 337 guard(mutex)(&qep->lock); 338 339 if (qep->enabled) 340 return -EBUSY; 341 342 pm_runtime_get_sync(qep->dev); 343 reg = intel_qep_readl(qep, INTEL_QEPCON); 344 if (val) 345 reg &= ~INTEL_QEPCON_COUNT_RST_MODE; 346 else 347 reg |= INTEL_QEPCON_COUNT_RST_MODE; 348 349 intel_qep_writel(qep, INTEL_QEPCON, reg); 350 pm_runtime_put(qep->dev); 351 352 return 0; 353 } 354 355 static struct counter_comp intel_qep_count_ext[] = { 356 COUNTER_COMP_ENABLE(intel_qep_enable_read, intel_qep_enable_write), 357 COUNTER_COMP_CEILING(intel_qep_ceiling_read, intel_qep_ceiling_write), 358 COUNTER_COMP_PRESET_ENABLE(intel_qep_preset_enable_read, 359 intel_qep_preset_enable_write), 360 COUNTER_COMP_COUNT_U64("spike_filter_ns", 361 intel_qep_spike_filter_ns_read, 362 intel_qep_spike_filter_ns_write), 363 }; 364 365 static struct counter_count intel_qep_counter_count[] = { 366 { 367 .id = 0, 368 .name = "Channel 1 Count", 369 .functions_list = intel_qep_count_functions, 370 .num_functions = ARRAY_SIZE(intel_qep_count_functions), 371 .synapses = intel_qep_count_synapses, 372 .num_synapses = ARRAY_SIZE(intel_qep_count_synapses), 373 .ext = intel_qep_count_ext, 374 .num_ext = ARRAY_SIZE(intel_qep_count_ext), 375 }, 376 }; 377 378 static int intel_qep_probe(struct pci_dev *pci, const struct pci_device_id *id) 379 { 380 struct counter_device *counter; 381 struct intel_qep *qep; 382 struct device *dev = &pci->dev; 383 void __iomem *regs; 384 int ret; 385 386 counter = devm_counter_alloc(dev, sizeof(*qep)); 387 if (!counter) 388 return -ENOMEM; 389 qep = counter_priv(counter); 390 391 ret = pcim_enable_device(pci); 392 if (ret) 393 return ret; 394 395 pci_set_master(pci); 396 397 regs = pcim_iomap_region(pci, 0, pci_name(pci)); 398 if (IS_ERR(regs)) 399 return PTR_ERR(regs); 400 401 qep->dev = dev; 402 qep->regs = regs; 403 ret = devm_mutex_init(dev, &qep->lock); 404 if (ret) 405 return ret; 406 407 intel_qep_init(qep); 408 pci_set_drvdata(pci, qep); 409 410 counter->name = pci_name(pci); 411 counter->parent = dev; 412 counter->ops = &intel_qep_counter_ops; 413 counter->counts = intel_qep_counter_count; 414 counter->num_counts = ARRAY_SIZE(intel_qep_counter_count); 415 counter->signals = intel_qep_signals; 416 counter->num_signals = ARRAY_SIZE(intel_qep_signals); 417 qep->enabled = false; 418 419 pm_runtime_put(dev); 420 pm_runtime_allow(dev); 421 422 ret = devm_counter_add(&pci->dev, counter); 423 if (ret < 0) 424 return dev_err_probe(&pci->dev, ret, "Failed to add counter\n"); 425 426 return 0; 427 } 428 429 static void intel_qep_remove(struct pci_dev *pci) 430 { 431 struct intel_qep *qep = pci_get_drvdata(pci); 432 struct device *dev = &pci->dev; 433 434 pm_runtime_forbid(dev); 435 if (!qep->enabled) 436 pm_runtime_get(dev); 437 438 intel_qep_writel(qep, INTEL_QEPCON, 0); 439 } 440 441 static int __maybe_unused intel_qep_suspend(struct device *dev) 442 { 443 struct pci_dev *pdev = to_pci_dev(dev); 444 struct intel_qep *qep = pci_get_drvdata(pdev); 445 446 qep->qepcon = intel_qep_readl(qep, INTEL_QEPCON); 447 qep->qepflt = intel_qep_readl(qep, INTEL_QEPFLT); 448 qep->qepmax = intel_qep_readl(qep, INTEL_QEPMAX); 449 450 return 0; 451 } 452 453 static int __maybe_unused intel_qep_resume(struct device *dev) 454 { 455 struct pci_dev *pdev = to_pci_dev(dev); 456 struct intel_qep *qep = pci_get_drvdata(pdev); 457 458 /* 459 * Make sure peripheral is disabled when restoring registers and 460 * control register bits that are writable only when the peripheral 461 * is disabled 462 */ 463 intel_qep_writel(qep, INTEL_QEPCON, 0); 464 intel_qep_readl(qep, INTEL_QEPCON); 465 466 intel_qep_writel(qep, INTEL_QEPFLT, qep->qepflt); 467 intel_qep_writel(qep, INTEL_QEPMAX, qep->qepmax); 468 intel_qep_writel(qep, INTEL_QEPINT_MASK, INTEL_QEPINT_MASK_ALL); 469 470 /* Restore all other control register bits except enable status */ 471 intel_qep_writel(qep, INTEL_QEPCON, qep->qepcon & ~INTEL_QEPCON_EN); 472 intel_qep_readl(qep, INTEL_QEPCON); 473 474 /* Restore enable status */ 475 intel_qep_writel(qep, INTEL_QEPCON, qep->qepcon); 476 477 return 0; 478 } 479 480 static UNIVERSAL_DEV_PM_OPS(intel_qep_pm_ops, 481 intel_qep_suspend, intel_qep_resume, NULL); 482 483 static const struct pci_device_id intel_qep_id_table[] = { 484 /* EHL */ 485 { PCI_VDEVICE(INTEL, 0x4bc3), }, 486 { PCI_VDEVICE(INTEL, 0x4b81), }, 487 { PCI_VDEVICE(INTEL, 0x4b82), }, 488 { PCI_VDEVICE(INTEL, 0x4b83), }, 489 { } /* Terminating Entry */ 490 }; 491 MODULE_DEVICE_TABLE(pci, intel_qep_id_table); 492 493 static struct pci_driver intel_qep_driver = { 494 .name = "intel-qep", 495 .id_table = intel_qep_id_table, 496 .probe = intel_qep_probe, 497 .remove = intel_qep_remove, 498 .driver = { 499 .pm = &intel_qep_pm_ops, 500 } 501 }; 502 503 module_pci_driver(intel_qep_driver); 504 505 MODULE_AUTHOR("Felipe Balbi (Intel)"); 506 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>"); 507 MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>"); 508 MODULE_LICENSE("GPL"); 509 MODULE_DESCRIPTION("Intel Quadrature Encoder Peripheral driver"); 510 MODULE_IMPORT_NS("COUNTER"); 511