1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17 #include <linux/kvm_host.h>
18
19 #include <asm/cpufeature.h>
20 #include <asm/debugreg.h>
21 #include <asm/hardirq.h>
22 #include <asm/intel-family.h>
23 #include <asm/intel_pt.h>
24 #include <asm/apic.h>
25 #include <asm/cpu_device_id.h>
26
27 #include "../perf_event.h"
28
29 /*
30 * Intel PerfMon, used on Core and later.
31 */
32 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
33 {
34 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
35 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
36 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
37 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
38 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
39 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
40 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
41 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
42 };
43
44 static struct event_constraint intel_core_event_constraints[] __read_mostly =
45 {
46 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
47 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
48 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
49 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
50 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
51 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
52 EVENT_CONSTRAINT_END
53 };
54
55 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
56 {
57 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
58 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
59 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
60 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
61 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
62 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
63 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
64 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
65 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
66 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
67 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
68 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
69 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
70 EVENT_CONSTRAINT_END
71 };
72
73 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
74 {
75 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
76 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
77 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
78 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
79 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
80 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
81 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
82 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
83 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
84 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
85 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
86 EVENT_CONSTRAINT_END
87 };
88
89 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
90 {
91 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
92 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
93 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
94 EVENT_EXTRA_END
95 };
96
97 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
98 {
99 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
100 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
101 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
102 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
103 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
104 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
105 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
106 EVENT_CONSTRAINT_END
107 };
108
109 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
110 {
111 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
112 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
113 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
115 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
118 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
119 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
120 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
121 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
122 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
123
124 /*
125 * When HT is off these events can only run on the bottom 4 counters
126 * When HT is on, they are impacted by the HT bug and require EXCL access
127 */
128 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
129 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
130 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
131 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
132
133 EVENT_CONSTRAINT_END
134 };
135
136 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
137 {
138 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
139 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
140 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
141 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
142 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
143 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
144 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
146 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
149 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
150 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
151
152 /*
153 * When HT is off these events can only run on the bottom 4 counters
154 * When HT is on, they are impacted by the HT bug and require EXCL access
155 */
156 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
157 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
158 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
159 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
160
161 EVENT_CONSTRAINT_END
162 };
163
164 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
165 {
166 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
167 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
168 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
169 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
170 EVENT_EXTRA_END
171 };
172
173 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
174 {
175 EVENT_CONSTRAINT_END
176 };
177
178 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
179 {
180 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
181 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
182 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
183 EVENT_CONSTRAINT_END
184 };
185
186 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
187 {
188 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
189 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
190 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
191 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
192 FIXED_EVENT_CONSTRAINT(0x0500, 4),
193 FIXED_EVENT_CONSTRAINT(0x0600, 5),
194 FIXED_EVENT_CONSTRAINT(0x0700, 6),
195 FIXED_EVENT_CONSTRAINT(0x0800, 7),
196 FIXED_EVENT_CONSTRAINT(0x0900, 8),
197 FIXED_EVENT_CONSTRAINT(0x0a00, 9),
198 FIXED_EVENT_CONSTRAINT(0x0b00, 10),
199 FIXED_EVENT_CONSTRAINT(0x0c00, 11),
200 FIXED_EVENT_CONSTRAINT(0x0d00, 12),
201 FIXED_EVENT_CONSTRAINT(0x0e00, 13),
202 FIXED_EVENT_CONSTRAINT(0x0f00, 14),
203 FIXED_EVENT_CONSTRAINT(0x1000, 15),
204 EVENT_CONSTRAINT_END
205 };
206
207 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
208 {
209 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
210 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
211 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
212 EVENT_CONSTRAINT_END
213 };
214
215 static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
216 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
217 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
218 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
219 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
220 EVENT_CONSTRAINT_END
221 };
222
223 static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
224 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
225 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
226 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
227 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
228 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
229 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
230 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
231 EVENT_CONSTRAINT_END
232 };
233
234 static struct event_constraint intel_skl_event_constraints[] = {
235 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
236 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
237 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
238 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
239
240 /*
241 * when HT is off, these can only run on the bottom 4 counters
242 */
243 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
244 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
245 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
246 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
247 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
248
249 EVENT_CONSTRAINT_END
250 };
251
252 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
253 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
254 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
255 EVENT_EXTRA_END
256 };
257
258 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
259 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
260 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
261 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
262 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
263 EVENT_EXTRA_END
264 };
265
266 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
267 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
268 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
269 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
270 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
271 EVENT_EXTRA_END
272 };
273
274 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
275 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
276 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
277 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
278 /*
279 * Note the low 8 bits eventsel code is not a continuous field, containing
280 * some #GPing bits. These are masked out.
281 */
282 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
283 EVENT_EXTRA_END
284 };
285
286 static struct event_constraint intel_icl_event_constraints[] = {
287 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
288 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
289 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
290 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
291 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
292 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
293 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
294 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
297 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
298 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
299 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
300 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
301 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
302 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
303 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
304 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
305 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
306 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
307 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
308 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
309 INTEL_EVENT_CONSTRAINT(0xef, 0xf),
310 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
311 EVENT_CONSTRAINT_END
312 };
313
314 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
315 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
316 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
317 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
318 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
319 EVENT_EXTRA_END
320 };
321
322 static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
323 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
324 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
325 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
326 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
327 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
328 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
329 EVENT_EXTRA_END
330 };
331
332 static struct event_constraint intel_glc_event_constraints[] = {
333 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
334 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
335 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
336 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
337 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
338 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
339 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
340 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
341 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
342 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
343 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
344 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
345 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
346 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
347
348 INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
349 INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
350 /*
351 * Generally event codes < 0x90 are restricted to counters 0-3.
352 * The 0x2E and 0x3C are exception, which has no restriction.
353 */
354 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
355
356 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
357 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
358 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
359 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
360 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
361 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
362 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
363 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
364 /*
365 * Generally event codes >= 0x90 are likely to have no restrictions.
366 * The exception are defined as above.
367 */
368 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
369
370 EVENT_CONSTRAINT_END
371 };
372
373 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {
374 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
375 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
376 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
377 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
378 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
379 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
380 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
381 EVENT_EXTRA_END
382 };
383
384 static struct event_constraint intel_lnc_event_constraints[] = {
385 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
386 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
387 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
388 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
389 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
390 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
391 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
392 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
393 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
394 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
395 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
396 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
397 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
398 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
399
400 INTEL_EVENT_CONSTRAINT(0x20, 0xf),
401
402 INTEL_UEVENT_CONSTRAINT(0x012a, 0xf),
403 INTEL_UEVENT_CONSTRAINT(0x012b, 0xf),
404 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
405 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
406
407 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff),
408 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff),
409
410 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
411 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
412 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
413 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
414 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1),
415 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
416 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),
417 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
418
419 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
420
421 INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf),
422
423 EVENT_CONSTRAINT_END
424 };
425
426 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
427 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0),
428 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1),
429 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
430 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
431 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
432 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
433 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
434 EVENT_EXTRA_END
435 };
436
437 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
438 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
439 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
440
441 static struct attribute *nhm_mem_events_attrs[] = {
442 EVENT_PTR(mem_ld_nhm),
443 NULL,
444 };
445
446 /*
447 * topdown events for Intel Core CPUs.
448 *
449 * The events are all in slots, which is a free slot in a 4 wide
450 * pipeline. Some events are already reported in slots, for cycle
451 * events we multiply by the pipeline width (4).
452 *
453 * With Hyper Threading on, topdown metrics are either summed or averaged
454 * between the threads of a core: (count_t0 + count_t1).
455 *
456 * For the average case the metric is always scaled to pipeline width,
457 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
458 */
459
460 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
461 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
462 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
463 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
464 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
465 "event=0xe,umask=0x1"); /* uops_issued.any */
466 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
467 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
468 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
469 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
470 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
471 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
472 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
473 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
474 "4", "2");
475
476 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
477 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
478 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
479 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
480 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
481 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84");
482 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85");
483 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
484 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87");
485
486 static struct attribute *snb_events_attrs[] = {
487 EVENT_PTR(td_slots_issued),
488 EVENT_PTR(td_slots_retired),
489 EVENT_PTR(td_fetch_bubbles),
490 EVENT_PTR(td_total_slots),
491 EVENT_PTR(td_total_slots_scale),
492 EVENT_PTR(td_recovery_bubbles),
493 EVENT_PTR(td_recovery_bubbles_scale),
494 NULL,
495 };
496
497 static struct attribute *snb_mem_events_attrs[] = {
498 EVENT_PTR(mem_ld_snb),
499 EVENT_PTR(mem_st_snb),
500 NULL,
501 };
502
503 static struct event_constraint intel_hsw_event_constraints[] = {
504 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
505 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
506 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
507 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
508 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
509 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
510 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
511 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
512 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
513 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
514 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
515 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
516
517 /*
518 * When HT is off these events can only run on the bottom 4 counters
519 * When HT is on, they are impacted by the HT bug and require EXCL access
520 */
521 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
522 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
523 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
524 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
525
526 EVENT_CONSTRAINT_END
527 };
528
529 static struct event_constraint intel_bdw_event_constraints[] = {
530 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
531 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
532 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
533 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
534 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
535 /*
536 * when HT is off, these can only run on the bottom 4 counters
537 */
538 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
539 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
540 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
541 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
542 EVENT_CONSTRAINT_END
543 };
544
intel_pmu_event_map(int hw_event)545 static u64 intel_pmu_event_map(int hw_event)
546 {
547 return intel_perfmon_event_map[hw_event];
548 }
549
550 static __initconst const u64 glc_hw_cache_event_ids
551 [PERF_COUNT_HW_CACHE_MAX]
552 [PERF_COUNT_HW_CACHE_OP_MAX]
553 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
554 {
555 [ C(L1D ) ] = {
556 [ C(OP_READ) ] = {
557 [ C(RESULT_ACCESS) ] = 0x81d0,
558 [ C(RESULT_MISS) ] = 0xe124,
559 },
560 [ C(OP_WRITE) ] = {
561 [ C(RESULT_ACCESS) ] = 0x82d0,
562 },
563 },
564 [ C(L1I ) ] = {
565 [ C(OP_READ) ] = {
566 [ C(RESULT_MISS) ] = 0xe424,
567 },
568 [ C(OP_WRITE) ] = {
569 [ C(RESULT_ACCESS) ] = -1,
570 [ C(RESULT_MISS) ] = -1,
571 },
572 },
573 [ C(LL ) ] = {
574 [ C(OP_READ) ] = {
575 [ C(RESULT_ACCESS) ] = 0x12a,
576 [ C(RESULT_MISS) ] = 0x12a,
577 },
578 [ C(OP_WRITE) ] = {
579 [ C(RESULT_ACCESS) ] = 0x12a,
580 [ C(RESULT_MISS) ] = 0x12a,
581 },
582 },
583 [ C(DTLB) ] = {
584 [ C(OP_READ) ] = {
585 [ C(RESULT_ACCESS) ] = 0x81d0,
586 [ C(RESULT_MISS) ] = 0xe12,
587 },
588 [ C(OP_WRITE) ] = {
589 [ C(RESULT_ACCESS) ] = 0x82d0,
590 [ C(RESULT_MISS) ] = 0xe13,
591 },
592 },
593 [ C(ITLB) ] = {
594 [ C(OP_READ) ] = {
595 [ C(RESULT_ACCESS) ] = -1,
596 [ C(RESULT_MISS) ] = 0xe11,
597 },
598 [ C(OP_WRITE) ] = {
599 [ C(RESULT_ACCESS) ] = -1,
600 [ C(RESULT_MISS) ] = -1,
601 },
602 [ C(OP_PREFETCH) ] = {
603 [ C(RESULT_ACCESS) ] = -1,
604 [ C(RESULT_MISS) ] = -1,
605 },
606 },
607 [ C(BPU ) ] = {
608 [ C(OP_READ) ] = {
609 [ C(RESULT_ACCESS) ] = 0x4c4,
610 [ C(RESULT_MISS) ] = 0x4c5,
611 },
612 [ C(OP_WRITE) ] = {
613 [ C(RESULT_ACCESS) ] = -1,
614 [ C(RESULT_MISS) ] = -1,
615 },
616 [ C(OP_PREFETCH) ] = {
617 [ C(RESULT_ACCESS) ] = -1,
618 [ C(RESULT_MISS) ] = -1,
619 },
620 },
621 [ C(NODE) ] = {
622 [ C(OP_READ) ] = {
623 [ C(RESULT_ACCESS) ] = 0x12a,
624 [ C(RESULT_MISS) ] = 0x12a,
625 },
626 },
627 };
628
629 static __initconst const u64 glc_hw_cache_extra_regs
630 [PERF_COUNT_HW_CACHE_MAX]
631 [PERF_COUNT_HW_CACHE_OP_MAX]
632 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
633 {
634 [ C(LL ) ] = {
635 [ C(OP_READ) ] = {
636 [ C(RESULT_ACCESS) ] = 0x10001,
637 [ C(RESULT_MISS) ] = 0x3fbfc00001,
638 },
639 [ C(OP_WRITE) ] = {
640 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
641 [ C(RESULT_MISS) ] = 0x3f3fc00002,
642 },
643 },
644 [ C(NODE) ] = {
645 [ C(OP_READ) ] = {
646 [ C(RESULT_ACCESS) ] = 0x10c000001,
647 [ C(RESULT_MISS) ] = 0x3fb3000001,
648 },
649 },
650 };
651
652 /*
653 * Notes on the events:
654 * - data reads do not include code reads (comparable to earlier tables)
655 * - data counts include speculative execution (except L1 write, dtlb, bpu)
656 * - remote node access includes remote memory, remote cache, remote mmio.
657 * - prefetches are not included in the counts.
658 * - icache miss does not include decoded icache
659 */
660
661 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
662 #define SKL_DEMAND_RFO BIT_ULL(1)
663 #define SKL_ANY_RESPONSE BIT_ULL(16)
664 #define SKL_SUPPLIER_NONE BIT_ULL(17)
665 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
666 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
667 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
668 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
669 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
670 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
671 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
672 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
673 #define SKL_SPL_HIT BIT_ULL(30)
674 #define SKL_SNOOP_NONE BIT_ULL(31)
675 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
676 #define SKL_SNOOP_MISS BIT_ULL(33)
677 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
678 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
679 #define SKL_SNOOP_HITM BIT_ULL(36)
680 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
681 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
682 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
683 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
684 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
685 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
686 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
687 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
688 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
689 SKL_SNOOP_HITM|SKL_SPL_HIT)
690 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
691 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
692 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
693 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
694 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
695
696 static __initconst const u64 skl_hw_cache_event_ids
697 [PERF_COUNT_HW_CACHE_MAX]
698 [PERF_COUNT_HW_CACHE_OP_MAX]
699 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
700 {
701 [ C(L1D ) ] = {
702 [ C(OP_READ) ] = {
703 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
704 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
705 },
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
708 [ C(RESULT_MISS) ] = 0x0,
709 },
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = 0x0,
712 [ C(RESULT_MISS) ] = 0x0,
713 },
714 },
715 [ C(L1I ) ] = {
716 [ C(OP_READ) ] = {
717 [ C(RESULT_ACCESS) ] = 0x0,
718 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
719 },
720 [ C(OP_WRITE) ] = {
721 [ C(RESULT_ACCESS) ] = -1,
722 [ C(RESULT_MISS) ] = -1,
723 },
724 [ C(OP_PREFETCH) ] = {
725 [ C(RESULT_ACCESS) ] = 0x0,
726 [ C(RESULT_MISS) ] = 0x0,
727 },
728 },
729 [ C(LL ) ] = {
730 [ C(OP_READ) ] = {
731 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
732 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
733 },
734 [ C(OP_WRITE) ] = {
735 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
736 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
737 },
738 [ C(OP_PREFETCH) ] = {
739 [ C(RESULT_ACCESS) ] = 0x0,
740 [ C(RESULT_MISS) ] = 0x0,
741 },
742 },
743 [ C(DTLB) ] = {
744 [ C(OP_READ) ] = {
745 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
746 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
747 },
748 [ C(OP_WRITE) ] = {
749 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
750 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
751 },
752 [ C(OP_PREFETCH) ] = {
753 [ C(RESULT_ACCESS) ] = 0x0,
754 [ C(RESULT_MISS) ] = 0x0,
755 },
756 },
757 [ C(ITLB) ] = {
758 [ C(OP_READ) ] = {
759 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
760 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
761 },
762 [ C(OP_WRITE) ] = {
763 [ C(RESULT_ACCESS) ] = -1,
764 [ C(RESULT_MISS) ] = -1,
765 },
766 [ C(OP_PREFETCH) ] = {
767 [ C(RESULT_ACCESS) ] = -1,
768 [ C(RESULT_MISS) ] = -1,
769 },
770 },
771 [ C(BPU ) ] = {
772 [ C(OP_READ) ] = {
773 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
774 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
775 },
776 [ C(OP_WRITE) ] = {
777 [ C(RESULT_ACCESS) ] = -1,
778 [ C(RESULT_MISS) ] = -1,
779 },
780 [ C(OP_PREFETCH) ] = {
781 [ C(RESULT_ACCESS) ] = -1,
782 [ C(RESULT_MISS) ] = -1,
783 },
784 },
785 [ C(NODE) ] = {
786 [ C(OP_READ) ] = {
787 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
788 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
789 },
790 [ C(OP_WRITE) ] = {
791 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
792 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
793 },
794 [ C(OP_PREFETCH) ] = {
795 [ C(RESULT_ACCESS) ] = 0x0,
796 [ C(RESULT_MISS) ] = 0x0,
797 },
798 },
799 };
800
801 static __initconst const u64 skl_hw_cache_extra_regs
802 [PERF_COUNT_HW_CACHE_MAX]
803 [PERF_COUNT_HW_CACHE_OP_MAX]
804 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
805 {
806 [ C(LL ) ] = {
807 [ C(OP_READ) ] = {
808 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
809 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
810 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
811 SKL_L3_MISS|SKL_ANY_SNOOP|
812 SKL_SUPPLIER_NONE,
813 },
814 [ C(OP_WRITE) ] = {
815 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
816 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
817 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
818 SKL_L3_MISS|SKL_ANY_SNOOP|
819 SKL_SUPPLIER_NONE,
820 },
821 [ C(OP_PREFETCH) ] = {
822 [ C(RESULT_ACCESS) ] = 0x0,
823 [ C(RESULT_MISS) ] = 0x0,
824 },
825 },
826 [ C(NODE) ] = {
827 [ C(OP_READ) ] = {
828 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
829 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
830 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
831 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
832 },
833 [ C(OP_WRITE) ] = {
834 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
835 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
836 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
837 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
838 },
839 [ C(OP_PREFETCH) ] = {
840 [ C(RESULT_ACCESS) ] = 0x0,
841 [ C(RESULT_MISS) ] = 0x0,
842 },
843 },
844 };
845
846 #define SNB_DMND_DATA_RD (1ULL << 0)
847 #define SNB_DMND_RFO (1ULL << 1)
848 #define SNB_DMND_IFETCH (1ULL << 2)
849 #define SNB_DMND_WB (1ULL << 3)
850 #define SNB_PF_DATA_RD (1ULL << 4)
851 #define SNB_PF_RFO (1ULL << 5)
852 #define SNB_PF_IFETCH (1ULL << 6)
853 #define SNB_LLC_DATA_RD (1ULL << 7)
854 #define SNB_LLC_RFO (1ULL << 8)
855 #define SNB_LLC_IFETCH (1ULL << 9)
856 #define SNB_BUS_LOCKS (1ULL << 10)
857 #define SNB_STRM_ST (1ULL << 11)
858 #define SNB_OTHER (1ULL << 15)
859 #define SNB_RESP_ANY (1ULL << 16)
860 #define SNB_NO_SUPP (1ULL << 17)
861 #define SNB_LLC_HITM (1ULL << 18)
862 #define SNB_LLC_HITE (1ULL << 19)
863 #define SNB_LLC_HITS (1ULL << 20)
864 #define SNB_LLC_HITF (1ULL << 21)
865 #define SNB_LOCAL (1ULL << 22)
866 #define SNB_REMOTE (0xffULL << 23)
867 #define SNB_SNP_NONE (1ULL << 31)
868 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
869 #define SNB_SNP_MISS (1ULL << 33)
870 #define SNB_NO_FWD (1ULL << 34)
871 #define SNB_SNP_FWD (1ULL << 35)
872 #define SNB_HITM (1ULL << 36)
873 #define SNB_NON_DRAM (1ULL << 37)
874
875 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
876 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
877 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
878
879 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
880 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
881 SNB_HITM)
882
883 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
884 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
885
886 #define SNB_L3_ACCESS SNB_RESP_ANY
887 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
888
889 static __initconst const u64 snb_hw_cache_extra_regs
890 [PERF_COUNT_HW_CACHE_MAX]
891 [PERF_COUNT_HW_CACHE_OP_MAX]
892 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
893 {
894 [ C(LL ) ] = {
895 [ C(OP_READ) ] = {
896 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
897 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
898 },
899 [ C(OP_WRITE) ] = {
900 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
901 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
902 },
903 [ C(OP_PREFETCH) ] = {
904 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
905 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
906 },
907 },
908 [ C(NODE) ] = {
909 [ C(OP_READ) ] = {
910 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
911 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
912 },
913 [ C(OP_WRITE) ] = {
914 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
915 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
916 },
917 [ C(OP_PREFETCH) ] = {
918 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
919 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
920 },
921 },
922 };
923
924 static __initconst const u64 snb_hw_cache_event_ids
925 [PERF_COUNT_HW_CACHE_MAX]
926 [PERF_COUNT_HW_CACHE_OP_MAX]
927 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
928 {
929 [ C(L1D) ] = {
930 [ C(OP_READ) ] = {
931 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
932 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
933 },
934 [ C(OP_WRITE) ] = {
935 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
936 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
937 },
938 [ C(OP_PREFETCH) ] = {
939 [ C(RESULT_ACCESS) ] = 0x0,
940 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
941 },
942 },
943 [ C(L1I ) ] = {
944 [ C(OP_READ) ] = {
945 [ C(RESULT_ACCESS) ] = 0x0,
946 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
947 },
948 [ C(OP_WRITE) ] = {
949 [ C(RESULT_ACCESS) ] = -1,
950 [ C(RESULT_MISS) ] = -1,
951 },
952 [ C(OP_PREFETCH) ] = {
953 [ C(RESULT_ACCESS) ] = 0x0,
954 [ C(RESULT_MISS) ] = 0x0,
955 },
956 },
957 [ C(LL ) ] = {
958 [ C(OP_READ) ] = {
959 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
960 [ C(RESULT_ACCESS) ] = 0x01b7,
961 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
962 [ C(RESULT_MISS) ] = 0x01b7,
963 },
964 [ C(OP_WRITE) ] = {
965 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
966 [ C(RESULT_ACCESS) ] = 0x01b7,
967 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
968 [ C(RESULT_MISS) ] = 0x01b7,
969 },
970 [ C(OP_PREFETCH) ] = {
971 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
972 [ C(RESULT_ACCESS) ] = 0x01b7,
973 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
974 [ C(RESULT_MISS) ] = 0x01b7,
975 },
976 },
977 [ C(DTLB) ] = {
978 [ C(OP_READ) ] = {
979 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
980 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
981 },
982 [ C(OP_WRITE) ] = {
983 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
984 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
985 },
986 [ C(OP_PREFETCH) ] = {
987 [ C(RESULT_ACCESS) ] = 0x0,
988 [ C(RESULT_MISS) ] = 0x0,
989 },
990 },
991 [ C(ITLB) ] = {
992 [ C(OP_READ) ] = {
993 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
994 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
995 },
996 [ C(OP_WRITE) ] = {
997 [ C(RESULT_ACCESS) ] = -1,
998 [ C(RESULT_MISS) ] = -1,
999 },
1000 [ C(OP_PREFETCH) ] = {
1001 [ C(RESULT_ACCESS) ] = -1,
1002 [ C(RESULT_MISS) ] = -1,
1003 },
1004 },
1005 [ C(BPU ) ] = {
1006 [ C(OP_READ) ] = {
1007 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1008 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1009 },
1010 [ C(OP_WRITE) ] = {
1011 [ C(RESULT_ACCESS) ] = -1,
1012 [ C(RESULT_MISS) ] = -1,
1013 },
1014 [ C(OP_PREFETCH) ] = {
1015 [ C(RESULT_ACCESS) ] = -1,
1016 [ C(RESULT_MISS) ] = -1,
1017 },
1018 },
1019 [ C(NODE) ] = {
1020 [ C(OP_READ) ] = {
1021 [ C(RESULT_ACCESS) ] = 0x01b7,
1022 [ C(RESULT_MISS) ] = 0x01b7,
1023 },
1024 [ C(OP_WRITE) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x01b7,
1026 [ C(RESULT_MISS) ] = 0x01b7,
1027 },
1028 [ C(OP_PREFETCH) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x01b7,
1030 [ C(RESULT_MISS) ] = 0x01b7,
1031 },
1032 },
1033
1034 };
1035
1036 /*
1037 * Notes on the events:
1038 * - data reads do not include code reads (comparable to earlier tables)
1039 * - data counts include speculative execution (except L1 write, dtlb, bpu)
1040 * - remote node access includes remote memory, remote cache, remote mmio.
1041 * - prefetches are not included in the counts because they are not
1042 * reliably counted.
1043 */
1044
1045 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
1046 #define HSW_DEMAND_RFO BIT_ULL(1)
1047 #define HSW_ANY_RESPONSE BIT_ULL(16)
1048 #define HSW_SUPPLIER_NONE BIT_ULL(17)
1049 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
1050 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
1051 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
1052 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
1053 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
1054 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1055 HSW_L3_MISS_REMOTE_HOP2P)
1056 #define HSW_SNOOP_NONE BIT_ULL(31)
1057 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
1058 #define HSW_SNOOP_MISS BIT_ULL(33)
1059 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
1060 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
1061 #define HSW_SNOOP_HITM BIT_ULL(36)
1062 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
1063 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
1064 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
1065 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
1066 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
1067 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
1068 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
1069 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
1070 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
1071 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
1072 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
1073
1074 #define BDW_L3_MISS_LOCAL BIT(26)
1075 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
1076 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1077 HSW_L3_MISS_REMOTE_HOP2P)
1078
1079
1080 static __initconst const u64 hsw_hw_cache_event_ids
1081 [PERF_COUNT_HW_CACHE_MAX]
1082 [PERF_COUNT_HW_CACHE_OP_MAX]
1083 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1084 {
1085 [ C(L1D ) ] = {
1086 [ C(OP_READ) ] = {
1087 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1088 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1089 },
1090 [ C(OP_WRITE) ] = {
1091 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1092 [ C(RESULT_MISS) ] = 0x0,
1093 },
1094 [ C(OP_PREFETCH) ] = {
1095 [ C(RESULT_ACCESS) ] = 0x0,
1096 [ C(RESULT_MISS) ] = 0x0,
1097 },
1098 },
1099 [ C(L1I ) ] = {
1100 [ C(OP_READ) ] = {
1101 [ C(RESULT_ACCESS) ] = 0x0,
1102 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1103 },
1104 [ C(OP_WRITE) ] = {
1105 [ C(RESULT_ACCESS) ] = -1,
1106 [ C(RESULT_MISS) ] = -1,
1107 },
1108 [ C(OP_PREFETCH) ] = {
1109 [ C(RESULT_ACCESS) ] = 0x0,
1110 [ C(RESULT_MISS) ] = 0x0,
1111 },
1112 },
1113 [ C(LL ) ] = {
1114 [ C(OP_READ) ] = {
1115 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1116 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1117 },
1118 [ C(OP_WRITE) ] = {
1119 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1120 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1121 },
1122 [ C(OP_PREFETCH) ] = {
1123 [ C(RESULT_ACCESS) ] = 0x0,
1124 [ C(RESULT_MISS) ] = 0x0,
1125 },
1126 },
1127 [ C(DTLB) ] = {
1128 [ C(OP_READ) ] = {
1129 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1130 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1131 },
1132 [ C(OP_WRITE) ] = {
1133 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1134 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1135 },
1136 [ C(OP_PREFETCH) ] = {
1137 [ C(RESULT_ACCESS) ] = 0x0,
1138 [ C(RESULT_MISS) ] = 0x0,
1139 },
1140 },
1141 [ C(ITLB) ] = {
1142 [ C(OP_READ) ] = {
1143 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1144 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1145 },
1146 [ C(OP_WRITE) ] = {
1147 [ C(RESULT_ACCESS) ] = -1,
1148 [ C(RESULT_MISS) ] = -1,
1149 },
1150 [ C(OP_PREFETCH) ] = {
1151 [ C(RESULT_ACCESS) ] = -1,
1152 [ C(RESULT_MISS) ] = -1,
1153 },
1154 },
1155 [ C(BPU ) ] = {
1156 [ C(OP_READ) ] = {
1157 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1158 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1159 },
1160 [ C(OP_WRITE) ] = {
1161 [ C(RESULT_ACCESS) ] = -1,
1162 [ C(RESULT_MISS) ] = -1,
1163 },
1164 [ C(OP_PREFETCH) ] = {
1165 [ C(RESULT_ACCESS) ] = -1,
1166 [ C(RESULT_MISS) ] = -1,
1167 },
1168 },
1169 [ C(NODE) ] = {
1170 [ C(OP_READ) ] = {
1171 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1172 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1173 },
1174 [ C(OP_WRITE) ] = {
1175 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1176 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1177 },
1178 [ C(OP_PREFETCH) ] = {
1179 [ C(RESULT_ACCESS) ] = 0x0,
1180 [ C(RESULT_MISS) ] = 0x0,
1181 },
1182 },
1183 };
1184
1185 static __initconst const u64 hsw_hw_cache_extra_regs
1186 [PERF_COUNT_HW_CACHE_MAX]
1187 [PERF_COUNT_HW_CACHE_OP_MAX]
1188 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1189 {
1190 [ C(LL ) ] = {
1191 [ C(OP_READ) ] = {
1192 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1193 HSW_LLC_ACCESS,
1194 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1195 HSW_L3_MISS|HSW_ANY_SNOOP,
1196 },
1197 [ C(OP_WRITE) ] = {
1198 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1199 HSW_LLC_ACCESS,
1200 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1201 HSW_L3_MISS|HSW_ANY_SNOOP,
1202 },
1203 [ C(OP_PREFETCH) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x0,
1205 [ C(RESULT_MISS) ] = 0x0,
1206 },
1207 },
1208 [ C(NODE) ] = {
1209 [ C(OP_READ) ] = {
1210 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1211 HSW_L3_MISS_LOCAL_DRAM|
1212 HSW_SNOOP_DRAM,
1213 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1214 HSW_L3_MISS_REMOTE|
1215 HSW_SNOOP_DRAM,
1216 },
1217 [ C(OP_WRITE) ] = {
1218 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1219 HSW_L3_MISS_LOCAL_DRAM|
1220 HSW_SNOOP_DRAM,
1221 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1222 HSW_L3_MISS_REMOTE|
1223 HSW_SNOOP_DRAM,
1224 },
1225 [ C(OP_PREFETCH) ] = {
1226 [ C(RESULT_ACCESS) ] = 0x0,
1227 [ C(RESULT_MISS) ] = 0x0,
1228 },
1229 },
1230 };
1231
1232 static __initconst const u64 westmere_hw_cache_event_ids
1233 [PERF_COUNT_HW_CACHE_MAX]
1234 [PERF_COUNT_HW_CACHE_OP_MAX]
1235 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1236 {
1237 [ C(L1D) ] = {
1238 [ C(OP_READ) ] = {
1239 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1240 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1241 },
1242 [ C(OP_WRITE) ] = {
1243 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1244 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1245 },
1246 [ C(OP_PREFETCH) ] = {
1247 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1248 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1249 },
1250 },
1251 [ C(L1I ) ] = {
1252 [ C(OP_READ) ] = {
1253 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1254 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1255 },
1256 [ C(OP_WRITE) ] = {
1257 [ C(RESULT_ACCESS) ] = -1,
1258 [ C(RESULT_MISS) ] = -1,
1259 },
1260 [ C(OP_PREFETCH) ] = {
1261 [ C(RESULT_ACCESS) ] = 0x0,
1262 [ C(RESULT_MISS) ] = 0x0,
1263 },
1264 },
1265 [ C(LL ) ] = {
1266 [ C(OP_READ) ] = {
1267 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1268 [ C(RESULT_ACCESS) ] = 0x01b7,
1269 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1270 [ C(RESULT_MISS) ] = 0x01b7,
1271 },
1272 /*
1273 * Use RFO, not WRITEBACK, because a write miss would typically occur
1274 * on RFO.
1275 */
1276 [ C(OP_WRITE) ] = {
1277 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1278 [ C(RESULT_ACCESS) ] = 0x01b7,
1279 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1280 [ C(RESULT_MISS) ] = 0x01b7,
1281 },
1282 [ C(OP_PREFETCH) ] = {
1283 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1284 [ C(RESULT_ACCESS) ] = 0x01b7,
1285 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1286 [ C(RESULT_MISS) ] = 0x01b7,
1287 },
1288 },
1289 [ C(DTLB) ] = {
1290 [ C(OP_READ) ] = {
1291 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1292 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1293 },
1294 [ C(OP_WRITE) ] = {
1295 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1296 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1297 },
1298 [ C(OP_PREFETCH) ] = {
1299 [ C(RESULT_ACCESS) ] = 0x0,
1300 [ C(RESULT_MISS) ] = 0x0,
1301 },
1302 },
1303 [ C(ITLB) ] = {
1304 [ C(OP_READ) ] = {
1305 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1306 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1307 },
1308 [ C(OP_WRITE) ] = {
1309 [ C(RESULT_ACCESS) ] = -1,
1310 [ C(RESULT_MISS) ] = -1,
1311 },
1312 [ C(OP_PREFETCH) ] = {
1313 [ C(RESULT_ACCESS) ] = -1,
1314 [ C(RESULT_MISS) ] = -1,
1315 },
1316 },
1317 [ C(BPU ) ] = {
1318 [ C(OP_READ) ] = {
1319 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1320 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1321 },
1322 [ C(OP_WRITE) ] = {
1323 [ C(RESULT_ACCESS) ] = -1,
1324 [ C(RESULT_MISS) ] = -1,
1325 },
1326 [ C(OP_PREFETCH) ] = {
1327 [ C(RESULT_ACCESS) ] = -1,
1328 [ C(RESULT_MISS) ] = -1,
1329 },
1330 },
1331 [ C(NODE) ] = {
1332 [ C(OP_READ) ] = {
1333 [ C(RESULT_ACCESS) ] = 0x01b7,
1334 [ C(RESULT_MISS) ] = 0x01b7,
1335 },
1336 [ C(OP_WRITE) ] = {
1337 [ C(RESULT_ACCESS) ] = 0x01b7,
1338 [ C(RESULT_MISS) ] = 0x01b7,
1339 },
1340 [ C(OP_PREFETCH) ] = {
1341 [ C(RESULT_ACCESS) ] = 0x01b7,
1342 [ C(RESULT_MISS) ] = 0x01b7,
1343 },
1344 },
1345 };
1346
1347 /*
1348 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1349 * See IA32 SDM Vol 3B 30.6.1.3
1350 */
1351
1352 #define NHM_DMND_DATA_RD (1 << 0)
1353 #define NHM_DMND_RFO (1 << 1)
1354 #define NHM_DMND_IFETCH (1 << 2)
1355 #define NHM_DMND_WB (1 << 3)
1356 #define NHM_PF_DATA_RD (1 << 4)
1357 #define NHM_PF_DATA_RFO (1 << 5)
1358 #define NHM_PF_IFETCH (1 << 6)
1359 #define NHM_OFFCORE_OTHER (1 << 7)
1360 #define NHM_UNCORE_HIT (1 << 8)
1361 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1362 #define NHM_OTHER_CORE_HITM (1 << 10)
1363 /* reserved */
1364 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1365 #define NHM_REMOTE_DRAM (1 << 13)
1366 #define NHM_LOCAL_DRAM (1 << 14)
1367 #define NHM_NON_DRAM (1 << 15)
1368
1369 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1370 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1371
1372 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1373 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1374 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1375
1376 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1377 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1378 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1379
1380 static __initconst const u64 nehalem_hw_cache_extra_regs
1381 [PERF_COUNT_HW_CACHE_MAX]
1382 [PERF_COUNT_HW_CACHE_OP_MAX]
1383 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1384 {
1385 [ C(LL ) ] = {
1386 [ C(OP_READ) ] = {
1387 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1388 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1389 },
1390 [ C(OP_WRITE) ] = {
1391 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1392 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1393 },
1394 [ C(OP_PREFETCH) ] = {
1395 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1396 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1397 },
1398 },
1399 [ C(NODE) ] = {
1400 [ C(OP_READ) ] = {
1401 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1402 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1403 },
1404 [ C(OP_WRITE) ] = {
1405 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1406 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1407 },
1408 [ C(OP_PREFETCH) ] = {
1409 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1410 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1411 },
1412 },
1413 };
1414
1415 static __initconst const u64 nehalem_hw_cache_event_ids
1416 [PERF_COUNT_HW_CACHE_MAX]
1417 [PERF_COUNT_HW_CACHE_OP_MAX]
1418 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1419 {
1420 [ C(L1D) ] = {
1421 [ C(OP_READ) ] = {
1422 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1423 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1424 },
1425 [ C(OP_WRITE) ] = {
1426 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1427 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1428 },
1429 [ C(OP_PREFETCH) ] = {
1430 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1431 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1432 },
1433 },
1434 [ C(L1I ) ] = {
1435 [ C(OP_READ) ] = {
1436 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1437 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1438 },
1439 [ C(OP_WRITE) ] = {
1440 [ C(RESULT_ACCESS) ] = -1,
1441 [ C(RESULT_MISS) ] = -1,
1442 },
1443 [ C(OP_PREFETCH) ] = {
1444 [ C(RESULT_ACCESS) ] = 0x0,
1445 [ C(RESULT_MISS) ] = 0x0,
1446 },
1447 },
1448 [ C(LL ) ] = {
1449 [ C(OP_READ) ] = {
1450 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1451 [ C(RESULT_ACCESS) ] = 0x01b7,
1452 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1453 [ C(RESULT_MISS) ] = 0x01b7,
1454 },
1455 /*
1456 * Use RFO, not WRITEBACK, because a write miss would typically occur
1457 * on RFO.
1458 */
1459 [ C(OP_WRITE) ] = {
1460 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1461 [ C(RESULT_ACCESS) ] = 0x01b7,
1462 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1463 [ C(RESULT_MISS) ] = 0x01b7,
1464 },
1465 [ C(OP_PREFETCH) ] = {
1466 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1467 [ C(RESULT_ACCESS) ] = 0x01b7,
1468 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1469 [ C(RESULT_MISS) ] = 0x01b7,
1470 },
1471 },
1472 [ C(DTLB) ] = {
1473 [ C(OP_READ) ] = {
1474 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1475 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1476 },
1477 [ C(OP_WRITE) ] = {
1478 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1479 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1480 },
1481 [ C(OP_PREFETCH) ] = {
1482 [ C(RESULT_ACCESS) ] = 0x0,
1483 [ C(RESULT_MISS) ] = 0x0,
1484 },
1485 },
1486 [ C(ITLB) ] = {
1487 [ C(OP_READ) ] = {
1488 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1489 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1490 },
1491 [ C(OP_WRITE) ] = {
1492 [ C(RESULT_ACCESS) ] = -1,
1493 [ C(RESULT_MISS) ] = -1,
1494 },
1495 [ C(OP_PREFETCH) ] = {
1496 [ C(RESULT_ACCESS) ] = -1,
1497 [ C(RESULT_MISS) ] = -1,
1498 },
1499 },
1500 [ C(BPU ) ] = {
1501 [ C(OP_READ) ] = {
1502 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1503 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1504 },
1505 [ C(OP_WRITE) ] = {
1506 [ C(RESULT_ACCESS) ] = -1,
1507 [ C(RESULT_MISS) ] = -1,
1508 },
1509 [ C(OP_PREFETCH) ] = {
1510 [ C(RESULT_ACCESS) ] = -1,
1511 [ C(RESULT_MISS) ] = -1,
1512 },
1513 },
1514 [ C(NODE) ] = {
1515 [ C(OP_READ) ] = {
1516 [ C(RESULT_ACCESS) ] = 0x01b7,
1517 [ C(RESULT_MISS) ] = 0x01b7,
1518 },
1519 [ C(OP_WRITE) ] = {
1520 [ C(RESULT_ACCESS) ] = 0x01b7,
1521 [ C(RESULT_MISS) ] = 0x01b7,
1522 },
1523 [ C(OP_PREFETCH) ] = {
1524 [ C(RESULT_ACCESS) ] = 0x01b7,
1525 [ C(RESULT_MISS) ] = 0x01b7,
1526 },
1527 },
1528 };
1529
1530 static __initconst const u64 core2_hw_cache_event_ids
1531 [PERF_COUNT_HW_CACHE_MAX]
1532 [PERF_COUNT_HW_CACHE_OP_MAX]
1533 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1534 {
1535 [ C(L1D) ] = {
1536 [ C(OP_READ) ] = {
1537 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1538 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1539 },
1540 [ C(OP_WRITE) ] = {
1541 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1542 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1543 },
1544 [ C(OP_PREFETCH) ] = {
1545 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1546 [ C(RESULT_MISS) ] = 0,
1547 },
1548 },
1549 [ C(L1I ) ] = {
1550 [ C(OP_READ) ] = {
1551 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1552 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1553 },
1554 [ C(OP_WRITE) ] = {
1555 [ C(RESULT_ACCESS) ] = -1,
1556 [ C(RESULT_MISS) ] = -1,
1557 },
1558 [ C(OP_PREFETCH) ] = {
1559 [ C(RESULT_ACCESS) ] = 0,
1560 [ C(RESULT_MISS) ] = 0,
1561 },
1562 },
1563 [ C(LL ) ] = {
1564 [ C(OP_READ) ] = {
1565 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1566 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1567 },
1568 [ C(OP_WRITE) ] = {
1569 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1570 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1571 },
1572 [ C(OP_PREFETCH) ] = {
1573 [ C(RESULT_ACCESS) ] = 0,
1574 [ C(RESULT_MISS) ] = 0,
1575 },
1576 },
1577 [ C(DTLB) ] = {
1578 [ C(OP_READ) ] = {
1579 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1580 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1581 },
1582 [ C(OP_WRITE) ] = {
1583 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1584 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1585 },
1586 [ C(OP_PREFETCH) ] = {
1587 [ C(RESULT_ACCESS) ] = 0,
1588 [ C(RESULT_MISS) ] = 0,
1589 },
1590 },
1591 [ C(ITLB) ] = {
1592 [ C(OP_READ) ] = {
1593 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1594 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1595 },
1596 [ C(OP_WRITE) ] = {
1597 [ C(RESULT_ACCESS) ] = -1,
1598 [ C(RESULT_MISS) ] = -1,
1599 },
1600 [ C(OP_PREFETCH) ] = {
1601 [ C(RESULT_ACCESS) ] = -1,
1602 [ C(RESULT_MISS) ] = -1,
1603 },
1604 },
1605 [ C(BPU ) ] = {
1606 [ C(OP_READ) ] = {
1607 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1608 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1609 },
1610 [ C(OP_WRITE) ] = {
1611 [ C(RESULT_ACCESS) ] = -1,
1612 [ C(RESULT_MISS) ] = -1,
1613 },
1614 [ C(OP_PREFETCH) ] = {
1615 [ C(RESULT_ACCESS) ] = -1,
1616 [ C(RESULT_MISS) ] = -1,
1617 },
1618 },
1619 };
1620
1621 static __initconst const u64 atom_hw_cache_event_ids
1622 [PERF_COUNT_HW_CACHE_MAX]
1623 [PERF_COUNT_HW_CACHE_OP_MAX]
1624 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1625 {
1626 [ C(L1D) ] = {
1627 [ C(OP_READ) ] = {
1628 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1629 [ C(RESULT_MISS) ] = 0,
1630 },
1631 [ C(OP_WRITE) ] = {
1632 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1633 [ C(RESULT_MISS) ] = 0,
1634 },
1635 [ C(OP_PREFETCH) ] = {
1636 [ C(RESULT_ACCESS) ] = 0x0,
1637 [ C(RESULT_MISS) ] = 0,
1638 },
1639 },
1640 [ C(L1I ) ] = {
1641 [ C(OP_READ) ] = {
1642 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1643 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1644 },
1645 [ C(OP_WRITE) ] = {
1646 [ C(RESULT_ACCESS) ] = -1,
1647 [ C(RESULT_MISS) ] = -1,
1648 },
1649 [ C(OP_PREFETCH) ] = {
1650 [ C(RESULT_ACCESS) ] = 0,
1651 [ C(RESULT_MISS) ] = 0,
1652 },
1653 },
1654 [ C(LL ) ] = {
1655 [ C(OP_READ) ] = {
1656 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1657 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1658 },
1659 [ C(OP_WRITE) ] = {
1660 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1661 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1662 },
1663 [ C(OP_PREFETCH) ] = {
1664 [ C(RESULT_ACCESS) ] = 0,
1665 [ C(RESULT_MISS) ] = 0,
1666 },
1667 },
1668 [ C(DTLB) ] = {
1669 [ C(OP_READ) ] = {
1670 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1671 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1672 },
1673 [ C(OP_WRITE) ] = {
1674 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1675 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1676 },
1677 [ C(OP_PREFETCH) ] = {
1678 [ C(RESULT_ACCESS) ] = 0,
1679 [ C(RESULT_MISS) ] = 0,
1680 },
1681 },
1682 [ C(ITLB) ] = {
1683 [ C(OP_READ) ] = {
1684 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1685 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1686 },
1687 [ C(OP_WRITE) ] = {
1688 [ C(RESULT_ACCESS) ] = -1,
1689 [ C(RESULT_MISS) ] = -1,
1690 },
1691 [ C(OP_PREFETCH) ] = {
1692 [ C(RESULT_ACCESS) ] = -1,
1693 [ C(RESULT_MISS) ] = -1,
1694 },
1695 },
1696 [ C(BPU ) ] = {
1697 [ C(OP_READ) ] = {
1698 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1699 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1700 },
1701 [ C(OP_WRITE) ] = {
1702 [ C(RESULT_ACCESS) ] = -1,
1703 [ C(RESULT_MISS) ] = -1,
1704 },
1705 [ C(OP_PREFETCH) ] = {
1706 [ C(RESULT_ACCESS) ] = -1,
1707 [ C(RESULT_MISS) ] = -1,
1708 },
1709 },
1710 };
1711
1712 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1713 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1714 /* no_alloc_cycles.not_delivered */
1715 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1716 "event=0xca,umask=0x50");
1717 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1718 /* uops_retired.all */
1719 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1720 "event=0xc2,umask=0x10");
1721 /* uops_retired.all */
1722 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1723 "event=0xc2,umask=0x10");
1724
1725 static struct attribute *slm_events_attrs[] = {
1726 EVENT_PTR(td_total_slots_slm),
1727 EVENT_PTR(td_total_slots_scale_slm),
1728 EVENT_PTR(td_fetch_bubbles_slm),
1729 EVENT_PTR(td_fetch_bubbles_scale_slm),
1730 EVENT_PTR(td_slots_issued_slm),
1731 EVENT_PTR(td_slots_retired_slm),
1732 NULL
1733 };
1734
1735 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1736 {
1737 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1738 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1739 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1740 EVENT_EXTRA_END
1741 };
1742
1743 #define SLM_DMND_READ SNB_DMND_DATA_RD
1744 #define SLM_DMND_WRITE SNB_DMND_RFO
1745 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1746
1747 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1748 #define SLM_LLC_ACCESS SNB_RESP_ANY
1749 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1750
1751 static __initconst const u64 slm_hw_cache_extra_regs
1752 [PERF_COUNT_HW_CACHE_MAX]
1753 [PERF_COUNT_HW_CACHE_OP_MAX]
1754 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1755 {
1756 [ C(LL ) ] = {
1757 [ C(OP_READ) ] = {
1758 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1759 [ C(RESULT_MISS) ] = 0,
1760 },
1761 [ C(OP_WRITE) ] = {
1762 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1763 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1764 },
1765 [ C(OP_PREFETCH) ] = {
1766 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1767 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1768 },
1769 },
1770 };
1771
1772 static __initconst const u64 slm_hw_cache_event_ids
1773 [PERF_COUNT_HW_CACHE_MAX]
1774 [PERF_COUNT_HW_CACHE_OP_MAX]
1775 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1776 {
1777 [ C(L1D) ] = {
1778 [ C(OP_READ) ] = {
1779 [ C(RESULT_ACCESS) ] = 0,
1780 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1781 },
1782 [ C(OP_WRITE) ] = {
1783 [ C(RESULT_ACCESS) ] = 0,
1784 [ C(RESULT_MISS) ] = 0,
1785 },
1786 [ C(OP_PREFETCH) ] = {
1787 [ C(RESULT_ACCESS) ] = 0,
1788 [ C(RESULT_MISS) ] = 0,
1789 },
1790 },
1791 [ C(L1I ) ] = {
1792 [ C(OP_READ) ] = {
1793 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1794 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1795 },
1796 [ C(OP_WRITE) ] = {
1797 [ C(RESULT_ACCESS) ] = -1,
1798 [ C(RESULT_MISS) ] = -1,
1799 },
1800 [ C(OP_PREFETCH) ] = {
1801 [ C(RESULT_ACCESS) ] = 0,
1802 [ C(RESULT_MISS) ] = 0,
1803 },
1804 },
1805 [ C(LL ) ] = {
1806 [ C(OP_READ) ] = {
1807 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1808 [ C(RESULT_ACCESS) ] = 0x01b7,
1809 [ C(RESULT_MISS) ] = 0,
1810 },
1811 [ C(OP_WRITE) ] = {
1812 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1813 [ C(RESULT_ACCESS) ] = 0x01b7,
1814 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1815 [ C(RESULT_MISS) ] = 0x01b7,
1816 },
1817 [ C(OP_PREFETCH) ] = {
1818 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1819 [ C(RESULT_ACCESS) ] = 0x01b7,
1820 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1821 [ C(RESULT_MISS) ] = 0x01b7,
1822 },
1823 },
1824 [ C(DTLB) ] = {
1825 [ C(OP_READ) ] = {
1826 [ C(RESULT_ACCESS) ] = 0,
1827 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1828 },
1829 [ C(OP_WRITE) ] = {
1830 [ C(RESULT_ACCESS) ] = 0,
1831 [ C(RESULT_MISS) ] = 0,
1832 },
1833 [ C(OP_PREFETCH) ] = {
1834 [ C(RESULT_ACCESS) ] = 0,
1835 [ C(RESULT_MISS) ] = 0,
1836 },
1837 },
1838 [ C(ITLB) ] = {
1839 [ C(OP_READ) ] = {
1840 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1841 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1842 },
1843 [ C(OP_WRITE) ] = {
1844 [ C(RESULT_ACCESS) ] = -1,
1845 [ C(RESULT_MISS) ] = -1,
1846 },
1847 [ C(OP_PREFETCH) ] = {
1848 [ C(RESULT_ACCESS) ] = -1,
1849 [ C(RESULT_MISS) ] = -1,
1850 },
1851 },
1852 [ C(BPU ) ] = {
1853 [ C(OP_READ) ] = {
1854 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1855 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1856 },
1857 [ C(OP_WRITE) ] = {
1858 [ C(RESULT_ACCESS) ] = -1,
1859 [ C(RESULT_MISS) ] = -1,
1860 },
1861 [ C(OP_PREFETCH) ] = {
1862 [ C(RESULT_ACCESS) ] = -1,
1863 [ C(RESULT_MISS) ] = -1,
1864 },
1865 },
1866 };
1867
1868 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1869 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1870 /* UOPS_NOT_DELIVERED.ANY */
1871 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1872 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1873 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1874 /* UOPS_RETIRED.ANY */
1875 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1876 /* UOPS_ISSUED.ANY */
1877 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1878
1879 static struct attribute *glm_events_attrs[] = {
1880 EVENT_PTR(td_total_slots_glm),
1881 EVENT_PTR(td_total_slots_scale_glm),
1882 EVENT_PTR(td_fetch_bubbles_glm),
1883 EVENT_PTR(td_recovery_bubbles_glm),
1884 EVENT_PTR(td_slots_issued_glm),
1885 EVENT_PTR(td_slots_retired_glm),
1886 NULL
1887 };
1888
1889 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1890 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1891 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1892 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1893 EVENT_EXTRA_END
1894 };
1895
1896 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1897 #define GLM_DEMAND_RFO BIT_ULL(1)
1898 #define GLM_ANY_RESPONSE BIT_ULL(16)
1899 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1900 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1901 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1902 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1903 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1904 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1905 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1906
1907 static __initconst const u64 glm_hw_cache_event_ids
1908 [PERF_COUNT_HW_CACHE_MAX]
1909 [PERF_COUNT_HW_CACHE_OP_MAX]
1910 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1911 [C(L1D)] = {
1912 [C(OP_READ)] = {
1913 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1914 [C(RESULT_MISS)] = 0x0,
1915 },
1916 [C(OP_WRITE)] = {
1917 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1918 [C(RESULT_MISS)] = 0x0,
1919 },
1920 [C(OP_PREFETCH)] = {
1921 [C(RESULT_ACCESS)] = 0x0,
1922 [C(RESULT_MISS)] = 0x0,
1923 },
1924 },
1925 [C(L1I)] = {
1926 [C(OP_READ)] = {
1927 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1928 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1929 },
1930 [C(OP_WRITE)] = {
1931 [C(RESULT_ACCESS)] = -1,
1932 [C(RESULT_MISS)] = -1,
1933 },
1934 [C(OP_PREFETCH)] = {
1935 [C(RESULT_ACCESS)] = 0x0,
1936 [C(RESULT_MISS)] = 0x0,
1937 },
1938 },
1939 [C(LL)] = {
1940 [C(OP_READ)] = {
1941 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1942 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1943 },
1944 [C(OP_WRITE)] = {
1945 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1946 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1947 },
1948 [C(OP_PREFETCH)] = {
1949 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1950 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1951 },
1952 },
1953 [C(DTLB)] = {
1954 [C(OP_READ)] = {
1955 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1956 [C(RESULT_MISS)] = 0x0,
1957 },
1958 [C(OP_WRITE)] = {
1959 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1960 [C(RESULT_MISS)] = 0x0,
1961 },
1962 [C(OP_PREFETCH)] = {
1963 [C(RESULT_ACCESS)] = 0x0,
1964 [C(RESULT_MISS)] = 0x0,
1965 },
1966 },
1967 [C(ITLB)] = {
1968 [C(OP_READ)] = {
1969 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1970 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1971 },
1972 [C(OP_WRITE)] = {
1973 [C(RESULT_ACCESS)] = -1,
1974 [C(RESULT_MISS)] = -1,
1975 },
1976 [C(OP_PREFETCH)] = {
1977 [C(RESULT_ACCESS)] = -1,
1978 [C(RESULT_MISS)] = -1,
1979 },
1980 },
1981 [C(BPU)] = {
1982 [C(OP_READ)] = {
1983 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1984 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1985 },
1986 [C(OP_WRITE)] = {
1987 [C(RESULT_ACCESS)] = -1,
1988 [C(RESULT_MISS)] = -1,
1989 },
1990 [C(OP_PREFETCH)] = {
1991 [C(RESULT_ACCESS)] = -1,
1992 [C(RESULT_MISS)] = -1,
1993 },
1994 },
1995 };
1996
1997 static __initconst const u64 glm_hw_cache_extra_regs
1998 [PERF_COUNT_HW_CACHE_MAX]
1999 [PERF_COUNT_HW_CACHE_OP_MAX]
2000 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2001 [C(LL)] = {
2002 [C(OP_READ)] = {
2003 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2004 GLM_LLC_ACCESS,
2005 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2006 GLM_LLC_MISS,
2007 },
2008 [C(OP_WRITE)] = {
2009 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2010 GLM_LLC_ACCESS,
2011 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2012 GLM_LLC_MISS,
2013 },
2014 [C(OP_PREFETCH)] = {
2015 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
2016 GLM_LLC_ACCESS,
2017 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
2018 GLM_LLC_MISS,
2019 },
2020 },
2021 };
2022
2023 static __initconst const u64 glp_hw_cache_event_ids
2024 [PERF_COUNT_HW_CACHE_MAX]
2025 [PERF_COUNT_HW_CACHE_OP_MAX]
2026 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2027 [C(L1D)] = {
2028 [C(OP_READ)] = {
2029 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2030 [C(RESULT_MISS)] = 0x0,
2031 },
2032 [C(OP_WRITE)] = {
2033 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2034 [C(RESULT_MISS)] = 0x0,
2035 },
2036 [C(OP_PREFETCH)] = {
2037 [C(RESULT_ACCESS)] = 0x0,
2038 [C(RESULT_MISS)] = 0x0,
2039 },
2040 },
2041 [C(L1I)] = {
2042 [C(OP_READ)] = {
2043 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2044 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2045 },
2046 [C(OP_WRITE)] = {
2047 [C(RESULT_ACCESS)] = -1,
2048 [C(RESULT_MISS)] = -1,
2049 },
2050 [C(OP_PREFETCH)] = {
2051 [C(RESULT_ACCESS)] = 0x0,
2052 [C(RESULT_MISS)] = 0x0,
2053 },
2054 },
2055 [C(LL)] = {
2056 [C(OP_READ)] = {
2057 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2058 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2059 },
2060 [C(OP_WRITE)] = {
2061 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2062 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2063 },
2064 [C(OP_PREFETCH)] = {
2065 [C(RESULT_ACCESS)] = 0x0,
2066 [C(RESULT_MISS)] = 0x0,
2067 },
2068 },
2069 [C(DTLB)] = {
2070 [C(OP_READ)] = {
2071 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2072 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
2073 },
2074 [C(OP_WRITE)] = {
2075 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2076 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
2077 },
2078 [C(OP_PREFETCH)] = {
2079 [C(RESULT_ACCESS)] = 0x0,
2080 [C(RESULT_MISS)] = 0x0,
2081 },
2082 },
2083 [C(ITLB)] = {
2084 [C(OP_READ)] = {
2085 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2086 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2087 },
2088 [C(OP_WRITE)] = {
2089 [C(RESULT_ACCESS)] = -1,
2090 [C(RESULT_MISS)] = -1,
2091 },
2092 [C(OP_PREFETCH)] = {
2093 [C(RESULT_ACCESS)] = -1,
2094 [C(RESULT_MISS)] = -1,
2095 },
2096 },
2097 [C(BPU)] = {
2098 [C(OP_READ)] = {
2099 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2100 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2101 },
2102 [C(OP_WRITE)] = {
2103 [C(RESULT_ACCESS)] = -1,
2104 [C(RESULT_MISS)] = -1,
2105 },
2106 [C(OP_PREFETCH)] = {
2107 [C(RESULT_ACCESS)] = -1,
2108 [C(RESULT_MISS)] = -1,
2109 },
2110 },
2111 };
2112
2113 static __initconst const u64 glp_hw_cache_extra_regs
2114 [PERF_COUNT_HW_CACHE_MAX]
2115 [PERF_COUNT_HW_CACHE_OP_MAX]
2116 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2117 [C(LL)] = {
2118 [C(OP_READ)] = {
2119 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2120 GLM_LLC_ACCESS,
2121 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2122 GLM_LLC_MISS,
2123 },
2124 [C(OP_WRITE)] = {
2125 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2126 GLM_LLC_ACCESS,
2127 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2128 GLM_LLC_MISS,
2129 },
2130 [C(OP_PREFETCH)] = {
2131 [C(RESULT_ACCESS)] = 0x0,
2132 [C(RESULT_MISS)] = 0x0,
2133 },
2134 },
2135 };
2136
2137 #define TNT_LOCAL_DRAM BIT_ULL(26)
2138 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
2139 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
2140 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
2141 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2142 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2143 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2144
2145 static __initconst const u64 tnt_hw_cache_extra_regs
2146 [PERF_COUNT_HW_CACHE_MAX]
2147 [PERF_COUNT_HW_CACHE_OP_MAX]
2148 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2149 [C(LL)] = {
2150 [C(OP_READ)] = {
2151 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2152 TNT_LLC_ACCESS,
2153 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2154 TNT_LLC_MISS,
2155 },
2156 [C(OP_WRITE)] = {
2157 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2158 TNT_LLC_ACCESS,
2159 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2160 TNT_LLC_MISS,
2161 },
2162 [C(OP_PREFETCH)] = {
2163 [C(RESULT_ACCESS)] = 0x0,
2164 [C(RESULT_MISS)] = 0x0,
2165 },
2166 },
2167 };
2168
2169 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
2170 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
2171 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
2172 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
2173
2174 static struct attribute *tnt_events_attrs[] = {
2175 EVENT_PTR(td_fe_bound_tnt),
2176 EVENT_PTR(td_retiring_tnt),
2177 EVENT_PTR(td_bad_spec_tnt),
2178 EVENT_PTR(td_be_bound_tnt),
2179 NULL,
2180 };
2181
2182 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2183 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2184 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2185 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2186 EVENT_EXTRA_END
2187 };
2188
2189 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3");
2190 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
2191
2192 static struct attribute *grt_mem_attrs[] = {
2193 EVENT_PTR(mem_ld_grt),
2194 EVENT_PTR(mem_st_grt),
2195 NULL
2196 };
2197
2198 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2199 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2200 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
2201 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
2202 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2203 EVENT_EXTRA_END
2204 };
2205
2206 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0");
2207 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0");
2208
2209 static struct attribute *cmt_events_attrs[] = {
2210 EVENT_PTR(td_fe_bound_tnt),
2211 EVENT_PTR(td_retiring_cmt),
2212 EVENT_PTR(td_bad_spec_cmt),
2213 EVENT_PTR(td_be_bound_tnt),
2214 NULL
2215 };
2216
2217 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
2218 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2219 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
2220 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1),
2221 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2222 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2223 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2224 EVENT_EXTRA_END
2225 };
2226
2227 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
2228 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
2229 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
2230 #define KNL_MCDRAM_FAR BIT_ULL(22)
2231 #define KNL_DDR_LOCAL BIT_ULL(23)
2232 #define KNL_DDR_FAR BIT_ULL(24)
2233 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2234 KNL_DDR_LOCAL | KNL_DDR_FAR)
2235 #define KNL_L2_READ SLM_DMND_READ
2236 #define KNL_L2_WRITE SLM_DMND_WRITE
2237 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
2238 #define KNL_L2_ACCESS SLM_LLC_ACCESS
2239 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2240 KNL_DRAM_ANY | SNB_SNP_ANY | \
2241 SNB_NON_DRAM)
2242
2243 static __initconst const u64 knl_hw_cache_extra_regs
2244 [PERF_COUNT_HW_CACHE_MAX]
2245 [PERF_COUNT_HW_CACHE_OP_MAX]
2246 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2247 [C(LL)] = {
2248 [C(OP_READ)] = {
2249 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2250 [C(RESULT_MISS)] = 0,
2251 },
2252 [C(OP_WRITE)] = {
2253 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2254 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2255 },
2256 [C(OP_PREFETCH)] = {
2257 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2258 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2259 },
2260 },
2261 };
2262
2263 /*
2264 * Used from PMIs where the LBRs are already disabled.
2265 *
2266 * This function could be called consecutively. It is required to remain in
2267 * disabled state if called consecutively.
2268 *
2269 * During consecutive calls, the same disable value will be written to related
2270 * registers, so the PMU state remains unchanged.
2271 *
2272 * intel_bts events don't coexist with intel PMU's BTS events because of
2273 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2274 * disabled around intel PMU's event batching etc, only inside the PMI handler.
2275 *
2276 * Avoid PEBS_ENABLE MSR access in PMIs.
2277 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2278 * It doesn't matter if the PEBS is enabled or not.
2279 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2280 * access PEBS_ENABLE MSR in disable_all()/enable_all().
2281 * However, there are some cases which may change PEBS status, e.g. PMI
2282 * throttle. The PEBS_ENABLE should be updated where the status changes.
2283 */
__intel_pmu_disable_all(bool bts)2284 static __always_inline void __intel_pmu_disable_all(bool bts)
2285 {
2286 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2287
2288 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2289
2290 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2291 intel_pmu_disable_bts();
2292 }
2293
intel_pmu_disable_all(void)2294 static __always_inline void intel_pmu_disable_all(void)
2295 {
2296 __intel_pmu_disable_all(true);
2297 intel_pmu_pebs_disable_all();
2298 intel_pmu_lbr_disable_all();
2299 }
2300
__intel_pmu_enable_all(int added,bool pmi)2301 static void __intel_pmu_enable_all(int added, bool pmi)
2302 {
2303 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2304 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2305
2306 intel_pmu_lbr_enable_all(pmi);
2307
2308 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) {
2309 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val);
2310 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val;
2311 }
2312
2313 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
2314 intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2315
2316 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2317 struct perf_event *event =
2318 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2319
2320 if (WARN_ON_ONCE(!event))
2321 return;
2322
2323 intel_pmu_enable_bts(event->hw.config);
2324 }
2325 }
2326
intel_pmu_enable_all(int added)2327 static void intel_pmu_enable_all(int added)
2328 {
2329 intel_pmu_pebs_enable_all();
2330 __intel_pmu_enable_all(added, false);
2331 }
2332
2333 static noinline int
__intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt,unsigned long flags)2334 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries,
2335 unsigned int cnt, unsigned long flags)
2336 {
2337 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2338
2339 intel_pmu_lbr_read();
2340 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr);
2341
2342 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
2343 intel_pmu_enable_all(0);
2344 local_irq_restore(flags);
2345 return cnt;
2346 }
2347
2348 static int
intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2349 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2350 {
2351 unsigned long flags;
2352
2353 /* must not have branches... */
2354 local_irq_save(flags);
2355 __intel_pmu_disable_all(false); /* we don't care about BTS */
2356 __intel_pmu_lbr_disable();
2357 /* ... until here */
2358 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2359 }
2360
2361 static int
intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2362 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2363 {
2364 unsigned long flags;
2365
2366 /* must not have branches... */
2367 local_irq_save(flags);
2368 __intel_pmu_disable_all(false); /* we don't care about BTS */
2369 __intel_pmu_arch_lbr_disable();
2370 /* ... until here */
2371 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2372 }
2373
2374 /*
2375 * Workaround for:
2376 * Intel Errata AAK100 (model 26)
2377 * Intel Errata AAP53 (model 30)
2378 * Intel Errata BD53 (model 44)
2379 *
2380 * The official story:
2381 * These chips need to be 'reset' when adding counters by programming the
2382 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2383 * in sequence on the same PMC or on different PMCs.
2384 *
2385 * In practice it appears some of these events do in fact count, and
2386 * we need to program all 4 events.
2387 */
intel_pmu_nhm_workaround(void)2388 static void intel_pmu_nhm_workaround(void)
2389 {
2390 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2391 static const unsigned long nhm_magic[4] = {
2392 0x4300B5,
2393 0x4300D2,
2394 0x4300B1,
2395 0x4300B1
2396 };
2397 struct perf_event *event;
2398 int i;
2399
2400 /*
2401 * The Errata requires below steps:
2402 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2403 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2404 * the corresponding PMCx;
2405 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2406 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2407 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2408 */
2409
2410 /*
2411 * The real steps we choose are a little different from above.
2412 * A) To reduce MSR operations, we don't run step 1) as they
2413 * are already cleared before this function is called;
2414 * B) Call x86_perf_event_update to save PMCx before configuring
2415 * PERFEVTSELx with magic number;
2416 * C) With step 5), we do clear only when the PERFEVTSELx is
2417 * not used currently.
2418 * D) Call x86_perf_event_set_period to restore PMCx;
2419 */
2420
2421 /* We always operate 4 pairs of PERF Counters */
2422 for (i = 0; i < 4; i++) {
2423 event = cpuc->events[i];
2424 if (event)
2425 static_call(x86_pmu_update)(event);
2426 }
2427
2428 for (i = 0; i < 4; i++) {
2429 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2430 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2431 }
2432
2433 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2434 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2435
2436 for (i = 0; i < 4; i++) {
2437 event = cpuc->events[i];
2438
2439 if (event) {
2440 static_call(x86_pmu_set_period)(event);
2441 __x86_pmu_enable_event(&event->hw,
2442 ARCH_PERFMON_EVENTSEL_ENABLE);
2443 } else
2444 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2445 }
2446 }
2447
intel_pmu_nhm_enable_all(int added)2448 static void intel_pmu_nhm_enable_all(int added)
2449 {
2450 if (added)
2451 intel_pmu_nhm_workaround();
2452 intel_pmu_enable_all(added);
2453 }
2454
intel_set_tfa(struct cpu_hw_events * cpuc,bool on)2455 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2456 {
2457 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2458
2459 if (cpuc->tfa_shadow != val) {
2460 cpuc->tfa_shadow = val;
2461 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2462 }
2463 }
2464
intel_tfa_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)2465 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2466 {
2467 /*
2468 * We're going to use PMC3, make sure TFA is set before we touch it.
2469 */
2470 if (cntr == 3)
2471 intel_set_tfa(cpuc, true);
2472 }
2473
intel_tfa_pmu_enable_all(int added)2474 static void intel_tfa_pmu_enable_all(int added)
2475 {
2476 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2477
2478 /*
2479 * If we find PMC3 is no longer used when we enable the PMU, we can
2480 * clear TFA.
2481 */
2482 if (!test_bit(3, cpuc->active_mask))
2483 intel_set_tfa(cpuc, false);
2484
2485 intel_pmu_enable_all(added);
2486 }
2487
intel_pmu_get_status(void)2488 static inline u64 intel_pmu_get_status(void)
2489 {
2490 u64 status;
2491
2492 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2493
2494 return status;
2495 }
2496
intel_pmu_ack_status(u64 ack)2497 static inline void intel_pmu_ack_status(u64 ack)
2498 {
2499 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2500 }
2501
event_is_checkpointed(struct perf_event * event)2502 static inline bool event_is_checkpointed(struct perf_event *event)
2503 {
2504 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2505 }
2506
intel_set_masks(struct perf_event * event,int idx)2507 static inline void intel_set_masks(struct perf_event *event, int idx)
2508 {
2509 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2510
2511 if (event->attr.exclude_host)
2512 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2513 if (event->attr.exclude_guest)
2514 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2515 if (event_is_checkpointed(event))
2516 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2517 }
2518
intel_clear_masks(struct perf_event * event,int idx)2519 static inline void intel_clear_masks(struct perf_event *event, int idx)
2520 {
2521 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2522
2523 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2524 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2525 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2526 }
2527
intel_pmu_disable_fixed(struct perf_event * event)2528 static void intel_pmu_disable_fixed(struct perf_event *event)
2529 {
2530 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2531 struct hw_perf_event *hwc = &event->hw;
2532 int idx = hwc->idx;
2533 u64 mask;
2534
2535 if (is_topdown_idx(idx)) {
2536 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2537
2538 /*
2539 * When there are other active TopDown events,
2540 * don't disable the fixed counter 3.
2541 */
2542 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2543 return;
2544 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2545 }
2546
2547 intel_clear_masks(event, idx);
2548
2549 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);
2550 cpuc->fixed_ctrl_val &= ~mask;
2551 }
2552
intel_pmu_disable_event(struct perf_event * event)2553 static void intel_pmu_disable_event(struct perf_event *event)
2554 {
2555 struct hw_perf_event *hwc = &event->hw;
2556 int idx = hwc->idx;
2557
2558 switch (idx) {
2559 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2560 intel_clear_masks(event, idx);
2561 x86_pmu_disable_event(event);
2562 break;
2563 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2564 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2565 intel_pmu_disable_fixed(event);
2566 break;
2567 case INTEL_PMC_IDX_FIXED_BTS:
2568 intel_pmu_disable_bts();
2569 intel_pmu_drain_bts_buffer();
2570 return;
2571 case INTEL_PMC_IDX_FIXED_VLBR:
2572 intel_clear_masks(event, idx);
2573 break;
2574 default:
2575 intel_clear_masks(event, idx);
2576 pr_warn("Failed to disable the event with invalid index %d\n",
2577 idx);
2578 return;
2579 }
2580
2581 /*
2582 * Needs to be called after x86_pmu_disable_event,
2583 * so we don't trigger the event without PEBS bit set.
2584 */
2585 if (unlikely(event->attr.precise_ip))
2586 intel_pmu_pebs_disable(event);
2587 }
2588
intel_pmu_assign_event(struct perf_event * event,int idx)2589 static void intel_pmu_assign_event(struct perf_event *event, int idx)
2590 {
2591 if (is_pebs_pt(event))
2592 perf_report_aux_output_id(event, idx);
2593 }
2594
intel_pmu_needs_branch_stack(struct perf_event * event)2595 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event)
2596 {
2597 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK;
2598 }
2599
intel_pmu_del_event(struct perf_event * event)2600 static void intel_pmu_del_event(struct perf_event *event)
2601 {
2602 if (intel_pmu_needs_branch_stack(event))
2603 intel_pmu_lbr_del(event);
2604 if (event->attr.precise_ip)
2605 intel_pmu_pebs_del(event);
2606 }
2607
icl_set_topdown_event_period(struct perf_event * event)2608 static int icl_set_topdown_event_period(struct perf_event *event)
2609 {
2610 struct hw_perf_event *hwc = &event->hw;
2611 s64 left = local64_read(&hwc->period_left);
2612
2613 /*
2614 * The values in PERF_METRICS MSR are derived from fixed counter 3.
2615 * Software should start both registers, PERF_METRICS and fixed
2616 * counter 3, from zero.
2617 * Clear PERF_METRICS and Fixed counter 3 in initialization.
2618 * After that, both MSRs will be cleared for each read.
2619 * Don't need to clear them again.
2620 */
2621 if (left == x86_pmu.max_period) {
2622 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2623 wrmsrl(MSR_PERF_METRICS, 0);
2624 hwc->saved_slots = 0;
2625 hwc->saved_metric = 0;
2626 }
2627
2628 if ((hwc->saved_slots) && is_slots_event(event)) {
2629 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2630 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2631 }
2632
2633 perf_event_update_userpage(event);
2634
2635 return 0;
2636 }
2637
2638 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period);
2639
icl_get_metrics_event_value(u64 metric,u64 slots,int idx)2640 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2641 {
2642 u32 val;
2643
2644 /*
2645 * The metric is reported as an 8bit integer fraction
2646 * summing up to 0xff.
2647 * slots-in-metric = (Metric / 0xff) * slots
2648 */
2649 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2650 return mul_u64_u32_div(slots, val, 0xff);
2651 }
2652
icl_get_topdown_value(struct perf_event * event,u64 slots,u64 metrics)2653 static u64 icl_get_topdown_value(struct perf_event *event,
2654 u64 slots, u64 metrics)
2655 {
2656 int idx = event->hw.idx;
2657 u64 delta;
2658
2659 if (is_metric_idx(idx))
2660 delta = icl_get_metrics_event_value(metrics, slots, idx);
2661 else
2662 delta = slots;
2663
2664 return delta;
2665 }
2666
__icl_update_topdown_event(struct perf_event * event,u64 slots,u64 metrics,u64 last_slots,u64 last_metrics)2667 static void __icl_update_topdown_event(struct perf_event *event,
2668 u64 slots, u64 metrics,
2669 u64 last_slots, u64 last_metrics)
2670 {
2671 u64 delta, last = 0;
2672
2673 delta = icl_get_topdown_value(event, slots, metrics);
2674 if (last_slots)
2675 last = icl_get_topdown_value(event, last_slots, last_metrics);
2676
2677 /*
2678 * The 8bit integer fraction of metric may be not accurate,
2679 * especially when the changes is very small.
2680 * For example, if only a few bad_spec happens, the fraction
2681 * may be reduced from 1 to 0. If so, the bad_spec event value
2682 * will be 0 which is definitely less than the last value.
2683 * Avoid update event->count for this case.
2684 */
2685 if (delta > last) {
2686 delta -= last;
2687 local64_add(delta, &event->count);
2688 }
2689 }
2690
update_saved_topdown_regs(struct perf_event * event,u64 slots,u64 metrics,int metric_end)2691 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2692 u64 metrics, int metric_end)
2693 {
2694 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2695 struct perf_event *other;
2696 int idx;
2697
2698 event->hw.saved_slots = slots;
2699 event->hw.saved_metric = metrics;
2700
2701 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2702 if (!is_topdown_idx(idx))
2703 continue;
2704 other = cpuc->events[idx];
2705 other->hw.saved_slots = slots;
2706 other->hw.saved_metric = metrics;
2707 }
2708 }
2709
2710 /*
2711 * Update all active Topdown events.
2712 *
2713 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2714 * modify by a NMI. PMU has to be disabled before calling this function.
2715 */
2716
intel_update_topdown_event(struct perf_event * event,int metric_end,u64 * val)2717 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end, u64 *val)
2718 {
2719 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2720 struct perf_event *other;
2721 u64 slots, metrics;
2722 bool reset = true;
2723 int idx;
2724
2725 if (!val) {
2726 /* read Fixed counter 3 */
2727 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2728 if (!slots)
2729 return 0;
2730
2731 /* read PERF_METRICS */
2732 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2733 } else {
2734 slots = val[0];
2735 metrics = val[1];
2736 /*
2737 * Don't reset the PERF_METRICS and Fixed counter 3
2738 * for each PEBS record read. Utilize the RDPMC metrics
2739 * clear mode.
2740 */
2741 reset = false;
2742 }
2743
2744 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2745 if (!is_topdown_idx(idx))
2746 continue;
2747 other = cpuc->events[idx];
2748 __icl_update_topdown_event(other, slots, metrics,
2749 event ? event->hw.saved_slots : 0,
2750 event ? event->hw.saved_metric : 0);
2751 }
2752
2753 /*
2754 * Check and update this event, which may have been cleared
2755 * in active_mask e.g. x86_pmu_stop()
2756 */
2757 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2758 __icl_update_topdown_event(event, slots, metrics,
2759 event->hw.saved_slots,
2760 event->hw.saved_metric);
2761
2762 /*
2763 * In x86_pmu_stop(), the event is cleared in active_mask first,
2764 * then drain the delta, which indicates context switch for
2765 * counting.
2766 * Save metric and slots for context switch.
2767 * Don't need to reset the PERF_METRICS and Fixed counter 3.
2768 * Because the values will be restored in next schedule in.
2769 */
2770 update_saved_topdown_regs(event, slots, metrics, metric_end);
2771 reset = false;
2772 }
2773
2774 if (reset) {
2775 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2776 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2777 wrmsrl(MSR_PERF_METRICS, 0);
2778 if (event)
2779 update_saved_topdown_regs(event, 0, 0, metric_end);
2780 }
2781
2782 return slots;
2783 }
2784
icl_update_topdown_event(struct perf_event * event,u64 * val)2785 static u64 icl_update_topdown_event(struct perf_event *event, u64 *val)
2786 {
2787 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2788 x86_pmu.num_topdown_events - 1,
2789 val);
2790 }
2791
2792 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update);
2793
intel_pmu_read_event(struct perf_event * event)2794 static void intel_pmu_read_event(struct perf_event *event)
2795 {
2796 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN) ||
2797 is_pebs_counter_event_group(event)) {
2798 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2799 bool pmu_enabled = cpuc->enabled;
2800
2801 /* Only need to call update_topdown_event() once for group read. */
2802 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ))
2803 return;
2804
2805 cpuc->enabled = 0;
2806 if (pmu_enabled)
2807 intel_pmu_disable_all();
2808
2809 /*
2810 * If the PEBS counters snapshotting is enabled,
2811 * the topdown event is available in PEBS records.
2812 */
2813 if (is_topdown_event(event) && !is_pebs_counter_event_group(event))
2814 static_call(intel_pmu_update_topdown_event)(event, NULL);
2815 else
2816 intel_pmu_drain_pebs_buffer();
2817
2818 cpuc->enabled = pmu_enabled;
2819 if (pmu_enabled)
2820 intel_pmu_enable_all(0);
2821
2822 return;
2823 }
2824
2825 x86_perf_event_update(event);
2826 }
2827
intel_pmu_enable_fixed(struct perf_event * event)2828 static void intel_pmu_enable_fixed(struct perf_event *event)
2829 {
2830 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2831 struct hw_perf_event *hwc = &event->hw;
2832 u64 mask, bits = 0;
2833 int idx = hwc->idx;
2834
2835 if (is_topdown_idx(idx)) {
2836 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2837 /*
2838 * When there are other active TopDown events,
2839 * don't enable the fixed counter 3 again.
2840 */
2841 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2842 return;
2843
2844 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2845
2846 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR)
2847 bits |= INTEL_FIXED_3_METRICS_CLEAR;
2848 }
2849
2850 intel_set_masks(event, idx);
2851
2852 /*
2853 * Enable IRQ generation (0x8), if not PEBS,
2854 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2855 * if requested:
2856 */
2857 if (!event->attr.precise_ip)
2858 bits |= INTEL_FIXED_0_ENABLE_PMI;
2859 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2860 bits |= INTEL_FIXED_0_USER;
2861 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2862 bits |= INTEL_FIXED_0_KERNEL;
2863
2864 /*
2865 * ANY bit is supported in v3 and up
2866 */
2867 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2868 bits |= INTEL_FIXED_0_ANYTHREAD;
2869
2870 idx -= INTEL_PMC_IDX_FIXED;
2871 bits = intel_fixed_bits_by_idx(idx, bits);
2872 mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK);
2873
2874 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2875 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
2876 mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
2877 }
2878
2879 cpuc->fixed_ctrl_val &= ~mask;
2880 cpuc->fixed_ctrl_val |= bits;
2881 }
2882
intel_pmu_enable_event(struct perf_event * event)2883 static void intel_pmu_enable_event(struct perf_event *event)
2884 {
2885 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE;
2886 struct hw_perf_event *hwc = &event->hw;
2887 int idx = hwc->idx;
2888
2889 if (unlikely(event->attr.precise_ip))
2890 intel_pmu_pebs_enable(event);
2891
2892 switch (idx) {
2893 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2894 if (branch_sample_counters(event))
2895 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR;
2896 intel_set_masks(event, idx);
2897 __x86_pmu_enable_event(hwc, enable_mask);
2898 break;
2899 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2900 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2901 intel_pmu_enable_fixed(event);
2902 break;
2903 case INTEL_PMC_IDX_FIXED_BTS:
2904 if (!__this_cpu_read(cpu_hw_events.enabled))
2905 return;
2906 intel_pmu_enable_bts(hwc->config);
2907 break;
2908 case INTEL_PMC_IDX_FIXED_VLBR:
2909 intel_set_masks(event, idx);
2910 break;
2911 default:
2912 pr_warn("Failed to enable the event with invalid index %d\n",
2913 idx);
2914 }
2915 }
2916
intel_pmu_add_event(struct perf_event * event)2917 static void intel_pmu_add_event(struct perf_event *event)
2918 {
2919 if (event->attr.precise_ip)
2920 intel_pmu_pebs_add(event);
2921 if (intel_pmu_needs_branch_stack(event))
2922 intel_pmu_lbr_add(event);
2923 }
2924
2925 /*
2926 * Save and restart an expired event. Called by NMI contexts,
2927 * so it has to be careful about preempting normal event ops:
2928 */
intel_pmu_save_and_restart(struct perf_event * event)2929 int intel_pmu_save_and_restart(struct perf_event *event)
2930 {
2931 static_call(x86_pmu_update)(event);
2932 /*
2933 * For a checkpointed counter always reset back to 0. This
2934 * avoids a situation where the counter overflows, aborts the
2935 * transaction and is then set back to shortly before the
2936 * overflow, and overflows and aborts again.
2937 */
2938 if (unlikely(event_is_checkpointed(event))) {
2939 /* No race with NMIs because the counter should not be armed */
2940 wrmsrl(event->hw.event_base, 0);
2941 local64_set(&event->hw.prev_count, 0);
2942 }
2943 return static_call(x86_pmu_set_period)(event);
2944 }
2945
intel_pmu_set_period(struct perf_event * event)2946 static int intel_pmu_set_period(struct perf_event *event)
2947 {
2948 if (unlikely(is_topdown_count(event)))
2949 return static_call(intel_pmu_set_topdown_event_period)(event);
2950
2951 return x86_perf_event_set_period(event);
2952 }
2953
intel_pmu_update(struct perf_event * event)2954 static u64 intel_pmu_update(struct perf_event *event)
2955 {
2956 if (unlikely(is_topdown_count(event)))
2957 return static_call(intel_pmu_update_topdown_event)(event, NULL);
2958
2959 return x86_perf_event_update(event);
2960 }
2961
intel_pmu_reset(void)2962 static void intel_pmu_reset(void)
2963 {
2964 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2965 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2966 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask);
2967 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);
2968 unsigned long flags;
2969 int idx;
2970
2971 if (!*(u64 *)cntr_mask)
2972 return;
2973
2974 local_irq_save(flags);
2975
2976 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2977
2978 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) {
2979 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2980 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2981 }
2982 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) {
2983 if (fixed_counter_disabled(idx, cpuc->pmu))
2984 continue;
2985 wrmsrl_safe(x86_pmu_fixed_ctr_addr(idx), 0ull);
2986 }
2987
2988 if (ds)
2989 ds->bts_index = ds->bts_buffer_base;
2990
2991 /* Ack all overflows and disable fixed counters */
2992 if (x86_pmu.version >= 2) {
2993 intel_pmu_ack_status(intel_pmu_get_status());
2994 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2995 }
2996
2997 /* Reset LBRs and LBR freezing */
2998 if (x86_pmu.lbr_nr) {
2999 update_debugctlmsr(get_debugctlmsr() &
3000 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
3001 }
3002
3003 local_irq_restore(flags);
3004 }
3005
3006 /*
3007 * We may be running with guest PEBS events created by KVM, and the
3008 * PEBS records are logged into the guest's DS and invisible to host.
3009 *
3010 * In the case of guest PEBS overflow, we only trigger a fake event
3011 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM.
3012 * The guest will then vm-entry and check the guest DS area to read
3013 * the guest PEBS records.
3014 *
3015 * The contents and other behavior of the guest event do not matter.
3016 */
x86_pmu_handle_guest_pebs(struct pt_regs * regs,struct perf_sample_data * data)3017 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs,
3018 struct perf_sample_data *data)
3019 {
3020 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3021 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
3022 struct perf_event *event = NULL;
3023 int bit;
3024
3025 if (!unlikely(perf_guest_state()))
3026 return;
3027
3028 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active ||
3029 !guest_pebs_idxs)
3030 return;
3031
3032 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) {
3033 event = cpuc->events[bit];
3034 if (!event->attr.precise_ip)
3035 continue;
3036
3037 perf_sample_data_init(data, 0, event->hw.last_period);
3038 if (perf_event_overflow(event, data, regs))
3039 x86_pmu_stop(event, 0);
3040
3041 /* Inject one fake event is enough. */
3042 break;
3043 }
3044 }
3045
handle_pmi_common(struct pt_regs * regs,u64 status)3046 static int handle_pmi_common(struct pt_regs *regs, u64 status)
3047 {
3048 struct perf_sample_data data;
3049 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3050 int bit;
3051 int handled = 0;
3052 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
3053
3054 inc_irq_stat(apic_perf_irqs);
3055
3056 /*
3057 * Ignore a range of extra bits in status that do not indicate
3058 * overflow by themselves.
3059 */
3060 status &= ~(GLOBAL_STATUS_COND_CHG |
3061 GLOBAL_STATUS_ASIF |
3062 GLOBAL_STATUS_LBRS_FROZEN);
3063 if (!status)
3064 return 0;
3065 /*
3066 * In case multiple PEBS events are sampled at the same time,
3067 * it is possible to have GLOBAL_STATUS bit 62 set indicating
3068 * PEBS buffer overflow and also seeing at most 3 PEBS counters
3069 * having their bits set in the status register. This is a sign
3070 * that there was at least one PEBS record pending at the time
3071 * of the PMU interrupt. PEBS counters must only be processed
3072 * via the drain_pebs() calls and not via the regular sample
3073 * processing loop coming after that the function, otherwise
3074 * phony regular samples may be generated in the sampling buffer
3075 * not marked with the EXACT tag. Another possibility is to have
3076 * one PEBS event and at least one non-PEBS event which overflows
3077 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
3078 * not be set, yet the overflow status bit for the PEBS counter will
3079 * be on Skylake.
3080 *
3081 * To avoid this problem, we systematically ignore the PEBS-enabled
3082 * counters from the GLOBAL_STATUS mask and we always process PEBS
3083 * events via drain_pebs().
3084 */
3085 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
3086
3087 /*
3088 * PEBS overflow sets bit 62 in the global status register
3089 */
3090 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
3091 u64 pebs_enabled = cpuc->pebs_enabled;
3092
3093 handled++;
3094 x86_pmu_handle_guest_pebs(regs, &data);
3095 static_call(x86_pmu_drain_pebs)(regs, &data);
3096 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
3097
3098 /*
3099 * PMI throttle may be triggered, which stops the PEBS event.
3100 * Although cpuc->pebs_enabled is updated accordingly, the
3101 * MSR_IA32_PEBS_ENABLE is not updated. Because the
3102 * cpuc->enabled has been forced to 0 in PMI.
3103 * Update the MSR if pebs_enabled is changed.
3104 */
3105 if (pebs_enabled != cpuc->pebs_enabled)
3106 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
3107 }
3108
3109 /*
3110 * Intel PT
3111 */
3112 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
3113 handled++;
3114 if (!perf_guest_handle_intel_pt_intr())
3115 intel_pt_interrupt();
3116 }
3117
3118 /*
3119 * Intel Perf metrics
3120 */
3121 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
3122 handled++;
3123 static_call(intel_pmu_update_topdown_event)(NULL, NULL);
3124 }
3125
3126 /*
3127 * Checkpointed counters can lead to 'spurious' PMIs because the
3128 * rollback caused by the PMI will have cleared the overflow status
3129 * bit. Therefore always force probe these counters.
3130 */
3131 status |= cpuc->intel_cp_status;
3132
3133 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
3134 struct perf_event *event = cpuc->events[bit];
3135
3136 handled++;
3137
3138 if (!test_bit(bit, cpuc->active_mask))
3139 continue;
3140
3141 /*
3142 * There may be unprocessed PEBS records in the PEBS buffer,
3143 * which still stores the previous values.
3144 * Process those records first before handling the latest value.
3145 * For example,
3146 * A is a regular counter
3147 * B is a PEBS event which reads A
3148 * C is a PEBS event
3149 *
3150 * The following can happen:
3151 * B-assist A=1
3152 * C A=2
3153 * B-assist A=3
3154 * A-overflow-PMI A=4
3155 * C-assist-PMI (PEBS buffer) A=5
3156 *
3157 * The PEBS buffer has to be drained before handling the A-PMI
3158 */
3159 if (is_pebs_counter_event_group(event))
3160 x86_pmu.drain_pebs(regs, &data);
3161
3162 if (!intel_pmu_save_and_restart(event))
3163 continue;
3164
3165 perf_sample_data_init(&data, 0, event->hw.last_period);
3166
3167 if (has_branch_stack(event))
3168 intel_pmu_lbr_save_brstack(&data, cpuc, event);
3169
3170 if (perf_event_overflow(event, &data, regs))
3171 x86_pmu_stop(event, 0);
3172 }
3173
3174 return handled;
3175 }
3176
3177 /*
3178 * This handler is triggered by the local APIC, so the APIC IRQ handling
3179 * rules apply:
3180 */
intel_pmu_handle_irq(struct pt_regs * regs)3181 static int intel_pmu_handle_irq(struct pt_regs *regs)
3182 {
3183 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3184 bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
3185 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
3186 int loops;
3187 u64 status;
3188 int handled;
3189 int pmu_enabled;
3190
3191 /*
3192 * Save the PMU state.
3193 * It needs to be restored when leaving the handler.
3194 */
3195 pmu_enabled = cpuc->enabled;
3196 /*
3197 * In general, the early ACK is only applied for old platforms.
3198 * For the big core starts from Haswell, the late ACK should be
3199 * applied.
3200 * For the small core after Tremont, we have to do the ACK right
3201 * before re-enabling counters, which is in the middle of the
3202 * NMI handler.
3203 */
3204 if (!late_ack && !mid_ack)
3205 apic_write(APIC_LVTPC, APIC_DM_NMI);
3206 intel_bts_disable_local();
3207 cpuc->enabled = 0;
3208 __intel_pmu_disable_all(true);
3209 handled = intel_pmu_drain_bts_buffer();
3210 handled += intel_bts_interrupt();
3211 status = intel_pmu_get_status();
3212 if (!status)
3213 goto done;
3214
3215 loops = 0;
3216 again:
3217 intel_pmu_lbr_read();
3218 intel_pmu_ack_status(status);
3219 if (++loops > 100) {
3220 static bool warned;
3221
3222 if (!warned) {
3223 WARN(1, "perfevents: irq loop stuck!\n");
3224 perf_event_print_debug();
3225 warned = true;
3226 }
3227 intel_pmu_reset();
3228 goto done;
3229 }
3230
3231 handled += handle_pmi_common(regs, status);
3232
3233 /*
3234 * Repeat if there is more work to be done:
3235 */
3236 status = intel_pmu_get_status();
3237 if (status)
3238 goto again;
3239
3240 done:
3241 if (mid_ack)
3242 apic_write(APIC_LVTPC, APIC_DM_NMI);
3243 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
3244 cpuc->enabled = pmu_enabled;
3245 if (pmu_enabled)
3246 __intel_pmu_enable_all(0, true);
3247 intel_bts_enable_local();
3248
3249 /*
3250 * Only unmask the NMI after the overflow counters
3251 * have been reset. This avoids spurious NMIs on
3252 * Haswell CPUs.
3253 */
3254 if (late_ack)
3255 apic_write(APIC_LVTPC, APIC_DM_NMI);
3256 return handled;
3257 }
3258
3259 static struct event_constraint *
intel_bts_constraints(struct perf_event * event)3260 intel_bts_constraints(struct perf_event *event)
3261 {
3262 if (unlikely(intel_pmu_has_bts(event)))
3263 return &bts_constraint;
3264
3265 return NULL;
3266 }
3267
3268 /*
3269 * Note: matches a fake event, like Fixed2.
3270 */
3271 static struct event_constraint *
intel_vlbr_constraints(struct perf_event * event)3272 intel_vlbr_constraints(struct perf_event *event)
3273 {
3274 struct event_constraint *c = &vlbr_constraint;
3275
3276 if (unlikely(constraint_match(c, event->hw.config))) {
3277 event->hw.flags |= c->flags;
3278 return c;
3279 }
3280
3281 return NULL;
3282 }
3283
intel_alt_er(struct cpu_hw_events * cpuc,int idx,u64 config)3284 static int intel_alt_er(struct cpu_hw_events *cpuc,
3285 int idx, u64 config)
3286 {
3287 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
3288 int alt_idx = idx;
3289
3290 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
3291 return idx;
3292
3293 if (idx == EXTRA_REG_RSP_0)
3294 alt_idx = EXTRA_REG_RSP_1;
3295
3296 if (idx == EXTRA_REG_RSP_1)
3297 alt_idx = EXTRA_REG_RSP_0;
3298
3299 if (config & ~extra_regs[alt_idx].valid_mask)
3300 return idx;
3301
3302 return alt_idx;
3303 }
3304
intel_fixup_er(struct perf_event * event,int idx)3305 static void intel_fixup_er(struct perf_event *event, int idx)
3306 {
3307 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
3308 event->hw.extra_reg.idx = idx;
3309
3310 if (idx == EXTRA_REG_RSP_0) {
3311 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3312 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
3313 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
3314 } else if (idx == EXTRA_REG_RSP_1) {
3315 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3316 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
3317 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
3318 }
3319 }
3320
3321 /*
3322 * manage allocation of shared extra msr for certain events
3323 *
3324 * sharing can be:
3325 * per-cpu: to be shared between the various events on a single PMU
3326 * per-core: per-cpu + shared by HT threads
3327 */
3328 static struct event_constraint *
__intel_shared_reg_get_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct hw_perf_event_extra * reg)3329 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3330 struct perf_event *event,
3331 struct hw_perf_event_extra *reg)
3332 {
3333 struct event_constraint *c = &emptyconstraint;
3334 struct er_account *era;
3335 unsigned long flags;
3336 int idx = reg->idx;
3337
3338 /*
3339 * reg->alloc can be set due to existing state, so for fake cpuc we
3340 * need to ignore this, otherwise we might fail to allocate proper fake
3341 * state for this extra reg constraint. Also see the comment below.
3342 */
3343 if (reg->alloc && !cpuc->is_fake)
3344 return NULL; /* call x86_get_event_constraint() */
3345
3346 again:
3347 era = &cpuc->shared_regs->regs[idx];
3348 /*
3349 * we use spin_lock_irqsave() to avoid lockdep issues when
3350 * passing a fake cpuc
3351 */
3352 raw_spin_lock_irqsave(&era->lock, flags);
3353
3354 if (!atomic_read(&era->ref) || era->config == reg->config) {
3355
3356 /*
3357 * If its a fake cpuc -- as per validate_{group,event}() we
3358 * shouldn't touch event state and we can avoid doing so
3359 * since both will only call get_event_constraints() once
3360 * on each event, this avoids the need for reg->alloc.
3361 *
3362 * Not doing the ER fixup will only result in era->reg being
3363 * wrong, but since we won't actually try and program hardware
3364 * this isn't a problem either.
3365 */
3366 if (!cpuc->is_fake) {
3367 if (idx != reg->idx)
3368 intel_fixup_er(event, idx);
3369
3370 /*
3371 * x86_schedule_events() can call get_event_constraints()
3372 * multiple times on events in the case of incremental
3373 * scheduling(). reg->alloc ensures we only do the ER
3374 * allocation once.
3375 */
3376 reg->alloc = 1;
3377 }
3378
3379 /* lock in msr value */
3380 era->config = reg->config;
3381 era->reg = reg->reg;
3382
3383 /* one more user */
3384 atomic_inc(&era->ref);
3385
3386 /*
3387 * need to call x86_get_event_constraint()
3388 * to check if associated event has constraints
3389 */
3390 c = NULL;
3391 } else {
3392 idx = intel_alt_er(cpuc, idx, reg->config);
3393 if (idx != reg->idx) {
3394 raw_spin_unlock_irqrestore(&era->lock, flags);
3395 goto again;
3396 }
3397 }
3398 raw_spin_unlock_irqrestore(&era->lock, flags);
3399
3400 return c;
3401 }
3402
3403 static void
__intel_shared_reg_put_constraints(struct cpu_hw_events * cpuc,struct hw_perf_event_extra * reg)3404 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3405 struct hw_perf_event_extra *reg)
3406 {
3407 struct er_account *era;
3408
3409 /*
3410 * Only put constraint if extra reg was actually allocated. Also takes
3411 * care of event which do not use an extra shared reg.
3412 *
3413 * Also, if this is a fake cpuc we shouldn't touch any event state
3414 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3415 * either since it'll be thrown out.
3416 */
3417 if (!reg->alloc || cpuc->is_fake)
3418 return;
3419
3420 era = &cpuc->shared_regs->regs[reg->idx];
3421
3422 /* one fewer user */
3423 atomic_dec(&era->ref);
3424
3425 /* allocate again next time */
3426 reg->alloc = 0;
3427 }
3428
3429 static struct event_constraint *
intel_shared_regs_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3430 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3431 struct perf_event *event)
3432 {
3433 struct event_constraint *c = NULL, *d;
3434 struct hw_perf_event_extra *xreg, *breg;
3435
3436 xreg = &event->hw.extra_reg;
3437 if (xreg->idx != EXTRA_REG_NONE) {
3438 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3439 if (c == &emptyconstraint)
3440 return c;
3441 }
3442 breg = &event->hw.branch_reg;
3443 if (breg->idx != EXTRA_REG_NONE) {
3444 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3445 if (d == &emptyconstraint) {
3446 __intel_shared_reg_put_constraints(cpuc, xreg);
3447 c = d;
3448 }
3449 }
3450 return c;
3451 }
3452
3453 struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3454 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3455 struct perf_event *event)
3456 {
3457 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
3458 struct event_constraint *c;
3459
3460 if (event_constraints) {
3461 for_each_event_constraint(c, event_constraints) {
3462 if (constraint_match(c, event->hw.config)) {
3463 event->hw.flags |= c->flags;
3464 return c;
3465 }
3466 }
3467 }
3468
3469 return &hybrid_var(cpuc->pmu, unconstrained);
3470 }
3471
3472 static struct event_constraint *
__intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3473 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3474 struct perf_event *event)
3475 {
3476 struct event_constraint *c;
3477
3478 c = intel_vlbr_constraints(event);
3479 if (c)
3480 return c;
3481
3482 c = intel_bts_constraints(event);
3483 if (c)
3484 return c;
3485
3486 c = intel_shared_regs_constraints(cpuc, event);
3487 if (c)
3488 return c;
3489
3490 c = intel_pebs_constraints(event);
3491 if (c)
3492 return c;
3493
3494 return x86_get_event_constraints(cpuc, idx, event);
3495 }
3496
3497 static void
intel_start_scheduling(struct cpu_hw_events * cpuc)3498 intel_start_scheduling(struct cpu_hw_events *cpuc)
3499 {
3500 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3501 struct intel_excl_states *xl;
3502 int tid = cpuc->excl_thread_id;
3503
3504 /*
3505 * nothing needed if in group validation mode
3506 */
3507 if (cpuc->is_fake || !is_ht_workaround_enabled())
3508 return;
3509
3510 /*
3511 * no exclusion needed
3512 */
3513 if (WARN_ON_ONCE(!excl_cntrs))
3514 return;
3515
3516 xl = &excl_cntrs->states[tid];
3517
3518 xl->sched_started = true;
3519 /*
3520 * lock shared state until we are done scheduling
3521 * in stop_event_scheduling()
3522 * makes scheduling appear as a transaction
3523 */
3524 raw_spin_lock(&excl_cntrs->lock);
3525 }
3526
intel_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)3527 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3528 {
3529 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3530 struct event_constraint *c = cpuc->event_constraint[idx];
3531 struct intel_excl_states *xl;
3532 int tid = cpuc->excl_thread_id;
3533
3534 if (cpuc->is_fake || !is_ht_workaround_enabled())
3535 return;
3536
3537 if (WARN_ON_ONCE(!excl_cntrs))
3538 return;
3539
3540 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3541 return;
3542
3543 xl = &excl_cntrs->states[tid];
3544
3545 lockdep_assert_held(&excl_cntrs->lock);
3546
3547 if (c->flags & PERF_X86_EVENT_EXCL)
3548 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3549 else
3550 xl->state[cntr] = INTEL_EXCL_SHARED;
3551 }
3552
3553 static void
intel_stop_scheduling(struct cpu_hw_events * cpuc)3554 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3555 {
3556 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3557 struct intel_excl_states *xl;
3558 int tid = cpuc->excl_thread_id;
3559
3560 /*
3561 * nothing needed if in group validation mode
3562 */
3563 if (cpuc->is_fake || !is_ht_workaround_enabled())
3564 return;
3565 /*
3566 * no exclusion needed
3567 */
3568 if (WARN_ON_ONCE(!excl_cntrs))
3569 return;
3570
3571 xl = &excl_cntrs->states[tid];
3572
3573 xl->sched_started = false;
3574 /*
3575 * release shared state lock (acquired in intel_start_scheduling())
3576 */
3577 raw_spin_unlock(&excl_cntrs->lock);
3578 }
3579
3580 static struct event_constraint *
dyn_constraint(struct cpu_hw_events * cpuc,struct event_constraint * c,int idx)3581 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3582 {
3583 WARN_ON_ONCE(!cpuc->constraint_list);
3584
3585 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3586 struct event_constraint *cx;
3587
3588 /*
3589 * grab pre-allocated constraint entry
3590 */
3591 cx = &cpuc->constraint_list[idx];
3592
3593 /*
3594 * initialize dynamic constraint
3595 * with static constraint
3596 */
3597 *cx = *c;
3598
3599 /*
3600 * mark constraint as dynamic
3601 */
3602 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3603 c = cx;
3604 }
3605
3606 return c;
3607 }
3608
3609 static struct event_constraint *
intel_get_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,int idx,struct event_constraint * c)3610 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3611 int idx, struct event_constraint *c)
3612 {
3613 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3614 struct intel_excl_states *xlo;
3615 int tid = cpuc->excl_thread_id;
3616 int is_excl, i, w;
3617
3618 /*
3619 * validating a group does not require
3620 * enforcing cross-thread exclusion
3621 */
3622 if (cpuc->is_fake || !is_ht_workaround_enabled())
3623 return c;
3624
3625 /*
3626 * no exclusion needed
3627 */
3628 if (WARN_ON_ONCE(!excl_cntrs))
3629 return c;
3630
3631 /*
3632 * because we modify the constraint, we need
3633 * to make a copy. Static constraints come
3634 * from static const tables.
3635 *
3636 * only needed when constraint has not yet
3637 * been cloned (marked dynamic)
3638 */
3639 c = dyn_constraint(cpuc, c, idx);
3640
3641 /*
3642 * From here on, the constraint is dynamic.
3643 * Either it was just allocated above, or it
3644 * was allocated during a earlier invocation
3645 * of this function
3646 */
3647
3648 /*
3649 * state of sibling HT
3650 */
3651 xlo = &excl_cntrs->states[tid ^ 1];
3652
3653 /*
3654 * event requires exclusive counter access
3655 * across HT threads
3656 */
3657 is_excl = c->flags & PERF_X86_EVENT_EXCL;
3658 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3659 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3660 if (!cpuc->n_excl++)
3661 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3662 }
3663
3664 /*
3665 * Modify static constraint with current dynamic
3666 * state of thread
3667 *
3668 * EXCLUSIVE: sibling counter measuring exclusive event
3669 * SHARED : sibling counter measuring non-exclusive event
3670 * UNUSED : sibling counter unused
3671 */
3672 w = c->weight;
3673 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3674 /*
3675 * exclusive event in sibling counter
3676 * our corresponding counter cannot be used
3677 * regardless of our event
3678 */
3679 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3680 __clear_bit(i, c->idxmsk);
3681 w--;
3682 continue;
3683 }
3684 /*
3685 * if measuring an exclusive event, sibling
3686 * measuring non-exclusive, then counter cannot
3687 * be used
3688 */
3689 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3690 __clear_bit(i, c->idxmsk);
3691 w--;
3692 continue;
3693 }
3694 }
3695
3696 /*
3697 * if we return an empty mask, then switch
3698 * back to static empty constraint to avoid
3699 * the cost of freeing later on
3700 */
3701 if (!w)
3702 c = &emptyconstraint;
3703
3704 c->weight = w;
3705
3706 return c;
3707 }
3708
3709 static struct event_constraint *
intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3710 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3711 struct perf_event *event)
3712 {
3713 struct event_constraint *c1, *c2;
3714
3715 c1 = cpuc->event_constraint[idx];
3716
3717 /*
3718 * first time only
3719 * - static constraint: no change across incremental scheduling calls
3720 * - dynamic constraint: handled by intel_get_excl_constraints()
3721 */
3722 c2 = __intel_get_event_constraints(cpuc, idx, event);
3723 if (c1) {
3724 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3725 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3726 c1->weight = c2->weight;
3727 c2 = c1;
3728 }
3729
3730 if (cpuc->excl_cntrs)
3731 return intel_get_excl_constraints(cpuc, event, idx, c2);
3732
3733 /* Not all counters support the branch counter feature. */
3734 if (branch_sample_counters(event)) {
3735 c2 = dyn_constraint(cpuc, c2, idx);
3736 c2->idxmsk64 &= x86_pmu.lbr_counters;
3737 c2->weight = hweight64(c2->idxmsk64);
3738 }
3739
3740 return c2;
3741 }
3742
intel_put_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3743 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3744 struct perf_event *event)
3745 {
3746 struct hw_perf_event *hwc = &event->hw;
3747 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3748 int tid = cpuc->excl_thread_id;
3749 struct intel_excl_states *xl;
3750
3751 /*
3752 * nothing needed if in group validation mode
3753 */
3754 if (cpuc->is_fake)
3755 return;
3756
3757 if (WARN_ON_ONCE(!excl_cntrs))
3758 return;
3759
3760 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3761 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3762 if (!--cpuc->n_excl)
3763 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3764 }
3765
3766 /*
3767 * If event was actually assigned, then mark the counter state as
3768 * unused now.
3769 */
3770 if (hwc->idx >= 0) {
3771 xl = &excl_cntrs->states[tid];
3772
3773 /*
3774 * put_constraint may be called from x86_schedule_events()
3775 * which already has the lock held so here make locking
3776 * conditional.
3777 */
3778 if (!xl->sched_started)
3779 raw_spin_lock(&excl_cntrs->lock);
3780
3781 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3782
3783 if (!xl->sched_started)
3784 raw_spin_unlock(&excl_cntrs->lock);
3785 }
3786 }
3787
3788 static void
intel_put_shared_regs_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3789 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3790 struct perf_event *event)
3791 {
3792 struct hw_perf_event_extra *reg;
3793
3794 reg = &event->hw.extra_reg;
3795 if (reg->idx != EXTRA_REG_NONE)
3796 __intel_shared_reg_put_constraints(cpuc, reg);
3797
3798 reg = &event->hw.branch_reg;
3799 if (reg->idx != EXTRA_REG_NONE)
3800 __intel_shared_reg_put_constraints(cpuc, reg);
3801 }
3802
intel_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3803 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3804 struct perf_event *event)
3805 {
3806 intel_put_shared_regs_event_constraints(cpuc, event);
3807
3808 /*
3809 * is PMU has exclusive counter restrictions, then
3810 * all events are subject to and must call the
3811 * put_excl_constraints() routine
3812 */
3813 if (cpuc->excl_cntrs)
3814 intel_put_excl_constraints(cpuc, event);
3815 }
3816
intel_pebs_aliases_core2(struct perf_event * event)3817 static void intel_pebs_aliases_core2(struct perf_event *event)
3818 {
3819 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3820 /*
3821 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3822 * (0x003c) so that we can use it with PEBS.
3823 *
3824 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3825 * PEBS capable. However we can use INST_RETIRED.ANY_P
3826 * (0x00c0), which is a PEBS capable event, to get the same
3827 * count.
3828 *
3829 * INST_RETIRED.ANY_P counts the number of cycles that retires
3830 * CNTMASK instructions. By setting CNTMASK to a value (16)
3831 * larger than the maximum number of instructions that can be
3832 * retired per cycle (4) and then inverting the condition, we
3833 * count all cycles that retire 16 or less instructions, which
3834 * is every cycle.
3835 *
3836 * Thereby we gain a PEBS capable cycle counter.
3837 */
3838 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3839
3840 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3841 event->hw.config = alt_config;
3842 }
3843 }
3844
intel_pebs_aliases_snb(struct perf_event * event)3845 static void intel_pebs_aliases_snb(struct perf_event *event)
3846 {
3847 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3848 /*
3849 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3850 * (0x003c) so that we can use it with PEBS.
3851 *
3852 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3853 * PEBS capable. However we can use UOPS_RETIRED.ALL
3854 * (0x01c2), which is a PEBS capable event, to get the same
3855 * count.
3856 *
3857 * UOPS_RETIRED.ALL counts the number of cycles that retires
3858 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3859 * larger than the maximum number of micro-ops that can be
3860 * retired per cycle (4) and then inverting the condition, we
3861 * count all cycles that retire 16 or less micro-ops, which
3862 * is every cycle.
3863 *
3864 * Thereby we gain a PEBS capable cycle counter.
3865 */
3866 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3867
3868 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3869 event->hw.config = alt_config;
3870 }
3871 }
3872
intel_pebs_aliases_precdist(struct perf_event * event)3873 static void intel_pebs_aliases_precdist(struct perf_event *event)
3874 {
3875 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3876 /*
3877 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3878 * (0x003c) so that we can use it with PEBS.
3879 *
3880 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3881 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3882 * (0x01c0), which is a PEBS capable event, to get the same
3883 * count.
3884 *
3885 * The PREC_DIST event has special support to minimize sample
3886 * shadowing effects. One drawback is that it can be
3887 * only programmed on counter 1, but that seems like an
3888 * acceptable trade off.
3889 */
3890 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3891
3892 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3893 event->hw.config = alt_config;
3894 }
3895 }
3896
intel_pebs_aliases_ivb(struct perf_event * event)3897 static void intel_pebs_aliases_ivb(struct perf_event *event)
3898 {
3899 if (event->attr.precise_ip < 3)
3900 return intel_pebs_aliases_snb(event);
3901 return intel_pebs_aliases_precdist(event);
3902 }
3903
intel_pebs_aliases_skl(struct perf_event * event)3904 static void intel_pebs_aliases_skl(struct perf_event *event)
3905 {
3906 if (event->attr.precise_ip < 3)
3907 return intel_pebs_aliases_core2(event);
3908 return intel_pebs_aliases_precdist(event);
3909 }
3910
intel_pmu_large_pebs_flags(struct perf_event * event)3911 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3912 {
3913 unsigned long flags = x86_pmu.large_pebs_flags;
3914
3915 if (event->attr.use_clockid)
3916 flags &= ~PERF_SAMPLE_TIME;
3917 if (!event->attr.exclude_kernel)
3918 flags &= ~PERF_SAMPLE_REGS_USER;
3919 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3920 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3921 return flags;
3922 }
3923
intel_pmu_bts_config(struct perf_event * event)3924 static int intel_pmu_bts_config(struct perf_event *event)
3925 {
3926 struct perf_event_attr *attr = &event->attr;
3927
3928 if (unlikely(intel_pmu_has_bts(event))) {
3929 /* BTS is not supported by this architecture. */
3930 if (!x86_pmu.bts_active)
3931 return -EOPNOTSUPP;
3932
3933 /* BTS is currently only allowed for user-mode. */
3934 if (!attr->exclude_kernel)
3935 return -EOPNOTSUPP;
3936
3937 /* BTS is not allowed for precise events. */
3938 if (attr->precise_ip)
3939 return -EOPNOTSUPP;
3940
3941 /* disallow bts if conflicting events are present */
3942 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3943 return -EBUSY;
3944
3945 event->destroy = hw_perf_lbr_event_destroy;
3946 }
3947
3948 return 0;
3949 }
3950
core_pmu_hw_config(struct perf_event * event)3951 static int core_pmu_hw_config(struct perf_event *event)
3952 {
3953 int ret = x86_pmu_hw_config(event);
3954
3955 if (ret)
3956 return ret;
3957
3958 return intel_pmu_bts_config(event);
3959 }
3960
3961 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \
3962 ((x86_pmu.num_topdown_events - 1) << 8))
3963
is_available_metric_event(struct perf_event * event)3964 static bool is_available_metric_event(struct perf_event *event)
3965 {
3966 return is_metric_event(event) &&
3967 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
3968 }
3969
is_mem_loads_event(struct perf_event * event)3970 static inline bool is_mem_loads_event(struct perf_event *event)
3971 {
3972 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
3973 }
3974
is_mem_loads_aux_event(struct perf_event * event)3975 static inline bool is_mem_loads_aux_event(struct perf_event *event)
3976 {
3977 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
3978 }
3979
require_mem_loads_aux_event(struct perf_event * event)3980 static inline bool require_mem_loads_aux_event(struct perf_event *event)
3981 {
3982 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
3983 return false;
3984
3985 if (is_hybrid())
3986 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big;
3987
3988 return true;
3989 }
3990
intel_pmu_has_cap(struct perf_event * event,int idx)3991 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
3992 {
3993 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
3994
3995 return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
3996 }
3997
intel_pmu_freq_start_period(struct perf_event * event)3998 static u64 intel_pmu_freq_start_period(struct perf_event *event)
3999 {
4000 int type = event->attr.type;
4001 u64 config, factor;
4002 s64 start;
4003
4004 /*
4005 * The 127 is the lowest possible recommended SAV (sample after value)
4006 * for a 4000 freq (default freq), according to the event list JSON file.
4007 * Also, assume the workload is idle 50% time.
4008 */
4009 factor = 64 * 4000;
4010 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE)
4011 goto end;
4012
4013 /*
4014 * The estimation of the start period in the freq mode is
4015 * based on the below assumption.
4016 *
4017 * For a cycles or an instructions event, 1GHZ of the
4018 * underlying platform, 1 IPC. The workload is idle 50% time.
4019 * The start period = 1,000,000,000 * 1 / freq / 2.
4020 * = 500,000,000 / freq
4021 *
4022 * Usually, the branch-related events occur less than the
4023 * instructions event. According to the Intel event list JSON
4024 * file, the SAV (sample after value) of a branch-related event
4025 * is usually 1/4 of an instruction event.
4026 * The start period of branch-related events = 125,000,000 / freq.
4027 *
4028 * The cache-related events occurs even less. The SAV is usually
4029 * 1/20 of an instruction event.
4030 * The start period of cache-related events = 25,000,000 / freq.
4031 */
4032 config = event->attr.config & PERF_HW_EVENT_MASK;
4033 if (type == PERF_TYPE_HARDWARE) {
4034 switch (config) {
4035 case PERF_COUNT_HW_CPU_CYCLES:
4036 case PERF_COUNT_HW_INSTRUCTIONS:
4037 case PERF_COUNT_HW_BUS_CYCLES:
4038 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND:
4039 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND:
4040 case PERF_COUNT_HW_REF_CPU_CYCLES:
4041 factor = 500000000;
4042 break;
4043 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS:
4044 case PERF_COUNT_HW_BRANCH_MISSES:
4045 factor = 125000000;
4046 break;
4047 case PERF_COUNT_HW_CACHE_REFERENCES:
4048 case PERF_COUNT_HW_CACHE_MISSES:
4049 factor = 25000000;
4050 break;
4051 default:
4052 goto end;
4053 }
4054 }
4055
4056 if (type == PERF_TYPE_HW_CACHE)
4057 factor = 25000000;
4058 end:
4059 /*
4060 * Usually, a prime or a number with less factors (close to prime)
4061 * is chosen as an SAV, which makes it less likely that the sampling
4062 * period synchronizes with some periodic event in the workload.
4063 * Minus 1 to make it at least avoiding values near power of twos
4064 * for the default freq.
4065 */
4066 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1;
4067
4068 if (start > x86_pmu.max_period)
4069 start = x86_pmu.max_period;
4070
4071 if (x86_pmu.limit_period)
4072 x86_pmu.limit_period(event, &start);
4073
4074 return start;
4075 }
4076
intel_pmu_hw_config(struct perf_event * event)4077 static int intel_pmu_hw_config(struct perf_event *event)
4078 {
4079 int ret = x86_pmu_hw_config(event);
4080
4081 if (ret)
4082 return ret;
4083
4084 ret = intel_pmu_bts_config(event);
4085 if (ret)
4086 return ret;
4087
4088 if (event->attr.freq && event->attr.sample_freq) {
4089 event->hw.sample_period = intel_pmu_freq_start_period(event);
4090 event->hw.last_period = event->hw.sample_period;
4091 local64_set(&event->hw.period_left, event->hw.sample_period);
4092 }
4093
4094 if (event->attr.precise_ip) {
4095 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
4096 return -EINVAL;
4097
4098 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
4099 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
4100 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) &&
4101 !has_aux_action(event)) {
4102 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
4103 event->attach_state |= PERF_ATTACH_SCHED_CB;
4104 }
4105 }
4106 if (x86_pmu.pebs_aliases)
4107 x86_pmu.pebs_aliases(event);
4108 }
4109
4110 if (needs_branch_stack(event)) {
4111 /* Avoid branch stack setup for counting events in SAMPLE READ */
4112 if (is_sampling_event(event) ||
4113 !(event->attr.sample_type & PERF_SAMPLE_READ))
4114 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK;
4115 }
4116
4117 if (branch_sample_counters(event)) {
4118 struct perf_event *leader, *sibling;
4119 int num = 0;
4120
4121 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) ||
4122 (event->attr.config & ~INTEL_ARCH_EVENT_MASK))
4123 return -EINVAL;
4124
4125 /*
4126 * The branch counter logging is not supported in the call stack
4127 * mode yet, since we cannot simply flush the LBR during e.g.,
4128 * multiplexing. Also, there is no obvious usage with the call
4129 * stack mode. Simply forbids it for now.
4130 *
4131 * If any events in the group enable the branch counter logging
4132 * feature, the group is treated as a branch counter logging
4133 * group, which requires the extra space to store the counters.
4134 */
4135 leader = event->group_leader;
4136 if (branch_sample_call_stack(leader))
4137 return -EINVAL;
4138 if (branch_sample_counters(leader))
4139 num++;
4140 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS;
4141
4142 for_each_sibling_event(sibling, leader) {
4143 if (branch_sample_call_stack(sibling))
4144 return -EINVAL;
4145 if (branch_sample_counters(sibling))
4146 num++;
4147 }
4148
4149 if (num > fls(x86_pmu.lbr_counters))
4150 return -EINVAL;
4151 /*
4152 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't
4153 * require any branch stack setup.
4154 * Clear the bit to avoid unnecessary branch stack setup.
4155 */
4156 if (0 == (event->attr.branch_sample_type &
4157 ~(PERF_SAMPLE_BRANCH_PLM_ALL |
4158 PERF_SAMPLE_BRANCH_COUNTERS)))
4159 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK;
4160
4161 /*
4162 * Force the leader to be a LBR event. So LBRs can be reset
4163 * with the leader event. See intel_pmu_lbr_del() for details.
4164 */
4165 if (!intel_pmu_needs_branch_stack(leader))
4166 return -EINVAL;
4167 }
4168
4169 if (intel_pmu_needs_branch_stack(event)) {
4170 ret = intel_pmu_setup_lbr_filter(event);
4171 if (ret)
4172 return ret;
4173 event->attach_state |= PERF_ATTACH_SCHED_CB;
4174
4175 /*
4176 * BTS is set up earlier in this path, so don't account twice
4177 */
4178 if (!unlikely(intel_pmu_has_bts(event))) {
4179 /* disallow lbr if conflicting events are present */
4180 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
4181 return -EBUSY;
4182
4183 event->destroy = hw_perf_lbr_event_destroy;
4184 }
4185 }
4186
4187 if (event->attr.aux_output) {
4188 if (!event->attr.precise_ip)
4189 return -EINVAL;
4190
4191 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
4192 }
4193
4194 if ((event->attr.sample_type & PERF_SAMPLE_READ) &&
4195 (x86_pmu.intel_cap.pebs_format >= 6) &&
4196 x86_pmu.intel_cap.pebs_baseline &&
4197 is_sampling_event(event) &&
4198 event->attr.precise_ip)
4199 event->group_leader->hw.flags |= PERF_X86_EVENT_PEBS_CNTR;
4200
4201 if ((event->attr.type == PERF_TYPE_HARDWARE) ||
4202 (event->attr.type == PERF_TYPE_HW_CACHE))
4203 return 0;
4204
4205 /*
4206 * Config Topdown slots and metric events
4207 *
4208 * The slots event on Fixed Counter 3 can support sampling,
4209 * which will be handled normally in x86_perf_event_update().
4210 *
4211 * Metric events don't support sampling and require being paired
4212 * with a slots event as group leader. When the slots event
4213 * is used in a metrics group, it too cannot support sampling.
4214 */
4215 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
4216 /* The metrics_clear can only be set for the slots event */
4217 if (event->attr.config1 &&
4218 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR)))
4219 return -EINVAL;
4220
4221 if (event->attr.config2)
4222 return -EINVAL;
4223
4224 /*
4225 * The TopDown metrics events and slots event don't
4226 * support any filters.
4227 */
4228 if (event->attr.config & X86_ALL_EVENT_FLAGS)
4229 return -EINVAL;
4230
4231 if (is_available_metric_event(event)) {
4232 struct perf_event *leader = event->group_leader;
4233
4234 /* The metric events don't support sampling. */
4235 if (is_sampling_event(event))
4236 return -EINVAL;
4237
4238 /* The metric events require a slots group leader. */
4239 if (!is_slots_event(leader))
4240 return -EINVAL;
4241
4242 /*
4243 * The leader/SLOTS must not be a sampling event for
4244 * metric use; hardware requires it starts at 0 when used
4245 * in conjunction with MSR_PERF_METRICS.
4246 */
4247 if (is_sampling_event(leader))
4248 return -EINVAL;
4249
4250 event->event_caps |= PERF_EV_CAP_SIBLING;
4251 /*
4252 * Only once we have a METRICs sibling do we
4253 * need TopDown magic.
4254 */
4255 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
4256 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
4257 }
4258 }
4259
4260 /*
4261 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
4262 * doesn't function quite right. As a work-around it needs to always be
4263 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
4264 * The actual count of this second event is irrelevant it just needs
4265 * to be active to make the first event function correctly.
4266 *
4267 * In a group, the auxiliary event must be in front of the load latency
4268 * event. The rule is to simplify the implementation of the check.
4269 * That's because perf cannot have a complete group at the moment.
4270 */
4271 if (require_mem_loads_aux_event(event) &&
4272 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
4273 is_mem_loads_event(event)) {
4274 struct perf_event *leader = event->group_leader;
4275 struct perf_event *sibling = NULL;
4276
4277 /*
4278 * When this memload event is also the first event (no group
4279 * exists yet), then there is no aux event before it.
4280 */
4281 if (leader == event)
4282 return -ENODATA;
4283
4284 if (!is_mem_loads_aux_event(leader)) {
4285 for_each_sibling_event(sibling, leader) {
4286 if (is_mem_loads_aux_event(sibling))
4287 break;
4288 }
4289 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
4290 return -ENODATA;
4291 }
4292 }
4293
4294 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
4295 return 0;
4296
4297 if (x86_pmu.version < 3)
4298 return -EINVAL;
4299
4300 ret = perf_allow_cpu();
4301 if (ret)
4302 return ret;
4303
4304 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
4305
4306 return 0;
4307 }
4308
4309 /*
4310 * Currently, the only caller of this function is the atomic_switch_perf_msrs().
4311 * The host perf context helps to prepare the values of the real hardware for
4312 * a set of msrs that need to be switched atomically in a vmx transaction.
4313 *
4314 * For example, the pseudocode needed to add a new msr should look like:
4315 *
4316 * arr[(*nr)++] = (struct perf_guest_switch_msr){
4317 * .msr = the hardware msr address,
4318 * .host = the value the hardware has when it doesn't run a guest,
4319 * .guest = the value the hardware has when it runs a guest,
4320 * };
4321 *
4322 * These values have nothing to do with the emulated values the guest sees
4323 * when it uses {RD,WR}MSR, which should be handled by the KVM context,
4324 * specifically in the intel_pmu_{get,set}_msr().
4325 */
intel_guest_get_msrs(int * nr,void * data)4326 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
4327 {
4328 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4329 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4330 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data;
4331 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
4332 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
4333 int global_ctrl, pebs_enable;
4334
4335 /*
4336 * In addition to obeying exclude_guest/exclude_host, remove bits being
4337 * used for PEBS when running a guest, because PEBS writes to virtual
4338 * addresses (not physical addresses).
4339 */
4340 *nr = 0;
4341 global_ctrl = (*nr)++;
4342 arr[global_ctrl] = (struct perf_guest_switch_msr){
4343 .msr = MSR_CORE_PERF_GLOBAL_CTRL,
4344 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
4345 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask,
4346 };
4347
4348 if (!x86_pmu.pebs)
4349 return arr;
4350
4351 /*
4352 * If PMU counter has PEBS enabled it is not enough to
4353 * disable counter on a guest entry since PEBS memory
4354 * write can overshoot guest entry and corrupt guest
4355 * memory. Disabling PEBS solves the problem.
4356 *
4357 * Don't do this if the CPU already enforces it.
4358 */
4359 if (x86_pmu.pebs_no_isolation) {
4360 arr[(*nr)++] = (struct perf_guest_switch_msr){
4361 .msr = MSR_IA32_PEBS_ENABLE,
4362 .host = cpuc->pebs_enabled,
4363 .guest = 0,
4364 };
4365 return arr;
4366 }
4367
4368 if (!kvm_pmu || !x86_pmu.pebs_ept)
4369 return arr;
4370
4371 arr[(*nr)++] = (struct perf_guest_switch_msr){
4372 .msr = MSR_IA32_DS_AREA,
4373 .host = (unsigned long)cpuc->ds,
4374 .guest = kvm_pmu->ds_area,
4375 };
4376
4377 if (x86_pmu.intel_cap.pebs_baseline) {
4378 arr[(*nr)++] = (struct perf_guest_switch_msr){
4379 .msr = MSR_PEBS_DATA_CFG,
4380 .host = cpuc->active_pebs_data_cfg,
4381 .guest = kvm_pmu->pebs_data_cfg,
4382 };
4383 }
4384
4385 pebs_enable = (*nr)++;
4386 arr[pebs_enable] = (struct perf_guest_switch_msr){
4387 .msr = MSR_IA32_PEBS_ENABLE,
4388 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
4389 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask,
4390 };
4391
4392 if (arr[pebs_enable].host) {
4393 /* Disable guest PEBS if host PEBS is enabled. */
4394 arr[pebs_enable].guest = 0;
4395 } else {
4396 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */
4397 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
4398 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask;
4399 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
4400 arr[global_ctrl].guest |= arr[pebs_enable].guest;
4401 }
4402
4403 return arr;
4404 }
4405
core_guest_get_msrs(int * nr,void * data)4406 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data)
4407 {
4408 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4409 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4410 int idx;
4411
4412 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
4413 struct perf_event *event = cpuc->events[idx];
4414
4415 arr[idx].msr = x86_pmu_config_addr(idx);
4416 arr[idx].host = arr[idx].guest = 0;
4417
4418 if (!test_bit(idx, cpuc->active_mask))
4419 continue;
4420
4421 arr[idx].host = arr[idx].guest =
4422 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
4423
4424 if (event->attr.exclude_host)
4425 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4426 else if (event->attr.exclude_guest)
4427 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4428 }
4429
4430 *nr = x86_pmu_max_num_counters(cpuc->pmu);
4431 return arr;
4432 }
4433
core_pmu_enable_event(struct perf_event * event)4434 static void core_pmu_enable_event(struct perf_event *event)
4435 {
4436 if (!event->attr.exclude_host)
4437 x86_pmu_enable_event(event);
4438 }
4439
core_pmu_enable_all(int added)4440 static void core_pmu_enable_all(int added)
4441 {
4442 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4443 int idx;
4444
4445 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
4446 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
4447
4448 if (!test_bit(idx, cpuc->active_mask) ||
4449 cpuc->events[idx]->attr.exclude_host)
4450 continue;
4451
4452 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
4453 }
4454 }
4455
hsw_hw_config(struct perf_event * event)4456 static int hsw_hw_config(struct perf_event *event)
4457 {
4458 int ret = intel_pmu_hw_config(event);
4459
4460 if (ret)
4461 return ret;
4462 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
4463 return 0;
4464 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
4465
4466 /*
4467 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
4468 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
4469 * this combination.
4470 */
4471 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
4472 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
4473 event->attr.precise_ip > 0))
4474 return -EOPNOTSUPP;
4475
4476 if (event_is_checkpointed(event)) {
4477 /*
4478 * Sampling of checkpointed events can cause situations where
4479 * the CPU constantly aborts because of a overflow, which is
4480 * then checkpointed back and ignored. Forbid checkpointing
4481 * for sampling.
4482 *
4483 * But still allow a long sampling period, so that perf stat
4484 * from KVM works.
4485 */
4486 if (event->attr.sample_period > 0 &&
4487 event->attr.sample_period < 0x7fffffff)
4488 return -EOPNOTSUPP;
4489 }
4490 return 0;
4491 }
4492
4493 static struct event_constraint counter0_constraint =
4494 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
4495
4496 static struct event_constraint counter1_constraint =
4497 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2);
4498
4499 static struct event_constraint counter0_1_constraint =
4500 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3);
4501
4502 static struct event_constraint counter2_constraint =
4503 EVENT_CONSTRAINT(0, 0x4, 0);
4504
4505 static struct event_constraint fixed0_constraint =
4506 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
4507
4508 static struct event_constraint fixed0_counter0_constraint =
4509 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
4510
4511 static struct event_constraint fixed0_counter0_1_constraint =
4512 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL);
4513
4514 static struct event_constraint counters_1_7_constraint =
4515 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL);
4516
4517 static struct event_constraint *
hsw_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4518 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4519 struct perf_event *event)
4520 {
4521 struct event_constraint *c;
4522
4523 c = intel_get_event_constraints(cpuc, idx, event);
4524
4525 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
4526 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
4527 if (c->idxmsk64 & (1U << 2))
4528 return &counter2_constraint;
4529 return &emptyconstraint;
4530 }
4531
4532 return c;
4533 }
4534
4535 static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4536 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4537 struct perf_event *event)
4538 {
4539 /*
4540 * Fixed counter 0 has less skid.
4541 * Force instruction:ppp in Fixed counter 0
4542 */
4543 if ((event->attr.precise_ip == 3) &&
4544 constraint_match(&fixed0_constraint, event->hw.config))
4545 return &fixed0_constraint;
4546
4547 return hsw_get_event_constraints(cpuc, idx, event);
4548 }
4549
4550 static struct event_constraint *
glc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4551 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4552 struct perf_event *event)
4553 {
4554 struct event_constraint *c;
4555
4556 c = icl_get_event_constraints(cpuc, idx, event);
4557
4558 /*
4559 * The :ppp indicates the Precise Distribution (PDist) facility, which
4560 * is only supported on the GP counter 0. If a :ppp event which is not
4561 * available on the GP counter 0, error out.
4562 * Exception: Instruction PDIR is only available on the fixed counter 0.
4563 */
4564 if ((event->attr.precise_ip == 3) &&
4565 !constraint_match(&fixed0_constraint, event->hw.config)) {
4566 if (c->idxmsk64 & BIT_ULL(0))
4567 return &counter0_constraint;
4568
4569 return &emptyconstraint;
4570 }
4571
4572 return c;
4573 }
4574
4575 static struct event_constraint *
glp_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4576 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4577 struct perf_event *event)
4578 {
4579 struct event_constraint *c;
4580
4581 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
4582 if (event->attr.precise_ip == 3)
4583 return &counter0_constraint;
4584
4585 c = intel_get_event_constraints(cpuc, idx, event);
4586
4587 return c;
4588 }
4589
4590 static struct event_constraint *
tnt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4591 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4592 struct perf_event *event)
4593 {
4594 struct event_constraint *c;
4595
4596 c = intel_get_event_constraints(cpuc, idx, event);
4597
4598 /*
4599 * :ppp means to do reduced skid PEBS,
4600 * which is available on PMC0 and fixed counter 0.
4601 */
4602 if (event->attr.precise_ip == 3) {
4603 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4604 if (constraint_match(&fixed0_constraint, event->hw.config))
4605 return &fixed0_counter0_constraint;
4606
4607 return &counter0_constraint;
4608 }
4609
4610 return c;
4611 }
4612
4613 static bool allow_tsx_force_abort = true;
4614
4615 static struct event_constraint *
tfa_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4616 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4617 struct perf_event *event)
4618 {
4619 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
4620
4621 /*
4622 * Without TFA we must not use PMC3.
4623 */
4624 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
4625 c = dyn_constraint(cpuc, c, idx);
4626 c->idxmsk64 &= ~(1ULL << 3);
4627 c->weight--;
4628 }
4629
4630 return c;
4631 }
4632
4633 static struct event_constraint *
adl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4634 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4635 struct perf_event *event)
4636 {
4637 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4638
4639 if (pmu->pmu_type == hybrid_big)
4640 return glc_get_event_constraints(cpuc, idx, event);
4641 else if (pmu->pmu_type == hybrid_small)
4642 return tnt_get_event_constraints(cpuc, idx, event);
4643
4644 WARN_ON(1);
4645 return &emptyconstraint;
4646 }
4647
4648 static struct event_constraint *
cmt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4649 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4650 struct perf_event *event)
4651 {
4652 struct event_constraint *c;
4653
4654 c = intel_get_event_constraints(cpuc, idx, event);
4655
4656 /*
4657 * The :ppp indicates the Precise Distribution (PDist) facility, which
4658 * is only supported on the GP counter 0 & 1 and Fixed counter 0.
4659 * If a :ppp event which is not available on the above eligible counters,
4660 * error out.
4661 */
4662 if (event->attr.precise_ip == 3) {
4663 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */
4664 if (constraint_match(&fixed0_constraint, event->hw.config)) {
4665 /* The fixed counter 0 doesn't support LBR event logging. */
4666 if (branch_sample_counters(event))
4667 return &counter0_1_constraint;
4668 else
4669 return &fixed0_counter0_1_constraint;
4670 }
4671
4672 switch (c->idxmsk64 & 0x3ull) {
4673 case 0x1:
4674 return &counter0_constraint;
4675 case 0x2:
4676 return &counter1_constraint;
4677 case 0x3:
4678 return &counter0_1_constraint;
4679 }
4680 return &emptyconstraint;
4681 }
4682
4683 return c;
4684 }
4685
4686 static struct event_constraint *
rwc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4687 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4688 struct perf_event *event)
4689 {
4690 struct event_constraint *c;
4691
4692 c = glc_get_event_constraints(cpuc, idx, event);
4693
4694 /* The Retire Latency is not supported by the fixed counter 0. */
4695 if (event->attr.precise_ip &&
4696 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
4697 constraint_match(&fixed0_constraint, event->hw.config)) {
4698 /*
4699 * The Instruction PDIR is only available
4700 * on the fixed counter 0. Error out for this case.
4701 */
4702 if (event->attr.precise_ip == 3)
4703 return &emptyconstraint;
4704 return &counters_1_7_constraint;
4705 }
4706
4707 return c;
4708 }
4709
4710 static struct event_constraint *
mtl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4711 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4712 struct perf_event *event)
4713 {
4714 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4715
4716 if (pmu->pmu_type == hybrid_big)
4717 return rwc_get_event_constraints(cpuc, idx, event);
4718 if (pmu->pmu_type == hybrid_small)
4719 return cmt_get_event_constraints(cpuc, idx, event);
4720
4721 WARN_ON(1);
4722 return &emptyconstraint;
4723 }
4724
adl_hw_config(struct perf_event * event)4725 static int adl_hw_config(struct perf_event *event)
4726 {
4727 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4728
4729 if (pmu->pmu_type == hybrid_big)
4730 return hsw_hw_config(event);
4731 else if (pmu->pmu_type == hybrid_small)
4732 return intel_pmu_hw_config(event);
4733
4734 WARN_ON(1);
4735 return -EOPNOTSUPP;
4736 }
4737
adl_get_hybrid_cpu_type(void)4738 static enum intel_cpu_type adl_get_hybrid_cpu_type(void)
4739 {
4740 return INTEL_CPU_TYPE_CORE;
4741 }
4742
erratum_hsw11(struct perf_event * event)4743 static inline bool erratum_hsw11(struct perf_event *event)
4744 {
4745 return (event->hw.config & INTEL_ARCH_EVENT_MASK) ==
4746 X86_CONFIG(.event=0xc0, .umask=0x01);
4747 }
4748
4749 static struct event_constraint *
arl_h_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4750 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4751 struct perf_event *event)
4752 {
4753 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4754
4755 if (pmu->pmu_type == hybrid_tiny)
4756 return cmt_get_event_constraints(cpuc, idx, event);
4757
4758 return mtl_get_event_constraints(cpuc, idx, event);
4759 }
4760
arl_h_hw_config(struct perf_event * event)4761 static int arl_h_hw_config(struct perf_event *event)
4762 {
4763 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4764
4765 if (pmu->pmu_type == hybrid_tiny)
4766 return intel_pmu_hw_config(event);
4767
4768 return adl_hw_config(event);
4769 }
4770
4771 /*
4772 * The HSW11 requires a period larger than 100 which is the same as the BDM11.
4773 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL.
4774 *
4775 * The message 'interrupt took too long' can be observed on any counter which
4776 * was armed with a period < 32 and two events expired in the same NMI.
4777 * A minimum period of 32 is enforced for the rest of the events.
4778 */
hsw_limit_period(struct perf_event * event,s64 * left)4779 static void hsw_limit_period(struct perf_event *event, s64 *left)
4780 {
4781 *left = max(*left, erratum_hsw11(event) ? 128 : 32);
4782 }
4783
4784 /*
4785 * Broadwell:
4786 *
4787 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
4788 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
4789 * the two to enforce a minimum period of 128 (the smallest value that has bits
4790 * 0-5 cleared and >= 100).
4791 *
4792 * Because of how the code in x86_perf_event_set_period() works, the truncation
4793 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
4794 * to make up for the 'lost' events due to carrying the 'error' in period_left.
4795 *
4796 * Therefore the effective (average) period matches the requested period,
4797 * despite coarser hardware granularity.
4798 */
bdw_limit_period(struct perf_event * event,s64 * left)4799 static void bdw_limit_period(struct perf_event *event, s64 *left)
4800 {
4801 if (erratum_hsw11(event)) {
4802 if (*left < 128)
4803 *left = 128;
4804 *left &= ~0x3fULL;
4805 }
4806 }
4807
nhm_limit_period(struct perf_event * event,s64 * left)4808 static void nhm_limit_period(struct perf_event *event, s64 *left)
4809 {
4810 *left = max(*left, 32LL);
4811 }
4812
glc_limit_period(struct perf_event * event,s64 * left)4813 static void glc_limit_period(struct perf_event *event, s64 *left)
4814 {
4815 if (event->attr.precise_ip == 3)
4816 *left = max(*left, 128LL);
4817 }
4818
4819 PMU_FORMAT_ATTR(event, "config:0-7" );
4820 PMU_FORMAT_ATTR(umask, "config:8-15" );
4821 PMU_FORMAT_ATTR(edge, "config:18" );
4822 PMU_FORMAT_ATTR(pc, "config:19" );
4823 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
4824 PMU_FORMAT_ATTR(inv, "config:23" );
4825 PMU_FORMAT_ATTR(cmask, "config:24-31" );
4826 PMU_FORMAT_ATTR(in_tx, "config:32" );
4827 PMU_FORMAT_ATTR(in_tx_cp, "config:33" );
4828 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */
4829
4830 PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
4831
umask2_show(struct device * dev,struct device_attribute * attr,char * page)4832 static ssize_t umask2_show(struct device *dev,
4833 struct device_attribute *attr,
4834 char *page)
4835 {
4836 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2;
4837
4838 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2)
4839 return sprintf(page, "config:8-15,40-47\n");
4840
4841 /* Roll back to the old format if umask2 is not supported. */
4842 return sprintf(page, "config:8-15\n");
4843 }
4844
4845 static struct device_attribute format_attr_umask2 =
4846 __ATTR(umask, 0444, umask2_show, NULL);
4847
4848 static struct attribute *format_evtsel_ext_attrs[] = {
4849 &format_attr_umask2.attr,
4850 &format_attr_eq.attr,
4851 &format_attr_metrics_clear.attr,
4852 NULL
4853 };
4854
4855 static umode_t
evtsel_ext_is_visible(struct kobject * kobj,struct attribute * attr,int i)4856 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4857 {
4858 struct device *dev = kobj_to_dev(kobj);
4859 u64 mask;
4860
4861 /*
4862 * The umask and umask2 have different formats but share the
4863 * same attr name. In update mode, the previous value of the
4864 * umask is unconditionally removed before is_visible. If
4865 * umask2 format is not enumerated, it's impossible to roll
4866 * back to the old format.
4867 * Does the check in umask2_show rather than is_visible.
4868 */
4869 if (i == 0)
4870 return attr->mode;
4871
4872 mask = hybrid(dev_get_drvdata(dev), config_mask);
4873 if (i == 1)
4874 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0;
4875
4876 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
4877 if (i == 2) {
4878 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap);
4879
4880 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0;
4881 }
4882
4883 return 0;
4884 }
4885
4886 static struct attribute *intel_arch_formats_attr[] = {
4887 &format_attr_event.attr,
4888 &format_attr_umask.attr,
4889 &format_attr_edge.attr,
4890 &format_attr_pc.attr,
4891 &format_attr_inv.attr,
4892 &format_attr_cmask.attr,
4893 NULL,
4894 };
4895
intel_event_sysfs_show(char * page,u64 config)4896 ssize_t intel_event_sysfs_show(char *page, u64 config)
4897 {
4898 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
4899
4900 return x86_event_sysfs_show(page, config, event);
4901 }
4902
allocate_shared_regs(int cpu)4903 static struct intel_shared_regs *allocate_shared_regs(int cpu)
4904 {
4905 struct intel_shared_regs *regs;
4906 int i;
4907
4908 regs = kzalloc_node(sizeof(struct intel_shared_regs),
4909 GFP_KERNEL, cpu_to_node(cpu));
4910 if (regs) {
4911 /*
4912 * initialize the locks to keep lockdep happy
4913 */
4914 for (i = 0; i < EXTRA_REG_MAX; i++)
4915 raw_spin_lock_init(®s->regs[i].lock);
4916
4917 regs->core_id = -1;
4918 }
4919 return regs;
4920 }
4921
allocate_excl_cntrs(int cpu)4922 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
4923 {
4924 struct intel_excl_cntrs *c;
4925
4926 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
4927 GFP_KERNEL, cpu_to_node(cpu));
4928 if (c) {
4929 raw_spin_lock_init(&c->lock);
4930 c->core_id = -1;
4931 }
4932 return c;
4933 }
4934
4935
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)4936 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4937 {
4938 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4939
4940 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4941 cpuc->shared_regs = allocate_shared_regs(cpu);
4942 if (!cpuc->shared_regs)
4943 goto err;
4944 }
4945
4946 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_BR_CNTR)) {
4947 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4948
4949 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4950 if (!cpuc->constraint_list)
4951 goto err_shared_regs;
4952 }
4953
4954 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4955 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4956 if (!cpuc->excl_cntrs)
4957 goto err_constraint_list;
4958
4959 cpuc->excl_thread_id = 0;
4960 }
4961
4962 return 0;
4963
4964 err_constraint_list:
4965 kfree(cpuc->constraint_list);
4966 cpuc->constraint_list = NULL;
4967
4968 err_shared_regs:
4969 kfree(cpuc->shared_regs);
4970 cpuc->shared_regs = NULL;
4971
4972 err:
4973 return -ENOMEM;
4974 }
4975
intel_pmu_cpu_prepare(int cpu)4976 static int intel_pmu_cpu_prepare(int cpu)
4977 {
4978 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4979 }
4980
flip_smm_bit(void * data)4981 static void flip_smm_bit(void *data)
4982 {
4983 unsigned long set = *(unsigned long *)data;
4984
4985 if (set > 0) {
4986 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4987 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4988 } else {
4989 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4990 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4991 }
4992 }
4993
intel_pmu_check_counters_mask(u64 * cntr_mask,u64 * fixed_cntr_mask,u64 * intel_ctrl)4994 static void intel_pmu_check_counters_mask(u64 *cntr_mask,
4995 u64 *fixed_cntr_mask,
4996 u64 *intel_ctrl)
4997 {
4998 unsigned int bit;
4999
5000 bit = fls64(*cntr_mask);
5001 if (bit > INTEL_PMC_MAX_GENERIC) {
5002 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5003 bit, INTEL_PMC_MAX_GENERIC);
5004 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
5005 }
5006 *intel_ctrl = *cntr_mask;
5007
5008 bit = fls64(*fixed_cntr_mask);
5009 if (bit > INTEL_PMC_MAX_FIXED) {
5010 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5011 bit, INTEL_PMC_MAX_FIXED);
5012 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
5013 }
5014
5015 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED;
5016 }
5017
5018 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
5019 u64 cntr_mask,
5020 u64 fixed_cntr_mask,
5021 u64 intel_ctrl);
5022
5023 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs);
5024
intel_pmu_broken_perf_cap(void)5025 static inline bool intel_pmu_broken_perf_cap(void)
5026 {
5027 /* The Perf Metric (Bit 15) is always cleared */
5028 if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE ||
5029 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L)
5030 return true;
5031
5032 return false;
5033 }
5034
update_pmu_cap(struct x86_hybrid_pmu * pmu)5035 static void update_pmu_cap(struct x86_hybrid_pmu *pmu)
5036 {
5037 unsigned int cntr, fixed_cntr, ecx, edx;
5038 union cpuid35_eax eax;
5039 union cpuid35_ebx ebx;
5040
5041 cpuid(ARCH_PERFMON_EXT_LEAF, &eax.full, &ebx.full, &ecx, &edx);
5042
5043 if (ebx.split.umask2)
5044 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_UMASK2;
5045 if (ebx.split.eq)
5046 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ;
5047
5048 if (eax.split.cntr_subleaf) {
5049 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
5050 &cntr, &fixed_cntr, &ecx, &edx);
5051 pmu->cntr_mask64 = cntr;
5052 pmu->fixed_cntr_mask64 = fixed_cntr;
5053 }
5054
5055 if (!intel_pmu_broken_perf_cap()) {
5056 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */
5057 rdmsrl(MSR_IA32_PERF_CAPABILITIES, pmu->intel_cap.capabilities);
5058 }
5059 }
5060
intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu * pmu)5061 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu)
5062 {
5063 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64,
5064 &pmu->intel_ctrl);
5065 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
5066 pmu->unconstrained = (struct event_constraint)
5067 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
5068 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
5069
5070 if (pmu->intel_cap.perf_metrics)
5071 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
5072 else
5073 pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
5074
5075 intel_pmu_check_event_constraints(pmu->event_constraints,
5076 pmu->cntr_mask64,
5077 pmu->fixed_cntr_mask64,
5078 pmu->intel_ctrl);
5079
5080 intel_pmu_check_extra_regs(pmu->extra_regs);
5081 }
5082
find_hybrid_pmu_for_cpu(void)5083 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void)
5084 {
5085 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
5086 enum intel_cpu_type cpu_type = c->topo.intel_type;
5087 int i;
5088
5089 /*
5090 * This is running on a CPU model that is known to have hybrid
5091 * configurations. But the CPU told us it is not hybrid, shame
5092 * on it. There should be a fixup function provided for these
5093 * troublesome CPUs (->get_hybrid_cpu_type).
5094 */
5095 if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) {
5096 if (x86_pmu.get_hybrid_cpu_type)
5097 cpu_type = x86_pmu.get_hybrid_cpu_type();
5098 else
5099 return NULL;
5100 }
5101
5102 /*
5103 * This essentially just maps between the 'hybrid_cpu_type'
5104 * and 'hybrid_pmu_type' enums except for ARL-H processor
5105 * which needs to compare atom uarch native id since ARL-H
5106 * contains two different atom uarchs.
5107 */
5108 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
5109 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type;
5110 u32 native_id;
5111
5112 if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big)
5113 return &x86_pmu.hybrid_pmu[i];
5114 if (cpu_type == INTEL_CPU_TYPE_ATOM) {
5115 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small)
5116 return &x86_pmu.hybrid_pmu[i];
5117
5118 native_id = c->topo.intel_native_model_id;
5119 if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small)
5120 return &x86_pmu.hybrid_pmu[i];
5121 if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny)
5122 return &x86_pmu.hybrid_pmu[i];
5123 }
5124 }
5125
5126 return NULL;
5127 }
5128
init_hybrid_pmu(int cpu)5129 static bool init_hybrid_pmu(int cpu)
5130 {
5131 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5132 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu();
5133
5134 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
5135 cpuc->pmu = NULL;
5136 return false;
5137 }
5138
5139 /* Only check and dump the PMU information for the first CPU */
5140 if (!cpumask_empty(&pmu->supported_cpus))
5141 goto end;
5142
5143 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
5144 update_pmu_cap(pmu);
5145
5146 intel_pmu_check_hybrid_pmus(pmu);
5147
5148 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask))
5149 return false;
5150
5151 pr_info("%s PMU driver: ", pmu->name);
5152
5153 pr_cont("\n");
5154
5155 x86_pmu_show_pmu_cap(&pmu->pmu);
5156
5157 end:
5158 cpumask_set_cpu(cpu, &pmu->supported_cpus);
5159 cpuc->pmu = &pmu->pmu;
5160
5161 return true;
5162 }
5163
intel_pmu_cpu_starting(int cpu)5164 static void intel_pmu_cpu_starting(int cpu)
5165 {
5166 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5167 int core_id = topology_core_id(cpu);
5168 int i;
5169
5170 if (is_hybrid() && !init_hybrid_pmu(cpu))
5171 return;
5172
5173 init_debug_store_on_cpu(cpu);
5174 /*
5175 * Deal with CPUs that don't clear their LBRs on power-up, and that may
5176 * even boot with LBRs enabled.
5177 */
5178 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr)
5179 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT);
5180 intel_pmu_lbr_reset();
5181
5182 cpuc->lbr_sel = NULL;
5183
5184 if (x86_pmu.flags & PMU_FL_TFA) {
5185 WARN_ON_ONCE(cpuc->tfa_shadow);
5186 cpuc->tfa_shadow = ~0ULL;
5187 intel_set_tfa(cpuc, false);
5188 }
5189
5190 if (x86_pmu.version > 1)
5191 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
5192
5193 /*
5194 * Disable perf metrics if any added CPU doesn't support it.
5195 *
5196 * Turn off the check for a hybrid architecture, because the
5197 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
5198 * the architecture features. The perf metrics is a model-specific
5199 * feature for now. The corresponding bit should always be 0 on
5200 * a hybrid platform, e.g., Alder Lake.
5201 */
5202 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
5203 union perf_capabilities perf_cap;
5204
5205 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
5206 if (!perf_cap.perf_metrics) {
5207 x86_pmu.intel_cap.perf_metrics = 0;
5208 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
5209 }
5210 }
5211
5212 if (!cpuc->shared_regs)
5213 return;
5214
5215 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
5216 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
5217 struct intel_shared_regs *pc;
5218
5219 pc = per_cpu(cpu_hw_events, i).shared_regs;
5220 if (pc && pc->core_id == core_id) {
5221 cpuc->kfree_on_online[0] = cpuc->shared_regs;
5222 cpuc->shared_regs = pc;
5223 break;
5224 }
5225 }
5226 cpuc->shared_regs->core_id = core_id;
5227 cpuc->shared_regs->refcnt++;
5228 }
5229
5230 if (x86_pmu.lbr_sel_map)
5231 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
5232
5233 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
5234 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
5235 struct cpu_hw_events *sibling;
5236 struct intel_excl_cntrs *c;
5237
5238 sibling = &per_cpu(cpu_hw_events, i);
5239 c = sibling->excl_cntrs;
5240 if (c && c->core_id == core_id) {
5241 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
5242 cpuc->excl_cntrs = c;
5243 if (!sibling->excl_thread_id)
5244 cpuc->excl_thread_id = 1;
5245 break;
5246 }
5247 }
5248 cpuc->excl_cntrs->core_id = core_id;
5249 cpuc->excl_cntrs->refcnt++;
5250 }
5251 }
5252
free_excl_cntrs(struct cpu_hw_events * cpuc)5253 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
5254 {
5255 struct intel_excl_cntrs *c;
5256
5257 c = cpuc->excl_cntrs;
5258 if (c) {
5259 if (c->core_id == -1 || --c->refcnt == 0)
5260 kfree(c);
5261 cpuc->excl_cntrs = NULL;
5262 }
5263
5264 kfree(cpuc->constraint_list);
5265 cpuc->constraint_list = NULL;
5266 }
5267
intel_pmu_cpu_dying(int cpu)5268 static void intel_pmu_cpu_dying(int cpu)
5269 {
5270 fini_debug_store_on_cpu(cpu);
5271 }
5272
intel_cpuc_finish(struct cpu_hw_events * cpuc)5273 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
5274 {
5275 struct intel_shared_regs *pc;
5276
5277 pc = cpuc->shared_regs;
5278 if (pc) {
5279 if (pc->core_id == -1 || --pc->refcnt == 0)
5280 kfree(pc);
5281 cpuc->shared_regs = NULL;
5282 }
5283
5284 free_excl_cntrs(cpuc);
5285 }
5286
intel_pmu_cpu_dead(int cpu)5287 static void intel_pmu_cpu_dead(int cpu)
5288 {
5289 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5290
5291 intel_cpuc_finish(cpuc);
5292
5293 if (is_hybrid() && cpuc->pmu)
5294 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
5295 }
5296
intel_pmu_sched_task(struct perf_event_pmu_context * pmu_ctx,struct task_struct * task,bool sched_in)5297 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
5298 struct task_struct *task, bool sched_in)
5299 {
5300 intel_pmu_pebs_sched_task(pmu_ctx, sched_in);
5301 intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in);
5302 }
5303
intel_pmu_check_period(struct perf_event * event,u64 value)5304 static int intel_pmu_check_period(struct perf_event *event, u64 value)
5305 {
5306 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
5307 }
5308
intel_aux_output_init(void)5309 static void intel_aux_output_init(void)
5310 {
5311 /* Refer also intel_pmu_aux_output_match() */
5312 if (x86_pmu.intel_cap.pebs_output_pt_available)
5313 x86_pmu.assign = intel_pmu_assign_event;
5314 }
5315
intel_pmu_aux_output_match(struct perf_event * event)5316 static int intel_pmu_aux_output_match(struct perf_event *event)
5317 {
5318 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
5319 if (!x86_pmu.intel_cap.pebs_output_pt_available)
5320 return 0;
5321
5322 return is_intel_pt_event(event);
5323 }
5324
intel_pmu_filter(struct pmu * pmu,int cpu,bool * ret)5325 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
5326 {
5327 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu);
5328
5329 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus);
5330 }
5331
5332 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
5333
5334 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
5335
5336 PMU_FORMAT_ATTR(frontend, "config1:0-23");
5337
5338 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
5339
5340 static struct attribute *intel_arch3_formats_attr[] = {
5341 &format_attr_event.attr,
5342 &format_attr_umask.attr,
5343 &format_attr_edge.attr,
5344 &format_attr_pc.attr,
5345 &format_attr_any.attr,
5346 &format_attr_inv.attr,
5347 &format_attr_cmask.attr,
5348 NULL,
5349 };
5350
5351 static struct attribute *hsw_format_attr[] = {
5352 &format_attr_in_tx.attr,
5353 &format_attr_in_tx_cp.attr,
5354 &format_attr_offcore_rsp.attr,
5355 &format_attr_ldlat.attr,
5356 NULL
5357 };
5358
5359 static struct attribute *nhm_format_attr[] = {
5360 &format_attr_offcore_rsp.attr,
5361 &format_attr_ldlat.attr,
5362 NULL
5363 };
5364
5365 static struct attribute *slm_format_attr[] = {
5366 &format_attr_offcore_rsp.attr,
5367 NULL
5368 };
5369
5370 static struct attribute *cmt_format_attr[] = {
5371 &format_attr_offcore_rsp.attr,
5372 &format_attr_ldlat.attr,
5373 &format_attr_snoop_rsp.attr,
5374 NULL
5375 };
5376
5377 static struct attribute *skl_format_attr[] = {
5378 &format_attr_frontend.attr,
5379 NULL,
5380 };
5381
5382 static __initconst const struct x86_pmu core_pmu = {
5383 .name = "core",
5384 .handle_irq = x86_pmu_handle_irq,
5385 .disable_all = x86_pmu_disable_all,
5386 .enable_all = core_pmu_enable_all,
5387 .enable = core_pmu_enable_event,
5388 .disable = x86_pmu_disable_event,
5389 .hw_config = core_pmu_hw_config,
5390 .schedule_events = x86_schedule_events,
5391 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
5392 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
5393 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
5394 .event_map = intel_pmu_event_map,
5395 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
5396 .apic = 1,
5397 .large_pebs_flags = LARGE_PEBS_FLAGS,
5398
5399 /*
5400 * Intel PMCs cannot be accessed sanely above 32-bit width,
5401 * so we install an artificial 1<<31 period regardless of
5402 * the generic event period:
5403 */
5404 .max_period = (1ULL<<31) - 1,
5405 .get_event_constraints = intel_get_event_constraints,
5406 .put_event_constraints = intel_put_event_constraints,
5407 .event_constraints = intel_core_event_constraints,
5408 .guest_get_msrs = core_guest_get_msrs,
5409 .format_attrs = intel_arch_formats_attr,
5410 .events_sysfs_show = intel_event_sysfs_show,
5411
5412 /*
5413 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
5414 * together with PMU version 1 and thus be using core_pmu with
5415 * shared_regs. We need following callbacks here to allocate
5416 * it properly.
5417 */
5418 .cpu_prepare = intel_pmu_cpu_prepare,
5419 .cpu_starting = intel_pmu_cpu_starting,
5420 .cpu_dying = intel_pmu_cpu_dying,
5421 .cpu_dead = intel_pmu_cpu_dead,
5422
5423 .check_period = intel_pmu_check_period,
5424
5425 .lbr_reset = intel_pmu_lbr_reset_64,
5426 .lbr_read = intel_pmu_lbr_read_64,
5427 .lbr_save = intel_pmu_lbr_save,
5428 .lbr_restore = intel_pmu_lbr_restore,
5429 };
5430
5431 static __initconst const struct x86_pmu intel_pmu = {
5432 .name = "Intel",
5433 .handle_irq = intel_pmu_handle_irq,
5434 .disable_all = intel_pmu_disable_all,
5435 .enable_all = intel_pmu_enable_all,
5436 .enable = intel_pmu_enable_event,
5437 .disable = intel_pmu_disable_event,
5438 .add = intel_pmu_add_event,
5439 .del = intel_pmu_del_event,
5440 .read = intel_pmu_read_event,
5441 .set_period = intel_pmu_set_period,
5442 .update = intel_pmu_update,
5443 .hw_config = intel_pmu_hw_config,
5444 .schedule_events = x86_schedule_events,
5445 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
5446 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
5447 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
5448 .event_map = intel_pmu_event_map,
5449 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
5450 .apic = 1,
5451 .large_pebs_flags = LARGE_PEBS_FLAGS,
5452 /*
5453 * Intel PMCs cannot be accessed sanely above 32 bit width,
5454 * so we install an artificial 1<<31 period regardless of
5455 * the generic event period:
5456 */
5457 .max_period = (1ULL << 31) - 1,
5458 .get_event_constraints = intel_get_event_constraints,
5459 .put_event_constraints = intel_put_event_constraints,
5460 .pebs_aliases = intel_pebs_aliases_core2,
5461
5462 .format_attrs = intel_arch3_formats_attr,
5463 .events_sysfs_show = intel_event_sysfs_show,
5464
5465 .cpu_prepare = intel_pmu_cpu_prepare,
5466 .cpu_starting = intel_pmu_cpu_starting,
5467 .cpu_dying = intel_pmu_cpu_dying,
5468 .cpu_dead = intel_pmu_cpu_dead,
5469
5470 .guest_get_msrs = intel_guest_get_msrs,
5471 .sched_task = intel_pmu_sched_task,
5472
5473 .check_period = intel_pmu_check_period,
5474
5475 .aux_output_match = intel_pmu_aux_output_match,
5476
5477 .lbr_reset = intel_pmu_lbr_reset_64,
5478 .lbr_read = intel_pmu_lbr_read_64,
5479 .lbr_save = intel_pmu_lbr_save,
5480 .lbr_restore = intel_pmu_lbr_restore,
5481
5482 /*
5483 * SMM has access to all 4 rings and while traditionally SMM code only
5484 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
5485 *
5486 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
5487 * between SMM or not, this results in what should be pure userspace
5488 * counters including SMM data.
5489 *
5490 * This is a clear privilege issue, therefore globally disable
5491 * counting SMM by default.
5492 */
5493 .attr_freeze_on_smi = 1,
5494 };
5495
intel_clovertown_quirk(void)5496 static __init void intel_clovertown_quirk(void)
5497 {
5498 /*
5499 * PEBS is unreliable due to:
5500 *
5501 * AJ67 - PEBS may experience CPL leaks
5502 * AJ68 - PEBS PMI may be delayed by one event
5503 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
5504 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
5505 *
5506 * AJ67 could be worked around by restricting the OS/USR flags.
5507 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
5508 *
5509 * AJ106 could possibly be worked around by not allowing LBR
5510 * usage from PEBS, including the fixup.
5511 * AJ68 could possibly be worked around by always programming
5512 * a pebs_event_reset[0] value and coping with the lost events.
5513 *
5514 * But taken together it might just make sense to not enable PEBS on
5515 * these chips.
5516 */
5517 pr_warn("PEBS disabled due to CPU errata\n");
5518 x86_pmu.pebs = 0;
5519 x86_pmu.pebs_constraints = NULL;
5520 }
5521
5522 static const struct x86_cpu_id isolation_ucodes[] = {
5523 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f),
5524 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e),
5525 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015),
5526 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037),
5527 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a),
5528 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023),
5529 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014),
5530 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010),
5531 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009),
5532 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009),
5533 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002),
5534 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014),
5535 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021),
5536 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000),
5537 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000),
5538 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c),
5539 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c),
5540 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e),
5541 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e),
5542 {}
5543 };
5544
intel_check_pebs_isolation(void)5545 static void intel_check_pebs_isolation(void)
5546 {
5547 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes);
5548 }
5549
intel_pebs_isolation_quirk(void)5550 static __init void intel_pebs_isolation_quirk(void)
5551 {
5552 WARN_ON_ONCE(x86_pmu.check_microcode);
5553 x86_pmu.check_microcode = intel_check_pebs_isolation;
5554 intel_check_pebs_isolation();
5555 }
5556
5557 static const struct x86_cpu_id pebs_ucodes[] = {
5558 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028),
5559 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618),
5560 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c),
5561 {}
5562 };
5563
intel_snb_pebs_broken(void)5564 static bool intel_snb_pebs_broken(void)
5565 {
5566 return !x86_match_min_microcode_rev(pebs_ucodes);
5567 }
5568
intel_snb_check_microcode(void)5569 static void intel_snb_check_microcode(void)
5570 {
5571 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
5572 return;
5573
5574 /*
5575 * Serialized by the microcode lock..
5576 */
5577 if (x86_pmu.pebs_broken) {
5578 pr_info("PEBS enabled due to microcode update\n");
5579 x86_pmu.pebs_broken = 0;
5580 } else {
5581 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
5582 x86_pmu.pebs_broken = 1;
5583 }
5584 }
5585
is_lbr_from(unsigned long msr)5586 static bool is_lbr_from(unsigned long msr)
5587 {
5588 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
5589
5590 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
5591 }
5592
5593 /*
5594 * Under certain circumstances, access certain MSR may cause #GP.
5595 * The function tests if the input MSR can be safely accessed.
5596 */
check_msr(unsigned long msr,u64 mask)5597 static bool check_msr(unsigned long msr, u64 mask)
5598 {
5599 u64 val_old, val_new, val_tmp;
5600
5601 /*
5602 * Disable the check for real HW, so we don't
5603 * mess with potentially enabled registers:
5604 */
5605 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
5606 return true;
5607
5608 /*
5609 * Read the current value, change it and read it back to see if it
5610 * matches, this is needed to detect certain hardware emulators
5611 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
5612 */
5613 if (rdmsrl_safe(msr, &val_old))
5614 return false;
5615
5616 /*
5617 * Only change the bits which can be updated by wrmsrl.
5618 */
5619 val_tmp = val_old ^ mask;
5620
5621 if (is_lbr_from(msr))
5622 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
5623
5624 if (wrmsrl_safe(msr, val_tmp) ||
5625 rdmsrl_safe(msr, &val_new))
5626 return false;
5627
5628 /*
5629 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
5630 * should equal rdmsrl()'s even with the quirk.
5631 */
5632 if (val_new != val_tmp)
5633 return false;
5634
5635 if (is_lbr_from(msr))
5636 val_old = lbr_from_signext_quirk_wr(val_old);
5637
5638 /* Here it's sure that the MSR can be safely accessed.
5639 * Restore the old value and return.
5640 */
5641 wrmsrl(msr, val_old);
5642
5643 return true;
5644 }
5645
intel_sandybridge_quirk(void)5646 static __init void intel_sandybridge_quirk(void)
5647 {
5648 x86_pmu.check_microcode = intel_snb_check_microcode;
5649 cpus_read_lock();
5650 intel_snb_check_microcode();
5651 cpus_read_unlock();
5652 }
5653
5654 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
5655 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
5656 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
5657 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
5658 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
5659 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
5660 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
5661 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
5662 };
5663
intel_arch_events_quirk(void)5664 static __init void intel_arch_events_quirk(void)
5665 {
5666 int bit;
5667
5668 /* disable event that reported as not present by cpuid */
5669 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
5670 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
5671 pr_warn("CPUID marked event: \'%s\' unavailable\n",
5672 intel_arch_events_map[bit].name);
5673 }
5674 }
5675
intel_nehalem_quirk(void)5676 static __init void intel_nehalem_quirk(void)
5677 {
5678 union cpuid10_ebx ebx;
5679
5680 ebx.full = x86_pmu.events_maskl;
5681 if (ebx.split.no_branch_misses_retired) {
5682 /*
5683 * Erratum AAJ80 detected, we work it around by using
5684 * the BR_MISP_EXEC.ANY event. This will over-count
5685 * branch-misses, but it's still much better than the
5686 * architectural event which is often completely bogus:
5687 */
5688 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
5689 ebx.split.no_branch_misses_retired = 0;
5690 x86_pmu.events_maskl = ebx.full;
5691 pr_info("CPU erratum AAJ80 worked around\n");
5692 }
5693 }
5694
5695 /*
5696 * enable software workaround for errata:
5697 * SNB: BJ122
5698 * IVB: BV98
5699 * HSW: HSD29
5700 *
5701 * Only needed when HT is enabled. However detecting
5702 * if HT is enabled is difficult (model specific). So instead,
5703 * we enable the workaround in the early boot, and verify if
5704 * it is needed in a later initcall phase once we have valid
5705 * topology information to check if HT is actually enabled
5706 */
intel_ht_bug(void)5707 static __init void intel_ht_bug(void)
5708 {
5709 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
5710
5711 x86_pmu.start_scheduling = intel_start_scheduling;
5712 x86_pmu.commit_scheduling = intel_commit_scheduling;
5713 x86_pmu.stop_scheduling = intel_stop_scheduling;
5714 }
5715
5716 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
5717 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
5718
5719 /* Haswell special events */
5720 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
5721 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
5722 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
5723 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
5724 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
5725 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
5726 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
5727 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
5728 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
5729 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
5730 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
5731 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
5732
5733 static struct attribute *hsw_events_attrs[] = {
5734 EVENT_PTR(td_slots_issued),
5735 EVENT_PTR(td_slots_retired),
5736 EVENT_PTR(td_fetch_bubbles),
5737 EVENT_PTR(td_total_slots),
5738 EVENT_PTR(td_total_slots_scale),
5739 EVENT_PTR(td_recovery_bubbles),
5740 EVENT_PTR(td_recovery_bubbles_scale),
5741 NULL
5742 };
5743
5744 static struct attribute *hsw_mem_events_attrs[] = {
5745 EVENT_PTR(mem_ld_hsw),
5746 EVENT_PTR(mem_st_hsw),
5747 NULL,
5748 };
5749
5750 static struct attribute *hsw_tsx_events_attrs[] = {
5751 EVENT_PTR(tx_start),
5752 EVENT_PTR(tx_commit),
5753 EVENT_PTR(tx_abort),
5754 EVENT_PTR(tx_capacity),
5755 EVENT_PTR(tx_conflict),
5756 EVENT_PTR(el_start),
5757 EVENT_PTR(el_commit),
5758 EVENT_PTR(el_abort),
5759 EVENT_PTR(el_capacity),
5760 EVENT_PTR(el_conflict),
5761 EVENT_PTR(cycles_t),
5762 EVENT_PTR(cycles_ct),
5763 NULL
5764 };
5765
5766 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
5767 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
5768 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
5769 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
5770
5771 static struct attribute *icl_events_attrs[] = {
5772 EVENT_PTR(mem_ld_hsw),
5773 EVENT_PTR(mem_st_hsw),
5774 NULL,
5775 };
5776
5777 static struct attribute *icl_td_events_attrs[] = {
5778 EVENT_PTR(slots),
5779 EVENT_PTR(td_retiring),
5780 EVENT_PTR(td_bad_spec),
5781 EVENT_PTR(td_fe_bound),
5782 EVENT_PTR(td_be_bound),
5783 NULL,
5784 };
5785
5786 static struct attribute *icl_tsx_events_attrs[] = {
5787 EVENT_PTR(tx_start),
5788 EVENT_PTR(tx_abort),
5789 EVENT_PTR(tx_commit),
5790 EVENT_PTR(tx_capacity_read),
5791 EVENT_PTR(tx_capacity_write),
5792 EVENT_PTR(tx_conflict),
5793 EVENT_PTR(el_start),
5794 EVENT_PTR(el_abort),
5795 EVENT_PTR(el_commit),
5796 EVENT_PTR(el_capacity_read),
5797 EVENT_PTR(el_capacity_write),
5798 EVENT_PTR(el_conflict),
5799 EVENT_PTR(cycles_t),
5800 EVENT_PTR(cycles_ct),
5801 NULL,
5802 };
5803
5804
5805 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
5806 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
5807
5808 static struct attribute *glc_events_attrs[] = {
5809 EVENT_PTR(mem_ld_hsw),
5810 EVENT_PTR(mem_st_spr),
5811 EVENT_PTR(mem_ld_aux),
5812 NULL,
5813 };
5814
5815 static struct attribute *glc_td_events_attrs[] = {
5816 EVENT_PTR(slots),
5817 EVENT_PTR(td_retiring),
5818 EVENT_PTR(td_bad_spec),
5819 EVENT_PTR(td_fe_bound),
5820 EVENT_PTR(td_be_bound),
5821 EVENT_PTR(td_heavy_ops),
5822 EVENT_PTR(td_br_mispredict),
5823 EVENT_PTR(td_fetch_lat),
5824 EVENT_PTR(td_mem_bound),
5825 NULL,
5826 };
5827
5828 static struct attribute *glc_tsx_events_attrs[] = {
5829 EVENT_PTR(tx_start),
5830 EVENT_PTR(tx_abort),
5831 EVENT_PTR(tx_commit),
5832 EVENT_PTR(tx_capacity_read),
5833 EVENT_PTR(tx_capacity_write),
5834 EVENT_PTR(tx_conflict),
5835 EVENT_PTR(cycles_t),
5836 EVENT_PTR(cycles_ct),
5837 NULL,
5838 };
5839
freeze_on_smi_show(struct device * cdev,struct device_attribute * attr,char * buf)5840 static ssize_t freeze_on_smi_show(struct device *cdev,
5841 struct device_attribute *attr,
5842 char *buf)
5843 {
5844 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
5845 }
5846
5847 static DEFINE_MUTEX(freeze_on_smi_mutex);
5848
freeze_on_smi_store(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)5849 static ssize_t freeze_on_smi_store(struct device *cdev,
5850 struct device_attribute *attr,
5851 const char *buf, size_t count)
5852 {
5853 unsigned long val;
5854 ssize_t ret;
5855
5856 ret = kstrtoul(buf, 0, &val);
5857 if (ret)
5858 return ret;
5859
5860 if (val > 1)
5861 return -EINVAL;
5862
5863 mutex_lock(&freeze_on_smi_mutex);
5864
5865 if (x86_pmu.attr_freeze_on_smi == val)
5866 goto done;
5867
5868 x86_pmu.attr_freeze_on_smi = val;
5869
5870 cpus_read_lock();
5871 on_each_cpu(flip_smm_bit, &val, 1);
5872 cpus_read_unlock();
5873 done:
5874 mutex_unlock(&freeze_on_smi_mutex);
5875
5876 return count;
5877 }
5878
update_tfa_sched(void * ignored)5879 static void update_tfa_sched(void *ignored)
5880 {
5881 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5882
5883 /*
5884 * check if PMC3 is used
5885 * and if so force schedule out for all event types all contexts
5886 */
5887 if (test_bit(3, cpuc->active_mask))
5888 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
5889 }
5890
show_sysctl_tfa(struct device * cdev,struct device_attribute * attr,char * buf)5891 static ssize_t show_sysctl_tfa(struct device *cdev,
5892 struct device_attribute *attr,
5893 char *buf)
5894 {
5895 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
5896 }
5897
set_sysctl_tfa(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)5898 static ssize_t set_sysctl_tfa(struct device *cdev,
5899 struct device_attribute *attr,
5900 const char *buf, size_t count)
5901 {
5902 bool val;
5903 ssize_t ret;
5904
5905 ret = kstrtobool(buf, &val);
5906 if (ret)
5907 return ret;
5908
5909 /* no change */
5910 if (val == allow_tsx_force_abort)
5911 return count;
5912
5913 allow_tsx_force_abort = val;
5914
5915 cpus_read_lock();
5916 on_each_cpu(update_tfa_sched, NULL, 1);
5917 cpus_read_unlock();
5918
5919 return count;
5920 }
5921
5922
5923 static DEVICE_ATTR_RW(freeze_on_smi);
5924
branches_show(struct device * cdev,struct device_attribute * attr,char * buf)5925 static ssize_t branches_show(struct device *cdev,
5926 struct device_attribute *attr,
5927 char *buf)
5928 {
5929 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
5930 }
5931
5932 static DEVICE_ATTR_RO(branches);
5933
branch_counter_nr_show(struct device * cdev,struct device_attribute * attr,char * buf)5934 static ssize_t branch_counter_nr_show(struct device *cdev,
5935 struct device_attribute *attr,
5936 char *buf)
5937 {
5938 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters));
5939 }
5940
5941 static DEVICE_ATTR_RO(branch_counter_nr);
5942
branch_counter_width_show(struct device * cdev,struct device_attribute * attr,char * buf)5943 static ssize_t branch_counter_width_show(struct device *cdev,
5944 struct device_attribute *attr,
5945 char *buf)
5946 {
5947 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS);
5948 }
5949
5950 static DEVICE_ATTR_RO(branch_counter_width);
5951
5952 static struct attribute *lbr_attrs[] = {
5953 &dev_attr_branches.attr,
5954 &dev_attr_branch_counter_nr.attr,
5955 &dev_attr_branch_counter_width.attr,
5956 NULL
5957 };
5958
5959 static umode_t
lbr_is_visible(struct kobject * kobj,struct attribute * attr,int i)5960 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5961 {
5962 /* branches */
5963 if (i == 0)
5964 return x86_pmu.lbr_nr ? attr->mode : 0;
5965
5966 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0;
5967 }
5968
5969 static char pmu_name_str[30];
5970
5971 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str);
5972
5973 static struct attribute *intel_pmu_caps_attrs[] = {
5974 &dev_attr_pmu_name.attr.attr,
5975 NULL
5976 };
5977
5978 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
5979 show_sysctl_tfa,
5980 set_sysctl_tfa);
5981
5982 static struct attribute *intel_pmu_attrs[] = {
5983 &dev_attr_freeze_on_smi.attr,
5984 &dev_attr_allow_tsx_force_abort.attr,
5985 NULL,
5986 };
5987
5988 static umode_t
default_is_visible(struct kobject * kobj,struct attribute * attr,int i)5989 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5990 {
5991 if (attr == &dev_attr_allow_tsx_force_abort.attr)
5992 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
5993
5994 return attr->mode;
5995 }
5996
5997 static umode_t
tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)5998 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5999 {
6000 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
6001 }
6002
6003 static umode_t
pebs_is_visible(struct kobject * kobj,struct attribute * attr,int i)6004 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6005 {
6006 return x86_pmu.pebs ? attr->mode : 0;
6007 }
6008
6009 static umode_t
mem_is_visible(struct kobject * kobj,struct attribute * attr,int i)6010 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6011 {
6012 if (attr == &event_attr_mem_ld_aux.attr.attr)
6013 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;
6014
6015 return pebs_is_visible(kobj, attr, i);
6016 }
6017
6018 static umode_t
exra_is_visible(struct kobject * kobj,struct attribute * attr,int i)6019 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6020 {
6021 return x86_pmu.version >= 2 ? attr->mode : 0;
6022 }
6023
6024 static umode_t
td_is_visible(struct kobject * kobj,struct attribute * attr,int i)6025 td_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6026 {
6027 /*
6028 * Hide the perf metrics topdown events
6029 * if the feature is not enumerated.
6030 */
6031 if (x86_pmu.num_topdown_events)
6032 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0;
6033
6034 return attr->mode;
6035 }
6036
6037 static struct attribute_group group_events_td = {
6038 .name = "events",
6039 .is_visible = td_is_visible,
6040 };
6041
6042 static struct attribute_group group_events_mem = {
6043 .name = "events",
6044 .is_visible = mem_is_visible,
6045 };
6046
6047 static struct attribute_group group_events_tsx = {
6048 .name = "events",
6049 .is_visible = tsx_is_visible,
6050 };
6051
6052 static struct attribute_group group_caps_gen = {
6053 .name = "caps",
6054 .attrs = intel_pmu_caps_attrs,
6055 };
6056
6057 static struct attribute_group group_caps_lbr = {
6058 .name = "caps",
6059 .attrs = lbr_attrs,
6060 .is_visible = lbr_is_visible,
6061 };
6062
6063 static struct attribute_group group_format_extra = {
6064 .name = "format",
6065 .is_visible = exra_is_visible,
6066 };
6067
6068 static struct attribute_group group_format_extra_skl = {
6069 .name = "format",
6070 .is_visible = exra_is_visible,
6071 };
6072
6073 static struct attribute_group group_format_evtsel_ext = {
6074 .name = "format",
6075 .attrs = format_evtsel_ext_attrs,
6076 .is_visible = evtsel_ext_is_visible,
6077 };
6078
6079 static struct attribute_group group_default = {
6080 .attrs = intel_pmu_attrs,
6081 .is_visible = default_is_visible,
6082 };
6083
6084 static const struct attribute_group *attr_update[] = {
6085 &group_events_td,
6086 &group_events_mem,
6087 &group_events_tsx,
6088 &group_caps_gen,
6089 &group_caps_lbr,
6090 &group_format_extra,
6091 &group_format_extra_skl,
6092 &group_format_evtsel_ext,
6093 &group_default,
6094 NULL,
6095 };
6096
6097 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big);
6098 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
6099 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
6100 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
6101 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
6102 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big);
6103 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big);
6104 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big);
6105 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big);
6106
6107 static struct attribute *adl_hybrid_events_attrs[] = {
6108 EVENT_PTR(slots_adl),
6109 EVENT_PTR(td_retiring_adl),
6110 EVENT_PTR(td_bad_spec_adl),
6111 EVENT_PTR(td_fe_bound_adl),
6112 EVENT_PTR(td_be_bound_adl),
6113 EVENT_PTR(td_heavy_ops_adl),
6114 EVENT_PTR(td_br_mis_adl),
6115 EVENT_PTR(td_fetch_lat_adl),
6116 EVENT_PTR(td_mem_bound_adl),
6117 NULL,
6118 };
6119
6120 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small);
6121 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small);
6122 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small);
6123
6124 static struct attribute *lnl_hybrid_events_attrs[] = {
6125 EVENT_PTR(slots_adl),
6126 EVENT_PTR(td_retiring_lnl),
6127 EVENT_PTR(td_bad_spec_adl),
6128 EVENT_PTR(td_fe_bound_lnl),
6129 EVENT_PTR(td_be_bound_lnl),
6130 EVENT_PTR(td_heavy_ops_adl),
6131 EVENT_PTR(td_br_mis_adl),
6132 EVENT_PTR(td_fetch_lat_adl),
6133 EVENT_PTR(td_mem_bound_adl),
6134 NULL
6135 };
6136
6137 /* The event string must be in PMU IDX order. */
6138 EVENT_ATTR_STR_HYBRID(topdown-retiring,
6139 td_retiring_arl_h,
6140 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0",
6141 hybrid_big_small_tiny);
6142 EVENT_ATTR_STR_HYBRID(topdown-bad-spec,
6143 td_bad_spec_arl_h,
6144 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0",
6145 hybrid_big_small_tiny);
6146 EVENT_ATTR_STR_HYBRID(topdown-fe-bound,
6147 td_fe_bound_arl_h,
6148 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0",
6149 hybrid_big_small_tiny);
6150 EVENT_ATTR_STR_HYBRID(topdown-be-bound,
6151 td_be_bound_arl_h,
6152 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0",
6153 hybrid_big_small_tiny);
6154
6155 static struct attribute *arl_h_hybrid_events_attrs[] = {
6156 EVENT_PTR(slots_adl),
6157 EVENT_PTR(td_retiring_arl_h),
6158 EVENT_PTR(td_bad_spec_arl_h),
6159 EVENT_PTR(td_fe_bound_arl_h),
6160 EVENT_PTR(td_be_bound_arl_h),
6161 EVENT_PTR(td_heavy_ops_adl),
6162 EVENT_PTR(td_br_mis_adl),
6163 EVENT_PTR(td_fetch_lat_adl),
6164 EVENT_PTR(td_mem_bound_adl),
6165 NULL,
6166 };
6167
6168 /* Must be in IDX order */
6169 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
6170 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
6171 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big);
6172
6173 static struct attribute *adl_hybrid_mem_attrs[] = {
6174 EVENT_PTR(mem_ld_adl),
6175 EVENT_PTR(mem_st_adl),
6176 EVENT_PTR(mem_ld_aux_adl),
6177 NULL,
6178 };
6179
6180 static struct attribute *mtl_hybrid_mem_attrs[] = {
6181 EVENT_PTR(mem_ld_adl),
6182 EVENT_PTR(mem_st_adl),
6183 NULL
6184 };
6185
6186 EVENT_ATTR_STR_HYBRID(mem-loads,
6187 mem_ld_arl_h,
6188 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3",
6189 hybrid_big_small_tiny);
6190 EVENT_ATTR_STR_HYBRID(mem-stores,
6191 mem_st_arl_h,
6192 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6",
6193 hybrid_big_small_tiny);
6194
6195 static struct attribute *arl_h_hybrid_mem_attrs[] = {
6196 EVENT_PTR(mem_ld_arl_h),
6197 EVENT_PTR(mem_st_arl_h),
6198 NULL,
6199 };
6200
6201 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
6202 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
6203 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
6204 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big);
6205 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big);
6206 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
6207 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big);
6208 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big);
6209
6210 static struct attribute *adl_hybrid_tsx_attrs[] = {
6211 EVENT_PTR(tx_start_adl),
6212 EVENT_PTR(tx_abort_adl),
6213 EVENT_PTR(tx_commit_adl),
6214 EVENT_PTR(tx_capacity_read_adl),
6215 EVENT_PTR(tx_capacity_write_adl),
6216 EVENT_PTR(tx_conflict_adl),
6217 EVENT_PTR(cycles_t_adl),
6218 EVENT_PTR(cycles_ct_adl),
6219 NULL,
6220 };
6221
6222 FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
6223 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
6224 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny);
6225 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny);
6226 FORMAT_ATTR_HYBRID(frontend, hybrid_big);
6227
6228 #define ADL_HYBRID_RTM_FORMAT_ATTR \
6229 FORMAT_HYBRID_PTR(in_tx), \
6230 FORMAT_HYBRID_PTR(in_tx_cp)
6231
6232 #define ADL_HYBRID_FORMAT_ATTR \
6233 FORMAT_HYBRID_PTR(offcore_rsp), \
6234 FORMAT_HYBRID_PTR(ldlat), \
6235 FORMAT_HYBRID_PTR(frontend)
6236
6237 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
6238 ADL_HYBRID_RTM_FORMAT_ATTR,
6239 ADL_HYBRID_FORMAT_ATTR,
6240 NULL
6241 };
6242
6243 static struct attribute *adl_hybrid_extra_attr[] = {
6244 ADL_HYBRID_FORMAT_ATTR,
6245 NULL
6246 };
6247
6248 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny);
6249
6250 static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
6251 ADL_HYBRID_RTM_FORMAT_ATTR,
6252 ADL_HYBRID_FORMAT_ATTR,
6253 FORMAT_HYBRID_PTR(snoop_rsp),
6254 NULL
6255 };
6256
6257 static struct attribute *mtl_hybrid_extra_attr[] = {
6258 ADL_HYBRID_FORMAT_ATTR,
6259 FORMAT_HYBRID_PTR(snoop_rsp),
6260 NULL
6261 };
6262
is_attr_for_this_pmu(struct kobject * kobj,struct attribute * attr)6263 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
6264 {
6265 struct device *dev = kobj_to_dev(kobj);
6266 struct x86_hybrid_pmu *pmu =
6267 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6268 struct perf_pmu_events_hybrid_attr *pmu_attr =
6269 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
6270
6271 return pmu->pmu_type & pmu_attr->pmu_type;
6272 }
6273
hybrid_events_is_visible(struct kobject * kobj,struct attribute * attr,int i)6274 static umode_t hybrid_events_is_visible(struct kobject *kobj,
6275 struct attribute *attr, int i)
6276 {
6277 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
6278 }
6279
hybrid_find_supported_cpu(struct x86_hybrid_pmu * pmu)6280 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
6281 {
6282 int cpu = cpumask_first(&pmu->supported_cpus);
6283
6284 return (cpu >= nr_cpu_ids) ? -1 : cpu;
6285 }
6286
hybrid_tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)6287 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
6288 struct attribute *attr, int i)
6289 {
6290 struct device *dev = kobj_to_dev(kobj);
6291 struct x86_hybrid_pmu *pmu =
6292 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6293 int cpu = hybrid_find_supported_cpu(pmu);
6294
6295 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
6296 }
6297
hybrid_format_is_visible(struct kobject * kobj,struct attribute * attr,int i)6298 static umode_t hybrid_format_is_visible(struct kobject *kobj,
6299 struct attribute *attr, int i)
6300 {
6301 struct device *dev = kobj_to_dev(kobj);
6302 struct x86_hybrid_pmu *pmu =
6303 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6304 struct perf_pmu_format_hybrid_attr *pmu_attr =
6305 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
6306 int cpu = hybrid_find_supported_cpu(pmu);
6307
6308 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0;
6309 }
6310
hybrid_td_is_visible(struct kobject * kobj,struct attribute * attr,int i)6311 static umode_t hybrid_td_is_visible(struct kobject *kobj,
6312 struct attribute *attr, int i)
6313 {
6314 struct device *dev = kobj_to_dev(kobj);
6315 struct x86_hybrid_pmu *pmu =
6316 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6317
6318 if (!is_attr_for_this_pmu(kobj, attr))
6319 return 0;
6320
6321
6322 /* Only the big core supports perf metrics */
6323 if (pmu->pmu_type == hybrid_big)
6324 return pmu->intel_cap.perf_metrics ? attr->mode : 0;
6325
6326 return attr->mode;
6327 }
6328
6329 static struct attribute_group hybrid_group_events_td = {
6330 .name = "events",
6331 .is_visible = hybrid_td_is_visible,
6332 };
6333
6334 static struct attribute_group hybrid_group_events_mem = {
6335 .name = "events",
6336 .is_visible = hybrid_events_is_visible,
6337 };
6338
6339 static struct attribute_group hybrid_group_events_tsx = {
6340 .name = "events",
6341 .is_visible = hybrid_tsx_is_visible,
6342 };
6343
6344 static struct attribute_group hybrid_group_format_extra = {
6345 .name = "format",
6346 .is_visible = hybrid_format_is_visible,
6347 };
6348
intel_hybrid_get_attr_cpus(struct device * dev,struct device_attribute * attr,char * buf)6349 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
6350 struct device_attribute *attr,
6351 char *buf)
6352 {
6353 struct x86_hybrid_pmu *pmu =
6354 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6355
6356 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus);
6357 }
6358
6359 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
6360 static struct attribute *intel_hybrid_cpus_attrs[] = {
6361 &dev_attr_cpus.attr,
6362 NULL,
6363 };
6364
6365 static struct attribute_group hybrid_group_cpus = {
6366 .attrs = intel_hybrid_cpus_attrs,
6367 };
6368
6369 static const struct attribute_group *hybrid_attr_update[] = {
6370 &hybrid_group_events_td,
6371 &hybrid_group_events_mem,
6372 &hybrid_group_events_tsx,
6373 &group_caps_gen,
6374 &group_caps_lbr,
6375 &hybrid_group_format_extra,
6376 &group_format_evtsel_ext,
6377 &group_default,
6378 &hybrid_group_cpus,
6379 NULL,
6380 };
6381
6382 static struct attribute *empty_attrs;
6383
intel_pmu_check_event_constraints(struct event_constraint * event_constraints,u64 cntr_mask,u64 fixed_cntr_mask,u64 intel_ctrl)6384 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
6385 u64 cntr_mask,
6386 u64 fixed_cntr_mask,
6387 u64 intel_ctrl)
6388 {
6389 struct event_constraint *c;
6390
6391 if (!event_constraints)
6392 return;
6393
6394 /*
6395 * event on fixed counter2 (REF_CYCLES) only works on this
6396 * counter, so do not extend mask to generic counters
6397 */
6398 for_each_event_constraint(c, event_constraints) {
6399 /*
6400 * Don't extend the topdown slots and metrics
6401 * events to the generic counters.
6402 */
6403 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
6404 /*
6405 * Disable topdown slots and metrics events,
6406 * if slots event is not in CPUID.
6407 */
6408 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
6409 c->idxmsk64 = 0;
6410 c->weight = hweight64(c->idxmsk64);
6411 continue;
6412 }
6413
6414 if (c->cmask == FIXED_EVENT_FLAGS) {
6415 /* Disabled fixed counters which are not in CPUID */
6416 c->idxmsk64 &= intel_ctrl;
6417
6418 /*
6419 * Don't extend the pseudo-encoding to the
6420 * generic counters
6421 */
6422 if (!use_fixed_pseudo_encoding(c->code))
6423 c->idxmsk64 |= cntr_mask;
6424 }
6425 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED);
6426 c->weight = hweight64(c->idxmsk64);
6427 }
6428 }
6429
intel_pmu_check_extra_regs(struct extra_reg * extra_regs)6430 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
6431 {
6432 struct extra_reg *er;
6433
6434 /*
6435 * Access extra MSR may cause #GP under certain circumstances.
6436 * E.g. KVM doesn't support offcore event
6437 * Check all extra_regs here.
6438 */
6439 if (!extra_regs)
6440 return;
6441
6442 for (er = extra_regs; er->msr; er++) {
6443 er->extra_msr_access = check_msr(er->msr, 0x11UL);
6444 /* Disable LBR select mapping */
6445 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
6446 x86_pmu.lbr_sel_map = NULL;
6447 }
6448 }
6449
intel_pmu_v6_addr_offset(int index,bool eventsel)6450 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel)
6451 {
6452 return MSR_IA32_PMC_V6_STEP * index;
6453 }
6454
6455 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = {
6456 { hybrid_small, "cpu_atom" },
6457 { hybrid_big, "cpu_core" },
6458 { hybrid_tiny, "cpu_lowpower" },
6459 };
6460
intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)6461 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
6462 {
6463 unsigned long pmus_mask = pmus;
6464 struct x86_hybrid_pmu *pmu;
6465 int idx = 0, bit;
6466
6467 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask);
6468 x86_pmu.hybrid_pmu = kcalloc(x86_pmu.num_hybrid_pmus,
6469 sizeof(struct x86_hybrid_pmu),
6470 GFP_KERNEL);
6471 if (!x86_pmu.hybrid_pmu)
6472 return -ENOMEM;
6473
6474 static_branch_enable(&perf_is_hybrid);
6475 x86_pmu.filter = intel_pmu_filter;
6476
6477 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) {
6478 pmu = &x86_pmu.hybrid_pmu[idx++];
6479 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id;
6480 pmu->name = intel_hybrid_pmu_type_map[bit].name;
6481
6482 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
6483 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
6484 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
6485 pmu->config_mask = X86_RAW_EVENT_MASK;
6486 pmu->unconstrained = (struct event_constraint)
6487 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
6488 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
6489
6490 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6491 if (pmu->pmu_type & hybrid_small_tiny) {
6492 pmu->intel_cap.perf_metrics = 0;
6493 pmu->mid_ack = true;
6494 } else if (pmu->pmu_type & hybrid_big) {
6495 pmu->intel_cap.perf_metrics = 1;
6496 pmu->late_ack = true;
6497 }
6498 }
6499
6500 return 0;
6501 }
6502
intel_pmu_ref_cycles_ext(void)6503 static __always_inline void intel_pmu_ref_cycles_ext(void)
6504 {
6505 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))
6506 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c;
6507 }
6508
intel_pmu_init_glc(struct pmu * pmu)6509 static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
6510 {
6511 x86_pmu.late_ack = true;
6512 x86_pmu.limit_period = glc_limit_period;
6513 x86_pmu.pebs_aliases = NULL;
6514 x86_pmu.pebs_prec_dist = true;
6515 x86_pmu.pebs_block = true;
6516 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6517 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6518 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6519 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6520 x86_pmu.lbr_pt_coexist = true;
6521 x86_pmu.num_topdown_events = 8;
6522 static_call_update(intel_pmu_update_topdown_event,
6523 &icl_update_topdown_event);
6524 static_call_update(intel_pmu_set_topdown_event_period,
6525 &icl_set_topdown_event_period);
6526
6527 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6528 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6529 hybrid(pmu, event_constraints) = intel_glc_event_constraints;
6530 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;
6531
6532 intel_pmu_ref_cycles_ext();
6533 }
6534
intel_pmu_init_grt(struct pmu * pmu)6535 static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
6536 {
6537 x86_pmu.mid_ack = true;
6538 x86_pmu.limit_period = glc_limit_period;
6539 x86_pmu.pebs_aliases = NULL;
6540 x86_pmu.pebs_prec_dist = true;
6541 x86_pmu.pebs_block = true;
6542 x86_pmu.lbr_pt_coexist = true;
6543 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6544 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6545
6546 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6547 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6548 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6549 hybrid(pmu, event_constraints) = intel_grt_event_constraints;
6550 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
6551 hybrid(pmu, extra_regs) = intel_grt_extra_regs;
6552
6553 intel_pmu_ref_cycles_ext();
6554 }
6555
intel_pmu_init_lnc(struct pmu * pmu)6556 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
6557 {
6558 intel_pmu_init_glc(pmu);
6559 hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
6560 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
6561 hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
6562 }
6563
intel_pmu_init_skt(struct pmu * pmu)6564 static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
6565 {
6566 intel_pmu_init_grt(pmu);
6567 hybrid(pmu, event_constraints) = intel_skt_event_constraints;
6568 hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
6569 }
6570
intel_pmu_init(void)6571 __init int intel_pmu_init(void)
6572 {
6573 struct attribute **extra_skl_attr = &empty_attrs;
6574 struct attribute **extra_attr = &empty_attrs;
6575 struct attribute **td_attr = &empty_attrs;
6576 struct attribute **mem_attr = &empty_attrs;
6577 struct attribute **tsx_attr = &empty_attrs;
6578 union cpuid10_edx edx;
6579 union cpuid10_eax eax;
6580 union cpuid10_ebx ebx;
6581 unsigned int fixed_mask;
6582 bool pmem = false;
6583 int version, i;
6584 char *name;
6585 struct x86_hybrid_pmu *pmu;
6586
6587 /* Architectural Perfmon was introduced starting with Core "Yonah" */
6588 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
6589 switch (boot_cpu_data.x86) {
6590 case 6:
6591 if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH)
6592 return p6_pmu_init();
6593 break;
6594 case 11:
6595 return knc_pmu_init();
6596 case 15:
6597 return p4_pmu_init();
6598 }
6599
6600 pr_cont("unsupported CPU family %d model %d ",
6601 boot_cpu_data.x86, boot_cpu_data.x86_model);
6602 return -ENODEV;
6603 }
6604
6605 /*
6606 * Check whether the Architectural PerfMon supports
6607 * Branch Misses Retired hw_event or not.
6608 */
6609 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
6610 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
6611 return -ENODEV;
6612
6613 version = eax.split.version_id;
6614 if (version < 2)
6615 x86_pmu = core_pmu;
6616 else
6617 x86_pmu = intel_pmu;
6618
6619 x86_pmu.version = version;
6620 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0);
6621 x86_pmu.cntval_bits = eax.split.bit_width;
6622 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
6623
6624 x86_pmu.events_maskl = ebx.full;
6625 x86_pmu.events_mask_len = eax.split.mask_length;
6626
6627 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64);
6628 x86_pmu.pebs_capable = PEBS_COUNTER_MASK;
6629
6630 /*
6631 * Quirk: v2 perfmon does not report fixed-purpose events, so
6632 * assume at least 3 events, when not running in a hypervisor:
6633 */
6634 if (version > 1 && version < 5) {
6635 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
6636
6637 x86_pmu.fixed_cntr_mask64 =
6638 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0);
6639 } else if (version >= 5)
6640 x86_pmu.fixed_cntr_mask64 = fixed_mask;
6641
6642 if (boot_cpu_has(X86_FEATURE_PDCM)) {
6643 u64 capabilities;
6644
6645 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
6646 x86_pmu.intel_cap.capabilities = capabilities;
6647 }
6648
6649 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
6650 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
6651 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
6652 }
6653
6654 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
6655 intel_pmu_arch_lbr_init();
6656
6657 intel_ds_init();
6658
6659 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
6660
6661 if (version >= 5) {
6662 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
6663 if (x86_pmu.intel_cap.anythread_deprecated)
6664 pr_cont(" AnyThread deprecated, ");
6665 }
6666
6667 /*
6668 * Install the hw-cache-events table:
6669 */
6670 switch (boot_cpu_data.x86_vfm) {
6671 case INTEL_CORE_YONAH:
6672 pr_cont("Core events, ");
6673 name = "core";
6674 break;
6675
6676 case INTEL_CORE2_MEROM:
6677 x86_add_quirk(intel_clovertown_quirk);
6678 fallthrough;
6679
6680 case INTEL_CORE2_MEROM_L:
6681 case INTEL_CORE2_PENRYN:
6682 case INTEL_CORE2_DUNNINGTON:
6683 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
6684 sizeof(hw_cache_event_ids));
6685
6686 intel_pmu_lbr_init_core();
6687
6688 x86_pmu.event_constraints = intel_core2_event_constraints;
6689 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
6690 pr_cont("Core2 events, ");
6691 name = "core2";
6692 break;
6693
6694 case INTEL_NEHALEM:
6695 case INTEL_NEHALEM_EP:
6696 case INTEL_NEHALEM_EX:
6697 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
6698 sizeof(hw_cache_event_ids));
6699 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
6700 sizeof(hw_cache_extra_regs));
6701
6702 intel_pmu_lbr_init_nhm();
6703
6704 x86_pmu.event_constraints = intel_nehalem_event_constraints;
6705 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
6706 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
6707 x86_pmu.extra_regs = intel_nehalem_extra_regs;
6708 x86_pmu.limit_period = nhm_limit_period;
6709
6710 mem_attr = nhm_mem_events_attrs;
6711
6712 /* UOPS_ISSUED.STALLED_CYCLES */
6713 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6714 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6715 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
6716 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6717 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
6718
6719 intel_pmu_pebs_data_source_nhm();
6720 x86_add_quirk(intel_nehalem_quirk);
6721 x86_pmu.pebs_no_tlb = 1;
6722 extra_attr = nhm_format_attr;
6723
6724 pr_cont("Nehalem events, ");
6725 name = "nehalem";
6726 break;
6727
6728 case INTEL_ATOM_BONNELL:
6729 case INTEL_ATOM_BONNELL_MID:
6730 case INTEL_ATOM_SALTWELL:
6731 case INTEL_ATOM_SALTWELL_MID:
6732 case INTEL_ATOM_SALTWELL_TABLET:
6733 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
6734 sizeof(hw_cache_event_ids));
6735
6736 intel_pmu_lbr_init_atom();
6737
6738 x86_pmu.event_constraints = intel_gen_event_constraints;
6739 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
6740 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
6741 pr_cont("Atom events, ");
6742 name = "bonnell";
6743 break;
6744
6745 case INTEL_ATOM_SILVERMONT:
6746 case INTEL_ATOM_SILVERMONT_D:
6747 case INTEL_ATOM_SILVERMONT_MID:
6748 case INTEL_ATOM_AIRMONT:
6749 case INTEL_ATOM_SILVERMONT_MID2:
6750 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
6751 sizeof(hw_cache_event_ids));
6752 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
6753 sizeof(hw_cache_extra_regs));
6754
6755 intel_pmu_lbr_init_slm();
6756
6757 x86_pmu.event_constraints = intel_slm_event_constraints;
6758 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
6759 x86_pmu.extra_regs = intel_slm_extra_regs;
6760 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6761 td_attr = slm_events_attrs;
6762 extra_attr = slm_format_attr;
6763 pr_cont("Silvermont events, ");
6764 name = "silvermont";
6765 break;
6766
6767 case INTEL_ATOM_GOLDMONT:
6768 case INTEL_ATOM_GOLDMONT_D:
6769 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
6770 sizeof(hw_cache_event_ids));
6771 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
6772 sizeof(hw_cache_extra_regs));
6773
6774 intel_pmu_lbr_init_skl();
6775
6776 x86_pmu.event_constraints = intel_slm_event_constraints;
6777 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
6778 x86_pmu.extra_regs = intel_glm_extra_regs;
6779 /*
6780 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6781 * for precise cycles.
6782 * :pp is identical to :ppp
6783 */
6784 x86_pmu.pebs_aliases = NULL;
6785 x86_pmu.pebs_prec_dist = true;
6786 x86_pmu.lbr_pt_coexist = true;
6787 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6788 td_attr = glm_events_attrs;
6789 extra_attr = slm_format_attr;
6790 pr_cont("Goldmont events, ");
6791 name = "goldmont";
6792 break;
6793
6794 case INTEL_ATOM_GOLDMONT_PLUS:
6795 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
6796 sizeof(hw_cache_event_ids));
6797 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
6798 sizeof(hw_cache_extra_regs));
6799
6800 intel_pmu_lbr_init_skl();
6801
6802 x86_pmu.event_constraints = intel_slm_event_constraints;
6803 x86_pmu.extra_regs = intel_glm_extra_regs;
6804 /*
6805 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6806 * for precise cycles.
6807 */
6808 x86_pmu.pebs_aliases = NULL;
6809 x86_pmu.pebs_prec_dist = true;
6810 x86_pmu.lbr_pt_coexist = true;
6811 x86_pmu.pebs_capable = ~0ULL;
6812 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6813 x86_pmu.flags |= PMU_FL_PEBS_ALL;
6814 x86_pmu.get_event_constraints = glp_get_event_constraints;
6815 td_attr = glm_events_attrs;
6816 /* Goldmont Plus has 4-wide pipeline */
6817 event_attr_td_total_slots_scale_glm.event_str = "4";
6818 extra_attr = slm_format_attr;
6819 pr_cont("Goldmont plus events, ");
6820 name = "goldmont_plus";
6821 break;
6822
6823 case INTEL_ATOM_TREMONT_D:
6824 case INTEL_ATOM_TREMONT:
6825 case INTEL_ATOM_TREMONT_L:
6826 x86_pmu.late_ack = true;
6827 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
6828 sizeof(hw_cache_event_ids));
6829 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
6830 sizeof(hw_cache_extra_regs));
6831 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6832
6833 intel_pmu_lbr_init_skl();
6834
6835 x86_pmu.event_constraints = intel_slm_event_constraints;
6836 x86_pmu.extra_regs = intel_tnt_extra_regs;
6837 /*
6838 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6839 * for precise cycles.
6840 */
6841 x86_pmu.pebs_aliases = NULL;
6842 x86_pmu.pebs_prec_dist = true;
6843 x86_pmu.lbr_pt_coexist = true;
6844 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6845 x86_pmu.get_event_constraints = tnt_get_event_constraints;
6846 td_attr = tnt_events_attrs;
6847 extra_attr = slm_format_attr;
6848 pr_cont("Tremont events, ");
6849 name = "Tremont";
6850 break;
6851
6852 case INTEL_ATOM_GRACEMONT:
6853 intel_pmu_init_grt(NULL);
6854 intel_pmu_pebs_data_source_grt();
6855 x86_pmu.pebs_latency_data = grt_latency_data;
6856 x86_pmu.get_event_constraints = tnt_get_event_constraints;
6857 td_attr = tnt_events_attrs;
6858 mem_attr = grt_mem_attrs;
6859 extra_attr = nhm_format_attr;
6860 pr_cont("Gracemont events, ");
6861 name = "gracemont";
6862 break;
6863
6864 case INTEL_ATOM_CRESTMONT:
6865 case INTEL_ATOM_CRESTMONT_X:
6866 intel_pmu_init_grt(NULL);
6867 x86_pmu.extra_regs = intel_cmt_extra_regs;
6868 intel_pmu_pebs_data_source_cmt();
6869 x86_pmu.pebs_latency_data = cmt_latency_data;
6870 x86_pmu.get_event_constraints = cmt_get_event_constraints;
6871 td_attr = cmt_events_attrs;
6872 mem_attr = grt_mem_attrs;
6873 extra_attr = cmt_format_attr;
6874 pr_cont("Crestmont events, ");
6875 name = "crestmont";
6876 break;
6877
6878 case INTEL_WESTMERE:
6879 case INTEL_WESTMERE_EP:
6880 case INTEL_WESTMERE_EX:
6881 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
6882 sizeof(hw_cache_event_ids));
6883 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
6884 sizeof(hw_cache_extra_regs));
6885
6886 intel_pmu_lbr_init_nhm();
6887
6888 x86_pmu.event_constraints = intel_westmere_event_constraints;
6889 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
6890 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
6891 x86_pmu.extra_regs = intel_westmere_extra_regs;
6892 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6893
6894 mem_attr = nhm_mem_events_attrs;
6895
6896 /* UOPS_ISSUED.STALLED_CYCLES */
6897 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6898 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6899 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
6900 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6901 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
6902
6903 intel_pmu_pebs_data_source_nhm();
6904 extra_attr = nhm_format_attr;
6905 pr_cont("Westmere events, ");
6906 name = "westmere";
6907 break;
6908
6909 case INTEL_SANDYBRIDGE:
6910 case INTEL_SANDYBRIDGE_X:
6911 x86_add_quirk(intel_sandybridge_quirk);
6912 x86_add_quirk(intel_ht_bug);
6913 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6914 sizeof(hw_cache_event_ids));
6915 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6916 sizeof(hw_cache_extra_regs));
6917
6918 intel_pmu_lbr_init_snb();
6919
6920 x86_pmu.event_constraints = intel_snb_event_constraints;
6921 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
6922 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
6923 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X)
6924 x86_pmu.extra_regs = intel_snbep_extra_regs;
6925 else
6926 x86_pmu.extra_regs = intel_snb_extra_regs;
6927
6928
6929 /* all extra regs are per-cpu when HT is on */
6930 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6931 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6932
6933 td_attr = snb_events_attrs;
6934 mem_attr = snb_mem_events_attrs;
6935
6936 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6937 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6938 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6939 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
6940 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6941 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
6942
6943 extra_attr = nhm_format_attr;
6944
6945 pr_cont("SandyBridge events, ");
6946 name = "sandybridge";
6947 break;
6948
6949 case INTEL_IVYBRIDGE:
6950 case INTEL_IVYBRIDGE_X:
6951 x86_add_quirk(intel_ht_bug);
6952 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6953 sizeof(hw_cache_event_ids));
6954 /* dTLB-load-misses on IVB is different than SNB */
6955 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
6956
6957 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6958 sizeof(hw_cache_extra_regs));
6959
6960 intel_pmu_lbr_init_snb();
6961
6962 x86_pmu.event_constraints = intel_ivb_event_constraints;
6963 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
6964 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6965 x86_pmu.pebs_prec_dist = true;
6966 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X)
6967 x86_pmu.extra_regs = intel_snbep_extra_regs;
6968 else
6969 x86_pmu.extra_regs = intel_snb_extra_regs;
6970 /* all extra regs are per-cpu when HT is on */
6971 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6972 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6973
6974 td_attr = snb_events_attrs;
6975 mem_attr = snb_mem_events_attrs;
6976
6977 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6978 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6979 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6980
6981 extra_attr = nhm_format_attr;
6982
6983 pr_cont("IvyBridge events, ");
6984 name = "ivybridge";
6985 break;
6986
6987
6988 case INTEL_HASWELL:
6989 case INTEL_HASWELL_X:
6990 case INTEL_HASWELL_L:
6991 case INTEL_HASWELL_G:
6992 x86_add_quirk(intel_ht_bug);
6993 x86_add_quirk(intel_pebs_isolation_quirk);
6994 x86_pmu.late_ack = true;
6995 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6996 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6997
6998 intel_pmu_lbr_init_hsw();
6999
7000 x86_pmu.event_constraints = intel_hsw_event_constraints;
7001 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
7002 x86_pmu.extra_regs = intel_snbep_extra_regs;
7003 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
7004 x86_pmu.pebs_prec_dist = true;
7005 /* all extra regs are per-cpu when HT is on */
7006 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7007 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7008
7009 x86_pmu.hw_config = hsw_hw_config;
7010 x86_pmu.get_event_constraints = hsw_get_event_constraints;
7011 x86_pmu.limit_period = hsw_limit_period;
7012 x86_pmu.lbr_double_abort = true;
7013 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7014 hsw_format_attr : nhm_format_attr;
7015 td_attr = hsw_events_attrs;
7016 mem_attr = hsw_mem_events_attrs;
7017 tsx_attr = hsw_tsx_events_attrs;
7018 pr_cont("Haswell events, ");
7019 name = "haswell";
7020 break;
7021
7022 case INTEL_BROADWELL:
7023 case INTEL_BROADWELL_D:
7024 case INTEL_BROADWELL_G:
7025 case INTEL_BROADWELL_X:
7026 x86_add_quirk(intel_pebs_isolation_quirk);
7027 x86_pmu.late_ack = true;
7028 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7029 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7030
7031 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
7032 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
7033 BDW_L3_MISS|HSW_SNOOP_DRAM;
7034 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
7035 HSW_SNOOP_DRAM;
7036 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
7037 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
7038 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
7039 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
7040
7041 intel_pmu_lbr_init_hsw();
7042
7043 x86_pmu.event_constraints = intel_bdw_event_constraints;
7044 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
7045 x86_pmu.extra_regs = intel_snbep_extra_regs;
7046 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
7047 x86_pmu.pebs_prec_dist = true;
7048 /* all extra regs are per-cpu when HT is on */
7049 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7050 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7051
7052 x86_pmu.hw_config = hsw_hw_config;
7053 x86_pmu.get_event_constraints = hsw_get_event_constraints;
7054 x86_pmu.limit_period = bdw_limit_period;
7055 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7056 hsw_format_attr : nhm_format_attr;
7057 td_attr = hsw_events_attrs;
7058 mem_attr = hsw_mem_events_attrs;
7059 tsx_attr = hsw_tsx_events_attrs;
7060 pr_cont("Broadwell events, ");
7061 name = "broadwell";
7062 break;
7063
7064 case INTEL_XEON_PHI_KNL:
7065 case INTEL_XEON_PHI_KNM:
7066 memcpy(hw_cache_event_ids,
7067 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7068 memcpy(hw_cache_extra_regs,
7069 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7070 intel_pmu_lbr_init_knl();
7071
7072 x86_pmu.event_constraints = intel_slm_event_constraints;
7073 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
7074 x86_pmu.extra_regs = intel_knl_extra_regs;
7075
7076 /* all extra regs are per-cpu when HT is on */
7077 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7078 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7079 extra_attr = slm_format_attr;
7080 pr_cont("Knights Landing/Mill events, ");
7081 name = "knights-landing";
7082 break;
7083
7084 case INTEL_SKYLAKE_X:
7085 pmem = true;
7086 fallthrough;
7087 case INTEL_SKYLAKE_L:
7088 case INTEL_SKYLAKE:
7089 case INTEL_KABYLAKE_L:
7090 case INTEL_KABYLAKE:
7091 case INTEL_COMETLAKE_L:
7092 case INTEL_COMETLAKE:
7093 x86_add_quirk(intel_pebs_isolation_quirk);
7094 x86_pmu.late_ack = true;
7095 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7096 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7097 intel_pmu_lbr_init_skl();
7098
7099 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
7100 event_attr_td_recovery_bubbles.event_str_noht =
7101 "event=0xd,umask=0x1,cmask=1";
7102 event_attr_td_recovery_bubbles.event_str_ht =
7103 "event=0xd,umask=0x1,cmask=1,any=1";
7104
7105 x86_pmu.event_constraints = intel_skl_event_constraints;
7106 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
7107 x86_pmu.extra_regs = intel_skl_extra_regs;
7108 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
7109 x86_pmu.pebs_prec_dist = true;
7110 /* all extra regs are per-cpu when HT is on */
7111 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7112 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7113
7114 x86_pmu.hw_config = hsw_hw_config;
7115 x86_pmu.get_event_constraints = hsw_get_event_constraints;
7116 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7117 hsw_format_attr : nhm_format_attr;
7118 extra_skl_attr = skl_format_attr;
7119 td_attr = hsw_events_attrs;
7120 mem_attr = hsw_mem_events_attrs;
7121 tsx_attr = hsw_tsx_events_attrs;
7122 intel_pmu_pebs_data_source_skl(pmem);
7123
7124 /*
7125 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
7126 * TSX force abort hooks are not required on these systems. Only deploy
7127 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
7128 */
7129 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
7130 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
7131 x86_pmu.flags |= PMU_FL_TFA;
7132 x86_pmu.get_event_constraints = tfa_get_event_constraints;
7133 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
7134 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
7135 }
7136
7137 pr_cont("Skylake events, ");
7138 name = "skylake";
7139 break;
7140
7141 case INTEL_ICELAKE_X:
7142 case INTEL_ICELAKE_D:
7143 x86_pmu.pebs_ept = 1;
7144 pmem = true;
7145 fallthrough;
7146 case INTEL_ICELAKE_L:
7147 case INTEL_ICELAKE:
7148 case INTEL_TIGERLAKE_L:
7149 case INTEL_TIGERLAKE:
7150 case INTEL_ROCKETLAKE:
7151 x86_pmu.late_ack = true;
7152 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7153 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7154 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7155 intel_pmu_lbr_init_skl();
7156
7157 x86_pmu.event_constraints = intel_icl_event_constraints;
7158 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
7159 x86_pmu.extra_regs = intel_icl_extra_regs;
7160 x86_pmu.pebs_aliases = NULL;
7161 x86_pmu.pebs_prec_dist = true;
7162 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7163 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7164
7165 x86_pmu.hw_config = hsw_hw_config;
7166 x86_pmu.get_event_constraints = icl_get_event_constraints;
7167 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7168 hsw_format_attr : nhm_format_attr;
7169 extra_skl_attr = skl_format_attr;
7170 mem_attr = icl_events_attrs;
7171 td_attr = icl_td_events_attrs;
7172 tsx_attr = icl_tsx_events_attrs;
7173 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
7174 x86_pmu.lbr_pt_coexist = true;
7175 intel_pmu_pebs_data_source_skl(pmem);
7176 x86_pmu.num_topdown_events = 4;
7177 static_call_update(intel_pmu_update_topdown_event,
7178 &icl_update_topdown_event);
7179 static_call_update(intel_pmu_set_topdown_event_period,
7180 &icl_set_topdown_event_period);
7181 pr_cont("Icelake events, ");
7182 name = "icelake";
7183 break;
7184
7185 case INTEL_SAPPHIRERAPIDS_X:
7186 case INTEL_EMERALDRAPIDS_X:
7187 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
7188 x86_pmu.extra_regs = intel_glc_extra_regs;
7189 pr_cont("Sapphire Rapids events, ");
7190 name = "sapphire_rapids";
7191 goto glc_common;
7192
7193 case INTEL_GRANITERAPIDS_X:
7194 case INTEL_GRANITERAPIDS_D:
7195 x86_pmu.extra_regs = intel_rwc_extra_regs;
7196 pr_cont("Granite Rapids events, ");
7197 name = "granite_rapids";
7198
7199 glc_common:
7200 intel_pmu_init_glc(NULL);
7201 x86_pmu.pebs_ept = 1;
7202 x86_pmu.hw_config = hsw_hw_config;
7203 x86_pmu.get_event_constraints = glc_get_event_constraints;
7204 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7205 hsw_format_attr : nhm_format_attr;
7206 extra_skl_attr = skl_format_attr;
7207 mem_attr = glc_events_attrs;
7208 td_attr = glc_td_events_attrs;
7209 tsx_attr = glc_tsx_events_attrs;
7210 intel_pmu_pebs_data_source_skl(true);
7211 break;
7212
7213 case INTEL_ALDERLAKE:
7214 case INTEL_ALDERLAKE_L:
7215 case INTEL_RAPTORLAKE:
7216 case INTEL_RAPTORLAKE_P:
7217 case INTEL_RAPTORLAKE_S:
7218 /*
7219 * Alder Lake has 2 types of CPU, core and atom.
7220 *
7221 * Initialize the common PerfMon capabilities here.
7222 */
7223 intel_pmu_init_hybrid(hybrid_big_small);
7224
7225 x86_pmu.pebs_latency_data = grt_latency_data;
7226 x86_pmu.get_event_constraints = adl_get_event_constraints;
7227 x86_pmu.hw_config = adl_hw_config;
7228 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
7229
7230 td_attr = adl_hybrid_events_attrs;
7231 mem_attr = adl_hybrid_mem_attrs;
7232 tsx_attr = adl_hybrid_tsx_attrs;
7233 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7234 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
7235
7236 /* Initialize big core specific PerfMon capabilities.*/
7237 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7238 intel_pmu_init_glc(&pmu->pmu);
7239 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
7240 pmu->cntr_mask64 <<= 2;
7241 pmu->cntr_mask64 |= 0x3;
7242 pmu->fixed_cntr_mask64 <<= 1;
7243 pmu->fixed_cntr_mask64 |= 0x1;
7244 } else {
7245 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7246 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7247 }
7248
7249 /*
7250 * Quirk: For some Alder Lake machine, when all E-cores are disabled in
7251 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
7252 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
7253 * mistakenly add extra counters for P-cores. Correct the number of
7254 * counters here.
7255 */
7256 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) {
7257 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7258 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7259 }
7260
7261 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
7262 pmu->unconstrained = (struct event_constraint)
7263 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
7264 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
7265
7266 pmu->extra_regs = intel_glc_extra_regs;
7267
7268 /* Initialize Atom core specific PerfMon capabilities.*/
7269 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7270 intel_pmu_init_grt(&pmu->pmu);
7271
7272 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
7273 intel_pmu_pebs_data_source_adl();
7274 pr_cont("Alderlake Hybrid events, ");
7275 name = "alderlake_hybrid";
7276 break;
7277
7278 case INTEL_METEORLAKE:
7279 case INTEL_METEORLAKE_L:
7280 case INTEL_ARROWLAKE_U:
7281 intel_pmu_init_hybrid(hybrid_big_small);
7282
7283 x86_pmu.pebs_latency_data = cmt_latency_data;
7284 x86_pmu.get_event_constraints = mtl_get_event_constraints;
7285 x86_pmu.hw_config = adl_hw_config;
7286
7287 td_attr = adl_hybrid_events_attrs;
7288 mem_attr = mtl_hybrid_mem_attrs;
7289 tsx_attr = adl_hybrid_tsx_attrs;
7290 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7291 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7292
7293 /* Initialize big core specific PerfMon capabilities.*/
7294 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7295 intel_pmu_init_glc(&pmu->pmu);
7296 pmu->extra_regs = intel_rwc_extra_regs;
7297
7298 /* Initialize Atom core specific PerfMon capabilities.*/
7299 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7300 intel_pmu_init_grt(&pmu->pmu);
7301 pmu->extra_regs = intel_cmt_extra_regs;
7302
7303 intel_pmu_pebs_data_source_mtl();
7304 pr_cont("Meteorlake Hybrid events, ");
7305 name = "meteorlake_hybrid";
7306 break;
7307
7308 case INTEL_LUNARLAKE_M:
7309 case INTEL_ARROWLAKE:
7310 intel_pmu_init_hybrid(hybrid_big_small);
7311
7312 x86_pmu.pebs_latency_data = lnl_latency_data;
7313 x86_pmu.get_event_constraints = mtl_get_event_constraints;
7314 x86_pmu.hw_config = adl_hw_config;
7315
7316 td_attr = lnl_hybrid_events_attrs;
7317 mem_attr = mtl_hybrid_mem_attrs;
7318 tsx_attr = adl_hybrid_tsx_attrs;
7319 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7320 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7321
7322 /* Initialize big core specific PerfMon capabilities.*/
7323 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7324 intel_pmu_init_lnc(&pmu->pmu);
7325
7326 /* Initialize Atom core specific PerfMon capabilities.*/
7327 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7328 intel_pmu_init_skt(&pmu->pmu);
7329
7330 intel_pmu_pebs_data_source_lnl();
7331 pr_cont("Lunarlake Hybrid events, ");
7332 name = "lunarlake_hybrid";
7333 break;
7334
7335 case INTEL_ARROWLAKE_H:
7336 intel_pmu_init_hybrid(hybrid_big_small_tiny);
7337
7338 x86_pmu.pebs_latency_data = arl_h_latency_data;
7339 x86_pmu.get_event_constraints = arl_h_get_event_constraints;
7340 x86_pmu.hw_config = arl_h_hw_config;
7341
7342 td_attr = arl_h_hybrid_events_attrs;
7343 mem_attr = arl_h_hybrid_mem_attrs;
7344 tsx_attr = adl_hybrid_tsx_attrs;
7345 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7346 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7347
7348 /* Initialize big core specific PerfMon capabilities. */
7349 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7350 intel_pmu_init_lnc(&pmu->pmu);
7351
7352 /* Initialize Atom core specific PerfMon capabilities. */
7353 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7354 intel_pmu_init_skt(&pmu->pmu);
7355
7356 /* Initialize Lower Power Atom specific PerfMon capabilities. */
7357 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX];
7358 intel_pmu_init_grt(&pmu->pmu);
7359 pmu->extra_regs = intel_cmt_extra_regs;
7360
7361 intel_pmu_pebs_data_source_arl_h();
7362 pr_cont("ArrowLake-H Hybrid events, ");
7363 name = "arrowlake_h_hybrid";
7364 break;
7365
7366 default:
7367 switch (x86_pmu.version) {
7368 case 1:
7369 x86_pmu.event_constraints = intel_v1_event_constraints;
7370 pr_cont("generic architected perfmon v1, ");
7371 name = "generic_arch_v1";
7372 break;
7373 case 2:
7374 case 3:
7375 case 4:
7376 /*
7377 * default constraints for v2 and up
7378 */
7379 x86_pmu.event_constraints = intel_gen_event_constraints;
7380 pr_cont("generic architected perfmon, ");
7381 name = "generic_arch_v2+";
7382 break;
7383 default:
7384 /*
7385 * The default constraints for v5 and up can support up to
7386 * 16 fixed counters. For the fixed counters 4 and later,
7387 * the pseudo-encoding is applied.
7388 * The constraints may be cut according to the CPUID enumeration
7389 * by inserting the EVENT_CONSTRAINT_END.
7390 */
7391 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED)
7392 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
7393 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1;
7394 x86_pmu.event_constraints = intel_v5_gen_event_constraints;
7395 pr_cont("generic architected perfmon, ");
7396 name = "generic_arch_v5+";
7397 break;
7398 }
7399 }
7400
7401 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
7402
7403 if (!is_hybrid()) {
7404 group_events_td.attrs = td_attr;
7405 group_events_mem.attrs = mem_attr;
7406 group_events_tsx.attrs = tsx_attr;
7407 group_format_extra.attrs = extra_attr;
7408 group_format_extra_skl.attrs = extra_skl_attr;
7409
7410 x86_pmu.attr_update = attr_update;
7411 } else {
7412 hybrid_group_events_td.attrs = td_attr;
7413 hybrid_group_events_mem.attrs = mem_attr;
7414 hybrid_group_events_tsx.attrs = tsx_attr;
7415 hybrid_group_format_extra.attrs = extra_attr;
7416
7417 x86_pmu.attr_update = hybrid_attr_update;
7418 }
7419
7420 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64,
7421 &x86_pmu.fixed_cntr_mask64,
7422 &x86_pmu.intel_ctrl);
7423
7424 /* AnyThread may be deprecated on arch perfmon v5 or later */
7425 if (x86_pmu.intel_cap.anythread_deprecated)
7426 x86_pmu.format_attrs = intel_arch_formats_attr;
7427
7428 intel_pmu_check_event_constraints(x86_pmu.event_constraints,
7429 x86_pmu.cntr_mask64,
7430 x86_pmu.fixed_cntr_mask64,
7431 x86_pmu.intel_ctrl);
7432 /*
7433 * Access LBR MSR may cause #GP under certain circumstances.
7434 * Check all LBR MSR here.
7435 * Disable LBR access if any LBR MSRs can not be accessed.
7436 */
7437 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
7438 x86_pmu.lbr_nr = 0;
7439 for (i = 0; i < x86_pmu.lbr_nr; i++) {
7440 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
7441 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
7442 x86_pmu.lbr_nr = 0;
7443 }
7444
7445 if (x86_pmu.lbr_nr) {
7446 intel_pmu_lbr_init();
7447
7448 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
7449
7450 /* only support branch_stack snapshot for perfmon >= v2 */
7451 if (x86_pmu.disable_all == intel_pmu_disable_all) {
7452 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) {
7453 static_call_update(perf_snapshot_branch_stack,
7454 intel_pmu_snapshot_arch_branch_stack);
7455 } else {
7456 static_call_update(perf_snapshot_branch_stack,
7457 intel_pmu_snapshot_branch_stack);
7458 }
7459 }
7460 }
7461
7462 intel_pmu_check_extra_regs(x86_pmu.extra_regs);
7463
7464 /* Support full width counters using alternative MSR range */
7465 if (x86_pmu.intel_cap.full_width_write) {
7466 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
7467 x86_pmu.perfctr = MSR_IA32_PMC0;
7468 pr_cont("full-width counters, ");
7469 }
7470
7471 /* Support V6+ MSR Aliasing */
7472 if (x86_pmu.version >= 6) {
7473 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR;
7474 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A;
7475 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR;
7476 x86_pmu.addr_offset = intel_pmu_v6_addr_offset;
7477 }
7478
7479 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
7480 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
7481
7482 if (x86_pmu.intel_cap.pebs_timing_info)
7483 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;
7484
7485 intel_aux_output_init();
7486
7487 return 0;
7488 }
7489
7490 /*
7491 * HT bug: phase 2 init
7492 * Called once we have valid topology information to check
7493 * whether or not HT is enabled
7494 * If HT is off, then we disable the workaround
7495 */
fixup_ht_bug(void)7496 static __init int fixup_ht_bug(void)
7497 {
7498 int c;
7499 /*
7500 * problem not present on this CPU model, nothing to do
7501 */
7502 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
7503 return 0;
7504
7505 if (topology_max_smt_threads() > 1) {
7506 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
7507 return 0;
7508 }
7509
7510 cpus_read_lock();
7511
7512 hardlockup_detector_perf_stop();
7513
7514 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
7515
7516 x86_pmu.start_scheduling = NULL;
7517 x86_pmu.commit_scheduling = NULL;
7518 x86_pmu.stop_scheduling = NULL;
7519
7520 hardlockup_detector_perf_restart();
7521
7522 for_each_online_cpu(c)
7523 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
7524
7525 cpus_read_unlock();
7526 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
7527 return 0;
7528 }
7529 subsys_initcall(fixup_ht_bug)
7530