1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_INTEL_FAMILY_H 3 #define _ASM_X86_INTEL_FAMILY_H 4 5 /* 6 * "Big Core" Processors (Branded as Core, Xeon, etc...) 7 * 8 * While adding a new CPUID for a new microarchitecture, add a new 9 * group to keep logically sorted out in chronological order. Within 10 * that group keep the CPUID for the variants sorted by model number. 11 * 12 * The defined symbol names have the following form: 13 * INTEL_{OPTFAMILY}_{MICROARCH}{OPTDIFF} 14 * where: 15 * OPTFAMILY Describes the family of CPUs that this belongs to. Default 16 * is assumed to be "_CORE" (and should be omitted). Other values 17 * currently in use are _ATOM and _XEON_PHI 18 * MICROARCH Is the code name for the micro-architecture for this core. 19 * N.B. Not the platform name. 20 * OPTDIFF If needed, a short string to differentiate by market segment. 21 * 22 * Common OPTDIFFs: 23 * 24 * - regular client parts 25 * _L - regular mobile parts 26 * _G - parts with extra graphics on 27 * _X - regular server parts 28 * _D - micro server parts 29 * _N,_P - other mobile parts 30 * _H - premium mobile parts 31 * _S - other client parts 32 * _R - ruggedized for harsh environment 33 * 34 * Historical OPTDIFFs: 35 * 36 * _EP - 2 socket server parts 37 * _EX - 4+ socket server parts 38 * 39 * The #define line may optionally include a comment including platform or core 40 * names. An exception is made for skylake/kabylake where steppings seem to have gotten 41 * their own names :-( 42 */ 43 44 #define IFM(_fam, _model) VFM_MAKE(X86_VENDOR_INTEL, _fam, _model) 45 46 /* Wildcard match so X86_MATCH_VFM(ANY) works */ 47 #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) 48 49 /* Family 5 */ 50 #define INTEL_FAM5_START IFM(5, 0x00) /* Notational marker, also P5 A-step */ 51 #define INTEL_PENTIUM_75 IFM(5, 0x02) /* P54C */ 52 #define INTEL_PENTIUM_MMX IFM(5, 0x04) /* P55C */ 53 #define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */ 54 55 /* Family 6, 18, 19 */ 56 #define INTEL_PENTIUM_PRO IFM(6, 0x01) 57 #define INTEL_PENTIUM_II_KLAMATH IFM(6, 0x03) 58 #define INTEL_PENTIUM_III_DESCHUTES IFM(6, 0x05) 59 #define INTEL_PENTIUM_III_TUALATIN IFM(6, 0x0B) 60 #define INTEL_PENTIUM_M_DOTHAN IFM(6, 0x0D) 61 62 #define INTEL_CORE_YONAH IFM(6, 0x0E) 63 64 #define INTEL_CORE2_MEROM IFM(6, 0x0F) 65 #define INTEL_CORE2_MEROM_L IFM(6, 0x16) 66 #define INTEL_CORE2_PENRYN IFM(6, 0x17) 67 #define INTEL_CORE2_DUNNINGTON IFM(6, 0x1D) 68 69 #define INTEL_NEHALEM IFM(6, 0x1E) 70 #define INTEL_NEHALEM_G IFM(6, 0x1F) /* Auburndale / Havendale */ 71 #define INTEL_NEHALEM_EP IFM(6, 0x1A) 72 #define INTEL_NEHALEM_EX IFM(6, 0x2E) 73 74 #define INTEL_WESTMERE IFM(6, 0x25) 75 #define INTEL_WESTMERE_EP IFM(6, 0x2C) 76 #define INTEL_WESTMERE_EX IFM(6, 0x2F) 77 78 #define INTEL_SANDYBRIDGE IFM(6, 0x2A) 79 #define INTEL_SANDYBRIDGE_X IFM(6, 0x2D) 80 #define INTEL_IVYBRIDGE IFM(6, 0x3A) 81 #define INTEL_IVYBRIDGE_X IFM(6, 0x3E) 82 83 #define INTEL_HASWELL IFM(6, 0x3C) 84 #define INTEL_HASWELL_X IFM(6, 0x3F) 85 #define INTEL_HASWELL_L IFM(6, 0x45) 86 #define INTEL_HASWELL_G IFM(6, 0x46) 87 88 #define INTEL_BROADWELL IFM(6, 0x3D) 89 #define INTEL_BROADWELL_G IFM(6, 0x47) 90 #define INTEL_BROADWELL_X IFM(6, 0x4F) 91 #define INTEL_BROADWELL_D IFM(6, 0x56) 92 93 #define INTEL_SKYLAKE_L IFM(6, 0x4E) /* Sky Lake */ 94 #define INTEL_SKYLAKE IFM(6, 0x5E) /* Sky Lake */ 95 #define INTEL_SKYLAKE_X IFM(6, 0x55) /* Sky Lake */ 96 /* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */ 97 /* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */ 98 99 #define INTEL_KABYLAKE_L IFM(6, 0x8E) /* Sky Lake */ 100 /* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */ 101 /* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */ 102 /* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */ 103 104 #define INTEL_KABYLAKE IFM(6, 0x9E) /* Sky Lake */ 105 /* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */ 106 107 #define INTEL_COMETLAKE IFM(6, 0xA5) /* Sky Lake */ 108 #define INTEL_COMETLAKE_L IFM(6, 0xA6) /* Sky Lake */ 109 110 #define INTEL_CANNONLAKE_L IFM(6, 0x66) /* Palm Cove */ 111 112 #define INTEL_ICELAKE_X IFM(6, 0x6A) /* Sunny Cove */ 113 #define INTEL_ICELAKE_D IFM(6, 0x6C) /* Sunny Cove */ 114 #define INTEL_ICELAKE IFM(6, 0x7D) /* Sunny Cove */ 115 #define INTEL_ICELAKE_L IFM(6, 0x7E) /* Sunny Cove */ 116 #define INTEL_ICELAKE_NNPI IFM(6, 0x9D) /* Sunny Cove */ 117 118 #define INTEL_ROCKETLAKE IFM(6, 0xA7) /* Cypress Cove */ 119 120 #define INTEL_TIGERLAKE_L IFM(6, 0x8C) /* Willow Cove */ 121 #define INTEL_TIGERLAKE IFM(6, 0x8D) /* Willow Cove */ 122 123 #define INTEL_SAPPHIRERAPIDS_X IFM(6, 0x8F) /* Golden Cove */ 124 125 #define INTEL_EMERALDRAPIDS_X IFM(6, 0xCF) /* Raptor Cove */ 126 127 #define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) /* Redwood Cove */ 128 #define INTEL_GRANITERAPIDS_D IFM(6, 0xAE) 129 130 #define INTEL_DIAMONDRAPIDS_X IFM(19, 0x01) /* Panther Cove */ 131 132 #define INTEL_BARTLETTLAKE IFM(6, 0xD7) /* Raptor Cove */ 133 134 /* "Hybrid" Processors (P-Core/E-Core) */ 135 136 #define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */ 137 138 #define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */ 139 #define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */ 140 141 #define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */ 142 #define INTEL_RAPTORLAKE_P IFM(6, 0xBA) 143 #define INTEL_RAPTORLAKE_S IFM(6, 0xBF) 144 145 #define INTEL_METEORLAKE IFM(6, 0xAC) /* Redwood Cove / Crestmont */ 146 #define INTEL_METEORLAKE_L IFM(6, 0xAA) 147 148 #define INTEL_ARROWLAKE_H IFM(6, 0xC5) /* Lion Cove / Skymont */ 149 #define INTEL_ARROWLAKE IFM(6, 0xC6) 150 #define INTEL_ARROWLAKE_U IFM(6, 0xB5) 151 152 #define INTEL_LUNARLAKE_M IFM(6, 0xBD) /* Lion Cove / Skymont */ 153 154 #define INTEL_PANTHERLAKE_L IFM(6, 0xCC) /* Cougar Cove / Darkmont */ 155 #define INTEL_PANTHERLAKE_R IFM(6, 0xE5) /* Cougar Cove / Darkmont */ 156 157 #define INTEL_WILDCATLAKE_L IFM(6, 0xD5) 158 159 #define INTEL_NOVALAKE IFM(18, 0x01) /* Coyote Cove / Arctic Wolf */ 160 #define INTEL_NOVALAKE_L IFM(18, 0x03) /* Coyote Cove / Arctic Wolf */ 161 162 /* "Small Core" Processors (Atom/E-Core) */ 163 164 #define INTEL_ATOM_BONNELL IFM(6, 0x1C) /* Diamondville, Pineview */ 165 #define INTEL_ATOM_BONNELL_MID IFM(6, 0x26) /* Silverthorne, Lincroft */ 166 167 #define INTEL_ATOM_SALTWELL IFM(6, 0x36) /* Cedarview */ 168 #define INTEL_ATOM_SALTWELL_MID IFM(6, 0x27) /* Penwell */ 169 #define INTEL_ATOM_SALTWELL_TABLET IFM(6, 0x35) /* Cloverview */ 170 171 #define INTEL_ATOM_SILVERMONT IFM(6, 0x37) /* Bay Trail, Valleyview */ 172 #define INTEL_ATOM_SILVERMONT_D IFM(6, 0x4D) /* Avaton, Rangely */ 173 #define INTEL_ATOM_SILVERMONT_MID IFM(6, 0x4A) /* Merriefield */ 174 #define INTEL_ATOM_SILVERMONT_MID2 IFM(6, 0x5A) /* Anniedale */ 175 176 #define INTEL_ATOM_AIRMONT IFM(6, 0x4C) /* Cherry Trail, Braswell */ 177 #define INTEL_ATOM_AIRMONT_NP IFM(6, 0x75) /* Lightning Mountain */ 178 179 #define INTEL_ATOM_GOLDMONT IFM(6, 0x5C) /* Apollo Lake */ 180 #define INTEL_ATOM_GOLDMONT_D IFM(6, 0x5F) /* Denverton */ 181 182 /* Note: the micro-architecture is "Goldmont Plus" */ 183 #define INTEL_ATOM_GOLDMONT_PLUS IFM(6, 0x7A) /* Gemini Lake */ 184 185 #define INTEL_ATOM_TREMONT_D IFM(6, 0x86) /* Jacobsville */ 186 #define INTEL_ATOM_TREMONT IFM(6, 0x96) /* Elkhart Lake */ 187 #define INTEL_ATOM_TREMONT_L IFM(6, 0x9C) /* Jasper Lake */ 188 189 #define INTEL_ATOM_GRACEMONT IFM(6, 0xBE) /* Alderlake N */ 190 191 #define INTEL_ATOM_CRESTMONT_X IFM(6, 0xAF) /* Sierra Forest */ 192 #define INTEL_ATOM_CRESTMONT IFM(6, 0xB6) /* Grand Ridge */ 193 194 #define INTEL_ATOM_DARKMONT_X IFM(6, 0xDD) /* Clearwater Forest */ 195 196 /* Xeon Phi */ 197 198 #define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */ 199 #define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */ 200 201 /* Notational marker denoting the last Family 6 model */ 202 #define INTEL_FAM6_LAST IFM(6, 0xFF) 203 204 /* Family 15 - NetBurst */ 205 #define INTEL_P4_WILLAMETTE IFM(15, 0x01) /* Also Xeon Foster */ 206 #define INTEL_P4_PRESCOTT IFM(15, 0x03) 207 #define INTEL_P4_PRESCOTT_2M IFM(15, 0x04) 208 #define INTEL_P4_CEDARMILL IFM(15, 0x06) /* Also Xeon Dempsey */ 209 210 /* 211 * Intel CPU core types 212 * 213 * CPUID.1AH.EAX[31:0] uniquely identifies the microarchitecture 214 * of the core. Bits 31-24 indicates its core type (Core or Atom) 215 * and Bits [23:0] indicates the native model ID of the core. 216 * Core type and native model ID are defined in below enumerations. 217 */ 218 enum intel_cpu_type { 219 INTEL_CPU_TYPE_UNKNOWN, 220 INTEL_CPU_TYPE_ATOM = 0x20, 221 INTEL_CPU_TYPE_CORE = 0x40, 222 }; 223 224 enum intel_native_id { 225 INTEL_ATOM_CMT_NATIVE_ID = 0x2, /* Crestmont */ 226 INTEL_ATOM_SKT_NATIVE_ID = 0x3, /* Skymont */ 227 }; 228 229 #endif /* _ASM_X86_INTEL_FAMILY_H */ 230