xref: /linux/drivers/gpu/drm/i915/display/intel_dp_link_training.c (revision 1d9d3bc0dad332361e1363df50b058634dcd232d)

/*
 * Copyright © 2008-2015 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#include <kunit/visibility.h>

#include <linux/debugfs.h>
#include <linux/iopoll.h>

#include <drm/display/drm_dp_helper.h>
#include <drm/drm_print.h>

#include "intel_display.h"
#include "intel_display_core.h"
#include "intel_display_jiffies.h"
#include "intel_display_types.h"
#include "intel_display_utils.h"
#include "intel_dp.h"
#include "intel_dp_link_caps.h"
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
#include "intel_encoder.h"
#include "intel_hdmi.h"
#include "intel_hotplug.h"
#include "intel_modeset_lock.h"
#include "intel_panel.h"
#include "intel_psr.h"

/**
 * DOC: DisplayPort link training
 *
 * This documents the Intel DisplayPort link training implementation and
 * its internal interfaces, with a current focus on link recovery.
 *
 * Documentation of the full link training procedure is not yet included.
 *
 * The Intel DP link recovery logic governs how the driver reacts to
 * link training failures and to links that degrade asynchronously
 * after a previously successful training. Recovery is first attempted
 * via automatic retraining (``autoretrain``) and, when that is no
 * longer possible, by selecting fallback link configurations and
 * notifying userspace to recover the link via a modeset.
 *
 * Recovery sequence and userspace notification
 * --------------------------------------------
 *
 * After the first link training failure following initialization or a
 * previously successful training, recovery is first attempted by the
 * driver via automatic retraining, without userspace involvement.
 * During this phase, a given link configuration is attempted twice
 * before being abandoned: after the initial link training failure, an
 * automatic retraining modeset is performed with the same link
 * parameters, constituting the second attempt.
 *
 * Once automatic retraining is no longer possible, recovery is delegated
 * to userspace, which must select a new modeset configuration, as the
 * kernel must not do so. From this point onwards, each link configuration
 * may be attempted only once as userspace iterates through alternative
 * configurations. A successful link training restores the automatic
 * retraining model for subsequent failures.
 *
 * The failure of the last automatic retraining attempt is reported to
 * userspace, and from that point onward the driver notifies userspace of
 * each subsequent failure. This allows userspace to both initiate
 * recovery via modesets and observe the outcome of those recovery
 * attempts, even when no further fallback configurations remain.
 *
 * Link training failures are always reported to userspace, even when they
 * result from a kernel-internal modeset. Such modesets only re-apply the
 * existing userspace-provided state and must not modify it. A failure
 * triggered by such a modeset is therefore treated the same as a link
 * degradation after a previously successful training, and recovery is
 * handled by userspace in place of the kernel caller.
 *
 * Contexts
 * --------
 *
 * The following execution contexts (A/B/C) describe how the different
 * recovery states are reached but are not themselves implementation
 * states. The actual state machine is defined by &enum
 * intel_dp_link_training_recovery_state.
 *
 * A. Modeset context:
 *
 *   Triggered by:
 *     - link training during a modeset, or
 *     - via the "i915_dp_force_link_training_failure" debugfs entry,
 *       forcing this path by emulating a link training failure.
 *
 *   Transitions:
 *     - A1 Link training succeeds.
 *
 *       A link check work to recover any degraded link is scheduled
 *       (and handled if needed in context B).
 *
 *       State -> %INTEL_DP_LINK_RECOVERY_IDLE.
 *
 *     - A2 First link training fails after initialization or a previously
 *       successful link training.
 *
 *       An automatic retraining work is scheduled (and handled in
 *       context B) with the same link parameters with which the link
 *       training failed.
 *
 *       State -> %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_PENDING.
 *
 *     - A3 Link training fails again after A2 or A3.
 *
 *       Through fallback selection, the driver attempts to restrict the
 *       allowed link configurations for subsequent modesets. This may
 *       be done either by lowering global limits (rate/lane caps), or by
 *       disabling only the currently failing configuration while leaving
 *       all other configurations allowed, even if they use higher rate or
 *       lane count.
 *
 *       (The current implementation may still apply parameter capping as
 *       a coarse fallback selection mechanism. This is transitional and is
 *       expected to be replaced by a scheme that disables only the failing
 *       configuration, rather than removing configurations that have not
 *       been observed to fail and may still train successfully.)
 *
 *       This case may repeat in a loop:
 *           %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED ->
 *           %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED
 *
 *       via repeated A3a -> A3a transitions until the configuration fallback
 *       space is exhausted, reaching the A3b terminal case.
 *
 *       - A3a Fallback selection succeeds.
 *
 *         Userspace is notified to retry the modeset.
 *
 *         State -> %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED.
 *
 *       - A3b Fallback selection fails.
 *
 *         Userspace is notified of the failure and may continue recovery
 *         by retrying the modeset with the remaining allowed link
 *         configuration.
 *
 *         State -> %INTEL_DP_LINK_RECOVERY_NO_FALLBACK.
 *
 * B. Automatic retraining context:
 *
 *   Triggered by:
 *     - after a successful link training in context A1 followed by
 *       asynchronous link degradation, or
 *     - after the first failed link training attempt in context A2, or
 *     - via the "i915_dp_force_link_retrain" debugfs entry, which may
 *       bypass normal gating and force this path.
 *
 *   Transitions:
 *     - B1 ``Autoretrain`` modeset check and link training succeeds.
 *
 *       The case is handled as in A1, scheduling a link check work to
 *       recover any degraded link.
 *
 *       State -> %INTEL_DP_LINK_RECOVERY_IDLE.
 *
 *     - B2 ``Autoretrain`` modeset check succeeds but link training fails.
 *
 *       - B2a Previously the link degraded asynchronously (current state
 *         is %INTEL_DP_LINK_RECOVERY_IDLE).
 *
 *         This corresponds to a first failure in a new failure
 *         sequence and is handled as in A2: an automatic retraining
 *         attempt is scheduled with the same link parameters.
 *
 *         State -> %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_PENDING.
 *
 *       - B2b Previously a link training failed (current state is
 *         %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_PENDING).
 *
 *         In non-regular (debug-forced) scenarios this may also be
 *         reached from
 *         %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED or
 *         %INTEL_DP_LINK_RECOVERY_NO_FALLBACK, effectively behaving
 *         like a userspace-driven recovery attempt.
 *
 *         The failure is handled as in A3, performing a fallback selection:
 *
 *         State -> %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED (via A3a).
 *
 *         or
 *
 *         State -> %INTEL_DP_LINK_RECOVERY_NO_FALLBACK (via A3b).
 *
 *     - B3 ``Autoretrain`` modeset check fails (and hence the link training
 *       cannot be started).
 *
 *       The modeset check may fail, for example, due to external conditions
 *       such as changed shared link bandwidth, which can make previously
 *       valid modeset parameters no longer acceptable.
 *
 *       In this case, automatic retraining is disabled without selecting
 *       a fallback configuration. The driver hands recovery over to
 *       userspace without modifying the allowed configuration set, so a
 *       subsequent userspace modeset will retry with the current link
 *       configuration. Userspace is in a better position to select new
 *       modeset parameters (e.g. video mode or enabled outputs) that
 *       satisfy the updated constraints, as the driver is only allowed
 *       to retry the modeset with the existing userspace-provided modeset
 *       configuration.
 *
 *       This policy preserves the normal retry model, where a given link
 *       configuration is attempted twice in the automatic retraining
 *       flow before being abandoned: after a first link training failure,
 *       an automatic retraining modeset is performed with the same link
 *       parameters, and if its atomic check passes, the link training
 *       itself may either succeed or fail, constituting the second
 *       attempt. In this case, however, the retry modeset's atomic check
 *       failed, so no second link training attempt with those parameters
 *       was performed, and selecting a fallback would cause that
 *       configuration to be tried only once rather than twice.
 *
 *       The userspace-driven link recovery continues with subsequent
 *       userspace modesets handled in A3.
 *
 *       State -> %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED.
 *
 * C. State reset context:
 *
 *   Triggered by:
 *     - sink capability changes, or
 *     - sink disconnect/reconnect, or
 *     - system suspend/resume or power transitions where HPD
 *       handling may have been suppressed, or
 *     - successful link training.
 *
 *   Transitions:
 *     - The recovery state is reset from any of the recovery states
 *
 *       State -> %INTEL_DP_LINK_RECOVERY_IDLE.
 *
 *       After reset, the driver may re-check link status and schedule
 *       retraining if the link is found to remain degraded.
 *
 * State transition summary
 * ------------------------
 *
 * - From %INTEL_DP_LINK_RECOVERY_IDLE
 *
 *   - To %INTEL_DP_LINK_RECOVERY_IDLE
 *
 *     - | In context: B1
 *       | Action: no action
 *
 *   - To %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_PENDING
 *
 *     - | In contexts: A2, B2a
 *       | Action: queue ``autoretrain`` work
 *
 *   - To %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED
 *
 *     - | In context: B3
 *       | Action: notify userspace
 *
 * - From %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_PENDING
 *
 *   - To %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED
 *
 *     - | In contexts: A3a, B2b
 *       | Action: select fallback configurations, notify userspace
 *
 *     - | In context: B3
 *       | Action: notify userspace
 *
 *   - To %INTEL_DP_LINK_RECOVERY_NO_FALLBACK
 *
 *     - | In contexts: A3b, B2b
 *       | Action: notify userspace
 *
 * - From %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED
 *
 *   - To %INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED
 *
 *     - | In contexts: A3a, B2b
 *       | Action: select fallback configurations, notify userspace
 *
 *   - To %INTEL_DP_LINK_RECOVERY_NO_FALLBACK
 *
 *     - | In contexts: A3b, B2b
 *       | Action: notify userspace
 *
 * - From %INTEL_DP_LINK_RECOVERY_NO_FALLBACK
 *
 *   - To %INTEL_DP_LINK_RECOVERY_NO_FALLBACK
 *
 *     - | In contexts: A3b
 *       | Action: notify userspace
 *
 * - From any state
 *
 *   - To %INTEL_DP_LINK_RECOVERY_IDLE
 *
 *     - | In contexts: C
 *       | Action: no action
 *
 * Recovery flows
 * --------------
 *
 * Userspace modeset link recovery::
 *
 *                       [IDLE]
 *                          |
 *                          | userspace modeset link training fails
 *                          | (autoretrain link recovery work scheduled)
 *                          v
 *               [AUTORETRAIN_PENDING]-- autoretrain link recovery succeeds -> [IDLE]
 *                          |
 *                          | autoretrain link recovery modeset check or link training fails
 *                          |
 *                       +--o--+
 *  modeset check fails  |     | link training fails
 *  (userspace notified) |     |
 *                       |     o-------- no fallback (userspace notified) ---> [NO_FALLBACK]
 *                       |     |
 *   +-------------+     |     | fallback selected (userspace notified)
 *   |             |     |     |
 *   |             v     v     v
 *   |        [AUTORETRAIN_DISABLED]--- userspace link recovery succeeds ----> [IDLE]
 *   |                   |
 *   |                   | userspace link recovery fails
 *   |                   |
 *   +-------------------o------------- no fallback (userspace notified) ----> [NO_FALLBACK]
 *   fallback selected
 *   (userspace notified)
 *
 * Asynchronous link degradation recovery::
 *
 *                       [IDLE]
 *                          |
 *                          | link degrades
 *                          | (autoretrain link recovery performed)
 *                          |
 *                          o--- autoretrain link recovery succeeds ---> [IDLE]
 *                          |
 *                          | autoretrain link recovery modeset check or link training fails
 *                          |
 *                       +--o--+
 *  modeset check fails  |     | link training fails
 *  (userspace notified) |     | (autoretrain work scheduled)
 *                       v     v
 *  [AUTORETRAIN_DISABLED*]   [AUTORETRAIN_PENDING*]
 *
 * ``*`` marks states where the sequence continues from the corresponding state
 * in the Userspace modeset link recovery flow above.
 *
 */

#define LT_MSG_PREFIX			"[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] "
#define LT_MSG_ARGS(_intel_dp, _dp_phy)	(_intel_dp)->attached_connector->base.base.id, \
					(_intel_dp)->attached_connector->base.name, \
					dp_to_dig_port(_intel_dp)->base.base.base.id, \
					dp_to_dig_port(_intel_dp)->base.base.name, \
					drm_dp_phy_name(_dp_phy)

#define lt_dbg(_intel_dp, _dp_phy, _format, ...) \
	drm_dbg_kms(to_intel_display(_intel_dp)->drm, \
		    LT_MSG_PREFIX _format, \
		    LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__)

#define lt_err(_intel_dp, _dp_phy, _format, ...) do { \
	if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \
		drm_err(to_intel_display(_intel_dp)->drm, \
			LT_MSG_PREFIX _format, \
			LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \
	else \
		lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \
} while (0)

/*
 * enum intel_dp_link_recovery_state - LT recovery state
 * @INTEL_DP_LINK_RECOVERY_IDLE:
 *   No link training failure is currently tracked and no recovery is
 *   in progress. This is the initial state after driver initialization,
 *   power state transitions, sink (re-)connection, or after a successful
 *   link training.
 *
 * @INTEL_DP_LINK_RECOVERY_AUTORETRAIN_PENDING:
 *   A first link training failure has been observed and an automatic
 *   retraining attempt with the same link parameters is pending. Exactly
 *   one such attempt is allowed before switching to userspace-driven
 *   recovery.
 *
 * @INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED:
 *   Automatic retraining is no longer possible. At this point, a
 *   fallback selection is made and userspace is notified to take over
 *   recovery, performing modesets with parameters it determines are
 *   required. The driver then selects a link configuration from the
 *   remaining fallback configuration set. Subsequent link training
 *   failures trigger further fallback selections and userspace
 *   notifications.
 *
 * @INTEL_DP_LINK_RECOVERY_NO_FALLBACK:
 *   Fallback selection is no longer possible, as no usable fallback link
 *   configurations remain. Recovery must proceed via userspace modesets
 *   using the remaining allowed link configuration. Userspace continues
 *   to be notified of subsequent link training failures.
 *
 * Describes the link recovery state used by the Intel DP link recovery
 * logic.
 *
 * See also:
 *   - DOC: DisplayPort link training
 *   - link_recovery_autoretrain_pending()
 *   - link_recovery_autoretrain_allowed()
 *   - link_recovery_has_no_fallback()
 *   - link_recovery_mark_train_failure()
 *   - link_recovery_mark_autoretrain_modeset_failure()
 *   - link_recovery_mark_no_fallback()
 *   - link_recovery_reset()
 */
enum intel_dp_link_recovery_state {
	/*
	 * Keep the enum values ordered from least to most severe
	 * recovery state; helper logic relies on that ordering.
	 */
	INTEL_DP_LINK_RECOVERY_IDLE,
	INTEL_DP_LINK_RECOVERY_AUTORETRAIN_PENDING,
	INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED,
	INTEL_DP_LINK_RECOVERY_NO_FALLBACK,
};

struct intel_dp_link_training {
	struct intel_dp *dp;

	enum intel_dp_link_recovery_state recovery_state;

	int force_train_failure;
	bool force_retrain;
};

static struct intel_dp_link_training *connector_to_link_training(struct intel_connector *connector)
{
	return intel_attached_dp(connector)->link.training;
}

static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
{
	memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps));
}

static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
{
	intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
				    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
}

static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
				   enum drm_dp_phy dp_phy)
{
	return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];
}

static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
					 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
					 enum drm_dp_phy dp_phy)
{
	u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

	if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
		lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n");
		return;
	}

	lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n",
	       (int)sizeof(intel_dp->lttpr_phy_caps[0]),
	       phy_caps);
}

static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp,
					    const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
	int ret;

	ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
					    intel_dp->lttpr_common_caps);
	if (ret < 0)
		goto reset_caps;

	lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n",
	       (int)sizeof(intel_dp->lttpr_common_caps),
	       intel_dp->lttpr_common_caps);

	/* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */
	if (intel_dp->lttpr_common_caps[0] < 0x14)
		goto reset_caps;

	return true;

reset_caps:
	intel_dp_reset_lttpr_common_caps(intel_dp);
	return false;
}

static bool
intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
{
	u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
			  DP_PHY_REPEATER_MODE_NON_TRANSPARENT;

	intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -
				    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val;

	return true;
}

bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp)
{
	return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -
					   DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] ==
		DP_PHY_REPEATER_MODE_TRANSPARENT;
}

/*
 * Read the LTTPR common capabilities and switch the LTTPR PHYs to
 * non-transparent mode if this is supported. Preserve the
 * transparent/non-transparent mode on an active link.
 *
 * Return the number of detected LTTPRs in non-transparent mode or 0 if the
 * LTTPRs are in transparent mode or the detection failed.
 */
static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
	int lttpr_count;
	int ret;

	if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
		return 0;

	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
	/*
	 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are
	 * detected as this breaks link training at least on the Dell WD19TB
	 * dock.
	 */
	if (lttpr_count == 0)
		return 0;

	/*
	 * Don't change the mode on an active link, to prevent a loss of link
	 * synchronization. See DP Standard v2.0 3.6.7. about the LTTPR
	 * resetting its internal state when the mode is changed from
	 * non-transparent to transparent.
	 */
	if (intel_dp->link.active) {
		if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp))
			goto out_reset_lttpr_count;

		return lttpr_count;
	}

	ret = drm_dp_lttpr_init(&intel_dp->aux, lttpr_count);
	if (ret) {
		lt_dbg(intel_dp, DP_PHY_DPRX,
		       "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");

		intel_dp_set_lttpr_transparent_mode(intel_dp, true);

		goto out_reset_lttpr_count;
	}

	intel_dp_set_lttpr_transparent_mode(intel_dp, false);

	return lttpr_count;

out_reset_lttpr_count:
	intel_dp_reset_lttpr_count(intel_dp);

	return 0;
}

static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
	int lttpr_count;
	int i;

	lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd);

	for (i = 0; i < lttpr_count; i++) {
		intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
		drm_dp_dump_lttpr_desc(&intel_dp->aux, DP_PHY_LTTPR(i));
	}

	return lttpr_count;
}

int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
	struct intel_display *display = to_intel_display(intel_dp);

	if (intel_dp_is_edp(intel_dp))
		return 0;

	/*
	 * Detecting LTTPRs must be avoided on platforms with an AUX timeout
	 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
	 */
	if (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)
		if (drm_dp_dpcd_probe(&intel_dp->aux,
				      DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV))
			return -EIO;

	if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
		return -EIO;

	return 0;
}

/**
 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
 * @intel_dp: Intel DP struct
 *
 * Read the LTTPR common and DPRX capabilities and switch to non-transparent
 * link training mode if any is detected and read the PHY capabilities for all
 * detected LTTPRs. In case of an LTTPR detection error or if the number of
 * LTTPRs is more than is supported (8), fall back to the no-LTTPR,
 * transparent mode link training mode.
 *
 * Returns:
 * - >0  if LTTPRs were detected and the non-transparent LT mode was
 *       set. The DPRX capabilities are read out.
 * -  0  if no LTTPRs or more than 8 LTTPRs were detected or in case of
 *       a detection failure and the transparent LT mode was set. The
 *       DPRX capabilities are read out.
 * - <0  Reading out the DPRX capabilities failed.
 */
int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
{
	struct intel_display *display = to_intel_display(intel_dp);
	int lttpr_count = 0;

	/*
	 * Detecting LTTPRs must be avoided on platforms with an AUX timeout
	 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
	 */
	if (!intel_dp_is_edp(intel_dp) &&
	    (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)) {
		u8 dpcd[DP_RECEIVER_CAP_SIZE];
		int err = intel_dp_read_dprx_caps(intel_dp, dpcd);

		if (err != 0)
			return err;

		lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
	}

	/*
	 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
	 * it here.
	 */
	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
		intel_dp_reset_lttpr_common_caps(intel_dp);
		return -EIO;
	}

	return lttpr_count;
}

static u8 dp_voltage_max(u8 preemph)
{
	switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
	default:
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
	}
}

static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,
				     enum drm_dp_phy dp_phy)
{
	const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

	if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps))
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
	else
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
}

static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,
				     enum drm_dp_phy dp_phy)
{
	const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

	if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps))
		return DP_TRAIN_PRE_EMPH_LEVEL_3;
	else
		return DP_TRAIN_PRE_EMPH_LEVEL_2;
}

static bool
intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,
				     enum drm_dp_phy dp_phy)
{
	struct intel_display *display = to_intel_display(intel_dp);
	int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);

	drm_WARN_ON_ONCE(display->drm,
			 lttpr_count <= 0 && dp_phy != DP_PHY_DPRX);

	return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1);
}

static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,
				   const struct intel_crtc_state *crtc_state,
				   enum drm_dp_phy dp_phy)
{
	struct intel_display *display = to_intel_display(intel_dp);
	u8 voltage_max;

	/*
	 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from
	 * the DPRX_PHY we train.
	 */
	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
		voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
	else
		voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);

	drm_WARN_ON_ONCE(display->drm,
			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);

	return voltage_max;
}

static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
				   enum drm_dp_phy dp_phy)
{
	struct intel_display *display = to_intel_display(intel_dp);
	u8 preemph_max;

	/*
	 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from
	 * the DPRX_PHY we train.
	 */
	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
		preemph_max = intel_dp->preemph_max(intel_dp);
	else
		preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);

	drm_WARN_ON_ONCE(display->drm,
			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);

	return preemph_max;
}

static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
				       enum drm_dp_phy dp_phy)
{
	struct intel_display *display = to_intel_display(intel_dp);

	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
		DISPLAY_VER(display) >= 10 || display->platform.broxton;
}

/* 128b/132b */
static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp,
						 const struct intel_crtc_state *crtc_state,
						 enum drm_dp_phy dp_phy,
						 const u8 link_status[DP_LINK_STATUS_SIZE],
						 int lane)
{
	u8 tx_ffe = 0;

	if (has_per_lane_signal_levels(intel_dp, dp_phy)) {
		lane = min(lane, crtc_state->lane_count - 1);
		tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane);
	} else {
		for (lane = 0; lane < crtc_state->lane_count; lane++)
			tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane));
	}

	return tx_ffe;
}

/* 8b/10b */
static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,
						  const struct intel_crtc_state *crtc_state,
						  enum drm_dp_phy dp_phy,
						  const u8 link_status[DP_LINK_STATUS_SIZE],
						  int lane)
{
	u8 v = 0;
	u8 p = 0;
	u8 voltage_max;
	u8 preemph_max;

	if (has_per_lane_signal_levels(intel_dp, dp_phy)) {
		lane = min(lane, crtc_state->lane_count - 1);

		v = drm_dp_get_adjust_request_voltage(link_status, lane);
		p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
	} else {
		for (lane = 0; lane < crtc_state->lane_count; lane++) {
			v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
			p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
		}
	}

	preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;

	v = min(v, dp_voltage_max(p));

	voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;

	return v | p;
}

static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
					 const struct intel_crtc_state *crtc_state,
					 enum drm_dp_phy dp_phy,
					 const u8 link_status[DP_LINK_STATUS_SIZE],
					 int lane)
{
	if (intel_dp_is_uhbr(crtc_state))
		return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state,
							      dp_phy, link_status, lane);
	else
		return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state,
							       dp_phy, link_status, lane);
}

#define TRAIN_REQ_FMT "%d/%d/%d/%d"
#define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \
	(drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT)
#define TRAIN_REQ_VSWING_ARGS(link_status) \
	_TRAIN_REQ_VSWING_ARGS(link_status, 0), \
	_TRAIN_REQ_VSWING_ARGS(link_status, 1), \
	_TRAIN_REQ_VSWING_ARGS(link_status, 2), \
	_TRAIN_REQ_VSWING_ARGS(link_status, 3)
#define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \
	(drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT)
#define TRAIN_REQ_PREEMPH_ARGS(link_status) \
	_TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
	_TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
	_TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
	_TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
#define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \
	drm_dp_get_adjust_tx_ffe_preset((link_status), (lane))
#define TRAIN_REQ_TX_FFE_ARGS(link_status) \
	_TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \
	_TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \
	_TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
	_TRAIN_REQ_TX_FFE_ARGS(link_status, 3)

bool
intel_dp_get_adjust_train(struct intel_dp *intel_dp,
			  const struct intel_crtc_state *crtc_state,
			  enum drm_dp_phy dp_phy,
			  const u8 link_status[DP_LINK_STATUS_SIZE])
{
	bool changed = false;
	int lane;

	if (intel_dp_is_uhbr(crtc_state)) {
		lt_dbg(intel_dp, dp_phy,
		       "128b/132b, lanes: %d, "
		       "TX FFE request: " TRAIN_REQ_FMT "\n",
		       crtc_state->lane_count,
		       TRAIN_REQ_TX_FFE_ARGS(link_status));
	} else {
		lt_dbg(intel_dp, dp_phy,
		       "8b/10b, lanes: %d, "
		       "vswing request: " TRAIN_REQ_FMT ", "
		       "pre-emphasis request: " TRAIN_REQ_FMT "\n",
		       crtc_state->lane_count,
		       TRAIN_REQ_VSWING_ARGS(link_status),
		       TRAIN_REQ_PREEMPH_ARGS(link_status));
	}

	for (lane = 0; lane < 4; lane++) {
		u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
							dp_phy, link_status, lane);
		if (intel_dp->train_set[lane] == new)
			continue;

		intel_dp->train_set[lane] = new;
		changed = true;
	}

	return changed;
}

static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
					     enum drm_dp_phy dp_phy)
{
	return dp_phy == DP_PHY_DPRX ?
		DP_TRAINING_PATTERN_SET :
		DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy);
}

static bool
intel_dp_set_link_train(struct intel_dp *intel_dp,
			const struct intel_crtc_state *crtc_state,
			enum drm_dp_phy dp_phy,
			u8 dp_train_pat)
{
	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
	u8 buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;

	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
					       dp_phy, dp_train_pat);

	buf[0] = dp_train_pat;
	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
	memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
	len = crtc_state->lane_count + 1;

	ret = drm_dp_dpcd_write_data(&intel_dp->aux, reg, buf, len);

	return !ret;
}

static char dp_training_pattern_name(u8 train_pat)
{
	switch (train_pat) {
	case DP_TRAINING_PATTERN_1:
	case DP_TRAINING_PATTERN_2:
	case DP_TRAINING_PATTERN_3:
		return '0' + train_pat;
	case DP_TRAINING_PATTERN_4:
		return '4';
	default:
		MISSING_CASE(train_pat);
		return '?';
	}
}

void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
				       const struct intel_crtc_state *crtc_state,
				       enum drm_dp_phy dp_phy,
				       u8 dp_train_pat)
{
	u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);

	if (train_pat != DP_TRAINING_PATTERN_DISABLE)
		lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n",
		       dp_training_pattern_name(train_pat));

	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
}

#define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s"
#define _TRAIN_SET_VSWING_ARGS(train_set) \
	((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \
	(train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : ""
#define TRAIN_SET_VSWING_ARGS(train_set) \
	_TRAIN_SET_VSWING_ARGS((train_set)[0]), \
	_TRAIN_SET_VSWING_ARGS((train_set)[1]), \
	_TRAIN_SET_VSWING_ARGS((train_set)[2]), \
	_TRAIN_SET_VSWING_ARGS((train_set)[3])
#define _TRAIN_SET_PREEMPH_ARGS(train_set) \
	((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \
	(train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : ""
#define TRAIN_SET_PREEMPH_ARGS(train_set) \
	_TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \
	_TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \
	_TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \
	_TRAIN_SET_PREEMPH_ARGS((train_set)[3])
#define _TRAIN_SET_TX_FFE_ARGS(train_set) \
	((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), ""
#define TRAIN_SET_TX_FFE_ARGS(train_set) \
	_TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \
	_TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \
	_TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \
	_TRAIN_SET_TX_FFE_ARGS((train_set)[3])

void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
				const struct intel_crtc_state *crtc_state,
				enum drm_dp_phy dp_phy)
{
	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	if (intel_dp_is_uhbr(crtc_state)) {
		lt_dbg(intel_dp, dp_phy,
		       "128b/132b, lanes: %d, "
		       "TX FFE presets: " TRAIN_SET_FMT "\n",
		       crtc_state->lane_count,
		       TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
	} else {
		lt_dbg(intel_dp, dp_phy,
		       "8b/10b, lanes: %d, "
		       "vswing levels: " TRAIN_SET_FMT ", "
		       "pre-emphasis levels: " TRAIN_SET_FMT "\n",
		       crtc_state->lane_count,
		       TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
		       TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
	}

	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
		encoder->set_signal_levels(encoder, crtc_state);
}

static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp,
			  const struct intel_crtc_state *crtc_state,
			  enum drm_dp_phy dp_phy,
			  u8 dp_train_pat)
{
	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
	return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp,
			   const struct intel_crtc_state *crtc_state,
			   enum drm_dp_phy dp_phy)
{
	int reg = dp_phy == DP_PHY_DPRX ?
			    DP_TRAINING_LANE0_SET :
			    DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
	int ret;

	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);

	ret = drm_dp_dpcd_write_data(&intel_dp->aux, reg,
				     intel_dp->train_set, crtc_state->lane_count);

	return !ret;
}

/* 128b/132b */
static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane)
{
	return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) ==
		DP_TX_FFE_PRESET_VALUE_MASK;
}

/*
 * 8b/10b
 *
 * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to
 * have self contradicting tests around this area.
 *
 * In lieu of better ideas let's just stop when we've reached the max supported
 * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on
 * whether vswing level 3 is supported or not.
 */
static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane)
{
	u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>
		DP_TRAIN_VOLTAGE_SWING_SHIFT;
	u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>
		DP_TRAIN_PRE_EMPHASIS_SHIFT;

	if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0)
		return false;

	if (v + p != 3)
		return false;

	return true;
}

static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
					     const struct intel_crtc_state *crtc_state)
{
	int lane;

	for (lane = 0; lane < crtc_state->lane_count; lane++) {
		u8 train_set_lane = intel_dp->train_set[lane];

		if (intel_dp_is_uhbr(crtc_state)) {
			if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane))
				return false;
		} else {
			if (!intel_dp_lane_max_vswing_reached(train_set_lane))
				return false;
		}
	}

	return true;
}

void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
				     bool is_vrr,
				     bool pr_with_as_sdp_enable)
{
	u8 link_config[2];

	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
	link_config[0] |= pr_with_as_sdp_enable ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
	drm_dp_dpcd_write_data(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
}

static bool
intel_dp_pr_with_as_sdp_enabled(struct intel_dp *intel_dp,
				const struct intel_crtc_state *crtc_state)
{
	return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
		(crtc_state->infoframes.enable &
		 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC));
}

static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
					    const struct intel_crtc_state *crtc_state)
{
	 /*
	  * Currently, we set the MSA ignore bit based on vrr.in_range.
	  * We can't really read that out during driver load since we don't have
	  * the connector information read in yet. So if we do end up doing a
	  * modeset during initial_commit() we'll clear the MSA ignore bit.
	  * GOP likely wouldn't have set this bit so after the initial commit,
	  * if there are no modesets and we enable VRR mode seamlessly
	  * (without a full modeset), the MSA ignore bit might never get set.
	  *
	  * #TODO: Implement readout of vrr.in_range.
	  * We need fastset support for setting the MSA ignore bit in DPCD,
	  * especially on the first real commit when clearing the inherited flag.
	  */
	intel_dp_link_training_set_mode(intel_dp,
					crtc_state->port_clock,
					crtc_state->vrr.in_range,
					intel_dp_pr_with_as_sdp_enabled(intel_dp, crtc_state));
}

void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
				   int link_bw, int rate_select, int lane_count,
				   bool enhanced_framing, bool post_lt_adj_req)
{
	if (enhanced_framing)
		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

	if (post_lt_adj_req)
		lane_count |= DP_POST_LT_ADJ_REQ_GRANTED;

	if (link_bw) {
		/* DP and eDP v1.3 and earlier link bw set method. */
		u8 link_config[] = { link_bw, lane_count };

		drm_dp_dpcd_write_data(&intel_dp->aux, DP_LINK_BW_SET, link_config,
				       sizeof(link_config));
	} else {
		/*
		 * eDP v1.4 and later link rate set method.
		 *
		 * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if
		 * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET.
		 *
		 * eDP v1.5 sinks allow choosing either, and the last choice
		 * shall be active.
		 */
		drm_dp_dpcd_write_byte(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);
		drm_dp_dpcd_write_byte(&intel_dp->aux, DP_LINK_RATE_SET, rate_select);
	}
}

/*
 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
 * 1.2 devices that support it, TPS2 otherwise.
 */
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
				     const struct intel_crtc_state *crtc_state,
				     enum drm_dp_phy dp_phy)
{
	struct intel_display *display = to_intel_display(intel_dp);
	bool source_tps3, sink_tps3, source_tps4, sink_tps4;

	/* UHBR+ use separate 128b/132b TPS2 */
	if (intel_dp_is_uhbr(crtc_state))
		return DP_TRAINING_PATTERN_2;

	/*
	 * TPS4 support is mandatory for all downstream devices that
	 * support HBR3. There are no known eDP panels that support
	 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
	 * LTTPRs must support TPS4.
	 */
	source_tps4 = intel_dp_source_supports_tps4(display);
	sink_tps4 = dp_phy != DP_PHY_DPRX ||
		    drm_dp_tps4_supported(intel_dp->dpcd);
	if (source_tps4 && sink_tps4) {
		return DP_TRAINING_PATTERN_4;
	} else if (crtc_state->port_clock == 810000) {
		if (!source_tps4)
			lt_dbg(intel_dp, dp_phy,
			       "8.1 Gbps link rate without source TPS4 support\n");
		if (!sink_tps4)
			lt_dbg(intel_dp, dp_phy,
			       "8.1 Gbps link rate without sink TPS4 support\n");
	}

	/*
	 * TPS3 support is mandatory for downstream devices that
	 * support HBR2. However, not all sinks follow the spec.
	 */
	source_tps3 = intel_dp_source_supports_tps3(display);
	sink_tps3 = dp_phy != DP_PHY_DPRX ||
		    drm_dp_tps3_supported(intel_dp->dpcd);
	if (source_tps3 && sink_tps3) {
		return  DP_TRAINING_PATTERN_3;
	} else if (crtc_state->port_clock >= 540000) {
		if (!source_tps3)
			lt_dbg(intel_dp, dp_phy,
			       ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
		if (!sink_tps3)
			lt_dbg(intel_dp, dp_phy,
			       ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
	}

	return DP_TRAINING_PATTERN_2;
}

static bool intel_dp_use_post_lt_adj_req(struct intel_dp *intel_dp,
					 const struct intel_crtc_state *crtc_state)
{
	return intel_dp->set_idle_link_train &&
		drm_dp_post_lt_adj_req_supported(intel_dp->dpcd) &&
		intel_dp_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX) != DP_TRAINING_PATTERN_4;
}

static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
					const struct intel_crtc_state *crtc_state,
					u8 link_bw, u8 rate_select)
{
	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count,
				      crtc_state->enhanced_framing,
				      intel_dp_use_post_lt_adj_req(intel_dp, crtc_state));
}

/*
 * Prepare link training by configuring the link parameters. On DDI platforms
 * also enable the port here.
 */
static bool
intel_dp_prepare_link_train(struct intel_dp *intel_dp,
			    const struct intel_crtc_state *crtc_state)
{
	u8 link_bw, rate_select;

	if (intel_dp->prepare_link_retrain)
		intel_dp->prepare_link_retrain(intel_dp, crtc_state);

	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
			      &link_bw, &rate_select);

	/*
	 * WaEdpLinkRateDataReload
	 *
	 * Parade PS8461E MUX (used on various TGL+ laptops) needs
	 * to snoop the link rates reported by the sink when we
	 * use LINK_RATE_SET in order to operate in jitter cleaning
	 * mode (as opposed to redriver mode). Unfortunately it
	 * loses track of the snooped link rates when powered down,
	 * so we need to make it re-snoop often. Without this high
	 * link rates are not stable.
	 */
	if (!link_bw) {
		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];

		lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n");

		drm_dp_dpcd_read_data(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
				      sink_rates, sizeof(sink_rates));
	}

	if (link_bw)
		lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n",
		       link_bw);
	else
		lt_dbg(intel_dp, DP_PHY_DPRX,
		       "Using LINK_RATE_SET value %02x\n",
		       rate_select);
	/*
	 * Spec DP2.1 Section 3.5.2.16
	 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate
	 */
	intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
	intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
				    rate_select);

	return true;
}

static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state,
					    const u8 old_link_status[DP_LINK_STATUS_SIZE],
					    const u8 new_link_status[DP_LINK_STATUS_SIZE])
{
	int lane;

	for (lane = 0; lane < crtc_state->lane_count; lane++) {
		u8 old, new;

		if (intel_dp_is_uhbr(crtc_state)) {
			old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane);
			new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane);
		} else {
			old = drm_dp_get_adjust_request_voltage(old_link_status, lane) |
				drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane);
			new = drm_dp_get_adjust_request_voltage(new_link_status, lane) |
				drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane);
		}

		if (old != new)
			return true;
	}

	return false;
}

void
intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
			  const u8 link_status[DP_LINK_STATUS_SIZE])
{
	lt_dbg(intel_dp, dp_phy,
	       "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
	       link_status[0], link_status[1], link_status[2],
	       link_status[3], link_status[4], link_status[5]);
}

/*
 * Perform the link training clock recovery phase on the given DP PHY using
 * training pattern 1.
 */
static bool
intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
				      const struct intel_crtc_state *crtc_state,
				      enum drm_dp_phy dp_phy)
{
	u8 old_link_status[DP_LINK_STATUS_SIZE] = {};
	int voltage_tries, cr_tries, max_cr_tries;
	u8 link_status[DP_LINK_STATUS_SIZE];
	bool max_vswing_reached = false;
	int delay_us;

	delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
						    intel_dp->dpcd, dp_phy,
						    intel_dp_is_uhbr(crtc_state));

	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		lt_err(intel_dp, dp_phy, "Failed to enable link training\n");
		return false;
	}

	/*
	 * The DP 1.4 spec defines the max clock recovery retries value
	 * as 10 but for pre-DP 1.4 devices we set a very tolerant
	 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
	 * x 5 identical voltage retries). Since the previous specs didn't
	 * define a limit and created the possibility of an infinite loop
	 * we want to prevent any sync from triggering that corner case.
	 */
	if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
		max_cr_tries = 10;
	else
		max_cr_tries = 80;

	voltage_tries = 1;
	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
		fsleep(delay_us);

		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
						     link_status) < 0) {
			lt_err(intel_dp, dp_phy, "Failed to get link status\n");
			return false;
		}

		if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
			lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");
			return true;
		}

		if (voltage_tries == 5) {
			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
			lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n");
			return false;
		}

		if (max_vswing_reached) {
			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
			lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n");
			return false;
		}

		/* Update training set as requested by target */
		intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
					  link_status);
		if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
			lt_err(intel_dp, dp_phy, "Failed to update link training\n");
			return false;
		}

		if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status))
			++voltage_tries;
		else
			voltage_tries = 1;

		memcpy(old_link_status, link_status, sizeof(link_status));

		if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
			max_vswing_reached = true;
	}

	intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
	lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n",
	       max_cr_tries);

	return false;
}

/*
 * Perform the link training channel equalization phase on the given DP PHY
 * using one of training pattern 2, 3 or 4 depending on the source and
 * sink capabilities.
 */
static bool
intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
					    const struct intel_crtc_state *crtc_state,
					    enum drm_dp_phy dp_phy)
{
	int tries;
	u32 training_pattern;
	u8 link_status[DP_LINK_STATUS_SIZE];
	bool channel_eq = false;
	int delay_us;

	delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
						intel_dp->dpcd, dp_phy,
						intel_dp_is_uhbr(crtc_state));

	training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
	/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
	if (training_pattern != DP_TRAINING_PATTERN_4)
		training_pattern |= DP_LINK_SCRAMBLING_DISABLE;

	/* channel equalization */
	if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
				     training_pattern)) {
		lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n");
		return false;
	}

	for (tries = 0; tries < 5; tries++) {
		fsleep(delay_us);

		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
						     link_status) < 0) {
			lt_err(intel_dp, dp_phy, "Failed to get link status\n");
			break;
		}

		/* Make sure clock is still ok */
		if (!drm_dp_clock_recovery_ok(link_status,
					      crtc_state->lane_count)) {
			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
			lt_dbg(intel_dp, dp_phy,
			       "Clock recovery check failed, cannot continue channel equalization\n");
			break;
		}

		if (drm_dp_channel_eq_ok(link_status,
					 crtc_state->lane_count)) {
			channel_eq = true;
			lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n");
			break;
		}

		/* Update training set as requested by target */
		intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
					  link_status);
		if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
			lt_err(intel_dp, dp_phy, "Failed to update link training\n");
			break;
		}
	}

	/* Try 5 times, else fail and try at lower BW */
	if (tries == 5) {
		intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
		lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n");
	}

	return channel_eq;
}

static bool
intel_dp_post_lt_adj_req(struct intel_dp *intel_dp,
			 const struct intel_crtc_state *crtc_state)
{
	u8 link_status[DP_LINK_STATUS_SIZE];
	unsigned long deadline;
	bool timeout = false;
	bool success = false;
	int changes = 0;

	if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state))
		return true;

	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
					     link_status) < 0) {
		lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n");
		return false;
	}

	deadline = jiffies + msecs_to_jiffies_timeout(200);

	for (;;) {
		/* Make sure clock is still ok */
		if (!drm_dp_clock_recovery_ok(link_status,
					      crtc_state->lane_count)) {
			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
			lt_dbg(intel_dp, DP_PHY_DPRX,
			       "Clock recovery check failed, cannot continue POST_LT_ADJ_REQ\n");
			break;
		}

		if (!drm_dp_channel_eq_ok(link_status,
					  crtc_state->lane_count)) {
			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
			lt_dbg(intel_dp, DP_PHY_DPRX, "Channel EQ check failed. cannot continue POST_LT_ADJ_REQ\n");
			break;
		}

		if (!drm_dp_post_lt_adj_req_in_progress(link_status)) {
			success = true;
			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
			lt_dbg(intel_dp, DP_PHY_DPRX,
			       "POST_LT_ADJ_REQ done (%d changes). DP Training successful\n", changes);
			break;
		}

		if (changes == 6) {
			success = true;
			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
			lt_dbg(intel_dp, DP_PHY_DPRX,
			       "POST_LT_ADJ_REQ limit reached (%d changes). DP Training successful\n", changes);
			break;
		}

		if (timeout) {
			success = true;
			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
			lt_dbg(intel_dp, DP_PHY_DPRX,
			       "POST_LT_ADJ_REQ timeout reached (%d changes). DP Training successful\n", changes);
			break;
		}

		fsleep(5000);

		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
						     link_status) < 0) {
			lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n");
			break;
		}

		/* Update training set as requested by target */
		if (intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status)) {
			deadline = jiffies + msecs_to_jiffies_timeout(200);
			changes++;

			if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
				lt_err(intel_dp, DP_PHY_DPRX, "Failed to update link training\n");
				break;
			}
		} else if (time_after(jiffies, deadline)) {
			timeout = true;
		}
	}

	return success;
}

static void intel_dp_stop_post_lt_adj_req(struct intel_dp *intel_dp,
					  const struct intel_crtc_state *crtc_state)
{
	u8 lane_count;

	if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state))
		return;

	/* clear DP_POST_LT_ADJ_REQ_GRANTED */
	lane_count = crtc_state->lane_count;
	if (crtc_state->enhanced_framing)
		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

	drm_dp_dpcd_write_byte(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);
}

static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
						   enum drm_dp_phy dp_phy)
{
	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
	u8 val = DP_TRAINING_PATTERN_DISABLE;

	return drm_dp_dpcd_write_byte(&intel_dp->aux, reg, val) == 0;
}

static int
intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp,
			    const struct intel_crtc_state *crtc_state)
{
	u8 sink_status;
	int ret;

	ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_SINK_STATUS, &sink_status);
	if (ret < 0) {
		lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status (%pe)\n",
		       ERR_PTR(ret));
		return ret;
	}

	return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0;
}

static bool
link_recovery_autoretrain_pending(struct intel_dp_link_training *link_training)
{
	return link_training->recovery_state == INTEL_DP_LINK_RECOVERY_AUTORETRAIN_PENDING;
}

/*
 * Automatic retraining is a driver-driven link recovery mechanism that
 * retrains the link with the current userspace provided modeset
 * configuration and link parameters.
 *
 * Autoretrain is allowed while the link configurations available for
 * retraining, i.e. those not disabled yet via fallback selection, still
 * make it possible to retrain the link for the current userspace provided
 * modeset configuration.
 *
 * Once automatic retraining is no longer allowed, userspace driven link
 * recovery via userspace notifications and userspace modesets takes over.
 *
 * See also:
 *   - DOC: DisplayPort link training
 */
static bool
link_recovery_autoretrain_allowed(struct intel_dp_link_training *link_training)
{
	switch (link_training->recovery_state) {
	case INTEL_DP_LINK_RECOVERY_IDLE:
	case INTEL_DP_LINK_RECOVERY_AUTORETRAIN_PENDING:
		return true;
	default:
		return false;
	}
}

static bool
link_recovery_has_no_fallback(struct intel_dp_link_training *link_training)
{
	return link_training->recovery_state == INTEL_DP_LINK_RECOVERY_NO_FALLBACK;
}

/*
 * Record a link training failure and advance the recovery state to
 * indicate the next required recovery step.
 *
 * The caller must proceed with recovery as instructed by the return
 * value, either via automatic retraining or, once automatic retraining
 * is no longer possible, via userspace modesets after fallback
 * selection.
 *
 * Note that the error reported via this function is the error seen by
 * the link training failure handler proper after an actual link
 * training failure indicated by the sink device, and so the error and
 * corresponding actions required are distinct from an autoretrain
 * modeset failure. See link_recovery_mark_autoretrain_modeset_failure() to
 * report a modeset failure.
 *
 * See also:
 *   - DOC: DisplayPort link training
 */
static bool
link_recovery_mark_train_failure(struct intel_dp_link_training *link_training)
{
	switch (link_training->recovery_state) {
	case INTEL_DP_LINK_RECOVERY_IDLE:
		link_training->recovery_state = INTEL_DP_LINK_RECOVERY_AUTORETRAIN_PENDING;
		break;
	case INTEL_DP_LINK_RECOVERY_AUTORETRAIN_PENDING:
		link_training->recovery_state = INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED;
		break;
	default:
		break;
	}

	return link_recovery_autoretrain_allowed(link_training);
}

/*
 * Record a failure of the autoretrain modeset before link training
 * itself could run.
 *
 * Note that the error reported via this function and the corresponding
 * expected actions are distinct from an actual link training failure:
 * the modeset failed before a link training attempt could be performed.
 * See link_recovery_mark_train_failure() to report an actual link
 * training failure.
 *
 * Update the state to indicate that further recovery is to be delegated to
 * userspace via a regular modeset.
 *
 * See also:
 *   - DOC: DisplayPort link training
 */
static void
link_recovery_mark_autoretrain_modeset_failure(struct intel_dp_link_training *link_training)
{
	if (link_recovery_autoretrain_allowed(link_training))
		link_training->recovery_state = INTEL_DP_LINK_RECOVERY_AUTORETRAIN_DISABLED;
}

/* Record that no more link fallback configuration is available. */
static void
link_recovery_mark_no_fallback(struct intel_dp_link_training *link_training)
{
	link_training->recovery_state = INTEL_DP_LINK_RECOVERY_NO_FALLBACK;
}

/**
 * link_recovery_reset - reset the link recovery state
 * @link_training: link training state
 *
 * Reset the link recovery state to indicate that no link recovery is
 * required.
 */
static void link_recovery_reset(struct intel_dp_link_training *link_training)
{
	link_training->recovery_state = INTEL_DP_LINK_RECOVERY_IDLE;
}

/**
 * intel_dp_stop_link_train - stop link training
 * @intel_dp: DP struct
 * @crtc_state: state for CRTC attached to the encoder
 *
 * Stop the link training of the @intel_dp port, disabling the training
 * pattern in the sink's DPCD, and disabling the test pattern symbol
 * generation on the port.
 *
 * What symbols are output on the port after this point is
 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern
 * with the pipe being disabled, on older platforms it's HW specific if/how an
 * idle pattern is generated, as the pipe is already enabled here for those.
 *
 * This function must be called after intel_dp_start_link_train().
 */
void intel_dp_stop_link_train(struct intel_dp *intel_dp,
			      const struct intel_crtc_state *crtc_state)
{
	struct intel_dp_link_training *link_training = intel_dp->link.training;
	struct intel_display *display = to_intel_display(intel_dp);
	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
	int ret;

	intel_dp->link.active = true;

	intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
					       DP_TRAINING_PATTERN_DISABLE);

	if (intel_dp_is_uhbr(crtc_state)) {
		ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),
				      ret == 0,
				      500, 500 * 1000, false);
		if (ret)
			lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");
	}

	intel_hpd_unblock(encoder);

	if (!display->hotplug.ignore_long_hpd &&
	    link_recovery_autoretrain_allowed(link_training)) {
		int delay_ms = link_recovery_autoretrain_pending(link_training) ? 0 : 2000;

		intel_encoder_link_check_queue_work(encoder, delay_ms);
	}
}

static bool
intel_dp_link_train_phy(struct intel_dp *intel_dp,
			const struct intel_crtc_state *crtc_state,
			enum drm_dp_phy dp_phy)
{
	bool ret = false;

	if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
		goto out;

	if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))
		goto out;

	ret = true;

out:
	lt_dbg(intel_dp, dp_phy,
	       "Link Training %s at link rate = %d, lane count = %d\n",
	       ret ? "passed" : "failed",
	       crtc_state->port_clock, crtc_state->lane_count);

	return ret;
}

static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
						     int link_rate,
						     u8 lane_count)
{
	/* FIXME figure out what we actually want here */
	const struct drm_display_mode *fixed_mode =
		intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
	int mode_rate, max_rate;

	mode_rate = intel_dp_link_required(link_rate, lane_count,
					   fixed_mode->clock, fixed_mode->hdisplay,
					   fxp_q4_from_int(18), 0);
	max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
	if (mode_rate > max_rate)
		return false;

	return true;
}

static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,
			       int *new_link_rate, int *new_lane_count)
{
	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
	struct intel_dp_link_caps_order order =
		intel_dp_link_caps_connector_fallback_order(is_mst);
	struct intel_dp_link_config old_config = {
		.rate = crtc_state->port_clock,
		.lane_count = crtc_state->lane_count,
	};
	struct intel_dp_link_caps_iter iter;
	struct intel_dp_link_config config;
	bool old_found = false;
	bool new_found = false;

	intel_dp_link_caps_iter_start(&iter, link_caps, order, INTEL_DP_LINK_CAPS_FILTER_ALL);
	for_each_dp_link_config(&iter, &config) {
		if (!old_found) {
			if (config.rate == old_config.rate &&
			    config.lane_count == old_config.lane_count)
				old_found = true;

			continue;
		}

		*new_link_rate = config.rate;
		*new_lane_count = config.lane_count;
		new_found = true;

		break;
	}
	intel_dp_link_caps_iter_end(&iter);

	return new_found;
}

VISIBLE_IF_KUNIT
int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
					    const struct intel_crtc_state *crtc_state)
{
	struct intel_display *display = to_intel_display(intel_dp);
	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
	struct intel_dp_link_config max_link_limits;
	struct intel_dp_link_config current_config = {
		.rate = crtc_state->port_clock,
		.lane_count = crtc_state->lane_count,
	};
	int new_link_rate;
	int new_lane_count;
	int err = -1;

	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
		lt_dbg(intel_dp, DP_PHY_DPRX,
		       "Retrying Link training for eDP with max parameters\n");
		intel_dp->use_max_params = true;
		return 0;
	}

	/*
	 * Temporarily reset the max link limit before selecting the fallback
	 * config.
	 *
	 * After fallback, the current logic narrows the allowed configurations
	 * to the selected config's rate and lane count. That can make a later
	 * fallback candidate fall outside the current max_limit, so reset it
	 * before searching.
	 *
	 * TODO: Constrain the allowed configurations by only disabling individual
	 * configurations and remove setting maximum link parameters.
	 */
	intel_dp_link_caps_get_max_limits(link_caps, &max_link_limits);
	intel_dp_link_caps_reset_max_limits(link_caps);

	/*
	 * TODO: Make fallback depend only on disabling the current config,
	 * once max_limit no longer constrains the allowed config set. Then
	 * disabling the current config will define the allowed configs for
	 * the subsequent modeset, so there will be no need to select a
	 * reduced config separately here.
	 */
	if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count))
		goto out_restore_max_limits;

	if (intel_dp_is_edp(intel_dp) &&
	    !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) {
		lt_dbg(intel_dp, DP_PHY_DPRX,
		       "Retrying Link training for eDP with same parameters\n");

		err = 0;

		goto out_restore_max_limits;
	}

	/*
	 * Shouldn't fail: the current config was enabled, and reducing the
	 * link parameters should still leave the fallback config allowed.
	 */
	if (drm_WARN_ON(display->drm,
			!intel_dp_link_caps_disable_config(link_caps, &current_config)))
		return -1;

	lt_dbg(intel_dp, DP_PHY_DPRX,
	       "Reducing link parameters from %dx%d to %dx%d\n",
	       crtc_state->lane_count, crtc_state->port_clock,
	       new_lane_count, new_link_rate);

	max_link_limits.rate = new_link_rate;
	max_link_limits.lane_count = new_lane_count;

	err = 0;

out_restore_max_limits:
	/*
	 * Shouldn't fail: setting max_limits can only fail if they drop below
	 * the optionally forced rate/lane-count parameters, but the reduced
	 * config was chosen to satisfy those constraints.
	 */
	if (drm_WARN_ON(display->drm,
			!intel_dp_link_caps_set_max_limits(link_caps, &max_link_limits)))
		err = -1;

	return err;
}

static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state,
						     struct intel_dp *intel_dp,
						     const struct intel_crtc_state *crtc_state)
{
	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
		lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");
		return true;
	}

	if (intel_dp->hobl_active) {
		lt_dbg(intel_dp, DP_PHY_DPRX,
		       "Link Training failed with HOBL active, not enabling it from now on\n");
		intel_dp->hobl_failed = true;
	} else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) {
		return false;
	}

	/* Schedule a Hotplug Uevent to userspace to start modeset */
	intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);

	return true;
}

/* Perform the link training on all LTTPRs and the DPRX on a link. */
static bool
intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
			     const struct intel_crtc_state *crtc_state,
			     int lttpr_count)
{
	bool ret = true;
	int i;

	for (i = lttpr_count - 1; i >= 0; i--) {
		enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i);

		ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);
		intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);

		if (!ret)
			break;
	}

	if (ret)
		ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);

	intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
	intel_dp->set_idle_link_train(intel_dp, crtc_state);

	if (ret)
		ret = intel_dp_post_lt_adj_req(intel_dp, crtc_state);

	intel_dp_stop_post_lt_adj_req(intel_dp, crtc_state);

	return ret;
}

/*
 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1)
 */
static bool
intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
			  const struct intel_crtc_state *crtc_state)
{
	u8 link_status[DP_LINK_STATUS_SIZE];
	int delay_us;
	int try, max_tries = 20;
	unsigned long deadline;
	bool timeout = false;

	/*
	 * Reset signal levels. Start transmitting 128b/132b TPS1.
	 *
	 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1
	 * in DP_TRAINING_PATTERN_SET.
	 */
	if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
				       DP_TRAINING_PATTERN_1)) {
		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n");
		return false;
	}

	delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);

	/* Read the initial TX FFE settings. */
	if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
		lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n");
		return false;
	}

	/* Update signal levels and training set as requested. */
	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
	if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
		lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n");
		return false;
	}

	/* Start transmitting 128b/132b TPS2. */
	if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
				     DP_TRAINING_PATTERN_2)) {
		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n");
		return false;
	}

	/* Time budget for the LANEx_EQ_DONE Sequence */
	deadline = jiffies + msecs_to_jiffies_timeout(450);

	for (try = 0; try < max_tries; try++) {
		fsleep(delay_us);

		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
			return false;
		}

		if (drm_dp_128b132b_link_training_failed(link_status)) {
			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
			lt_err(intel_dp, DP_PHY_DPRX,
			       "Downstream link training failure\n");
			return false;
		}

		if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) {
			lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");
			break;
		}

		if (timeout) {
			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
			lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n");
			return false;
		}

		if (time_after(jiffies, deadline))
			timeout = true; /* try one last time after deadline */

		/*
		 * During LT, Tx shall read AUX_RD_INTERVAL just before writing the new FFE
		 * presets.
		 */
		delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);

		intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);

		/* Update signal levels and training set as requested. */
		if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
			return false;
		}
	}

	if (try == max_tries) {
		intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
		lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n");
		return false;
	}

	for (;;) {
		if (time_after(jiffies, deadline))
			timeout = true; /* try one last time after deadline */

		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
			return false;
		}

		if (drm_dp_128b132b_link_training_failed(link_status)) {
			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
			lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
			return false;
		}

		if (drm_dp_128b132b_eq_interlane_align_done(link_status)) {
			lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n");
			break;
		}

		if (timeout) {
			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
			lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n");
			return false;
		}

		usleep_range(2000, 3000);
	}

	return true;
}

/*
 * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2)
 */
static bool
intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,
			   const struct intel_crtc_state *crtc_state,
			   int lttpr_count)
{
	u8 link_status[DP_LINK_STATUS_SIZE];
	unsigned long deadline;
	int ret;

	ret = drm_dp_dpcd_write_byte(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				     DP_TRAINING_PATTERN_2_CDS);
	if (ret < 0) {
		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS (%pe)\n",
		       ERR_PTR(ret));
		return false;
	}

	/* Time budget for the LANEx_CDS_DONE Sequence */
	deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20);

	for (;;) {
		bool timeout = false;

		if (time_after(jiffies, deadline))
			timeout = true; /* try one last time after deadline */

		usleep_range(2000, 3000);

		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
			return false;
		}

		if (drm_dp_128b132b_eq_interlane_align_done(link_status) &&
		    drm_dp_128b132b_cds_interlane_align_done(link_status) &&
		    drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) {
			lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");
			break;
		}

		if (drm_dp_128b132b_link_training_failed(link_status)) {
			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
			lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
			return false;
		}

		if (timeout) {
			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
			lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n");
			return false;
		}
	}

	return true;
}

/*
 * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.)
 */
static bool
intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
			     const struct intel_crtc_state *crtc_state,
			     int lttpr_count)
{
	bool passed = false;
	int ret;

	ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),
			      ret == 0,
			      500, 500 * 1000, false);
	if (ret) {
		lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");
		goto out;
	}

	if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&
	    intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count))
		passed = true;

	lt_dbg(intel_dp, DP_PHY_DPRX,
	       "128b/132b Link Training %s at link rate = %d, lane count = %d\n",
	       passed ? "passed" : "failed",
	       crtc_state->port_clock, crtc_state->lane_count);

out:
	/*
	 * Ensure that the training pattern does get set to TPS2 even in case
	 * of a failure, as is the case at the end of a passing link training
	 * and what is expected by the transcoder. Leaving TPS1 set (and
	 * disabling the link train mode in DP_TP_CTL later from TPS1 directly)
	 * would result in a stuck transcoder HW state and flip-done timeouts
	 * later in the modeset sequence.
	 */
	if (!passed)
		intel_dp_program_link_training_pattern(intel_dp, crtc_state,
						       DP_PHY_DPRX, DP_TRAINING_PATTERN_2);

	intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);

	return passed;
}

/**
 * intel_dp_start_link_train - start link training
 * @state: Atomic state
 * @intel_dp: DP struct
 * @crtc_state: state for CRTC attached to the encoder
 *
 * Start the link training of the @intel_dp port, scheduling a fallback
 * retraining with reduced link rate/lane parameters if the link training
 * fails.
 * After calling this function intel_dp_stop_link_train() must be called.
 */
void intel_dp_start_link_train(struct intel_atomic_state *state,
			       struct intel_dp *intel_dp,
			       const struct intel_crtc_state *crtc_state)
{
	struct intel_display *display = to_intel_display(state);
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &dig_port->base;
	struct intel_dp_link_training *link_training =
		intel_dp->link.training;
	bool autoretrain_allowed;
	bool passed;
	/*
	 * Reinit the LTTPRs here to ensure that they are switched to
	 * non-transparent mode. During an earlier LTTPR detection this
	 * could've been prevented by an active link.
	 */
	int lttpr_count;

	intel_hpd_block(encoder);

	lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);

	if (lttpr_count < 0)
		/* Still continue with enabling the port and link training. */
		lttpr_count = 0;

	intel_dp_prepare_link_train(intel_dp, crtc_state);

	if (intel_dp_is_uhbr(crtc_state))
		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
	else
		passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count);

	if (link_training->force_train_failure) {
		link_training->force_train_failure--;
		lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n");
	} else if (passed) {
		link_recovery_reset(link_training);
		return;
	}

	autoretrain_allowed = link_recovery_mark_train_failure(link_training);

	/*
	 * Ignore the link failure in CI
	 *
	 * In fixed environments like CI, sometimes unexpected long HPDs are
	 * generated by the displays. If ignore_long_hpd flag is set, such long
	 * HPDs are ignored. And probably as a consequence of these ignored
	 * long HPDs, subsequent link trainings are failed resulting into CI
	 * execution failures.
	 *
	 * For test cases which rely on the link training or processing of HPDs
	 * ignore_long_hpd flag can unset from the testcase.
	 */
	if (display->hotplug.ignore_long_hpd) {
		lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
		return;
	}

	if (autoretrain_allowed)
		return;

	if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state))
		return;

	link_recovery_mark_no_fallback(link_training);

	if (!passed)
		lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n");
	else
		lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n");
}

void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
				 const struct intel_crtc_state *crtc_state)
{
	/*
	 * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
	 * disable SDP CRC. This is applicable for Display version 13.
	 * Default value of bit 31 is '0' hence discarding the write
	 * TODO: Corrective actions on SDP corruption yet to be defined
	 */
	if (!intel_dp_is_uhbr(crtc_state))
		return;

	/* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
	drm_dp_dpcd_write_byte(&intel_dp->aux,
			       DP_SDP_ERROR_DETECTION_CONFIGURATION,
			       DP_SDP_CRC16_128B132B_EN);

	lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
}

bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
				u8 lane_count)
{
	struct intel_dp_link_config max_link_limits;

	/*
	 * FIXME: we need to synchronize the current link parameters with
	 * hardware readout. Currently fast link training doesn't work on
	 * boot-up.
	 *
	 * NOTE:
	 * This may be called from both serialized (locked and synced against
	 * async commit tails) and unserialized (e.g. HPD IRQ) contexts. It
	 * uses the current max link limits as upper bounds to reject
	 * obviously bogus values, even if those bounds may be observed in a
	 * transient or slightly stale state.
	 *
	 * This is not a full validation of the link configuration. Even in
	 * serialized contexts, additional constraints (e.g. source limitations,
	 * bandwidth checks, and other atomic state dependencies) are only
	 * verified during the atomic check of the subsequent commit.
	 *
	 * max_link_limits only provides independent upper bounds for rate and
	 * lane count. Callers must not assume it is itself an allowed link
	 * configuration. Although that happens to be true for now, it will
	 * stop being guaranteed once fallback depends only on disabled configs.
	 */
	intel_dp_link_caps_get_max_limits(intel_dp->link.caps, &max_link_limits);

	if (link_rate == 0 ||
	    link_rate > max_link_limits.rate)
		return false;

	if (lane_count == 0 ||
	    lane_count > max_link_limits.lane_count)
		return false;

	return true;
}

static bool intel_dp_link_ok(struct intel_dp *intel_dp,
			     u8 link_status[DP_LINK_STATUS_SIZE])
{
	struct intel_display *display = to_intel_display(intel_dp);
	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
	bool uhbr = intel_dp->link_rate >= 1000000;
	bool ok;

	if (uhbr)
		ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
							  intel_dp->lane_count);
	else
		ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);

	if (ok)
		return true;

	intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
	drm_dbg_kms(display->drm,
		    "[ENCODER:%d:%s] %s link not ok, retraining\n",
		    encoder->base.base.id, encoder->base.name,
		    uhbr ? "128b/132b" : "8b/10b");

	return false;
}

static int
intel_dp_read_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
{
	int err;

	memset(link_status, 0, DP_LINK_STATUS_SIZE);

	if (intel_dp_mst_active_streams(intel_dp) > 0)
		err = drm_dp_dpcd_read_data(&intel_dp->aux, DP_LANE0_1_STATUS_ESI,
					    link_status, DP_LINK_STATUS_SIZE - 2);
	else
		err = drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
						       link_status);

	if (err)
		return err;

	if (link_status[DP_LANE_ALIGN_STATUS_UPDATED - DP_LANE0_1_STATUS] &
	    DP_DOWNSTREAM_PORT_STATUS_CHANGED)
		WRITE_ONCE(intel_dp->downstream_port_changed, true);

	return 0;
}

bool intel_dp_link_training_get_force_retrain(struct intel_dp_link_training *link_training)
{
	return link_training->force_retrain;
}

static void intel_dp_link_training_set_force_retrain(struct intel_dp_link_training *link_training,
						     bool forced)
{
	link_training->force_retrain = forced;
}

static bool
intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
{
	struct intel_dp_link_training *link_training = intel_dp->link.training;
	u8 link_status[DP_LINK_STATUS_SIZE];

	if (!intel_dp->link.active)
		return false;

	/*
	 * While PSR source HW is enabled, it will control main-link sending
	 * frames, enabling and disabling it so trying to do a retrain will fail
	 * as the link would or not be on or it could mix training patterns
	 * and frame data at the same time causing retrain to fail.
	 * Also when exiting PSR, HW will retrain the link anyways fixing
	 * any link status error.
	 */
	if (intel_psr_enabled(intel_dp))
		return false;

	if (intel_dp_link_training_get_force_retrain(link_training))
		return true;

	if (intel_dp_read_link_status(intel_dp, link_status) < 0)
		return false;

	/*
	 * Validate the cached values of intel_dp->link_rate and
	 * intel_dp->lane_count before attempting to retrain.
	 *
	 * FIXME would be nice to user the crtc state here, but since
	 * we need to call this from the short HPD handler that seems
	 * a bit hard.
	 */
	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
					intel_dp->lane_count))
		return false;

	if (!link_recovery_autoretrain_allowed(link_training))
		return false;

	if (link_recovery_autoretrain_pending(link_training))
		return true;

	/* Retrain if link not ok */
	return !intel_dp_link_ok(intel_dp, link_status) &&
		!intel_psr_link_ok(intel_dp);
}

static bool intel_dp_is_connected(struct intel_dp *intel_dp)
{
	struct intel_connector *connector = intel_dp->attached_connector;

	return connector->base.status == connector_status_connected ||
		intel_dp->is_mst;
}

static void queue_modeset_retry_for_links_in_state(struct intel_atomic_state *state,
						   struct intel_encoder *encoder,
						   u8 pipe_mask)
{
	const struct intel_crtc_state *crtc_state;
	struct intel_crtc *crtc;

	for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {
		if (!(BIT(crtc->pipe) & pipe_mask))
			continue;

		intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
	}
}

static int intel_dp_retrain_link(struct intel_encoder *encoder,
				 struct drm_modeset_acquire_ctx *ctx)
{
	struct intel_display *display = to_intel_display(encoder);
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
	struct intel_dp_link_training *link_training =
		intel_dp->link.training;
	struct intel_atomic_state *state;
	struct drm_atomic_commit *_state;
	u8 pipe_mask;
	int ret;

	if (!intel_dp_is_connected(intel_dp))
		return 0;

	ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
			       ctx);
	if (ret)
		return ret;

	if (!intel_dp_needs_link_retrain(intel_dp))
		return 0;

	ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
	if (ret)
		return ret;

	if (pipe_mask == 0)
		return 0;

	if (!intel_dp_needs_link_retrain(intel_dp))
		return 0;

	drm_dbg_kms(display->drm,
		    "[ENCODER:%d:%s] retraining link (forced %s)\n",
		    encoder->base.base.id, encoder->base.name,
		    str_yes_no(intel_dp_link_training_get_force_retrain(link_training)));

	_state = drm_atomic_commit_alloc(display->drm);
	if (!_state)
		return -ENOMEM;

	state = to_intel_atomic_state(_state);

	ret = intel_modeset_commit_pipes_for_atomic_state(state, pipe_mask, ctx);
	if (ret == -EDEADLK)
		goto out;

	intel_dp_link_training_set_force_retrain(link_training, false);

	if (ret) {
		drm_dbg_kms(display->drm,
			    "[ENCODER:%d:%s] link retraining failed: %pe\n",
			    encoder->base.base.id, encoder->base.name,
			    ERR_PTR(ret));
		/*
		 * intel_dp_needs_link_retrain() only performs a coarse check of
		 * retrainability, so the modeset commit may still fail. Disable
		 * further auto-retrain attempts in that case.
		 *
		 * A sink capability change may restore the retrainable state (see
		 * intel_dp_update_sink_caps(), intel_dp_reset_link_params()),
		 * allowing retraining to be attempted again.
		 */
		link_recovery_mark_autoretrain_modeset_failure(link_training);
		queue_modeset_retry_for_links_in_state(state, encoder, pipe_mask);
	}
out:
	drm_atomic_commit_put(&state->base);

	return ret;
}

void intel_dp_link_check(struct intel_encoder *encoder)
{
	struct drm_modeset_acquire_ctx ctx;
	int ret;

	intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
		ret = intel_dp_retrain_link(encoder, &ctx);
}

void intel_dp_check_link_state(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &dig_port->base;

	if (!intel_dp_is_connected(intel_dp))
		return;

	/*
	 * NOTE:
	 * This may race with an ongoing modeset updating the max link limits
	 * and, with that, the link's retrainability, so
	 * intel_dp_needs_link_retrain() may observe stale state.
	 *
	 * This is harmless: stale params captured as valid may spuriously
	 * allow retraining here, but the decision is rechecked later in a
	 * properly serialized context.
	 *
	 * Conversely, stale params captured as invalid may skip retraining,
	 * but that can only happen before the modeset has completed its own
	 * link training for the new, valid configuration, after which the
	 * link state is rechecked.
	 *
	 * See intel_dp_link_params_valid() for capturing and validating the
	 * params.
	 */
	if (!intel_dp_needs_link_retrain(intel_dp))
		return;

	intel_encoder_link_check_queue_work(encoder, 0);
}

static int i915_dp_force_link_training_failure_show(void *data, u64 *val)
{
	struct intel_connector *connector = to_intel_connector(data);
	struct intel_display *display = to_intel_display(connector);
	struct intel_dp_link_training *link_training = connector_to_link_training(connector);
	int err;

	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
	if (err)
		return err;

	intel_dp_flush_connector_commits(connector);

	*val = link_training->force_train_failure;

	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

	return 0;
}

static int i915_dp_force_link_training_failure_write(void *data, u64 val)
{
	struct intel_connector *connector = to_intel_connector(data);
	struct intel_display *display = to_intel_display(connector);
	struct intel_dp_link_training *link_training = connector_to_link_training(connector);
	int err;

	if (val > 2)
		return -EINVAL;

	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
	if (err)
		return err;

	intel_dp_flush_connector_commits(connector);

	link_training->force_train_failure = val;

	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

	return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops,
			 i915_dp_force_link_training_failure_show,
			 i915_dp_force_link_training_failure_write, "%llu\n");

static int i915_dp_force_link_retrain_show(void *data, u64 *val)
{
	struct intel_connector *connector = to_intel_connector(data);
	struct intel_display *display = to_intel_display(connector);
	struct intel_dp_link_training *link_training = connector_to_link_training(connector);
	int err;

	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
	if (err)
		return err;

	intel_dp_flush_connector_commits(connector);

	*val = intel_dp_link_training_get_force_retrain(link_training);

	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

	return 0;
}

static int i915_dp_force_link_retrain_write(void *data, u64 val)
{
	struct intel_connector *connector = to_intel_connector(data);
	struct intel_display *display = to_intel_display(connector);
	struct intel_dp_link_training *link_training = connector_to_link_training(connector);
	struct intel_dp *intel_dp = link_training->dp;
	int err;

	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
	if (err)
		return err;

	intel_dp_flush_connector_commits(connector);

	intel_dp_link_training_set_force_retrain(link_training, val);

	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

	intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));

	return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops,
			 i915_dp_force_link_retrain_show,
			 i915_dp_force_link_retrain_write, "%llu\n");

static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data)
{
	struct intel_connector *connector = to_intel_connector(m->private);
	struct intel_display *display = to_intel_display(connector);
	struct intel_dp_link_training *link_training = connector_to_link_training(connector);
	int err;

	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
	if (err)
		return err;

	intel_dp_flush_connector_commits(connector);

	/* TODO: Expose this via a debugfs entry reflecting what the state represents. */
	seq_printf(m, "%s\n", str_yes_no(link_recovery_has_no_fallback(link_training)));

	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(i915_dp_link_retrain_disabled);

void intel_dp_link_training_debugfs_add(struct intel_connector *connector)
{
	struct dentry *root = connector->base.debugfs_entry;

	if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort &&
	    connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
		return;

	debugfs_create_file("i915_dp_force_link_training_failure", 0644, root,
			    connector, &i915_dp_force_link_training_failure_fops);

	debugfs_create_file("i915_dp_force_link_retrain", 0644, root,
			    connector, &i915_dp_force_link_retrain_fops);

	debugfs_create_file("i915_dp_link_retrain_disabled", 0444, root,
			    connector, &i915_dp_link_retrain_disabled_fops);
}

void intel_dp_link_training_reset(struct intel_dp_link_training *link_training)
{
	link_recovery_reset(link_training);
}

struct intel_dp_link_training *intel_dp_link_training_init(struct intel_dp *intel_dp)
{
	struct intel_dp_link_training *link_training;

	link_training = kzalloc_obj(*link_training);
	if (!link_training)
		return NULL;

	link_training->dp = intel_dp;

	return link_training;
}

void intel_dp_link_training_cleanup(struct intel_dp_link_training *link_training)
{
	kfree(link_training);
}

#if IS_ENABLED(CONFIG_KUNIT)

#define __INIT_MEMBER(__name, __fn) \
	.__name = __fn,

#define INTEL_DP_LINK_TRAINING_TEST_OPS_INIT \
	INTEL_DP_LINK_TRAINING_TEST_OPS_MEMBERS(__INIT_MEMBER)

#ifdef I915

const struct intel_dp_link_training_test_ops i915_display_dp_link_training_test_ops = {
	INTEL_DP_LINK_TRAINING_TEST_OPS_INIT
};
EXPORT_SYMBOL_IF_KUNIT(i915_display_dp_link_training_test_ops);

#else

const struct intel_dp_link_training_test_ops intel_display_dp_link_training_test_ops = {
	INTEL_DP_LINK_TRAINING_TEST_OPS_INIT
};
EXPORT_SYMBOL_IF_KUNIT(intel_display_dp_link_training_test_ops);

#endif	/* I915 */

#undef INTEL_DP_LINK_TRAINING_TEST_OPS_INIT
#undef __INIT_MEMBER

#endif	/* CONFIG_KUNIT */