1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/seq_buf.h> 30 #include <linux/string_helpers.h> 31 32 #include <drm/display/drm_dp_helper.h> 33 #include <drm/display/drm_scdc_helper.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_privacy_screen_consumer.h> 36 #include <drm/intel/step.h> 37 38 #include "icl_dsi.h" 39 #include "intel_alpm.h" 40 #include "intel_audio.h" 41 #include "intel_audio_regs.h" 42 #include "intel_backlight.h" 43 #include "intel_combo_phy.h" 44 #include "intel_combo_phy_regs.h" 45 #include "intel_connector.h" 46 #include "intel_crtc.h" 47 #include "intel_cx0_phy.h" 48 #include "intel_cx0_phy_regs.h" 49 #include "intel_ddi.h" 50 #include "intel_ddi_buf_trans.h" 51 #include "intel_de.h" 52 #include "intel_dip.h" 53 #include "intel_display_power.h" 54 #include "intel_display_regs.h" 55 #include "intel_display_types.h" 56 #include "intel_display_utils.h" 57 #include "intel_display_wa.h" 58 #include "intel_dkl_phy.h" 59 #include "intel_dkl_phy_regs.h" 60 #include "intel_dp.h" 61 #include "intel_dp_aux.h" 62 #include "intel_dp_link_training.h" 63 #include "intel_dp_mst.h" 64 #include "intel_dp_test.h" 65 #include "intel_dp_tunnel.h" 66 #include "intel_dpio_phy.h" 67 #include "intel_dsi.h" 68 #include "intel_encoder.h" 69 #include "intel_fdi.h" 70 #include "intel_fifo_underrun.h" 71 #include "intel_gmbus.h" 72 #include "intel_hdcp.h" 73 #include "intel_hdmi.h" 74 #include "intel_hotplug.h" 75 #include "intel_hti.h" 76 #include "intel_lspcon.h" 77 #include "intel_lt_phy.h" 78 #include "intel_mg_phy_regs.h" 79 #include "intel_modeset_lock.h" 80 #include "intel_panel.h" 81 #include "intel_pfit.h" 82 #include "intel_pps.h" 83 #include "intel_psr.h" 84 #include "intel_quirks.h" 85 #include "intel_snps_phy.h" 86 #include "intel_tc.h" 87 #include "intel_vdsc.h" 88 #include "intel_vdsc_regs.h" 89 #include "intel_vrr.h" 90 #include "skl_scaler.h" 91 #include "skl_universal_plane.h" 92 93 struct intel_dpll; 94 95 static const u8 index_to_dp_signal_levels[] = { 96 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 97 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 98 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 99 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 100 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 101 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 102 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 103 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 104 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 105 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 106 }; 107 108 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 109 const struct intel_ddi_buf_trans *trans) 110 { 111 int level; 112 113 level = intel_bios_hdmi_level_shift(encoder->devdata); 114 if (level < 0) 115 level = trans->hdmi_default_entry; 116 117 return level; 118 } 119 120 static bool has_buf_trans_select(struct intel_display *display) 121 { 122 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 123 } 124 125 static bool has_iboost(struct intel_display *display) 126 { 127 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 128 } 129 130 /* 131 * Starting with Haswell, DDI port buffers must be programmed with correct 132 * values in advance. This function programs the correct values for 133 * DP/eDP/FDI use cases. 134 */ 135 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 136 const struct intel_crtc_state *crtc_state) 137 { 138 struct intel_display *display = to_intel_display(encoder); 139 u32 iboost_bit = 0; 140 int i, n_entries; 141 enum port port = encoder->port; 142 const struct intel_ddi_buf_trans *trans; 143 144 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 145 if (drm_WARN_ON_ONCE(display->drm, !trans)) 146 return; 147 148 /* If we're boosting the current, set bit 31 of trans1 */ 149 if (has_iboost(display) && 150 intel_bios_dp_boost_level(encoder->devdata)) 151 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 152 153 for (i = 0; i < n_entries; i++) { 154 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 155 trans->entries[i].hsw.trans1 | iboost_bit); 156 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 157 trans->entries[i].hsw.trans2); 158 } 159 } 160 161 /* 162 * Starting with Haswell, DDI port buffers must be programmed with correct 163 * values in advance. This function programs the correct values for 164 * HDMI/DVI use cases. 165 */ 166 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 167 const struct intel_crtc_state *crtc_state) 168 { 169 struct intel_display *display = to_intel_display(encoder); 170 int level = intel_ddi_level(encoder, crtc_state, 0); 171 u32 iboost_bit = 0; 172 int n_entries; 173 enum port port = encoder->port; 174 const struct intel_ddi_buf_trans *trans; 175 176 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 177 if (drm_WARN_ON_ONCE(display->drm, !trans)) 178 return; 179 180 /* If we're boosting the current, set bit 31 of trans1 */ 181 if (has_iboost(display) && 182 intel_bios_hdmi_boost_level(encoder->devdata)) 183 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 184 185 /* Entry 9 is for HDMI: */ 186 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 187 trans->entries[level].hsw.trans1 | iboost_bit); 188 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 189 trans->entries[level].hsw.trans2); 190 } 191 192 static intel_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 193 { 194 if (DISPLAY_VER(display) >= 14) 195 return XELPDP_PORT_BUF_CTL1(display, port); 196 else 197 return DDI_BUF_CTL(port); 198 } 199 200 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 201 { 202 /* 203 * Bspec's platform specific timeouts: 204 * MTL+ : 100 us 205 * BXT : fixed 16 us 206 * HSW-ADL: 8 us 207 * 208 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 209 */ 210 if (display->platform.broxton) { 211 udelay(16); 212 return; 213 } 214 215 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 216 if (intel_de_wait_for_set_ms(display, intel_ddi_buf_status_reg(display, port), 217 DDI_BUF_IS_IDLE, 10)) 218 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 219 port_name(port)); 220 } 221 222 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 223 { 224 struct intel_display *display = to_intel_display(encoder); 225 enum port port = encoder->port; 226 227 /* 228 * Bspec's platform specific timeouts: 229 * MTL+ : 10000 us 230 * DG2 : 1200 us 231 * TGL-ADL combo PHY: 1000 us 232 * TGL-ADL TypeC PHY: 3000 us 233 * HSW-ICL : fixed 518 us 234 */ 235 if (DISPLAY_VER(display) < 10) { 236 usleep_range(518, 1000); 237 return; 238 } 239 240 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 241 if (intel_de_wait_for_clear_ms(display, intel_ddi_buf_status_reg(display, port), 242 DDI_BUF_IS_IDLE, 10)) 243 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 244 port_name(port)); 245 } 246 247 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll) 248 { 249 switch (pll->info->id) { 250 case DPLL_ID_WRPLL1: 251 return PORT_CLK_SEL_WRPLL1; 252 case DPLL_ID_WRPLL2: 253 return PORT_CLK_SEL_WRPLL2; 254 case DPLL_ID_SPLL: 255 return PORT_CLK_SEL_SPLL; 256 case DPLL_ID_LCPLL_810: 257 return PORT_CLK_SEL_LCPLL_810; 258 case DPLL_ID_LCPLL_1350: 259 return PORT_CLK_SEL_LCPLL_1350; 260 case DPLL_ID_LCPLL_2700: 261 return PORT_CLK_SEL_LCPLL_2700; 262 default: 263 MISSING_CASE(pll->info->id); 264 return PORT_CLK_SEL_NONE; 265 } 266 } 267 268 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 269 const struct intel_crtc_state *crtc_state) 270 { 271 const struct intel_dpll *pll = crtc_state->intel_dpll; 272 int clock = crtc_state->port_clock; 273 const enum intel_dpll_id id = pll->info->id; 274 275 switch (id) { 276 default: 277 /* 278 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 279 * here, so do warn if this get passed in 280 */ 281 MISSING_CASE(id); 282 return DDI_CLK_SEL_NONE; 283 case DPLL_ID_ICL_TBTPLL: 284 switch (clock) { 285 case 162000: 286 return DDI_CLK_SEL_TBT_162; 287 case 270000: 288 return DDI_CLK_SEL_TBT_270; 289 case 540000: 290 return DDI_CLK_SEL_TBT_540; 291 case 810000: 292 return DDI_CLK_SEL_TBT_810; 293 default: 294 MISSING_CASE(clock); 295 return DDI_CLK_SEL_NONE; 296 } 297 case DPLL_ID_ICL_MGPLL1: 298 case DPLL_ID_ICL_MGPLL2: 299 case DPLL_ID_ICL_MGPLL3: 300 case DPLL_ID_ICL_MGPLL4: 301 case DPLL_ID_TGL_MGPLL5: 302 case DPLL_ID_TGL_MGPLL6: 303 return DDI_CLK_SEL_MG; 304 } 305 } 306 307 static u32 ddi_buf_phy_link_rate(int port_clock) 308 { 309 switch (port_clock) { 310 case 162000: 311 return DDI_BUF_PHY_LINK_RATE(0); 312 case 216000: 313 return DDI_BUF_PHY_LINK_RATE(4); 314 case 243000: 315 return DDI_BUF_PHY_LINK_RATE(5); 316 case 270000: 317 return DDI_BUF_PHY_LINK_RATE(1); 318 case 324000: 319 return DDI_BUF_PHY_LINK_RATE(6); 320 case 432000: 321 return DDI_BUF_PHY_LINK_RATE(7); 322 case 540000: 323 return DDI_BUF_PHY_LINK_RATE(2); 324 case 810000: 325 return DDI_BUF_PHY_LINK_RATE(3); 326 default: 327 MISSING_CASE(port_clock); 328 return DDI_BUF_PHY_LINK_RATE(0); 329 } 330 } 331 332 static int dp_phy_lane_stagger_delay(int port_clock) 333 { 334 /* 335 * Return the number of symbol clocks delay used to stagger the 336 * assertion/desassertion of the port lane enables. The target delay 337 * time is 100 ns or greater, return the number of symbols specific to 338 * the provided port_clock (aka link clock) corresponding to this delay 339 * time, i.e. so that 340 * 341 * number_of_symbols * duration_of_one_symbol >= 100 ns 342 * 343 * The delay must be applied only on TypeC DP outputs, for everything else 344 * the delay must be set to 0. 345 * 346 * Return the number of link symbols per 100 ns: 347 * port_clock (10 kHz) -> bits / 100 us 348 * / symbol_size -> symbols / 100 us 349 * / 1000 -> symbols / 100 ns 350 */ 351 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 352 } 353 354 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 355 const struct intel_crtc_state *crtc_state) 356 { 357 struct intel_display *display = to_intel_display(encoder); 358 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 359 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 360 361 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 362 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 363 DDI_BUF_TRANS_SELECT(0); 364 365 if (dig_port->lane_reversal) 366 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 367 if (dig_port->ddi_a_4_lanes) 368 intel_dp->DP |= DDI_A_4_LANES; 369 370 if (DISPLAY_VER(display) >= 14) { 371 if (intel_dp_is_uhbr(crtc_state)) 372 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 373 else 374 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 375 } 376 377 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 378 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 379 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 380 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 381 } 382 383 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 384 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 385 386 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 387 } 388 } 389 390 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 391 { 392 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 393 394 switch (val) { 395 case DDI_CLK_SEL_NONE: 396 return 0; 397 case DDI_CLK_SEL_TBT_162: 398 return 162000; 399 case DDI_CLK_SEL_TBT_270: 400 return 270000; 401 case DDI_CLK_SEL_TBT_540: 402 return 540000; 403 case DDI_CLK_SEL_TBT_810: 404 return 810000; 405 default: 406 MISSING_CASE(val); 407 return 0; 408 } 409 } 410 411 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 412 { 413 /* CRT dotclock is determined via other means */ 414 if (pipe_config->has_pch_encoder) 415 return; 416 417 pipe_config->hw.adjusted_mode.crtc_clock = 418 intel_crtc_dotclock(pipe_config); 419 } 420 421 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 422 const struct drm_connector_state *conn_state) 423 { 424 struct intel_display *display = to_intel_display(crtc_state); 425 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 426 u32 temp; 427 428 if (!intel_crtc_has_dp_encoder(crtc_state)) 429 return; 430 431 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 432 433 temp = DP_MSA_MISC_SYNC_CLOCK; 434 435 switch (crtc_state->pipe_bpp) { 436 case 18: 437 temp |= DP_MSA_MISC_6_BPC; 438 break; 439 case 24: 440 temp |= DP_MSA_MISC_8_BPC; 441 break; 442 case 30: 443 temp |= DP_MSA_MISC_10_BPC; 444 break; 445 case 36: 446 temp |= DP_MSA_MISC_12_BPC; 447 break; 448 default: 449 MISSING_CASE(crtc_state->pipe_bpp); 450 break; 451 } 452 453 /* nonsense combination */ 454 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 455 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 456 457 if (crtc_state->limited_color_range) 458 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 459 460 /* 461 * As per DP 1.2 spec section 2.3.4.3 while sending 462 * YCBCR 444 signals we should program MSA MISC1/0 fields with 463 * colorspace information. 464 */ 465 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 466 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 467 468 /* 469 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 470 * of Color Encoding Format and Content Color Gamut] while sending 471 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 472 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 473 * Only set the delegation bit when the content needs it and 474 * the sink advertises support. 475 */ 476 if (intel_dp_needs_vsc_colorimetry(crtc_state, conn_state)) 477 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 478 479 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 480 temp); 481 } 482 483 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 484 { 485 if (master_transcoder == TRANSCODER_EDP) 486 return 0; 487 else 488 return master_transcoder + 1; 489 } 490 491 static void 492 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 493 bool enable) 494 { 495 struct intel_display *display = to_intel_display(crtc_state); 496 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 497 u32 val = 0; 498 499 if (!HAS_DP20(display)) 500 return; 501 502 if (enable && intel_dp_is_uhbr(crtc_state)) 503 val = TRANS_DP2_128B132B_CHANNEL_CODING; 504 505 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 506 } 507 508 /* 509 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 510 * 511 * Only intended to be used by intel_ddi_enable_transcoder_func() and 512 * intel_ddi_config_transcoder_func(). 513 */ 514 static u32 515 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 516 const struct intel_crtc_state *crtc_state) 517 { 518 struct intel_display *display = to_intel_display(crtc_state); 519 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 520 enum pipe pipe = crtc->pipe; 521 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 522 enum port port = encoder->port; 523 u32 temp; 524 525 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 526 temp = TRANS_DDI_FUNC_ENABLE; 527 if (DISPLAY_VER(display) >= 12) 528 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 529 else 530 temp |= TRANS_DDI_SELECT_PORT(port); 531 532 switch (crtc_state->pipe_bpp) { 533 default: 534 MISSING_CASE(crtc_state->pipe_bpp); 535 fallthrough; 536 case 18: 537 temp |= TRANS_DDI_BPC_6; 538 break; 539 case 24: 540 temp |= TRANS_DDI_BPC_8; 541 break; 542 case 30: 543 temp |= TRANS_DDI_BPC_10; 544 break; 545 case 36: 546 temp |= TRANS_DDI_BPC_12; 547 break; 548 } 549 550 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 551 temp |= TRANS_DDI_PVSYNC; 552 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 553 temp |= TRANS_DDI_PHSYNC; 554 555 if (cpu_transcoder == TRANSCODER_EDP) { 556 switch (pipe) { 557 default: 558 MISSING_CASE(pipe); 559 fallthrough; 560 case PIPE_A: 561 /* On Haswell, can only use the always-on power well for 562 * eDP when not using the panel fitter, and when not 563 * using motion blur mitigation (which we don't 564 * support). */ 565 if (crtc_state->pch_pfit.force_thru) 566 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 567 else 568 temp |= TRANS_DDI_EDP_INPUT_A_ON; 569 break; 570 case PIPE_B: 571 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 572 break; 573 case PIPE_C: 574 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 575 break; 576 } 577 } 578 579 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 580 if (crtc_state->has_hdmi_sink) 581 temp |= TRANS_DDI_MODE_SELECT_HDMI; 582 else 583 temp |= TRANS_DDI_MODE_SELECT_DVI; 584 585 if (crtc_state->hdmi_scrambling) 586 temp |= TRANS_DDI_HDMI_SCRAMBLING; 587 if (crtc_state->hdmi_high_tmds_clock_ratio) 588 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 589 if (DISPLAY_VER(display) >= 14) 590 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 591 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 592 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 593 temp |= (crtc_state->fdi_lanes - 1) << 1; 594 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 595 intel_dp_is_uhbr(crtc_state)) { 596 if (intel_dp_is_uhbr(crtc_state)) 597 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 598 else 599 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 600 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 601 602 if (DISPLAY_VER(display) >= 12) { 603 enum transcoder master; 604 605 master = crtc_state->mst_master_transcoder; 606 if (drm_WARN_ON(display->drm, 607 master == INVALID_TRANSCODER)) 608 master = TRANSCODER_A; 609 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 610 } 611 } else { 612 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 613 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 614 } 615 616 if (IS_DISPLAY_VER(display, 8, 10) && 617 crtc_state->master_transcoder != INVALID_TRANSCODER) { 618 u8 master_select = 619 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 620 621 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 622 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 623 } 624 625 return temp; 626 } 627 628 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 629 const struct intel_crtc_state *crtc_state) 630 { 631 struct intel_display *display = to_intel_display(crtc_state); 632 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 633 634 if (DISPLAY_VER(display) >= 11) { 635 enum transcoder master_transcoder = crtc_state->master_transcoder; 636 u32 ctl2 = 0; 637 638 if (master_transcoder != INVALID_TRANSCODER) { 639 u8 master_select = 640 bdw_trans_port_sync_master_select(master_transcoder); 641 642 ctl2 |= PORT_SYNC_MODE_ENABLE | 643 PORT_SYNC_MODE_MASTER_SELECT(master_select); 644 } 645 646 intel_de_write(display, 647 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 648 ctl2); 649 } 650 651 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 652 intel_ddi_transcoder_func_reg_val_get(encoder, 653 crtc_state)); 654 } 655 656 /* 657 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 658 * bit for the DDI function and enables the DP2 configuration. Called for all 659 * transcoder types. 660 */ 661 void 662 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 663 const struct intel_crtc_state *crtc_state) 664 { 665 struct intel_display *display = to_intel_display(crtc_state); 666 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 667 u32 ctl; 668 669 intel_ddi_config_transcoder_dp2(crtc_state, true); 670 671 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 672 ctl &= ~TRANS_DDI_FUNC_ENABLE; 673 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 674 ctl); 675 } 676 677 /* 678 * Disable the DDI function and port syncing. 679 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 680 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 681 * transcoders these are done later in intel_ddi_post_disable_dp(). 682 */ 683 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 684 { 685 struct intel_display *display = to_intel_display(crtc_state); 686 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 687 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 688 u32 ctl; 689 690 if (DISPLAY_VER(display) >= 11) 691 intel_de_write(display, 692 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 693 0); 694 695 ctl = intel_de_read(display, 696 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 697 698 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 699 700 ctl &= ~TRANS_DDI_FUNC_ENABLE; 701 702 if (IS_DISPLAY_VER(display, 8, 10)) 703 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 704 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 705 706 if (DISPLAY_VER(display) >= 12) { 707 if (!intel_dp_mst_is_master_trans(crtc_state)) { 708 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 709 TRANS_DDI_MODE_SELECT_MASK); 710 } 711 } else { 712 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 713 } 714 715 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 716 ctl); 717 718 if (intel_dp_mst_is_slave_trans(crtc_state)) 719 intel_ddi_config_transcoder_dp2(crtc_state, false); 720 721 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 722 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 723 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 724 /* Quirk time at 100ms for reliable operation */ 725 msleep(100); 726 } 727 } 728 729 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 730 enum transcoder cpu_transcoder, 731 bool enable, u32 hdcp_mask) 732 { 733 struct intel_display *display = to_intel_display(intel_encoder); 734 struct ref_tracker *wakeref; 735 int ret = 0; 736 737 wakeref = intel_display_power_get_if_enabled(display, 738 intel_encoder->power_domain); 739 if (drm_WARN_ON(display->drm, !wakeref)) 740 return -ENXIO; 741 742 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 743 hdcp_mask, enable ? hdcp_mask : 0); 744 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 745 return ret; 746 } 747 748 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 749 { 750 struct intel_display *display = to_intel_display(intel_connector); 751 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 752 int type = intel_connector->base.connector_type; 753 enum port port = encoder->port; 754 enum transcoder cpu_transcoder; 755 struct ref_tracker *wakeref; 756 enum pipe pipe = 0; 757 u32 ddi_mode; 758 bool ret; 759 760 wakeref = intel_display_power_get_if_enabled(display, 761 encoder->power_domain); 762 if (!wakeref) 763 return false; 764 765 /* Note: This returns false for DP MST primary encoders. */ 766 if (!encoder->get_hw_state(encoder, &pipe)) { 767 ret = false; 768 goto out; 769 } 770 771 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 772 cpu_transcoder = TRANSCODER_EDP; 773 else 774 cpu_transcoder = (enum transcoder) pipe; 775 776 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 777 TRANS_DDI_MODE_SELECT_MASK; 778 779 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 780 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 781 ret = type == DRM_MODE_CONNECTOR_HDMIA; 782 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 783 ret = type == DRM_MODE_CONNECTOR_VGA; 784 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 785 ret = type == DRM_MODE_CONNECTOR_eDP || 786 type == DRM_MODE_CONNECTOR_DisplayPort; 787 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 788 /* 789 * encoder->get_hw_state() should have bailed out on MST. This 790 * must be SST and non-eDP. 791 */ 792 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 793 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 794 /* encoder->get_hw_state() should have bailed out on MST. */ 795 ret = false; 796 } else { 797 ret = false; 798 } 799 800 out: 801 intel_display_power_put(display, encoder->power_domain, wakeref); 802 803 return ret; 804 } 805 806 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 807 u8 *pipe_mask, bool *is_dp_mst) 808 { 809 struct intel_display *display = to_intel_display(encoder); 810 enum port port = encoder->port; 811 struct ref_tracker *wakeref; 812 enum pipe p; 813 u32 tmp; 814 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 815 816 *pipe_mask = 0; 817 *is_dp_mst = false; 818 819 wakeref = intel_display_power_get_if_enabled(display, 820 encoder->power_domain); 821 if (!wakeref) 822 return; 823 824 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 825 if (!(tmp & DDI_BUF_CTL_ENABLE)) 826 goto out; 827 828 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 829 tmp = intel_de_read(display, 830 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 831 832 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 833 default: 834 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 835 fallthrough; 836 case TRANS_DDI_EDP_INPUT_A_ON: 837 case TRANS_DDI_EDP_INPUT_A_ONOFF: 838 *pipe_mask = BIT(PIPE_A); 839 break; 840 case TRANS_DDI_EDP_INPUT_B_ONOFF: 841 *pipe_mask = BIT(PIPE_B); 842 break; 843 case TRANS_DDI_EDP_INPUT_C_ONOFF: 844 *pipe_mask = BIT(PIPE_C); 845 break; 846 } 847 848 goto out; 849 } 850 851 for_each_pipe(display, p) { 852 enum transcoder cpu_transcoder = (enum transcoder)p; 853 u32 port_mask, ddi_select, ddi_mode; 854 struct ref_tracker *trans_wakeref; 855 856 trans_wakeref = intel_display_power_get_if_enabled(display, 857 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 858 if (!trans_wakeref) 859 continue; 860 861 if (DISPLAY_VER(display) >= 12) { 862 port_mask = TGL_TRANS_DDI_PORT_MASK; 863 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 864 } else { 865 port_mask = TRANS_DDI_PORT_MASK; 866 ddi_select = TRANS_DDI_SELECT_PORT(port); 867 } 868 869 tmp = intel_de_read(display, 870 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 871 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 872 trans_wakeref); 873 874 if ((tmp & port_mask) != ddi_select) 875 continue; 876 877 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 878 879 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 880 mst_pipe_mask |= BIT(p); 881 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 882 dp128b132b_pipe_mask |= BIT(p); 883 884 *pipe_mask |= BIT(p); 885 } 886 887 if (!*pipe_mask) 888 drm_dbg_kms(display->drm, 889 "No pipe for [ENCODER:%d:%s] found\n", 890 encoder->base.base.id, encoder->base.name); 891 892 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 893 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 894 895 /* 896 * If we don't have 8b/10b MST, but have more than one 897 * transcoder in 128b/132b mode, we know it must be 128b/132b 898 * MST. 899 * 900 * Otherwise, we fall back to checking the current MST 901 * state. It's not accurate for hardware takeover at probe, but 902 * we don't expect MST to have been enabled at that point, and 903 * can assume it's SST. 904 */ 905 if (hweight8(dp128b132b_pipe_mask) > 1 || 906 intel_dp_mst_active_streams(intel_dp)) 907 mst_pipe_mask = dp128b132b_pipe_mask; 908 } 909 910 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 911 drm_dbg_kms(display->drm, 912 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 913 encoder->base.base.id, encoder->base.name, 914 *pipe_mask); 915 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 916 } 917 918 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 919 drm_dbg_kms(display->drm, 920 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 921 encoder->base.base.id, encoder->base.name, 922 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 923 else 924 *is_dp_mst = mst_pipe_mask; 925 926 out: 927 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 928 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 929 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 930 BXT_PHY_LANE_POWERDOWN_ACK | 931 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 932 drm_err(display->drm, 933 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 934 encoder->base.base.id, encoder->base.name, tmp); 935 } 936 937 intel_display_power_put(display, encoder->power_domain, wakeref); 938 } 939 940 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 941 enum pipe *pipe) 942 { 943 u8 pipe_mask; 944 bool is_mst; 945 946 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 947 948 if (is_mst || !pipe_mask) 949 return false; 950 951 *pipe = ffs(pipe_mask) - 1; 952 953 return true; 954 } 955 956 static enum intel_display_power_domain 957 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 958 const struct intel_crtc_state *crtc_state) 959 { 960 struct intel_display *display = to_intel_display(dig_port); 961 962 /* 963 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 964 * DC states enabled at the same time, while for driver initiated AUX 965 * transfers we need the same AUX IOs to be powered but with DC states 966 * disabled. Accordingly use the AUX_IO_<port> power domain here which 967 * leaves DC states enabled. 968 * 969 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 970 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 971 * well, so we can acquire a wider AUX_<port> power domain reference 972 * instead of a specific AUX_IO_<port> reference without powering up any 973 * extra wells. 974 */ 975 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 976 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 977 else if (DISPLAY_VER(display) < 14 && 978 (intel_crtc_has_dp_encoder(crtc_state) || 979 intel_encoder_is_tc(&dig_port->base))) 980 return intel_aux_power_domain(dig_port); 981 else 982 return POWER_DOMAIN_INVALID; 983 } 984 985 static void 986 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 987 const struct intel_crtc_state *crtc_state) 988 { 989 struct intel_display *display = to_intel_display(dig_port); 990 enum intel_display_power_domain domain = 991 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 992 993 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 994 995 if (domain == POWER_DOMAIN_INVALID) 996 return; 997 998 dig_port->aux_wakeref = intel_display_power_get(display, domain); 999 } 1000 1001 static void 1002 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 1003 const struct intel_crtc_state *crtc_state) 1004 { 1005 struct intel_display *display = to_intel_display(dig_port); 1006 enum intel_display_power_domain domain = 1007 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 1008 struct ref_tracker *wf; 1009 1010 wf = fetch_and_zero(&dig_port->aux_wakeref); 1011 if (!wf) 1012 return; 1013 1014 intel_display_power_put(display, domain, wf); 1015 } 1016 1017 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1018 struct intel_crtc_state *crtc_state) 1019 { 1020 struct intel_display *display = to_intel_display(encoder); 1021 struct intel_digital_port *dig_port; 1022 1023 /* 1024 * TODO: Add support for MST encoders. Atm, the following should never 1025 * happen since fake-MST encoders don't set their get_power_domains() 1026 * hook. 1027 */ 1028 if (drm_WARN_ON(display->drm, 1029 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1030 return; 1031 1032 dig_port = enc_to_dig_port(encoder); 1033 1034 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1035 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1036 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1037 dig_port->ddi_io_power_domain); 1038 } 1039 1040 main_link_aux_power_domain_get(dig_port, crtc_state); 1041 } 1042 1043 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1044 const struct intel_crtc_state *crtc_state) 1045 { 1046 struct intel_display *display = to_intel_display(crtc_state); 1047 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1048 enum phy phy = intel_encoder_to_phy(encoder); 1049 u32 val; 1050 1051 if (cpu_transcoder == TRANSCODER_EDP) 1052 return; 1053 1054 if (DISPLAY_VER(display) >= 13) 1055 val = TGL_TRANS_CLK_SEL_PORT(phy); 1056 else if (DISPLAY_VER(display) >= 12) 1057 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1058 else 1059 val = TRANS_CLK_SEL_PORT(encoder->port); 1060 1061 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1062 } 1063 1064 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1065 { 1066 struct intel_display *display = to_intel_display(crtc_state); 1067 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1068 u32 val; 1069 1070 if (cpu_transcoder == TRANSCODER_EDP) 1071 return; 1072 1073 if (DISPLAY_VER(display) >= 12) 1074 val = TGL_TRANS_CLK_SEL_DISABLED; 1075 else 1076 val = TRANS_CLK_SEL_DISABLED; 1077 1078 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1079 } 1080 1081 static void _skl_ddi_set_iboost(struct intel_display *display, 1082 enum port port, u8 iboost) 1083 { 1084 u32 tmp; 1085 1086 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1087 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1088 if (iboost) 1089 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1090 else 1091 tmp |= BALANCE_LEG_DISABLE(port); 1092 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1093 } 1094 1095 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1096 const struct intel_crtc_state *crtc_state, 1097 int level) 1098 { 1099 struct intel_display *display = to_intel_display(encoder); 1100 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1101 u8 iboost; 1102 1103 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1104 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1105 else 1106 iboost = intel_bios_dp_boost_level(encoder->devdata); 1107 1108 if (iboost == 0) { 1109 const struct intel_ddi_buf_trans *trans; 1110 int n_entries; 1111 1112 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1113 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1114 return; 1115 1116 iboost = trans->entries[level].hsw.i_boost; 1117 } 1118 1119 /* Make sure that the requested I_boost is valid */ 1120 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1121 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1122 return; 1123 } 1124 1125 _skl_ddi_set_iboost(display, encoder->port, iboost); 1126 1127 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1128 _skl_ddi_set_iboost(display, PORT_E, iboost); 1129 } 1130 1131 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1132 const struct intel_crtc_state *crtc_state) 1133 { 1134 struct intel_display *display = to_intel_display(intel_dp); 1135 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1136 int n_entries; 1137 1138 intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1139 1140 if (drm_WARN_ON(display->drm, n_entries < 1)) 1141 n_entries = 1; 1142 if (drm_WARN_ON(display->drm, 1143 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1144 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1145 1146 return index_to_dp_signal_levels[n_entries - 1] & 1147 DP_TRAIN_VOLTAGE_SWING_MASK; 1148 } 1149 1150 /* 1151 * We assume that the full set of pre-emphasis values can be 1152 * used on all DDI platforms. Should that change we need to 1153 * rethink this code. 1154 */ 1155 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1156 { 1157 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1158 } 1159 1160 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1161 int lane) 1162 { 1163 if (crtc_state->port_clock > 600000) 1164 return 0; 1165 1166 if (crtc_state->lane_count == 4) 1167 return lane >= 1 ? LOADGEN_SELECT : 0; 1168 else 1169 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1170 } 1171 1172 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1173 const struct intel_crtc_state *crtc_state) 1174 { 1175 struct intel_display *display = to_intel_display(encoder); 1176 const struct intel_ddi_buf_trans *trans; 1177 enum phy phy = intel_encoder_to_phy(encoder); 1178 int n_entries, ln; 1179 u32 val; 1180 1181 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1182 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1183 return; 1184 1185 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1186 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1187 1188 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1189 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1190 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1191 intel_dp->hobl_active ? val : 0); 1192 } 1193 1194 /* Set PORT_TX_DW5 */ 1195 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1196 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1197 COEFF_POLARITY | CURSOR_PROGRAM | 1198 TAP2_DISABLE | TAP3_DISABLE); 1199 val |= SCALING_MODE_SEL(0x2); 1200 val |= RTERM_SELECT(0x6); 1201 val |= TAP3_DISABLE; 1202 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1203 1204 /* Program PORT_TX_DW2 */ 1205 for (ln = 0; ln < 4; ln++) { 1206 int level = intel_ddi_level(encoder, crtc_state, ln); 1207 1208 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1209 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1210 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1211 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1212 RCOMP_SCALAR(0x98)); 1213 } 1214 1215 /* Program PORT_TX_DW4 */ 1216 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1217 for (ln = 0; ln < 4; ln++) { 1218 int level = intel_ddi_level(encoder, crtc_state, ln); 1219 1220 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1221 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1222 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1223 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1224 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1225 } 1226 1227 /* Program PORT_TX_DW7 */ 1228 for (ln = 0; ln < 4; ln++) { 1229 int level = intel_ddi_level(encoder, crtc_state, ln); 1230 1231 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1232 N_SCALAR_MASK, 1233 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1234 } 1235 } 1236 1237 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1238 const struct intel_crtc_state *crtc_state) 1239 { 1240 struct intel_display *display = to_intel_display(encoder); 1241 enum phy phy = intel_encoder_to_phy(encoder); 1242 u32 val; 1243 int ln; 1244 1245 /* 1246 * 1. If port type is eDP or DP, 1247 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1248 * else clear to 0b. 1249 */ 1250 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1251 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1252 val &= ~COMMON_KEEPER_EN; 1253 else 1254 val |= COMMON_KEEPER_EN; 1255 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1256 1257 /* 2. Program loadgen select */ 1258 /* 1259 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1260 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1261 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1262 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1263 */ 1264 for (ln = 0; ln < 4; ln++) { 1265 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1266 LOADGEN_SELECT, 1267 icl_combo_phy_loadgen_select(crtc_state, ln)); 1268 } 1269 1270 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1271 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1272 0, SUS_CLOCK_CONFIG); 1273 1274 /* 4. Clear training enable to change swing values */ 1275 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1276 val &= ~TX_TRAINING_EN; 1277 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1278 1279 /* 5. Program swing and de-emphasis */ 1280 icl_ddi_combo_vswing_program(encoder, crtc_state); 1281 1282 /* 6. Set training enable to trigger update */ 1283 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1284 val |= TX_TRAINING_EN; 1285 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1286 } 1287 1288 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1289 const struct intel_crtc_state *crtc_state) 1290 { 1291 struct intel_display *display = to_intel_display(encoder); 1292 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1293 const struct intel_ddi_buf_trans *trans; 1294 int n_entries, ln; 1295 1296 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1297 return; 1298 1299 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1300 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1301 return; 1302 1303 for (ln = 0; ln < 2; ln++) { 1304 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1305 CRI_USE_FS32, 0); 1306 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1307 CRI_USE_FS32, 0); 1308 } 1309 1310 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1311 for (ln = 0; ln < 2; ln++) { 1312 int level; 1313 1314 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1315 1316 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1317 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1318 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1319 1320 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1321 1322 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1323 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1324 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1325 } 1326 1327 /* Program MG_TX_DRVCTRL with values from vswing table */ 1328 for (ln = 0; ln < 2; ln++) { 1329 int level; 1330 1331 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1332 1333 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1334 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1335 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1336 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1337 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1338 CRI_TXDEEMPH_OVERRIDE_EN); 1339 1340 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1341 1342 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1343 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1344 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1345 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1346 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1347 CRI_TXDEEMPH_OVERRIDE_EN); 1348 1349 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1350 } 1351 1352 /* 1353 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1354 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1355 * values from table for which TX1 and TX2 enabled. 1356 */ 1357 for (ln = 0; ln < 2; ln++) { 1358 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1359 CFG_LOW_RATE_LKREN_EN, 1360 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1361 } 1362 1363 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1364 for (ln = 0; ln < 2; ln++) { 1365 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1366 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1367 CFG_AMI_CK_DIV_OVERRIDE_EN, 1368 crtc_state->port_clock > 500000 ? 1369 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1370 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1371 1372 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1373 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1374 CFG_AMI_CK_DIV_OVERRIDE_EN, 1375 crtc_state->port_clock > 500000 ? 1376 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1377 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1378 } 1379 1380 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1381 for (ln = 0; ln < 2; ln++) { 1382 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1383 0, CRI_CALCINIT); 1384 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1385 0, CRI_CALCINIT); 1386 } 1387 } 1388 1389 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1390 const struct intel_crtc_state *crtc_state) 1391 { 1392 struct intel_display *display = to_intel_display(encoder); 1393 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1394 const struct intel_ddi_buf_trans *trans; 1395 int n_entries, ln; 1396 1397 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1398 return; 1399 1400 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1401 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1402 return; 1403 1404 for (ln = 0; ln < 2; ln++) { 1405 int level; 1406 1407 /* Wa_16011342517:adl-p */ 1408 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011342517)) { 1409 if ((intel_encoder_is_hdmi(encoder) && 1410 crtc_state->port_clock == 594000) || 1411 (intel_encoder_is_dp(encoder) && 1412 crtc_state->port_clock == 162000)) { 1413 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1414 LOADGEN_SHARING_PMD_DISABLE, 1); 1415 } else { 1416 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1417 LOADGEN_SHARING_PMD_DISABLE, 0); 1418 } 1419 } 1420 1421 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1422 1423 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1424 1425 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1426 DKL_TX_PRESHOOT_COEFF_MASK | 1427 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1428 DKL_TX_VSWING_CONTROL_MASK, 1429 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1430 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1431 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1432 1433 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1434 1435 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1436 DKL_TX_PRESHOOT_COEFF_MASK | 1437 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1438 DKL_TX_VSWING_CONTROL_MASK, 1439 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1440 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1441 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1442 1443 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1444 DKL_TX_DP20BITMODE, 0); 1445 1446 if (display->platform.alderlake_p) { 1447 u32 val; 1448 1449 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1450 if (ln == 0) { 1451 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1452 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1453 } else { 1454 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1455 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1456 } 1457 } else { 1458 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1459 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1460 } 1461 1462 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1463 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1464 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1465 val); 1466 } 1467 } 1468 } 1469 1470 static int translate_signal_level(struct intel_dp *intel_dp, 1471 u8 signal_levels) 1472 { 1473 struct intel_display *display = to_intel_display(intel_dp); 1474 const u8 *signal_array; 1475 size_t array_size; 1476 int i; 1477 1478 signal_array = index_to_dp_signal_levels; 1479 array_size = ARRAY_SIZE(index_to_dp_signal_levels); 1480 1481 for (i = 0; i < array_size; i++) { 1482 if (signal_array[i] == signal_levels) 1483 return i; 1484 } 1485 1486 drm_WARN(display->drm, 1, 1487 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1488 signal_levels); 1489 1490 return 0; 1491 } 1492 1493 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1494 const struct intel_crtc_state *crtc_state, 1495 int lane) 1496 { 1497 u8 train_set = intel_dp->train_set[lane]; 1498 1499 if (intel_dp_is_uhbr(crtc_state)) { 1500 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1501 } else { 1502 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1503 DP_TRAIN_PRE_EMPHASIS_MASK); 1504 1505 return translate_signal_level(intel_dp, signal_levels); 1506 } 1507 } 1508 1509 int intel_ddi_level(struct intel_encoder *encoder, 1510 const struct intel_crtc_state *crtc_state, 1511 int lane) 1512 { 1513 struct intel_display *display = to_intel_display(encoder); 1514 const struct intel_ddi_buf_trans *trans; 1515 int level, n_entries; 1516 1517 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1518 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1519 return 0; 1520 1521 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1522 level = intel_ddi_hdmi_level(encoder, trans); 1523 else 1524 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1525 lane); 1526 1527 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1528 level = n_entries - 1; 1529 1530 return level; 1531 } 1532 1533 int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock) 1534 { 1535 if (intel_encoder_is_dp(encoder)) 1536 return intel_dp_link_symbol_clock(clock); 1537 1538 if (intel_hdmi_is_frl(clock)) 1539 return DIV_ROUND_CLOSEST(clock * 10, 18); 1540 1541 return clock; 1542 } 1543 1544 static void 1545 hsw_set_signal_levels(struct intel_encoder *encoder, 1546 const struct intel_crtc_state *crtc_state) 1547 { 1548 struct intel_display *display = to_intel_display(encoder); 1549 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1550 int level = intel_ddi_level(encoder, crtc_state, 0); 1551 enum port port = encoder->port; 1552 u32 signal_levels; 1553 1554 if (has_iboost(display)) 1555 skl_ddi_set_iboost(encoder, crtc_state, level); 1556 1557 /* HDMI ignores the rest */ 1558 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1559 return; 1560 1561 signal_levels = DDI_BUF_TRANS_SELECT(level); 1562 1563 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1564 signal_levels); 1565 1566 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1567 intel_dp->DP |= signal_levels; 1568 1569 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1570 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1571 } 1572 1573 static void _icl_ddi_enable_clock(struct intel_display *display, intel_reg_t reg, 1574 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1575 { 1576 mutex_lock(&display->dpll.lock); 1577 1578 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1579 1580 /* 1581 * "This step and the step before must be 1582 * done with separate register writes." 1583 */ 1584 intel_de_rmw(display, reg, clk_off, 0); 1585 1586 mutex_unlock(&display->dpll.lock); 1587 } 1588 1589 static void _icl_ddi_disable_clock(struct intel_display *display, intel_reg_t reg, 1590 u32 clk_off) 1591 { 1592 mutex_lock(&display->dpll.lock); 1593 1594 intel_de_rmw(display, reg, 0, clk_off); 1595 1596 mutex_unlock(&display->dpll.lock); 1597 } 1598 1599 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, intel_reg_t reg, 1600 u32 clk_off) 1601 { 1602 return !(intel_de_read(display, reg) & clk_off); 1603 } 1604 1605 static struct intel_dpll * 1606 _icl_ddi_get_pll(struct intel_display *display, intel_reg_t reg, 1607 u32 clk_sel_mask, u32 clk_sel_shift) 1608 { 1609 enum intel_dpll_id id; 1610 1611 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1612 1613 return intel_get_dpll_by_id(display, id); 1614 } 1615 1616 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1617 const struct intel_crtc_state *crtc_state) 1618 { 1619 struct intel_display *display = to_intel_display(encoder); 1620 const struct intel_dpll *pll = crtc_state->intel_dpll; 1621 enum phy phy = intel_encoder_to_phy(encoder); 1622 1623 if (drm_WARN_ON(display->drm, !pll)) 1624 return; 1625 1626 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1627 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1628 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1629 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1630 } 1631 1632 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1633 { 1634 struct intel_display *display = to_intel_display(encoder); 1635 enum phy phy = intel_encoder_to_phy(encoder); 1636 1637 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1638 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1639 } 1640 1641 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1642 { 1643 struct intel_display *display = to_intel_display(encoder); 1644 enum phy phy = intel_encoder_to_phy(encoder); 1645 1646 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1647 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1648 } 1649 1650 static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1651 { 1652 struct intel_display *display = to_intel_display(encoder); 1653 enum phy phy = intel_encoder_to_phy(encoder); 1654 1655 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1656 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1657 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1658 } 1659 1660 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1661 const struct intel_crtc_state *crtc_state) 1662 { 1663 struct intel_display *display = to_intel_display(encoder); 1664 const struct intel_dpll *pll = crtc_state->intel_dpll; 1665 enum phy phy = intel_encoder_to_phy(encoder); 1666 1667 if (drm_WARN_ON(display->drm, !pll)) 1668 return; 1669 1670 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1671 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1672 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1673 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1674 } 1675 1676 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1677 { 1678 struct intel_display *display = to_intel_display(encoder); 1679 enum phy phy = intel_encoder_to_phy(encoder); 1680 1681 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1682 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1683 } 1684 1685 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1686 { 1687 struct intel_display *display = to_intel_display(encoder); 1688 enum phy phy = intel_encoder_to_phy(encoder); 1689 1690 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1691 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1692 } 1693 1694 static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1695 { 1696 struct intel_display *display = to_intel_display(encoder); 1697 enum phy phy = intel_encoder_to_phy(encoder); 1698 1699 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1700 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1701 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1702 } 1703 1704 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1705 const struct intel_crtc_state *crtc_state) 1706 { 1707 struct intel_display *display = to_intel_display(encoder); 1708 const struct intel_dpll *pll = crtc_state->intel_dpll; 1709 enum phy phy = intel_encoder_to_phy(encoder); 1710 1711 if (drm_WARN_ON(display->drm, !pll)) 1712 return; 1713 1714 /* 1715 * If we fail this, something went very wrong: first 2 PLLs should be 1716 * used by first 2 phys and last 2 PLLs by last phys 1717 */ 1718 if (drm_WARN_ON(display->drm, 1719 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1720 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1721 return; 1722 1723 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1724 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1725 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1726 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1727 } 1728 1729 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1730 { 1731 struct intel_display *display = to_intel_display(encoder); 1732 enum phy phy = intel_encoder_to_phy(encoder); 1733 1734 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1735 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1736 } 1737 1738 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1739 { 1740 struct intel_display *display = to_intel_display(encoder); 1741 enum phy phy = intel_encoder_to_phy(encoder); 1742 1743 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1744 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1745 } 1746 1747 static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1748 { 1749 struct intel_display *display = to_intel_display(encoder); 1750 enum phy phy = intel_encoder_to_phy(encoder); 1751 enum intel_dpll_id id; 1752 u32 val; 1753 1754 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1755 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1756 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1757 id = val; 1758 1759 /* 1760 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1761 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1762 * bit for phy C and D. 1763 */ 1764 if (phy >= PHY_C) 1765 id += DPLL_ID_DG1_DPLL2; 1766 1767 return intel_get_dpll_by_id(display, id); 1768 } 1769 1770 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1771 const struct intel_crtc_state *crtc_state) 1772 { 1773 struct intel_display *display = to_intel_display(encoder); 1774 const struct intel_dpll *pll = crtc_state->intel_dpll; 1775 enum phy phy = intel_encoder_to_phy(encoder); 1776 1777 if (drm_WARN_ON(display->drm, !pll)) 1778 return; 1779 1780 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1781 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1782 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1783 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1784 } 1785 1786 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1787 { 1788 struct intel_display *display = to_intel_display(encoder); 1789 enum phy phy = intel_encoder_to_phy(encoder); 1790 1791 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1792 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1793 } 1794 1795 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1796 { 1797 struct intel_display *display = to_intel_display(encoder); 1798 enum phy phy = intel_encoder_to_phy(encoder); 1799 1800 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1801 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1802 } 1803 1804 struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1805 { 1806 struct intel_display *display = to_intel_display(encoder); 1807 enum phy phy = intel_encoder_to_phy(encoder); 1808 1809 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1810 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1811 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1812 } 1813 1814 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1815 const struct intel_crtc_state *crtc_state) 1816 { 1817 struct intel_display *display = to_intel_display(encoder); 1818 const struct intel_dpll *pll = crtc_state->intel_dpll; 1819 enum port port = encoder->port; 1820 1821 if (drm_WARN_ON(display->drm, !pll)) 1822 return; 1823 1824 /* 1825 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1826 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1827 */ 1828 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1829 1830 icl_ddi_combo_enable_clock(encoder, crtc_state); 1831 } 1832 1833 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1834 { 1835 struct intel_display *display = to_intel_display(encoder); 1836 enum port port = encoder->port; 1837 1838 icl_ddi_combo_disable_clock(encoder); 1839 1840 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1841 } 1842 1843 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1844 { 1845 struct intel_display *display = to_intel_display(encoder); 1846 enum port port = encoder->port; 1847 u32 tmp; 1848 1849 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1850 1851 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1852 return false; 1853 1854 return icl_ddi_combo_is_clock_enabled(encoder); 1855 } 1856 1857 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1858 const struct intel_crtc_state *crtc_state) 1859 { 1860 struct intel_display *display = to_intel_display(encoder); 1861 const struct intel_dpll *pll = crtc_state->intel_dpll; 1862 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1863 enum port port = encoder->port; 1864 1865 if (drm_WARN_ON(display->drm, !pll)) 1866 return; 1867 1868 intel_de_write(display, DDI_CLK_SEL(port), 1869 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1870 1871 mutex_lock(&display->dpll.lock); 1872 1873 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1874 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1875 1876 mutex_unlock(&display->dpll.lock); 1877 } 1878 1879 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1880 { 1881 struct intel_display *display = to_intel_display(encoder); 1882 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1883 enum port port = encoder->port; 1884 1885 mutex_lock(&display->dpll.lock); 1886 1887 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1888 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1889 1890 mutex_unlock(&display->dpll.lock); 1891 1892 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1893 } 1894 1895 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1896 { 1897 struct intel_display *display = to_intel_display(encoder); 1898 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1899 enum port port = encoder->port; 1900 u32 tmp; 1901 1902 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1903 1904 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1905 return false; 1906 1907 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1908 1909 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1910 } 1911 1912 static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1913 { 1914 struct intel_display *display = to_intel_display(encoder); 1915 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1916 enum port port = encoder->port; 1917 enum intel_dpll_id id; 1918 u32 tmp; 1919 1920 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1921 1922 switch (tmp & DDI_CLK_SEL_MASK) { 1923 case DDI_CLK_SEL_TBT_162: 1924 case DDI_CLK_SEL_TBT_270: 1925 case DDI_CLK_SEL_TBT_540: 1926 case DDI_CLK_SEL_TBT_810: 1927 id = DPLL_ID_ICL_TBTPLL; 1928 break; 1929 case DDI_CLK_SEL_MG: 1930 id = icl_tc_port_to_pll_id(tc_port); 1931 break; 1932 default: 1933 MISSING_CASE(tmp); 1934 fallthrough; 1935 case DDI_CLK_SEL_NONE: 1936 return NULL; 1937 } 1938 1939 return intel_get_dpll_by_id(display, id); 1940 } 1941 1942 static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1943 { 1944 struct intel_display *display = to_intel_display(encoder->base.dev); 1945 enum intel_dpll_id id; 1946 1947 switch (encoder->port) { 1948 case PORT_A: 1949 id = DPLL_ID_SKL_DPLL0; 1950 break; 1951 case PORT_B: 1952 id = DPLL_ID_SKL_DPLL1; 1953 break; 1954 case PORT_C: 1955 id = DPLL_ID_SKL_DPLL2; 1956 break; 1957 default: 1958 MISSING_CASE(encoder->port); 1959 return NULL; 1960 } 1961 1962 return intel_get_dpll_by_id(display, id); 1963 } 1964 1965 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1966 const struct intel_crtc_state *crtc_state) 1967 { 1968 struct intel_display *display = to_intel_display(encoder); 1969 const struct intel_dpll *pll = crtc_state->intel_dpll; 1970 enum port port = encoder->port; 1971 1972 if (drm_WARN_ON(display->drm, !pll)) 1973 return; 1974 1975 mutex_lock(&display->dpll.lock); 1976 1977 intel_de_rmw(display, DPLL_CTRL2, 1978 DPLL_CTRL2_DDI_CLK_OFF(port) | 1979 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1980 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1981 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1982 1983 mutex_unlock(&display->dpll.lock); 1984 } 1985 1986 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1987 { 1988 struct intel_display *display = to_intel_display(encoder); 1989 enum port port = encoder->port; 1990 1991 mutex_lock(&display->dpll.lock); 1992 1993 intel_de_rmw(display, DPLL_CTRL2, 1994 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1995 1996 mutex_unlock(&display->dpll.lock); 1997 } 1998 1999 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 2000 { 2001 struct intel_display *display = to_intel_display(encoder); 2002 enum port port = encoder->port; 2003 2004 /* 2005 * FIXME Not sure if the override affects both 2006 * the PLL selection and the CLK_OFF bit. 2007 */ 2008 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 2009 } 2010 2011 static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 2012 { 2013 struct intel_display *display = to_intel_display(encoder); 2014 enum port port = encoder->port; 2015 enum intel_dpll_id id; 2016 u32 tmp; 2017 2018 tmp = intel_de_read(display, DPLL_CTRL2); 2019 2020 /* 2021 * FIXME Not sure if the override affects both 2022 * the PLL selection and the CLK_OFF bit. 2023 */ 2024 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2025 return NULL; 2026 2027 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2028 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2029 2030 return intel_get_dpll_by_id(display, id); 2031 } 2032 2033 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2034 const struct intel_crtc_state *crtc_state) 2035 { 2036 struct intel_display *display = to_intel_display(encoder); 2037 const struct intel_dpll *pll = crtc_state->intel_dpll; 2038 enum port port = encoder->port; 2039 2040 if (drm_WARN_ON(display->drm, !pll)) 2041 return; 2042 2043 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2044 } 2045 2046 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2047 { 2048 struct intel_display *display = to_intel_display(encoder); 2049 enum port port = encoder->port; 2050 2051 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2052 } 2053 2054 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2055 { 2056 struct intel_display *display = to_intel_display(encoder); 2057 enum port port = encoder->port; 2058 2059 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2060 } 2061 2062 static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2063 { 2064 struct intel_display *display = to_intel_display(encoder); 2065 enum port port = encoder->port; 2066 enum intel_dpll_id id; 2067 u32 tmp; 2068 2069 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2070 2071 switch (tmp & PORT_CLK_SEL_MASK) { 2072 case PORT_CLK_SEL_WRPLL1: 2073 id = DPLL_ID_WRPLL1; 2074 break; 2075 case PORT_CLK_SEL_WRPLL2: 2076 id = DPLL_ID_WRPLL2; 2077 break; 2078 case PORT_CLK_SEL_SPLL: 2079 id = DPLL_ID_SPLL; 2080 break; 2081 case PORT_CLK_SEL_LCPLL_810: 2082 id = DPLL_ID_LCPLL_810; 2083 break; 2084 case PORT_CLK_SEL_LCPLL_1350: 2085 id = DPLL_ID_LCPLL_1350; 2086 break; 2087 case PORT_CLK_SEL_LCPLL_2700: 2088 id = DPLL_ID_LCPLL_2700; 2089 break; 2090 default: 2091 MISSING_CASE(tmp); 2092 fallthrough; 2093 case PORT_CLK_SEL_NONE: 2094 return NULL; 2095 } 2096 2097 return intel_get_dpll_by_id(display, id); 2098 } 2099 2100 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2101 const struct intel_crtc_state *crtc_state) 2102 { 2103 if (encoder->enable_clock) 2104 encoder->enable_clock(encoder, crtc_state); 2105 } 2106 2107 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2108 { 2109 if (encoder->disable_clock) 2110 encoder->disable_clock(encoder); 2111 } 2112 2113 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2114 { 2115 struct intel_display *display = to_intel_display(encoder); 2116 u32 port_mask; 2117 bool ddi_clk_needed; 2118 2119 /* 2120 * In case of DP MST, we sanitize the primary encoder only, not the 2121 * virtual ones. 2122 */ 2123 if (encoder->type == INTEL_OUTPUT_DP_MST) 2124 return; 2125 2126 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2127 u8 pipe_mask; 2128 bool is_mst; 2129 2130 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2131 /* 2132 * In the unlikely case that BIOS enables DP in MST mode, just 2133 * warn since our MST HW readout is incomplete. 2134 */ 2135 if (drm_WARN_ON(display->drm, is_mst)) 2136 return; 2137 } 2138 2139 port_mask = BIT(encoder->port); 2140 ddi_clk_needed = encoder->base.crtc; 2141 2142 if (encoder->type == INTEL_OUTPUT_DSI) { 2143 struct intel_encoder *other_encoder; 2144 2145 port_mask = intel_dsi_encoder_ports(encoder); 2146 /* 2147 * Sanity check that we haven't incorrectly registered another 2148 * encoder using any of the ports of this DSI encoder. 2149 */ 2150 for_each_intel_encoder(display->drm, other_encoder) { 2151 if (other_encoder == encoder) 2152 continue; 2153 2154 if (drm_WARN_ON(display->drm, 2155 port_mask & BIT(other_encoder->port))) 2156 return; 2157 } 2158 /* 2159 * For DSI we keep the ddi clocks gated 2160 * except during enable/disable sequence. 2161 */ 2162 ddi_clk_needed = false; 2163 } 2164 2165 if (ddi_clk_needed || !encoder->is_clock_enabled || 2166 !encoder->is_clock_enabled(encoder)) 2167 return; 2168 2169 drm_dbg_kms(display->drm, 2170 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2171 encoder->base.base.id, encoder->base.name); 2172 2173 encoder->disable_clock(encoder); 2174 } 2175 2176 static void 2177 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2178 enum tc_port tc_port, u32 ln0, u32 ln1) 2179 { 2180 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2181 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2182 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2183 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2184 } 2185 2186 static void 2187 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2188 const struct intel_crtc_state *crtc_state) 2189 { 2190 struct intel_display *display = to_intel_display(crtc_state); 2191 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2192 enum intel_tc_pin_assignment pin_assignment; 2193 u32 ln0, ln1; 2194 u8 width; 2195 2196 if (DISPLAY_VER(display) >= 14) 2197 return; 2198 2199 if (!intel_encoder_is_tc(&dig_port->base) || 2200 intel_tc_port_in_tbt_alt_mode(dig_port)) 2201 return; 2202 2203 if (DISPLAY_VER(display) >= 12) { 2204 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2205 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2206 } else { 2207 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2208 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2209 } 2210 2211 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2212 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2213 2214 /* DPPATC */ 2215 pin_assignment = intel_tc_port_get_pin_assignment(dig_port); 2216 width = crtc_state->lane_count; 2217 2218 switch (pin_assignment) { 2219 case INTEL_TC_PIN_ASSIGNMENT_NONE: 2220 drm_WARN_ON(display->drm, 2221 !intel_tc_port_in_legacy_mode(dig_port)); 2222 if (width == 1) { 2223 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2224 } else { 2225 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2226 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2227 } 2228 break; 2229 case INTEL_TC_PIN_ASSIGNMENT_A: 2230 if (width == 4) { 2231 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2232 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2233 } 2234 break; 2235 case INTEL_TC_PIN_ASSIGNMENT_B: 2236 if (width == 2) { 2237 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2238 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2239 } 2240 break; 2241 case INTEL_TC_PIN_ASSIGNMENT_C: 2242 case INTEL_TC_PIN_ASSIGNMENT_E: 2243 if (width == 1) { 2244 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2245 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2246 } else { 2247 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2248 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2249 } 2250 break; 2251 case INTEL_TC_PIN_ASSIGNMENT_D: 2252 case INTEL_TC_PIN_ASSIGNMENT_F: 2253 if (width == 1) { 2254 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2255 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2256 } else { 2257 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2258 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2259 } 2260 break; 2261 default: 2262 MISSING_CASE(pin_assignment); 2263 } 2264 2265 if (DISPLAY_VER(display) >= 12) { 2266 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2267 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2268 /* WA_14018221282 */ 2269 if (IS_DISPLAY_VER(display, 12, 13)) 2270 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2271 2272 } else { 2273 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2274 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2275 } 2276 } 2277 2278 static enum transcoder 2279 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2280 { 2281 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2282 return crtc_state->mst_master_transcoder; 2283 else 2284 return crtc_state->cpu_transcoder; 2285 } 2286 2287 intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2288 const struct intel_crtc_state *crtc_state) 2289 { 2290 struct intel_display *display = to_intel_display(encoder); 2291 2292 if (DISPLAY_VER(display) >= 12) 2293 return TGL_DP_TP_CTL(display, 2294 tgl_dp_tp_transcoder(crtc_state)); 2295 else 2296 return DP_TP_CTL(encoder->port); 2297 } 2298 2299 static intel_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2300 const struct intel_crtc_state *crtc_state) 2301 { 2302 struct intel_display *display = to_intel_display(encoder); 2303 2304 if (DISPLAY_VER(display) >= 12) 2305 return TGL_DP_TP_STATUS(display, 2306 tgl_dp_tp_transcoder(crtc_state)); 2307 else 2308 return DP_TP_STATUS(encoder->port); 2309 } 2310 2311 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2312 const struct intel_crtc_state *crtc_state) 2313 { 2314 struct intel_display *display = to_intel_display(encoder); 2315 2316 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2317 DP_TP_STATUS_ACT_SENT); 2318 } 2319 2320 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2321 const struct intel_crtc_state *crtc_state) 2322 { 2323 struct intel_display *display = to_intel_display(encoder); 2324 2325 if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state), 2326 DP_TP_STATUS_ACT_SENT, 1)) 2327 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2328 } 2329 2330 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2331 const struct intel_crtc_state *crtc_state, 2332 bool enable) 2333 { 2334 struct intel_display *display = to_intel_display(intel_dp); 2335 int ret; 2336 2337 if (!crtc_state->vrr.enable) 2338 return; 2339 2340 ret = drm_dp_dpcd_write_byte(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2341 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0); 2342 if (ret < 0) 2343 drm_dbg_kms(display->drm, 2344 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink (%pe)\n", 2345 str_enable_disable(enable), ERR_PTR(ret)); 2346 } 2347 2348 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2349 const struct intel_crtc_state *crtc_state, 2350 bool enable) 2351 { 2352 struct intel_display *display = to_intel_display(intel_dp); 2353 int ret; 2354 2355 if (!crtc_state->fec_enable) 2356 return; 2357 2358 ret = drm_dp_dpcd_write_byte(&intel_dp->aux, DP_FEC_CONFIGURATION, 2359 enable ? DP_FEC_READY : 0); 2360 if (ret < 0) 2361 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink (%pe)\n", 2362 str_enabled_disabled(enable), ERR_PTR(ret)); 2363 2364 if (enable) { 2365 ret = drm_dp_dpcd_write_byte(&intel_dp->aux, DP_FEC_STATUS, 2366 DP_FEC_DECODE_EN_DETECTED | 2367 DP_FEC_DECODE_DIS_DETECTED); 2368 if (ret < 0) 2369 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags (%pe)\n", 2370 ERR_PTR(ret)); 2371 } 2372 } 2373 2374 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2375 { 2376 struct intel_display *display = to_intel_display(aux->drm_dev); 2377 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2378 u8 status = 0; 2379 int ret, err; 2380 2381 ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status), 2382 err || (status & mask), 2383 10 * 1000, 200 * 1000, false); 2384 2385 /* Either can be non-zero, but not both */ 2386 ret = ret ?: err; 2387 if (ret) { 2388 drm_dbg_kms(display->drm, 2389 "Failed waiting for FEC %s to get detected: %d (status 0x%02x)\n", 2390 str_enabled_disabled(enabled), ret, status); 2391 return ret; 2392 } 2393 2394 return 0; 2395 } 2396 2397 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2398 const struct intel_crtc_state *crtc_state, 2399 bool enabled) 2400 { 2401 struct intel_display *display = to_intel_display(encoder); 2402 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2403 int ret; 2404 2405 if (!crtc_state->fec_enable) 2406 return 0; 2407 2408 if (enabled) 2409 ret = intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state), 2410 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2411 else 2412 ret = intel_de_wait_for_clear_ms(display, dp_tp_status_reg(encoder, crtc_state), 2413 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2414 2415 if (ret) { 2416 drm_err(display->drm, 2417 "Timeout waiting for FEC live state to get %s\n", 2418 str_enabled_disabled(enabled)); 2419 return ret; 2420 } 2421 /* 2422 * At least the Synoptics MST hub doesn't set the detected flag for 2423 * FEC decoding disabling so skip waiting for that. 2424 */ 2425 if (enabled) { 2426 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2427 if (ret) 2428 return ret; 2429 } 2430 2431 return 0; 2432 } 2433 2434 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2435 const struct intel_crtc_state *crtc_state) 2436 { 2437 struct intel_display *display = to_intel_display(encoder); 2438 int i; 2439 int ret; 2440 2441 if (!crtc_state->fec_enable) 2442 return; 2443 2444 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2445 0, DP_TP_CTL_FEC_ENABLE); 2446 2447 if (DISPLAY_VER(display) < 30) 2448 return; 2449 2450 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2451 if (!ret) 2452 return; 2453 2454 for (i = 0; i < 3; i++) { 2455 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2456 2457 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2458 DP_TP_CTL_FEC_ENABLE, 0); 2459 2460 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2461 if (ret) 2462 continue; 2463 2464 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2465 0, DP_TP_CTL_FEC_ENABLE); 2466 2467 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2468 if (!ret) 2469 return; 2470 } 2471 2472 drm_dbg_kms(display->drm, "Failed to enable FEC after retries\n"); 2473 } 2474 2475 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2476 const struct intel_crtc_state *crtc_state) 2477 { 2478 struct intel_display *display = to_intel_display(encoder); 2479 2480 if (!crtc_state->fec_enable) 2481 return; 2482 2483 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2484 DP_TP_CTL_FEC_ENABLE, 0); 2485 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2486 } 2487 2488 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2489 const struct intel_crtc_state *crtc_state) 2490 { 2491 struct intel_display *display = to_intel_display(encoder); 2492 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2493 2494 if (intel_encoder_is_combo(encoder)) { 2495 enum phy phy = intel_encoder_to_phy(encoder); 2496 2497 intel_combo_phy_power_up_lanes(display, phy, false, 2498 crtc_state->lane_count, 2499 dig_port->lane_reversal); 2500 } 2501 } 2502 2503 /* 2504 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2505 * platforms. 2506 */ 2507 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2508 { 2509 if (DISPLAY_VER(display) > 20) 2510 return ~0; 2511 else if (display->platform.alderlake_p) 2512 return BIT(PIPE_A) | BIT(PIPE_B); 2513 else 2514 return BIT(PIPE_A); 2515 } 2516 2517 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2518 struct intel_crtc_state *pipe_config) 2519 { 2520 struct intel_display *display = to_intel_display(pipe_config); 2521 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2522 enum pipe pipe = crtc->pipe; 2523 u32 dss1; 2524 2525 if (!HAS_MSO(display)) 2526 return; 2527 2528 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2529 2530 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2531 if (!pipe_config->splitter.enable) 2532 return; 2533 2534 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2535 pipe_config->splitter.enable = false; 2536 return; 2537 } 2538 2539 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2540 default: 2541 drm_WARN(display->drm, true, 2542 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2543 fallthrough; 2544 case SPLITTER_CONFIGURATION_2_SEGMENT: 2545 pipe_config->splitter.link_count = 2; 2546 break; 2547 case SPLITTER_CONFIGURATION_4_SEGMENT: 2548 pipe_config->splitter.link_count = 4; 2549 break; 2550 } 2551 2552 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2553 } 2554 2555 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2556 { 2557 struct intel_display *display = to_intel_display(crtc_state); 2558 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2559 enum pipe pipe = crtc->pipe; 2560 u32 dss1 = 0; 2561 2562 if (!HAS_MSO(display)) 2563 return; 2564 2565 if (crtc_state->splitter.enable) { 2566 dss1 |= SPLITTER_ENABLE; 2567 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2568 if (crtc_state->splitter.link_count == 2) 2569 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2570 else 2571 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2572 } 2573 2574 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2575 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2576 OVERLAP_PIXELS_MASK, dss1); 2577 } 2578 2579 static void 2580 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2581 { 2582 struct intel_display *display = to_intel_display(encoder); 2583 enum port port = encoder->port; 2584 intel_reg_t reg; 2585 u32 set_bits, wait_bits; 2586 int ret; 2587 2588 if (DISPLAY_VER(display) < 14) 2589 return; 2590 2591 if (DISPLAY_VER(display) >= 20) { 2592 reg = DDI_BUF_CTL(port); 2593 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2594 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2595 } else { 2596 reg = XELPDP_PORT_BUF_CTL1(display, port); 2597 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2598 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2599 } 2600 2601 intel_de_rmw(display, reg, 0, set_bits); 2602 2603 ret = intel_de_wait_for_set_us(display, reg, wait_bits, 100); 2604 if (ret) { 2605 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2606 port_name(port)); 2607 } 2608 } 2609 2610 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2611 const struct intel_crtc_state *crtc_state) 2612 { 2613 struct intel_display *display = to_intel_display(encoder); 2614 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2615 enum port port = encoder->port; 2616 u32 val = 0; 2617 2618 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2619 2620 if (intel_dp_is_uhbr(crtc_state)) 2621 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2622 else 2623 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2624 2625 if (dig_port->lane_reversal) 2626 val |= XELPDP_PORT_REVERSAL; 2627 2628 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2629 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2630 val); 2631 } 2632 2633 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2634 { 2635 struct intel_display *display = to_intel_display(encoder); 2636 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2637 u32 val; 2638 2639 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2640 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2641 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2642 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2643 } 2644 2645 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2646 struct intel_encoder *encoder, 2647 const struct intel_crtc_state *crtc_state, 2648 const struct drm_connector_state *conn_state) 2649 { 2650 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2651 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2652 bool transparent_mode; 2653 int ret; 2654 2655 intel_dp_set_link_params(intel_dp, 2656 crtc_state->port_clock, 2657 crtc_state->lane_count); 2658 2659 /* 2660 * We only configure what the register value will be here. Actual 2661 * enabling happens during link training farther down. 2662 */ 2663 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2664 2665 /* 2666 * 1. Enable Power Wells 2667 * 2668 * This was handled at the beginning of intel_atomic_commit_tail(), 2669 * before we called down into this function. 2670 */ 2671 2672 /* 2. PMdemand was already set */ 2673 2674 /* 3. Select Thunderbolt */ 2675 mtl_port_buf_ctl_io_selection(encoder); 2676 2677 /* 5. Enable the port PLL */ 2678 intel_ddi_enable_clock(encoder, crtc_state); 2679 2680 /* 2681 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2682 * Transcoder. 2683 */ 2684 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2685 2686 /* 2687 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2688 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2689 * Transport Select 2690 */ 2691 intel_ddi_config_transcoder_func(encoder, crtc_state); 2692 2693 /* 2694 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2695 */ 2696 intel_ddi_mso_configure(crtc_state); 2697 2698 if (!is_mst) 2699 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2700 2701 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2702 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2703 2704 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2705 if (!is_mst) 2706 intel_dp_sink_enable_decompression(state, 2707 to_intel_connector(conn_state->connector), 2708 crtc_state); 2709 2710 /* 2711 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2712 * in the FEC_CONFIGURATION register to 1 before initiating link 2713 * training 2714 */ 2715 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2716 2717 intel_dp_check_frl_training(intel_dp); 2718 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2719 2720 /* 2721 * 6. The rest of the below are substeps under the bspec's "Enable and 2722 * Train Display Port" step. Note that steps that are specific to 2723 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2724 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2725 * us when active_mst_links==0, so any steps designated for "single 2726 * stream or multi-stream master transcoder" can just be performed 2727 * unconditionally here. 2728 * 2729 * mtl_ddi_prepare_link_retrain() that is called by 2730 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2731 * 6.i and 6.j 2732 * 2733 * 6.k Follow DisplayPort specification training sequence (see notes for 2734 * failure handling) 2735 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2736 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2737 * (timeout after 800 us) 2738 */ 2739 intel_dp_start_link_train(state, intel_dp, crtc_state); 2740 2741 /* 6.n Set DP_TP_CTL link training to Normal */ 2742 if (!is_trans_port_sync_mode(crtc_state)) 2743 intel_dp_stop_link_train(intel_dp, crtc_state); 2744 2745 /* 6.o Configure and enable FEC if needed */ 2746 intel_ddi_enable_fec(encoder, crtc_state); 2747 2748 intel_dip_cmn_sdp_transmission_line_enable(crtc_state); 2749 2750 /* 7.a 128b/132b SST. */ 2751 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2752 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2753 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2754 if (ret < 0) 2755 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2756 } 2757 2758 if (!is_mst) 2759 intel_dsc_dp_pps_write(encoder, crtc_state); 2760 } 2761 2762 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2763 struct intel_encoder *encoder, 2764 const struct intel_crtc_state *crtc_state, 2765 const struct drm_connector_state *conn_state) 2766 { 2767 struct intel_display *display = to_intel_display(encoder); 2768 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2769 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2770 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2771 int ret; 2772 2773 intel_dp_set_link_params(intel_dp, 2774 crtc_state->port_clock, 2775 crtc_state->lane_count); 2776 2777 /* 2778 * We only configure what the register value will be here. Actual 2779 * enabling happens during link training farther down. 2780 */ 2781 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2782 2783 /* 2784 * 1. Enable Power Wells 2785 * 2786 * This was handled at the beginning of intel_atomic_commit_tail(), 2787 * before we called down into this function. 2788 */ 2789 2790 /* 2. Enable Panel Power if PPS is required */ 2791 intel_pps_on(intel_dp); 2792 2793 /* 2794 * 3. For non-TBT Type-C ports, set FIA lane count 2795 * (DFLEXDPSP.DPX4TXLATC) 2796 * 2797 * This was done before tgl_ddi_pre_enable_dp by 2798 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2799 */ 2800 2801 /* 2802 * 4. Enable the port PLL. 2803 * 2804 * The PLL enabling itself was already done before this function by 2805 * hsw_crtc_enable()->intel_enable_dpll(). We need only 2806 * configure the PLL to port mapping here. 2807 */ 2808 intel_ddi_enable_clock(encoder, crtc_state); 2809 2810 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2811 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2812 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2813 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2814 dig_port->ddi_io_power_domain); 2815 } 2816 2817 /* 6. Program DP_MODE */ 2818 icl_program_mg_dp_mode(dig_port, crtc_state); 2819 2820 /* 2821 * 7. The rest of the below are substeps under the bspec's "Enable and 2822 * Train Display Port" step. Note that steps that are specific to 2823 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2824 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2825 * us when active_mst_links==0, so any steps designated for "single 2826 * stream or multi-stream master transcoder" can just be performed 2827 * unconditionally here. 2828 */ 2829 2830 /* 2831 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2832 * Transcoder. 2833 */ 2834 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2835 2836 /* 2837 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2838 * Transport Select 2839 */ 2840 intel_ddi_config_transcoder_func(encoder, crtc_state); 2841 2842 /* 2843 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2844 * selected 2845 * 2846 * This will be handled by the intel_dp_start_link_train() farther 2847 * down this function. 2848 */ 2849 2850 /* 7.e Configure voltage swing and related IO settings */ 2851 encoder->set_signal_levels(encoder, crtc_state); 2852 2853 /* 2854 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2855 * the used lanes of the DDI. 2856 */ 2857 intel_ddi_power_up_lanes(encoder, crtc_state); 2858 2859 /* 2860 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2861 */ 2862 intel_ddi_mso_configure(crtc_state); 2863 2864 if (!is_mst) 2865 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2866 2867 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2868 if (!is_mst) 2869 intel_dp_sink_enable_decompression(state, 2870 to_intel_connector(conn_state->connector), 2871 crtc_state); 2872 /* 2873 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2874 * in the FEC_CONFIGURATION register to 1 before initiating link 2875 * training 2876 */ 2877 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2878 2879 intel_dp_check_frl_training(intel_dp); 2880 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2881 2882 /* 2883 * 7.i Follow DisplayPort specification training sequence (see notes for 2884 * failure handling) 2885 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2886 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2887 * (timeout after 800 us) 2888 */ 2889 intel_dp_start_link_train(state, intel_dp, crtc_state); 2890 2891 /* 7.k Set DP_TP_CTL link training to Normal */ 2892 if (!is_trans_port_sync_mode(crtc_state)) 2893 intel_dp_stop_link_train(intel_dp, crtc_state); 2894 2895 /* 7.l Configure and enable FEC if needed */ 2896 intel_ddi_enable_fec(encoder, crtc_state); 2897 2898 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2899 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2900 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2901 if (ret < 0) 2902 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2903 } 2904 2905 if (!is_mst) 2906 intel_dsc_dp_pps_write(encoder, crtc_state); 2907 } 2908 2909 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2910 struct intel_encoder *encoder, 2911 const struct intel_crtc_state *crtc_state, 2912 const struct drm_connector_state *conn_state) 2913 { 2914 struct intel_display *display = to_intel_display(encoder); 2915 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2916 enum port port = encoder->port; 2917 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2918 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2919 2920 if (DISPLAY_VER(display) < 11) 2921 drm_WARN_ON(display->drm, 2922 is_mst && (port == PORT_A || port == PORT_E)); 2923 else 2924 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2925 2926 intel_dp_set_link_params(intel_dp, 2927 crtc_state->port_clock, 2928 crtc_state->lane_count); 2929 2930 /* 2931 * We only configure what the register value will be here. Actual 2932 * enabling happens during link training farther down. 2933 */ 2934 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2935 2936 intel_pps_on(intel_dp); 2937 2938 intel_ddi_enable_clock(encoder, crtc_state); 2939 2940 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2941 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2942 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2943 dig_port->ddi_io_power_domain); 2944 } 2945 2946 icl_program_mg_dp_mode(dig_port, crtc_state); 2947 2948 if (has_buf_trans_select(display)) 2949 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2950 2951 encoder->set_signal_levels(encoder, crtc_state); 2952 2953 intel_ddi_power_up_lanes(encoder, crtc_state); 2954 2955 if (!is_mst) 2956 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2957 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2958 if (!is_mst) 2959 intel_dp_sink_enable_decompression(state, 2960 to_intel_connector(conn_state->connector), 2961 crtc_state); 2962 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2963 intel_dp_start_link_train(state, intel_dp, crtc_state); 2964 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2965 !is_trans_port_sync_mode(crtc_state)) 2966 intel_dp_stop_link_train(intel_dp, crtc_state); 2967 2968 intel_ddi_enable_fec(encoder, crtc_state); 2969 2970 if (!is_mst) { 2971 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2972 intel_dsc_dp_pps_write(encoder, crtc_state); 2973 } 2974 } 2975 2976 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2977 struct intel_encoder *encoder, 2978 const struct intel_crtc_state *crtc_state, 2979 const struct drm_connector_state *conn_state) 2980 { 2981 struct intel_display *display = to_intel_display(encoder); 2982 2983 if (HAS_DP20(display)) 2984 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2985 crtc_state); 2986 2987 /* Panel replay has to be enabled in sink dpcd before link training. */ 2988 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2989 2990 if (DISPLAY_VER(display) >= 14) 2991 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2992 else if (DISPLAY_VER(display) >= 12) 2993 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2994 else 2995 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2996 2997 /* MST will call a setting of MSA after an allocating of Virtual Channel 2998 * from MST encoder pre_enable callback. 2999 */ 3000 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 3001 intel_ddi_set_dp_msa(crtc_state, conn_state); 3002 } 3003 3004 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 3005 struct intel_encoder *encoder, 3006 const struct intel_crtc_state *crtc_state, 3007 const struct drm_connector_state *conn_state) 3008 { 3009 struct intel_display *display = to_intel_display(encoder); 3010 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3011 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3012 3013 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3014 intel_ddi_enable_clock(encoder, crtc_state); 3015 3016 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 3017 dig_port->ddi_io_wakeref = intel_display_power_get(display, 3018 dig_port->ddi_io_power_domain); 3019 3020 icl_program_mg_dp_mode(dig_port, crtc_state); 3021 3022 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 3023 3024 dig_port->set_infoframes(encoder, 3025 crtc_state->has_infoframe, 3026 crtc_state, conn_state); 3027 } 3028 3029 /* 3030 * Note: Also called from the ->pre_enable of the first active MST stream 3031 * encoder on its primary encoder. 3032 * 3033 * When called from DP MST code: 3034 * 3035 * - conn_state will be NULL 3036 * 3037 * - encoder will be the primary encoder (i.e. mst->primary) 3038 * 3039 * - the main connector associated with this port won't be active or linked to a 3040 * crtc 3041 * 3042 * - crtc_state will be the state of the first stream to be activated on this 3043 * port, and it may not be the same stream that will be deactivated last, but 3044 * each stream should have a state that is identical when it comes to the DP 3045 * link parameters. 3046 */ 3047 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3048 struct intel_encoder *encoder, 3049 const struct intel_crtc_state *crtc_state, 3050 const struct drm_connector_state *conn_state) 3051 { 3052 struct intel_display *display = to_intel_display(state); 3053 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3054 enum pipe pipe = crtc->pipe; 3055 3056 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3057 3058 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3059 3060 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3061 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3062 conn_state); 3063 } else { 3064 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3065 3066 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3067 conn_state); 3068 3069 /* FIXME precompute everything properly */ 3070 /* FIXME how do we turn infoframes off again? */ 3071 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3072 dig_port->set_infoframes(encoder, 3073 crtc_state->has_infoframe, 3074 crtc_state, conn_state); 3075 } 3076 } 3077 3078 static void 3079 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3080 { 3081 struct intel_display *display = to_intel_display(encoder); 3082 enum port port = encoder->port; 3083 intel_reg_t reg; 3084 u32 clr_bits, wait_bits; 3085 int ret; 3086 3087 if (DISPLAY_VER(display) < 14) 3088 return; 3089 3090 if (DISPLAY_VER(display) >= 20) { 3091 reg = DDI_BUF_CTL(port); 3092 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3093 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3094 } else { 3095 reg = XELPDP_PORT_BUF_CTL1(display, port); 3096 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3097 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3098 } 3099 3100 intel_de_rmw(display, reg, clr_bits, 0); 3101 3102 ret = intel_de_wait_for_clear_us(display, reg, wait_bits, 100); 3103 if (ret) 3104 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3105 port_name(port)); 3106 } 3107 3108 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3109 { 3110 struct intel_display *display = to_intel_display(encoder); 3111 enum port port = encoder->port; 3112 3113 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3114 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3115 3116 intel_wait_ddi_buf_active(encoder); 3117 } 3118 3119 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3120 const struct intel_crtc_state *crtc_state) 3121 { 3122 struct intel_display *display = to_intel_display(encoder); 3123 enum port port = encoder->port; 3124 3125 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3126 3127 if (DISPLAY_VER(display) >= 14) 3128 intel_wait_ddi_buf_idle(display, port); 3129 3130 mtl_ddi_disable_d2d(encoder); 3131 3132 if (intel_crtc_has_dp_encoder(crtc_state)) { 3133 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3134 DP_TP_CTL_ENABLE, 0); 3135 } 3136 3137 intel_dip_cmn_sdp_transmission_line_disable(crtc_state); 3138 intel_ddi_disable_fec(encoder, crtc_state); 3139 3140 if (DISPLAY_VER(display) < 14) 3141 intel_wait_ddi_buf_idle(display, port); 3142 3143 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3144 } 3145 3146 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3147 struct intel_encoder *encoder, 3148 const struct intel_crtc_state *old_crtc_state, 3149 const struct drm_connector_state *old_conn_state) 3150 { 3151 struct intel_display *display = to_intel_display(encoder); 3152 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3153 struct intel_dp *intel_dp = &dig_port->dp; 3154 struct ref_tracker *wakeref; 3155 bool is_mst = intel_crtc_has_type(old_crtc_state, 3156 INTEL_OUTPUT_DP_MST); 3157 3158 if (!is_mst) 3159 intel_dp_set_infoframes(encoder, false, 3160 old_crtc_state, old_conn_state); 3161 3162 /* 3163 * Power down sink before disabling the port, otherwise we end 3164 * up getting interrupts from the sink on detecting link loss. 3165 */ 3166 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3167 3168 if (DISPLAY_VER(display) >= 12) { 3169 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3170 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3171 3172 intel_de_rmw(display, 3173 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3174 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3175 0); 3176 } 3177 } else { 3178 if (!is_mst) 3179 intel_ddi_disable_transcoder_clock(old_crtc_state); 3180 } 3181 3182 intel_ddi_buf_disable(encoder, old_crtc_state); 3183 3184 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3185 3186 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3187 3188 /* 3189 * From TGL spec: "If single stream or multi-stream master transcoder: 3190 * Configure Transcoder Clock select to direct no clock to the 3191 * transcoder" 3192 */ 3193 if (DISPLAY_VER(display) >= 12) 3194 intel_ddi_disable_transcoder_clock(old_crtc_state); 3195 3196 intel_pps_vdd_on(intel_dp); 3197 intel_pps_off(intel_dp); 3198 3199 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3200 3201 if (wakeref) 3202 intel_display_power_put(display, 3203 dig_port->ddi_io_power_domain, 3204 wakeref); 3205 3206 intel_ddi_disable_clock(encoder); 3207 3208 /* De-select Thunderbolt */ 3209 if (DISPLAY_VER(display) >= 14) 3210 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3211 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3212 } 3213 3214 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3215 struct intel_encoder *encoder, 3216 const struct intel_crtc_state *old_crtc_state, 3217 const struct drm_connector_state *old_conn_state) 3218 { 3219 struct intel_display *display = to_intel_display(encoder); 3220 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3221 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3222 struct ref_tracker *wakeref; 3223 3224 dig_port->set_infoframes(encoder, false, 3225 old_crtc_state, old_conn_state); 3226 3227 if (DISPLAY_VER(display) < 12) 3228 intel_ddi_disable_transcoder_clock(old_crtc_state); 3229 3230 intel_ddi_buf_disable(encoder, old_crtc_state); 3231 3232 if (DISPLAY_VER(display) >= 12) 3233 intel_ddi_disable_transcoder_clock(old_crtc_state); 3234 3235 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3236 if (wakeref) 3237 intel_display_power_put(display, 3238 dig_port->ddi_io_power_domain, 3239 wakeref); 3240 3241 intel_ddi_disable_clock(encoder); 3242 3243 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3244 } 3245 3246 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3247 struct intel_encoder *encoder, 3248 const struct intel_crtc_state *old_crtc_state, 3249 const struct drm_connector_state *old_conn_state) 3250 { 3251 struct intel_display *display = to_intel_display(encoder); 3252 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3253 struct intel_crtc *pipe_crtc; 3254 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3255 3256 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) { 3257 const struct intel_crtc_state *old_pipe_crtc_state = 3258 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3259 3260 intel_crtc_vblank_off(old_pipe_crtc_state); 3261 } 3262 3263 intel_disable_transcoder(old_crtc_state); 3264 3265 /* 128b/132b SST */ 3266 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3267 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3268 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3269 3270 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3271 3272 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3273 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3274 3275 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3276 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3277 } 3278 3279 intel_vrr_transcoder_disable(old_crtc_state); 3280 3281 intel_ddi_disable_transcoder_func(old_crtc_state); 3282 3283 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) { 3284 const struct intel_crtc_state *old_pipe_crtc_state = 3285 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3286 3287 intel_dsc_disable(old_pipe_crtc_state); 3288 3289 if (DISPLAY_VER(display) >= 9) 3290 skl_scaler_disable(old_pipe_crtc_state); 3291 else 3292 ilk_pfit_disable(old_pipe_crtc_state); 3293 } 3294 } 3295 3296 /* 3297 * Note: Also called from the ->post_disable of the last active MST stream 3298 * encoder on its primary encoder. See also the comment for 3299 * intel_ddi_pre_enable(). 3300 */ 3301 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3302 struct intel_encoder *encoder, 3303 const struct intel_crtc_state *old_crtc_state, 3304 const struct drm_connector_state *old_conn_state) 3305 { 3306 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3307 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3308 old_conn_state); 3309 3310 /* 3311 * When called from DP MST code: 3312 * - old_conn_state will be NULL 3313 * - encoder will be the main encoder (ie. mst->primary) 3314 * - the main connector associated with this port 3315 * won't be active or linked to a crtc 3316 * - old_crtc_state will be the state of the last stream to 3317 * be deactivated on this port, and it may not be the same 3318 * stream that was activated last, but each stream 3319 * should have a state that is identical when it comes to 3320 * the DP link parameters 3321 */ 3322 3323 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3324 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3325 old_conn_state); 3326 else 3327 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3328 old_conn_state); 3329 } 3330 3331 /* 3332 * Note: Also called from the ->post_pll_disable of the last active MST stream 3333 * encoder on its primary encoder. See also the comment for 3334 * intel_ddi_pre_enable(). 3335 */ 3336 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3337 struct intel_encoder *encoder, 3338 const struct intel_crtc_state *old_crtc_state, 3339 const struct drm_connector_state *old_conn_state) 3340 { 3341 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3342 3343 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3344 3345 if (intel_encoder_is_tc(encoder)) 3346 intel_tc_port_put_link(dig_port); 3347 } 3348 3349 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3350 struct intel_encoder *encoder, 3351 const struct intel_crtc_state *crtc_state) 3352 { 3353 const struct drm_connector_state *conn_state; 3354 struct drm_connector *conn; 3355 int i; 3356 3357 if (!crtc_state->sync_mode_slaves_mask) 3358 return; 3359 3360 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3361 struct intel_encoder *slave_encoder = 3362 to_intel_encoder(conn_state->best_encoder); 3363 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3364 const struct intel_crtc_state *slave_crtc_state; 3365 3366 if (!slave_crtc) 3367 continue; 3368 3369 slave_crtc_state = 3370 intel_atomic_get_new_crtc_state(state, slave_crtc); 3371 3372 if (slave_crtc_state->master_transcoder != 3373 crtc_state->cpu_transcoder) 3374 continue; 3375 3376 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3377 slave_crtc_state); 3378 } 3379 3380 usleep_range(200, 400); 3381 3382 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3383 crtc_state); 3384 } 3385 3386 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3387 struct intel_encoder *encoder, 3388 const struct intel_crtc_state *crtc_state, 3389 const struct drm_connector_state *conn_state) 3390 { 3391 struct intel_display *display = to_intel_display(encoder); 3392 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3393 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3394 enum port port = encoder->port; 3395 3396 if (port == PORT_A && DISPLAY_VER(display) < 9) 3397 intel_dp_stop_link_train(intel_dp, crtc_state); 3398 3399 drm_connector_update_privacy_screen(conn_state); 3400 intel_edp_backlight_on(crtc_state, conn_state); 3401 3402 intel_panel_prepare(crtc_state, conn_state); 3403 3404 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3405 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3406 3407 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3408 } 3409 3410 static intel_reg_t 3411 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3412 { 3413 static const enum transcoder trans[] = { 3414 [PORT_A] = TRANSCODER_EDP, 3415 [PORT_B] = TRANSCODER_A, 3416 [PORT_C] = TRANSCODER_B, 3417 [PORT_D] = TRANSCODER_C, 3418 [PORT_E] = TRANSCODER_A, 3419 }; 3420 3421 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3422 3423 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3424 port = PORT_A; 3425 3426 return CHICKEN_TRANS(display, trans[port]); 3427 } 3428 3429 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3430 struct intel_encoder *encoder, 3431 const struct intel_crtc_state *crtc_state, 3432 const struct drm_connector_state *conn_state) 3433 { 3434 struct intel_display *display = to_intel_display(encoder); 3435 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3436 struct drm_connector *connector = conn_state->connector; 3437 enum port port = encoder->port; 3438 u32 buf_ctl = 0; 3439 3440 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3441 crtc_state->hdmi_high_tmds_clock_ratio, 3442 crtc_state->hdmi_scrambling)) 3443 drm_dbg_kms(display->drm, 3444 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3445 connector->base.id, connector->name); 3446 3447 if (has_buf_trans_select(display)) 3448 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3449 3450 /* e. Enable D2D Link for C10/C20 Phy */ 3451 mtl_ddi_enable_d2d(encoder); 3452 3453 encoder->set_signal_levels(encoder, crtc_state); 3454 3455 /* Display WA #1143: skl,kbl,cfl */ 3456 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3457 /* 3458 * For some reason these chicken bits have been 3459 * stuffed into a transcoder register, event though 3460 * the bits affect a specific DDI port rather than 3461 * a specific transcoder. 3462 */ 3463 intel_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3464 u32 val; 3465 3466 val = intel_de_read(display, reg); 3467 3468 if (port == PORT_E) 3469 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3470 DDIE_TRAINING_OVERRIDE_VALUE; 3471 else 3472 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3473 DDI_TRAINING_OVERRIDE_VALUE; 3474 3475 intel_de_write(display, reg, val); 3476 intel_de_posting_read(display, reg); 3477 3478 udelay(1); 3479 3480 if (port == PORT_E) 3481 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3482 DDIE_TRAINING_OVERRIDE_VALUE); 3483 else 3484 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3485 DDI_TRAINING_OVERRIDE_VALUE); 3486 3487 intel_de_write(display, reg, val); 3488 } 3489 3490 intel_ddi_power_up_lanes(encoder, crtc_state); 3491 3492 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3493 * are ignored so nothing special needs to be done besides 3494 * enabling the port. 3495 * 3496 * On ADL_P the PHY link rate and lane count must be programmed but 3497 * these are both 0 for HDMI. 3498 * 3499 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3500 * is filled with lane count, already set in the crtc_state. 3501 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3502 */ 3503 if (dig_port->lane_reversal) 3504 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3505 if (dig_port->ddi_a_4_lanes) 3506 buf_ctl |= DDI_A_4_LANES; 3507 3508 if (DISPLAY_VER(display) >= 14) { 3509 u32 port_buf = 0; 3510 3511 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3512 3513 if (dig_port->lane_reversal) 3514 port_buf |= XELPDP_PORT_REVERSAL; 3515 3516 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3517 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3518 3519 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3520 3521 if (DISPLAY_VER(display) >= 20) 3522 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3523 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3524 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3525 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3526 } 3527 3528 intel_ddi_buf_enable(encoder, buf_ctl); 3529 3530 intel_hdmi_poll_for_scrambling_enable(crtc_state, connector); 3531 } 3532 3533 static void intel_ddi_enable(struct intel_atomic_state *state, 3534 struct intel_encoder *encoder, 3535 const struct intel_crtc_state *crtc_state, 3536 const struct drm_connector_state *conn_state) 3537 { 3538 struct intel_display *display = to_intel_display(encoder); 3539 struct intel_crtc *pipe_crtc; 3540 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3541 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3542 3543 /* 128b/132b SST */ 3544 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3545 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3546 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3547 3548 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3549 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3550 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3551 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3552 } 3553 3554 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3555 3556 intel_vrr_transcoder_enable(crtc_state); 3557 3558 /* 128b/132b SST */ 3559 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3560 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3561 3562 intel_ddi_clear_act_sent(encoder, crtc_state); 3563 3564 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3565 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3566 3567 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3568 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3569 } 3570 3571 intel_enable_transcoder(crtc_state); 3572 3573 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3574 3575 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) { 3576 const struct intel_crtc_state *pipe_crtc_state = 3577 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3578 3579 intel_crtc_vblank_on(pipe_crtc_state); 3580 } 3581 3582 if (is_hdmi) 3583 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3584 else 3585 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3586 3587 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3588 3589 } 3590 3591 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3592 struct intel_encoder *encoder, 3593 const struct intel_crtc_state *old_crtc_state, 3594 const struct drm_connector_state *old_conn_state) 3595 { 3596 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3597 struct intel_connector *connector = 3598 to_intel_connector(old_conn_state->connector); 3599 3600 intel_dp->link.active = false; 3601 3602 intel_panel_unprepare(old_conn_state); 3603 intel_psr_disable(intel_dp, old_crtc_state); 3604 intel_alpm_disable(intel_dp); 3605 intel_edp_backlight_off(old_conn_state); 3606 /* Disable the decompression in DP Sink */ 3607 intel_dp_sink_disable_decompression(state, 3608 connector, old_crtc_state); 3609 /* Disable Ignore_MSA bit in DP Sink */ 3610 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3611 false); 3612 } 3613 3614 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3615 struct intel_encoder *encoder, 3616 const struct intel_crtc_state *old_crtc_state, 3617 const struct drm_connector_state *old_conn_state) 3618 { 3619 struct intel_display *display = to_intel_display(encoder); 3620 struct drm_connector *connector = old_conn_state->connector; 3621 3622 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3623 false, false)) 3624 drm_dbg_kms(display->drm, 3625 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3626 connector->base.id, connector->name); 3627 } 3628 3629 static void intel_ddi_disable(struct intel_atomic_state *state, 3630 struct intel_encoder *encoder, 3631 const struct intel_crtc_state *old_crtc_state, 3632 const struct drm_connector_state *old_conn_state) 3633 { 3634 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3635 3636 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3637 3638 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3639 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3640 old_conn_state); 3641 else 3642 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3643 old_conn_state); 3644 } 3645 3646 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3647 struct intel_encoder *encoder, 3648 const struct intel_crtc_state *crtc_state, 3649 const struct drm_connector_state *conn_state) 3650 { 3651 intel_ddi_set_dp_msa(crtc_state, conn_state); 3652 3653 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3654 3655 intel_backlight_update(state, encoder, crtc_state, conn_state); 3656 drm_connector_update_privacy_screen(conn_state); 3657 } 3658 3659 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3660 const struct intel_crtc_state *crtc_state, 3661 const struct drm_connector_state *conn_state) 3662 { 3663 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3664 } 3665 3666 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3667 struct intel_encoder *encoder, 3668 const struct intel_crtc_state *crtc_state, 3669 const struct drm_connector_state *conn_state) 3670 { 3671 3672 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3673 !intel_encoder_is_mst(encoder)) 3674 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3675 conn_state); 3676 3677 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3678 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3679 conn_state); 3680 3681 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3682 } 3683 3684 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3685 struct intel_encoder *encoder, 3686 struct intel_crtc *crtc) 3687 { 3688 struct intel_display *display = to_intel_display(encoder); 3689 const struct intel_crtc_state *crtc_state = 3690 intel_atomic_get_new_crtc_state(state, crtc); 3691 struct intel_crtc *pipe_crtc; 3692 3693 /* FIXME: Add NVL+ and DG2 pll_mgr */ 3694 if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr) 3695 return; 3696 3697 for_each_intel_crtc_in_pipe_mask(display, pipe_crtc, 3698 intel_crtc_joined_pipe_mask(crtc_state)) 3699 intel_dpll_update_active(state, pipe_crtc, encoder); 3700 } 3701 3702 /* 3703 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3704 * encoder on its primary encoder. See also the comment for 3705 * intel_ddi_pre_enable(). 3706 */ 3707 static void 3708 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3709 struct intel_encoder *encoder, 3710 const struct intel_crtc_state *crtc_state, 3711 const struct drm_connector_state *conn_state) 3712 { 3713 struct intel_display *display = to_intel_display(encoder); 3714 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3715 bool is_tc_port = intel_encoder_is_tc(encoder); 3716 3717 if (is_tc_port) { 3718 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3719 3720 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3721 intel_ddi_update_active_dpll(state, encoder, crtc); 3722 } 3723 3724 main_link_aux_power_domain_get(dig_port, crtc_state); 3725 3726 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3727 /* 3728 * Program the lane count for static/dynamic connections on 3729 * Type-C ports. Skip this step for TBT. 3730 */ 3731 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3732 else if (display->platform.geminilake || display->platform.broxton) 3733 bxt_dpio_phy_set_lane_optim_mask(encoder, 3734 crtc_state->lane_lat_optim_mask); 3735 3736 /* 3737 * There is no direct connection between the PLL and PPS, however 3738 * enabling PPS before PLL is required to avoid PLL/DDI BUF timeouts 3739 * during system resume. Do that matching the Bspec order as well. 3740 */ 3741 if (DISPLAY_VER(display) >= 14) 3742 intel_pps_on(&dig_port->dp); 3743 } 3744 3745 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3746 { 3747 struct intel_display *display = to_intel_display(encoder); 3748 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3749 int ln; 3750 3751 for (ln = 0; ln < 2; ln++) 3752 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3753 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3754 } 3755 3756 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3757 const struct intel_crtc_state *crtc_state) 3758 { 3759 struct intel_display *display = to_intel_display(crtc_state); 3760 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3761 struct intel_encoder *encoder = &dig_port->base; 3762 u32 dp_tp_ctl; 3763 3764 /* 3765 * TODO: To train with only a different voltage swing entry is not 3766 * necessary disable and enable port 3767 */ 3768 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3769 3770 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3771 3772 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3773 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3774 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3775 intel_dp_is_uhbr(crtc_state)) { 3776 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3777 } else { 3778 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3779 if (crtc_state->enhanced_framing) 3780 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3781 } 3782 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3783 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3784 3785 /* 6.f Enable D2D Link */ 3786 mtl_ddi_enable_d2d(encoder); 3787 3788 /* 6.g Configure voltage swing and related IO settings */ 3789 encoder->set_signal_levels(encoder, crtc_state); 3790 3791 /* 6.h Configure PORT_BUF_CTL1 */ 3792 mtl_port_buf_ctl_program(encoder, crtc_state); 3793 3794 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3795 if (DISPLAY_VER(display) >= 20) 3796 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3797 3798 intel_ddi_buf_enable(encoder, intel_dp->DP); 3799 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3800 3801 /* 3802 * 6.k If AUX-Less ALPM is going to be enabled: 3803 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here 3804 */ 3805 intel_alpm_port_configure(intel_dp, crtc_state); 3806 3807 /* 3808 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE 3809 * register 3810 */ 3811 intel_lnl_mac_transmit_lfps(encoder, crtc_state); 3812 } 3813 3814 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3815 const struct intel_crtc_state *crtc_state) 3816 { 3817 struct intel_display *display = to_intel_display(intel_dp); 3818 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3819 struct intel_encoder *encoder = &dig_port->base; 3820 u32 dp_tp_ctl; 3821 3822 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3823 3824 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3825 3826 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3827 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3828 intel_dp_is_uhbr(crtc_state)) { 3829 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3830 } else { 3831 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3832 if (crtc_state->enhanced_framing) 3833 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3834 } 3835 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3836 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3837 3838 if (display->platform.alderlake_p && 3839 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3840 adlp_tbt_to_dp_alt_switch_wa(encoder); 3841 3842 intel_ddi_buf_enable(encoder, intel_dp->DP); 3843 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3844 } 3845 3846 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3847 const struct intel_crtc_state *crtc_state, 3848 u8 dp_train_pat) 3849 { 3850 struct intel_display *display = to_intel_display(intel_dp); 3851 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3852 u32 temp; 3853 3854 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3855 3856 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3857 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3858 case DP_TRAINING_PATTERN_DISABLE: 3859 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3860 break; 3861 case DP_TRAINING_PATTERN_1: 3862 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3863 break; 3864 case DP_TRAINING_PATTERN_2: 3865 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3866 break; 3867 case DP_TRAINING_PATTERN_3: 3868 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3869 break; 3870 case DP_TRAINING_PATTERN_4: 3871 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3872 break; 3873 } 3874 3875 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3876 } 3877 3878 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3879 const struct intel_crtc_state *crtc_state) 3880 { 3881 struct intel_display *display = to_intel_display(intel_dp); 3882 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3883 enum port port = encoder->port; 3884 3885 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3886 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3887 3888 /* 3889 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3890 * reason we need to set idle transmission mode is to work around a HW 3891 * issue where we enable the pipe while not in idle link-training mode. 3892 * In this case there is requirement to wait for a minimum number of 3893 * idle patterns to be sent. 3894 */ 3895 if (port == PORT_A && DISPLAY_VER(display) < 12) 3896 return; 3897 3898 if (intel_de_wait_for_set_ms(display, 3899 dp_tp_status_reg(encoder, crtc_state), 3900 DP_TP_STATUS_IDLE_DONE, 2)) 3901 drm_err(display->drm, 3902 "Timed out waiting for DP idle patterns\n"); 3903 } 3904 3905 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3906 enum transcoder cpu_transcoder) 3907 { 3908 if (cpu_transcoder == TRANSCODER_EDP) 3909 return false; 3910 3911 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3912 return false; 3913 3914 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3915 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3916 } 3917 3918 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3919 { 3920 if (crtc_state->port_clock > 594000) 3921 return 2; 3922 else 3923 return 0; 3924 } 3925 3926 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3927 { 3928 if (crtc_state->port_clock > 594000) 3929 return 3; 3930 else 3931 return 0; 3932 } 3933 3934 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3935 { 3936 if (crtc_state->port_clock > 594000) 3937 return 1; 3938 else 3939 return 0; 3940 } 3941 3942 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3943 { 3944 struct intel_display *display = to_intel_display(crtc_state); 3945 3946 if (DISPLAY_VER(display) >= 14) 3947 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3948 else if (DISPLAY_VER(display) >= 12) 3949 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3950 else if (display->platform.jasperlake || display->platform.elkhartlake) 3951 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3952 else if (DISPLAY_VER(display) >= 11) 3953 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3954 } 3955 3956 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3957 enum transcoder cpu_transcoder) 3958 { 3959 u32 master_select; 3960 3961 if (DISPLAY_VER(display) >= 11) { 3962 u32 ctl2 = intel_de_read(display, 3963 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3964 3965 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3966 return INVALID_TRANSCODER; 3967 3968 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3969 } else { 3970 u32 ctl = intel_de_read(display, 3971 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3972 3973 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3974 return INVALID_TRANSCODER; 3975 3976 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3977 } 3978 3979 if (master_select == 0) 3980 return TRANSCODER_EDP; 3981 else 3982 return master_select - 1; 3983 } 3984 3985 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3986 { 3987 struct intel_display *display = to_intel_display(crtc_state); 3988 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3989 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3990 enum transcoder cpu_transcoder; 3991 3992 crtc_state->master_transcoder = 3993 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3994 3995 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3996 enum intel_display_power_domain power_domain; 3997 struct ref_tracker *trans_wakeref; 3998 3999 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4000 trans_wakeref = intel_display_power_get_if_enabled(display, 4001 power_domain); 4002 4003 if (!trans_wakeref) 4004 continue; 4005 4006 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 4007 crtc_state->cpu_transcoder) 4008 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 4009 4010 intel_display_power_put(display, power_domain, trans_wakeref); 4011 } 4012 4013 drm_WARN_ON(display->drm, 4014 crtc_state->master_transcoder != INVALID_TRANSCODER && 4015 crtc_state->sync_mode_slaves_mask); 4016 } 4017 4018 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 4019 struct intel_crtc_state *crtc_state, 4020 u32 ddi_func_ctl) 4021 { 4022 struct intel_display *display = to_intel_display(encoder); 4023 4024 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 4025 if (DISPLAY_VER(display) >= 14) 4026 crtc_state->lane_count = 4027 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4028 else 4029 crtc_state->lane_count = 4; 4030 } 4031 4032 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 4033 struct intel_crtc_state *crtc_state, 4034 u32 ddi_func_ctl) 4035 { 4036 crtc_state->has_hdmi_sink = true; 4037 4038 crtc_state->infoframes.enable |= 4039 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4040 4041 if (crtc_state->infoframes.enable) 4042 crtc_state->has_infoframe = true; 4043 4044 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4045 crtc_state->hdmi_scrambling = true; 4046 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4047 crtc_state->hdmi_high_tmds_clock_ratio = true; 4048 4049 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4050 } 4051 4052 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4053 struct intel_crtc_state *crtc_state, 4054 u32 ddi_func_ctl) 4055 { 4056 struct intel_display *display = to_intel_display(encoder); 4057 4058 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4059 crtc_state->enhanced_framing = 4060 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4061 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4062 } 4063 4064 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4065 struct intel_crtc_state *crtc_state, 4066 u32 ddi_func_ctl) 4067 { 4068 struct intel_display *display = to_intel_display(encoder); 4069 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4070 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4071 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4072 4073 if (encoder->type == INTEL_OUTPUT_EDP) 4074 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4075 else 4076 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4077 crtc_state->lane_count = 4078 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4079 4080 if (DISPLAY_VER(display) >= 12 && 4081 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4082 crtc_state->mst_master_transcoder = 4083 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4084 4085 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4086 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4087 4088 crtc_state->enhanced_framing = 4089 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4090 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4091 4092 if (DISPLAY_VER(display) >= 11) 4093 crtc_state->fec_enable = 4094 intel_de_read(display, 4095 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4096 4097 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4098 crtc_state->infoframes.enable |= 4099 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4100 else 4101 crtc_state->infoframes.enable |= 4102 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4103 } 4104 4105 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4106 struct intel_crtc_state *crtc_state, 4107 u32 ddi_func_ctl) 4108 { 4109 struct intel_display *display = to_intel_display(encoder); 4110 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4111 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4112 4113 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4114 crtc_state->lane_count = 4115 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4116 4117 if (DISPLAY_VER(display) >= 12) 4118 crtc_state->mst_master_transcoder = 4119 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4120 4121 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4122 4123 if (DISPLAY_VER(display) >= 11) 4124 crtc_state->fec_enable = 4125 intel_de_read(display, 4126 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4127 4128 crtc_state->infoframes.enable |= 4129 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4130 } 4131 4132 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4133 struct intel_crtc_state *pipe_config) 4134 { 4135 struct intel_display *display = to_intel_display(encoder); 4136 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4137 u32 ddi_func_ctl, ddi_mode, flags = 0; 4138 4139 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4140 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4141 flags |= DRM_MODE_FLAG_PHSYNC; 4142 else 4143 flags |= DRM_MODE_FLAG_NHSYNC; 4144 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4145 flags |= DRM_MODE_FLAG_PVSYNC; 4146 else 4147 flags |= DRM_MODE_FLAG_NVSYNC; 4148 4149 pipe_config->hw.adjusted_mode.flags |= flags; 4150 4151 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4152 case TRANS_DDI_BPC_6: 4153 pipe_config->pipe_bpp = 18; 4154 break; 4155 case TRANS_DDI_BPC_8: 4156 pipe_config->pipe_bpp = 24; 4157 break; 4158 case TRANS_DDI_BPC_10: 4159 pipe_config->pipe_bpp = 30; 4160 break; 4161 case TRANS_DDI_BPC_12: 4162 pipe_config->pipe_bpp = 36; 4163 break; 4164 default: 4165 break; 4166 } 4167 4168 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4169 4170 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4171 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4172 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4173 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4174 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4175 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4176 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4177 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4178 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4179 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4180 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4181 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4182 4183 /* 4184 * If this is true, we know we're being called from mst stream 4185 * encoder's ->get_config(). 4186 */ 4187 if (intel_dp_mst_active_streams(intel_dp)) 4188 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4189 else 4190 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4191 } 4192 } 4193 4194 /* 4195 * Note: Also called from the ->get_config of the MST stream encoders on their 4196 * primary encoder, via the platform specific hooks here. See also the comment 4197 * for intel_ddi_pre_enable(). 4198 */ 4199 static void intel_ddi_get_config(struct intel_encoder *encoder, 4200 struct intel_crtc_state *pipe_config) 4201 { 4202 struct intel_display *display = to_intel_display(encoder); 4203 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4204 4205 /* XXX: DSI transcoder paranoia */ 4206 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4207 return; 4208 4209 intel_ddi_read_func_ctl(encoder, pipe_config); 4210 4211 intel_ddi_mso_get_config(encoder, pipe_config); 4212 4213 pipe_config->has_audio = 4214 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4215 4216 if (encoder->type == INTEL_OUTPUT_EDP) 4217 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4218 4219 ddi_dotclock_get(pipe_config); 4220 4221 if (display->platform.geminilake || display->platform.broxton) 4222 pipe_config->lane_lat_optim_mask = 4223 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4224 4225 intel_ddi_compute_min_voltage_level(pipe_config); 4226 4227 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4228 4229 intel_read_infoframe(encoder, pipe_config, 4230 HDMI_INFOFRAME_TYPE_AVI, 4231 &pipe_config->infoframes.avi); 4232 intel_read_infoframe(encoder, pipe_config, 4233 HDMI_INFOFRAME_TYPE_SPD, 4234 &pipe_config->infoframes.spd); 4235 intel_read_infoframe(encoder, pipe_config, 4236 HDMI_INFOFRAME_TYPE_VENDOR, 4237 &pipe_config->infoframes.hdmi); 4238 intel_read_infoframe(encoder, pipe_config, 4239 HDMI_INFOFRAME_TYPE_DRM, 4240 &pipe_config->infoframes.drm); 4241 4242 if (DISPLAY_VER(display) >= 8) 4243 bdw_get_trans_port_sync_config(pipe_config); 4244 4245 intel_psr_get_config(encoder, pipe_config); 4246 4247 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4248 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4249 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4250 intel_dip_sdp_transmission_line_get_config(pipe_config); 4251 4252 intel_audio_codec_get_config(encoder, pipe_config); 4253 } 4254 4255 void intel_ddi_get_clock(struct intel_encoder *encoder, 4256 struct intel_crtc_state *crtc_state, 4257 struct intel_dpll *pll) 4258 { 4259 struct intel_display *display = to_intel_display(encoder); 4260 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4261 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4262 bool pll_active; 4263 4264 if (drm_WARN_ON(display->drm, !pll)) 4265 return; 4266 4267 port_dpll->pll = pll; 4268 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4269 drm_WARN_ON(display->drm, !pll_active); 4270 4271 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4272 4273 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4274 &crtc_state->dpll_hw_state); 4275 } 4276 4277 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4278 { 4279 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4280 } 4281 4282 static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder, 4283 struct intel_crtc_state *crtc_state, 4284 enum icl_port_dpll_id port_dpll_id, 4285 enum intel_dpll_id pll_id) 4286 { 4287 struct intel_display *display = to_intel_display(encoder); 4288 struct icl_port_dpll *port_dpll; 4289 struct intel_dpll *pll; 4290 bool pll_active; 4291 4292 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4293 pll = intel_get_dpll_by_id(display, pll_id); 4294 4295 if (drm_WARN_ON(display->drm, !pll)) 4296 return; 4297 4298 port_dpll->pll = pll; 4299 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4300 drm_WARN_ON(display->drm, !pll_active); 4301 4302 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4303 4304 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4305 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4306 else 4307 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4308 &crtc_state->dpll_hw_state); 4309 4310 intel_ddi_get_config(encoder, crtc_state); 4311 } 4312 4313 /* 4314 * Get the configuration for either a port using a C10 PHY PLL, or a port using a 4315 * C20 PHY PLL in the cases of: 4316 * - BMG port A/B 4317 * - PTL port B eDP over TypeC PHY 4318 */ 4319 static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder, 4320 struct intel_crtc_state *crtc_state) 4321 { 4322 struct intel_display *display = to_intel_display(encoder); 4323 4324 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4325 mtl_port_to_pll_id(display, encoder->port)); 4326 } 4327 4328 static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder, 4329 struct intel_crtc_state *crtc_state) 4330 { 4331 struct intel_display *display = to_intel_display(encoder); 4332 4333 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 4334 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4335 DPLL_ID_ICL_TBTPLL); 4336 else 4337 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY, 4338 mtl_port_to_pll_id(display, encoder->port)); 4339 } 4340 4341 static struct intel_dpll *dg2_ddi_get_pll(struct intel_encoder *encoder) 4342 { 4343 struct intel_display *display = to_intel_display(encoder); 4344 4345 return intel_get_dpll_by_id(display, dg2_port_to_pll_id(encoder->port)); 4346 } 4347 4348 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4349 struct intel_crtc_state *crtc_state) 4350 { 4351 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; 4352 struct intel_dpll *pll = dg2_ddi_get_pll(encoder); 4353 4354 if (pll) 4355 intel_ddi_get_clock(encoder, crtc_state, pll); 4356 4357 /* 4358 * Keep the hw readout robust against unexpected NULL PLL lookups, 4359 * so modeset verify always has intel_dpll populated for DG2. 4360 */ 4361 if (!crtc_state->intel_dpll) { 4362 port_dpll->pll = pll; 4363 intel_mpllb_readout_hw_state(encoder, &port_dpll->hw_state.mpllb); 4364 icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); 4365 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, 4366 &port_dpll->hw_state.mpllb); 4367 } 4368 4369 intel_ddi_get_config(encoder, crtc_state); 4370 } 4371 4372 static void adls_ddi_get_config(struct intel_encoder *encoder, 4373 struct intel_crtc_state *crtc_state) 4374 { 4375 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4376 intel_ddi_get_config(encoder, crtc_state); 4377 } 4378 4379 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4380 struct intel_crtc_state *crtc_state) 4381 { 4382 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4383 intel_ddi_get_config(encoder, crtc_state); 4384 } 4385 4386 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4387 struct intel_crtc_state *crtc_state) 4388 { 4389 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4390 intel_ddi_get_config(encoder, crtc_state); 4391 } 4392 4393 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4394 struct intel_crtc_state *crtc_state) 4395 { 4396 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4397 intel_ddi_get_config(encoder, crtc_state); 4398 } 4399 4400 static enum icl_port_dpll_id 4401 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4402 const struct intel_crtc_state *crtc_state) 4403 { 4404 struct intel_display *display = to_intel_display(encoder); 4405 const struct intel_dpll *pll = crtc_state->intel_dpll; 4406 4407 if (drm_WARN_ON(display->drm, !pll)) 4408 return ICL_PORT_DPLL_DEFAULT; 4409 4410 if (icl_ddi_tc_pll_is_tbt(pll)) 4411 return ICL_PORT_DPLL_DEFAULT; 4412 else 4413 return ICL_PORT_DPLL_MG_PHY; 4414 } 4415 4416 enum icl_port_dpll_id 4417 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4418 const struct intel_crtc_state *crtc_state) 4419 { 4420 if (!encoder->port_pll_type) 4421 return ICL_PORT_DPLL_DEFAULT; 4422 4423 return encoder->port_pll_type(encoder, crtc_state); 4424 } 4425 4426 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4427 struct intel_crtc_state *crtc_state, 4428 struct intel_dpll *pll) 4429 { 4430 struct intel_display *display = to_intel_display(encoder); 4431 enum icl_port_dpll_id port_dpll_id; 4432 struct icl_port_dpll *port_dpll; 4433 bool pll_active; 4434 4435 if (drm_WARN_ON(display->drm, !pll)) 4436 return; 4437 4438 if (icl_ddi_tc_pll_is_tbt(pll)) 4439 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4440 else 4441 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4442 4443 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4444 4445 port_dpll->pll = pll; 4446 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4447 drm_WARN_ON(display->drm, !pll_active); 4448 4449 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4450 4451 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4452 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4453 else 4454 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4455 &crtc_state->dpll_hw_state); 4456 } 4457 4458 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4459 struct intel_crtc_state *crtc_state) 4460 { 4461 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4462 intel_ddi_get_config(encoder, crtc_state); 4463 } 4464 4465 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4466 struct intel_crtc_state *crtc_state) 4467 { 4468 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4469 intel_ddi_get_config(encoder, crtc_state); 4470 } 4471 4472 static void skl_ddi_get_config(struct intel_encoder *encoder, 4473 struct intel_crtc_state *crtc_state) 4474 { 4475 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4476 intel_ddi_get_config(encoder, crtc_state); 4477 } 4478 4479 void hsw_ddi_get_config(struct intel_encoder *encoder, 4480 struct intel_crtc_state *crtc_state) 4481 { 4482 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4483 intel_ddi_get_config(encoder, crtc_state); 4484 } 4485 4486 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4487 const struct intel_crtc_state *crtc_state) 4488 { 4489 if (intel_encoder_is_tc(encoder)) 4490 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4491 crtc_state); 4492 4493 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4494 (!crtc_state && intel_encoder_is_dp(encoder))) 4495 intel_dp_sync_state(encoder, crtc_state); 4496 } 4497 4498 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4499 struct intel_crtc_state *crtc_state) 4500 { 4501 struct intel_display *display = to_intel_display(encoder); 4502 bool fastset = true; 4503 4504 if (intel_encoder_is_tc(encoder)) { 4505 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4506 encoder->base.base.id, encoder->base.name); 4507 crtc_state->uapi.mode_changed = true; 4508 fastset = false; 4509 } 4510 4511 if (intel_crtc_has_dp_encoder(crtc_state) && 4512 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4513 fastset = false; 4514 4515 return fastset; 4516 } 4517 4518 static enum intel_output_type 4519 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4520 struct intel_crtc_state *crtc_state, 4521 struct drm_connector_state *conn_state) 4522 { 4523 switch (conn_state->connector->connector_type) { 4524 case DRM_MODE_CONNECTOR_HDMIA: 4525 return INTEL_OUTPUT_HDMI; 4526 case DRM_MODE_CONNECTOR_eDP: 4527 return INTEL_OUTPUT_EDP; 4528 case DRM_MODE_CONNECTOR_DisplayPort: 4529 return INTEL_OUTPUT_DP; 4530 default: 4531 MISSING_CASE(conn_state->connector->connector_type); 4532 return INTEL_OUTPUT_UNUSED; 4533 } 4534 } 4535 4536 static int intel_ddi_compute_config(struct intel_atomic_state *state, 4537 struct intel_encoder *encoder, 4538 struct intel_crtc_state *pipe_config, 4539 struct drm_connector_state *conn_state) 4540 { 4541 struct intel_display *display = to_intel_display(encoder); 4542 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4543 enum port port = encoder->port; 4544 int ret; 4545 4546 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4547 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4548 4549 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4550 pipe_config->has_hdmi_sink = 4551 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4552 4553 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4554 } else { 4555 ret = intel_dp_compute_config(state, encoder, pipe_config, conn_state); 4556 } 4557 4558 if (ret) 4559 return ret; 4560 4561 if (display->platform.haswell && crtc->pipe == PIPE_A && 4562 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4563 pipe_config->pch_pfit.force_thru = 4564 pipe_config->pch_pfit.enabled || 4565 pipe_config->crc_enabled; 4566 4567 if (display->platform.geminilake || display->platform.broxton) 4568 pipe_config->lane_lat_optim_mask = 4569 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4570 4571 intel_ddi_compute_min_voltage_level(pipe_config); 4572 4573 return 0; 4574 } 4575 4576 static bool mode_equal(const struct drm_display_mode *mode1, 4577 const struct drm_display_mode *mode2) 4578 { 4579 return drm_mode_match(mode1, mode2, 4580 DRM_MODE_MATCH_TIMINGS | 4581 DRM_MODE_MATCH_FLAGS | 4582 DRM_MODE_MATCH_3D_FLAGS) && 4583 mode1->clock == mode2->clock; /* we want an exact match */ 4584 } 4585 4586 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4587 const struct intel_link_m_n *m_n_2) 4588 { 4589 return m_n_1->tu == m_n_2->tu && 4590 m_n_1->data_m == m_n_2->data_m && 4591 m_n_1->data_n == m_n_2->data_n && 4592 m_n_1->link_m == m_n_2->link_m && 4593 m_n_1->link_n == m_n_2->link_n; 4594 } 4595 4596 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4597 const struct intel_crtc_state *crtc_state2) 4598 { 4599 /* 4600 * FIXME the modeset sequence is currently wrong and 4601 * can't deal with joiner + port sync at the same time. 4602 */ 4603 return crtc_state1->hw.active && crtc_state2->hw.active && 4604 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4605 crtc_state1->output_types == crtc_state2->output_types && 4606 crtc_state1->output_format == crtc_state2->output_format && 4607 crtc_state1->lane_count == crtc_state2->lane_count && 4608 crtc_state1->port_clock == crtc_state2->port_clock && 4609 mode_equal(&crtc_state1->hw.adjusted_mode, 4610 &crtc_state2->hw.adjusted_mode) && 4611 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4612 } 4613 4614 static u16 4615 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4616 int tile_group_id) 4617 { 4618 struct intel_display *display = to_intel_display(ref_crtc_state); 4619 struct drm_connector *connector; 4620 const struct drm_connector_state *conn_state; 4621 struct intel_atomic_state *state = 4622 to_intel_atomic_state(ref_crtc_state->uapi.state); 4623 u16 transcoders = 0; 4624 int i; 4625 4626 /* 4627 * We don't enable port sync on BDW due to missing w/as and 4628 * due to not having adjusted the modeset sequence appropriately. 4629 * From, xe3lpd onwards we have defeatured this with reference to 4630 * Wa_16024710867 4631 */ 4632 if (!IS_DISPLAY_VER(display, 9, 20)) 4633 return 0; 4634 4635 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4636 return 0; 4637 4638 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4639 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4640 const struct intel_crtc_state *crtc_state; 4641 4642 if (!crtc) 4643 continue; 4644 4645 if (!connector->has_tile || 4646 connector->tile_group->id != 4647 tile_group_id) 4648 continue; 4649 crtc_state = intel_atomic_get_new_crtc_state(state, 4650 crtc); 4651 if (!crtcs_port_sync_compatible(ref_crtc_state, 4652 crtc_state)) 4653 continue; 4654 transcoders |= BIT(crtc_state->cpu_transcoder); 4655 } 4656 4657 return transcoders; 4658 } 4659 4660 static int intel_ddi_compute_config_late(struct intel_atomic_state *state, 4661 struct intel_encoder *encoder, 4662 struct intel_crtc_state *crtc_state, 4663 struct drm_connector_state *conn_state) 4664 { 4665 struct intel_display *display = to_intel_display(encoder); 4666 struct drm_connector *connector = conn_state->connector; 4667 u16 port_sync_transcoders = 0; 4668 int ret = 0; 4669 4670 if (intel_crtc_has_dp_encoder(crtc_state)) 4671 ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state); 4672 4673 if (ret) 4674 return ret; 4675 4676 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4677 encoder->base.base.id, encoder->base.name, 4678 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4679 4680 if (connector->has_tile) 4681 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4682 connector->tile_group->id); 4683 4684 /* 4685 * EDP Transcoders cannot be ensalved 4686 * make them a master always when present 4687 */ 4688 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4689 crtc_state->master_transcoder = TRANSCODER_EDP; 4690 else 4691 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4692 4693 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4694 crtc_state->master_transcoder = INVALID_TRANSCODER; 4695 crtc_state->sync_mode_slaves_mask = port_sync_transcoders & 4696 ~REG_BIT(crtc_state->cpu_transcoder); 4697 } 4698 4699 return 0; 4700 } 4701 4702 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4703 { 4704 struct intel_display *display = to_intel_display(encoder->dev); 4705 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4706 4707 intel_dp_encoder_flush_work(encoder); 4708 if (intel_encoder_is_tc(&dig_port->base)) 4709 intel_tc_port_cleanup(dig_port); 4710 intel_display_power_flush_work(display); 4711 4712 drm_encoder_cleanup(encoder); 4713 kfree(dig_port->hdcp.port_data.streams); 4714 intel_dp_link_cleanup(&dig_port->dp); 4715 kfree(dig_port); 4716 } 4717 4718 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4719 { 4720 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4721 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4722 4723 intel_dp->reset_link_params = true; 4724 intel_dp_invalidate_source_oui(intel_dp); 4725 4726 intel_pps_encoder_reset(intel_dp); 4727 4728 if (intel_encoder_is_tc(&dig_port->base)) 4729 intel_tc_port_init_mode(dig_port); 4730 } 4731 4732 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4733 { 4734 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4735 4736 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4737 4738 return 0; 4739 } 4740 4741 static const struct drm_encoder_funcs intel_ddi_funcs = { 4742 .reset = intel_ddi_encoder_reset, 4743 .destroy = intel_ddi_encoder_destroy, 4744 .late_register = intel_ddi_encoder_late_register, 4745 }; 4746 4747 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4748 { 4749 struct intel_display *display = to_intel_display(dig_port); 4750 struct intel_connector *connector; 4751 enum port port = dig_port->base.port; 4752 int err; 4753 4754 connector = intel_connector_alloc(); 4755 if (!connector) 4756 return -ENOMEM; 4757 4758 err = intel_dp_link_init(&dig_port->dp); 4759 if (err) 4760 goto err_dp_init; 4761 4762 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4763 if (DISPLAY_VER(display) >= 14) 4764 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4765 else 4766 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4767 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4768 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4769 4770 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4771 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4772 4773 if (!intel_dp_init_connector(dig_port, connector)) { 4774 err = -EINVAL; 4775 4776 goto err_init_connector; 4777 } 4778 4779 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4780 struct drm_privacy_screen *privacy_screen; 4781 4782 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4783 if (!IS_ERR(privacy_screen)) { 4784 drm_connector_attach_privacy_screen_provider(&connector->base, 4785 privacy_screen); 4786 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4787 drm_warn(display->drm, "Error getting privacy-screen\n"); 4788 } 4789 } 4790 4791 return 0; 4792 4793 err_init_connector: 4794 intel_dp_link_cleanup(&dig_port->dp); 4795 err_dp_init: 4796 kfree(connector); 4797 4798 return err; 4799 } 4800 4801 static void intel_ddi_cleanup_dp_connector(struct intel_digital_port *dig_port) 4802 { 4803 struct intel_dp *intel_dp = &dig_port->dp; 4804 struct intel_connector *connector = intel_dp->attached_connector; 4805 4806 intel_dp_cleanup_connector(dig_port, connector); 4807 intel_dp_link_cleanup(intel_dp); 4808 kfree(connector); 4809 } 4810 4811 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4812 struct drm_modeset_acquire_ctx *ctx) 4813 { 4814 struct intel_display *display = to_intel_display(encoder); 4815 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4816 struct intel_connector *connector = hdmi->attached_connector; 4817 struct i2c_adapter *ddc = connector->base.ddc; 4818 struct drm_connector_state *conn_state; 4819 struct intel_crtc_state *crtc_state; 4820 struct intel_crtc *crtc; 4821 u8 config; 4822 int ret; 4823 4824 if (connector->base.status != connector_status_connected) 4825 return 0; 4826 4827 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4828 ctx); 4829 if (ret) 4830 return ret; 4831 4832 conn_state = connector->base.state; 4833 4834 crtc = to_intel_crtc(conn_state->crtc); 4835 if (!crtc) 4836 return 0; 4837 4838 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4839 if (ret) 4840 return ret; 4841 4842 crtc_state = to_intel_crtc_state(crtc->base.state); 4843 4844 drm_WARN_ON(display->drm, 4845 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4846 4847 if (!crtc_state->hw.active) 4848 return 0; 4849 4850 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4851 !crtc_state->hdmi_scrambling) 4852 return 0; 4853 4854 if (conn_state->commit && 4855 !try_wait_for_completion(&conn_state->commit->hw_done)) 4856 return 0; 4857 4858 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4859 if (ret < 0) { 4860 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4861 connector->base.base.id, connector->base.name, ret); 4862 return 0; 4863 } 4864 4865 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4866 crtc_state->hdmi_high_tmds_clock_ratio && 4867 !!(config & SCDC_SCRAMBLING_ENABLE) == 4868 crtc_state->hdmi_scrambling) 4869 return 0; 4870 4871 /* 4872 * HDMI 2.0 says that one should not send scrambled data 4873 * prior to configuring the sink scrambling, and that 4874 * TMDS clock/data transmission should be suspended when 4875 * changing the TMDS clock rate in the sink. So let's 4876 * just do a full modeset here, even though some sinks 4877 * would be perfectly happy if were to just reconfigure 4878 * the SCDC settings on the fly. 4879 */ 4880 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4881 } 4882 4883 static void intel_ddi_link_check(struct intel_encoder *encoder) 4884 { 4885 struct intel_display *display = to_intel_display(encoder); 4886 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4887 4888 /* TODO: Move checking the HDMI link state here as well. */ 4889 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4890 4891 intel_dp_link_check(encoder); 4892 } 4893 4894 static enum intel_hotplug_state 4895 intel_ddi_hotplug(struct intel_encoder *encoder, 4896 struct intel_connector *connector) 4897 { 4898 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4899 struct intel_dp *intel_dp = &dig_port->dp; 4900 bool is_tc = intel_encoder_is_tc(encoder); 4901 struct drm_modeset_acquire_ctx ctx; 4902 enum intel_hotplug_state state; 4903 int ret; 4904 4905 if (intel_dp_test_phy(intel_dp)) 4906 return INTEL_HOTPLUG_UNCHANGED; 4907 4908 state = intel_encoder_hotplug(encoder, connector); 4909 4910 if (!intel_tc_port_link_reset(dig_port)) { 4911 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4912 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4913 ret = intel_hdmi_reset_link(encoder, &ctx); 4914 drm_WARN_ON(encoder->base.dev, ret); 4915 } else { 4916 intel_dp_check_link_state(intel_dp); 4917 } 4918 } 4919 4920 /* 4921 * Unpowered type-c dongles can take some time to boot and be 4922 * responsible, so here giving some time to those dongles to power up 4923 * and then retrying the probe. 4924 * 4925 * On many platforms the HDMI live state signal is known to be 4926 * unreliable, so we can't use it to detect if a sink is connected or 4927 * not. Instead we detect if it's connected based on whether we can 4928 * read the EDID or not. That in turn has a problem during disconnect, 4929 * since the HPD interrupt may be raised before the DDC lines get 4930 * disconnected (due to how the required length of DDC vs. HPD 4931 * connector pins are specified) and so we'll still be able to get a 4932 * valid EDID. To solve this schedule another detection cycle if this 4933 * time around we didn't detect any change in the sink's connection 4934 * status. 4935 * 4936 * Type-c connectors which get their HPD signal deasserted then 4937 * reasserted, without unplugging/replugging the sink from the 4938 * connector, introduce a delay until the AUX channel communication 4939 * becomes functional. Retry the detection for 5 seconds on type-c 4940 * connectors to account for this delay. 4941 */ 4942 if (state == INTEL_HOTPLUG_UNCHANGED && 4943 connector->hotplug_retries < (is_tc ? 5 : 1) && 4944 !dig_port->dp.is_mst) 4945 state = INTEL_HOTPLUG_RETRY; 4946 4947 return state; 4948 } 4949 4950 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4951 { 4952 struct intel_display *display = to_intel_display(encoder); 4953 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4954 4955 return intel_de_read(display, SDEISR) & bit; 4956 } 4957 4958 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4959 { 4960 struct intel_display *display = to_intel_display(encoder); 4961 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4962 4963 return intel_de_read(display, DEISR) & bit; 4964 } 4965 4966 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4967 { 4968 struct intel_display *display = to_intel_display(encoder); 4969 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4970 4971 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4972 } 4973 4974 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4975 { 4976 struct intel_connector *connector; 4977 enum port port = dig_port->base.port; 4978 4979 connector = intel_connector_alloc(); 4980 if (!connector) 4981 return -ENOMEM; 4982 4983 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4984 4985 if (!intel_hdmi_init_connector(dig_port, connector)) { 4986 /* 4987 * HDMI connector init failures may just mean conflicting DDC 4988 * pins or not having enough lanes. Handle them gracefully, but 4989 * don't fail the entire DDI init. 4990 */ 4991 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4992 kfree(connector); 4993 } 4994 4995 return 0; 4996 } 4997 4998 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4999 { 5000 struct intel_display *display = to_intel_display(dig_port); 5001 5002 if (dig_port->base.port != PORT_A) 5003 return false; 5004 5005 if (dig_port->ddi_a_4_lanes) 5006 return false; 5007 5008 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 5009 * supported configuration 5010 */ 5011 if (display->platform.geminilake || display->platform.broxton) 5012 return true; 5013 5014 return false; 5015 } 5016 5017 static int 5018 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 5019 { 5020 struct intel_display *display = to_intel_display(dig_port); 5021 enum port port = dig_port->base.port; 5022 int max_lanes = 4; 5023 5024 if (DISPLAY_VER(display) >= 11) 5025 return max_lanes; 5026 5027 if (port == PORT_A || port == PORT_E) { 5028 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 5029 max_lanes = port == PORT_A ? 4 : 0; 5030 else 5031 /* Both A and E share 2 lanes */ 5032 max_lanes = 2; 5033 } 5034 5035 /* 5036 * Some BIOS might fail to set this bit on port A if eDP 5037 * wasn't lit up at boot. Force this bit set when needed 5038 * so we use the proper lane count for our calculations. 5039 */ 5040 if (intel_ddi_a_force_4_lanes(dig_port)) { 5041 drm_dbg_kms(display->drm, 5042 "Forcing DDI_A_4_LANES for port A\n"); 5043 dig_port->ddi_a_4_lanes = true; 5044 max_lanes = 4; 5045 } 5046 5047 return max_lanes; 5048 } 5049 5050 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 5051 { 5052 if (port >= PORT_D_XELPD) 5053 return HPD_PORT_D + port - PORT_D_XELPD; 5054 else if (port >= PORT_TC1) 5055 return HPD_PORT_TC1 + port - PORT_TC1; 5056 else 5057 return HPD_PORT_A + port - PORT_A; 5058 } 5059 5060 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 5061 { 5062 if (port >= PORT_TC1) 5063 return HPD_PORT_C + port - PORT_TC1; 5064 else 5065 return HPD_PORT_A + port - PORT_A; 5066 } 5067 5068 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 5069 { 5070 if (port >= PORT_TC1) 5071 return HPD_PORT_TC1 + port - PORT_TC1; 5072 else 5073 return HPD_PORT_A + port - PORT_A; 5074 } 5075 5076 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 5077 { 5078 if (HAS_PCH_TGP(display)) 5079 return tgl_hpd_pin(display, port); 5080 5081 if (port >= PORT_TC1) 5082 return HPD_PORT_C + port - PORT_TC1; 5083 else 5084 return HPD_PORT_A + port - PORT_A; 5085 } 5086 5087 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 5088 { 5089 if (port >= PORT_C) 5090 return HPD_PORT_TC1 + port - PORT_C; 5091 else 5092 return HPD_PORT_A + port - PORT_A; 5093 } 5094 5095 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 5096 { 5097 if (port == PORT_D) 5098 return HPD_PORT_A; 5099 5100 if (HAS_PCH_TGP(display)) 5101 return icl_hpd_pin(display, port); 5102 5103 return HPD_PORT_A + port - PORT_A; 5104 } 5105 5106 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 5107 { 5108 if (HAS_PCH_TGP(display)) 5109 return icl_hpd_pin(display, port); 5110 5111 return HPD_PORT_A + port - PORT_A; 5112 } 5113 5114 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 5115 { 5116 if (DISPLAY_VER(display) >= 12) 5117 return port >= PORT_TC1; 5118 else if (DISPLAY_VER(display) >= 11) 5119 return port >= PORT_C; 5120 else 5121 return false; 5122 } 5123 5124 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 5125 { 5126 intel_dp_encoder_suspend(encoder); 5127 } 5128 5129 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 5130 { 5131 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5132 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5133 5134 /* 5135 * TODO: Move this to intel_dp_encoder_suspend(), 5136 * once modeset locking around that is removed. 5137 */ 5138 intel_encoder_link_check_flush_work(encoder); 5139 intel_tc_port_suspend(dig_port); 5140 } 5141 5142 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5143 { 5144 if (intel_encoder_is_dp(encoder)) 5145 intel_dp_encoder_shutdown(encoder); 5146 if (intel_encoder_is_hdmi(encoder)) 5147 intel_hdmi_encoder_shutdown(encoder); 5148 } 5149 5150 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5151 { 5152 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5153 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5154 5155 intel_tc_port_cleanup(dig_port); 5156 } 5157 5158 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5159 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5160 5161 static bool port_strap_detected(struct intel_display *display, enum port port) 5162 { 5163 /* straps not used on skl+ */ 5164 if (DISPLAY_VER(display) >= 9) 5165 return true; 5166 5167 switch (port) { 5168 case PORT_A: 5169 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5170 case PORT_B: 5171 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5172 case PORT_C: 5173 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5174 case PORT_D: 5175 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5176 case PORT_E: 5177 return true; /* no strap for DDI-E */ 5178 default: 5179 MISSING_CASE(port); 5180 return false; 5181 } 5182 } 5183 5184 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5185 { 5186 return init_dp || intel_encoder_is_tc(encoder); 5187 } 5188 5189 static bool assert_has_icl_dsi(struct intel_display *display) 5190 { 5191 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5192 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5193 "Platform does not support DSI\n"); 5194 } 5195 5196 static bool port_in_use(struct intel_display *display, enum port port) 5197 { 5198 struct intel_encoder *encoder; 5199 5200 for_each_intel_encoder(display->drm, encoder) { 5201 /* FIXME what about second port for dual link DSI? */ 5202 if (encoder->port == port) 5203 return true; 5204 } 5205 5206 return false; 5207 } 5208 5209 static const char *intel_ddi_encoder_name(struct intel_display *display, 5210 enum port port, enum phy phy, 5211 struct seq_buf *s) 5212 { 5213 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5214 seq_buf_printf(s, "DDI %c/PHY %c", 5215 port_name(port - PORT_D_XELPD + PORT_D), 5216 phy_name(phy)); 5217 } else if (DISPLAY_VER(display) >= 12) { 5218 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5219 5220 seq_buf_printf(s, "DDI %s%c/PHY %s%c", 5221 port >= PORT_TC1 ? "TC" : "", 5222 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5223 tc_port != TC_PORT_NONE ? "TC" : "", 5224 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5225 } else if (DISPLAY_VER(display) >= 11) { 5226 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5227 5228 seq_buf_printf(s, "DDI %c%s/PHY %s%c", 5229 port_name(port), 5230 port >= PORT_C ? " (TC)" : "", 5231 tc_port != TC_PORT_NONE ? "TC" : "", 5232 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5233 } else { 5234 seq_buf_printf(s, "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5235 } 5236 5237 drm_WARN_ON(display->drm, seq_buf_has_overflowed(s)); 5238 5239 return seq_buf_str(s); 5240 } 5241 5242 void intel_ddi_init(struct intel_display *display, 5243 const struct intel_bios_encoder_data *devdata) 5244 { 5245 struct intel_digital_port *dig_port; 5246 struct intel_encoder *encoder; 5247 DECLARE_SEQ_BUF(encoder_name, 20); 5248 bool init_hdmi, init_dp; 5249 enum port port; 5250 enum phy phy; 5251 u32 ddi_buf_ctl; 5252 5253 port = intel_bios_encoder_port(devdata); 5254 if (port == PORT_NONE) 5255 return; 5256 5257 if (!port_strap_detected(display, port)) { 5258 drm_dbg_kms(display->drm, 5259 "Port %c strap not detected\n", port_name(port)); 5260 return; 5261 } 5262 5263 if (!assert_port_valid(display, port)) 5264 return; 5265 5266 if (port_in_use(display, port)) { 5267 drm_dbg_kms(display->drm, 5268 "Port %c already claimed\n", port_name(port)); 5269 return; 5270 } 5271 5272 if (intel_bios_encoder_supports_dsi(devdata)) { 5273 /* BXT/GLK handled elsewhere, for now at least */ 5274 if (!assert_has_icl_dsi(display)) 5275 return; 5276 5277 icl_dsi_init(display, devdata); 5278 return; 5279 } 5280 5281 phy = intel_port_to_phy(display, port); 5282 5283 /* 5284 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5285 * have taken over some of the PHYs and made them unavailable to the 5286 * driver. In that case we should skip initializing the corresponding 5287 * outputs. 5288 */ 5289 if (intel_hti_uses_phy(display, phy)) { 5290 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5291 port_name(port), phy_name(phy)); 5292 return; 5293 } 5294 5295 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5296 intel_bios_encoder_supports_hdmi(devdata); 5297 init_dp = intel_bios_encoder_supports_dp(devdata); 5298 5299 if (intel_bios_encoder_is_lspcon(devdata)) { 5300 /* 5301 * Lspcon device needs to be driven with DP connector 5302 * with special detection sequence. So make sure DP 5303 * is initialized before lspcon. 5304 */ 5305 init_dp = true; 5306 init_hdmi = false; 5307 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5308 port_name(port)); 5309 } 5310 5311 if (!init_dp && !init_hdmi) { 5312 drm_dbg_kms(display->drm, 5313 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5314 port_name(port)); 5315 return; 5316 } 5317 5318 if (intel_phy_is_snps(display, phy) && 5319 display->snps.phy_failed_calibration & BIT(phy)) { 5320 drm_dbg_kms(display->drm, 5321 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5322 phy_name(phy)); 5323 } 5324 5325 dig_port = intel_dig_port_alloc(); 5326 if (!dig_port) 5327 return; 5328 5329 encoder = &dig_port->base; 5330 encoder->devdata = devdata; 5331 5332 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5333 DRM_MODE_ENCODER_TMDS, "%s", 5334 intel_ddi_encoder_name(display, port, phy, &encoder_name)); 5335 5336 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5337 5338 encoder->hotplug = intel_ddi_hotplug; 5339 encoder->compute_output_type = intel_ddi_compute_output_type; 5340 encoder->compute_config = intel_ddi_compute_config; 5341 encoder->compute_config_late = intel_ddi_compute_config_late; 5342 encoder->enable = intel_ddi_enable; 5343 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5344 encoder->pre_enable = intel_ddi_pre_enable; 5345 encoder->disable = intel_ddi_disable; 5346 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5347 encoder->post_disable = intel_ddi_post_disable; 5348 encoder->update_pipe = intel_ddi_update_pipe; 5349 encoder->audio_enable = intel_audio_codec_enable; 5350 encoder->audio_disable = intel_audio_codec_disable; 5351 encoder->get_hw_state = intel_ddi_get_hw_state; 5352 encoder->sync_state = intel_ddi_sync_state; 5353 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5354 encoder->suspend = intel_ddi_encoder_suspend; 5355 encoder->shutdown = intel_ddi_encoder_shutdown; 5356 encoder->get_power_domains = intel_ddi_get_power_domains; 5357 5358 encoder->type = INTEL_OUTPUT_DDI; 5359 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5360 encoder->port = port; 5361 encoder->cloneable = 0; 5362 encoder->pipe_mask = ~0; 5363 5364 if (HAS_LT_PHY(display)) { 5365 encoder->enable_clock = intel_mtl_pll_enable_clock; 5366 encoder->disable_clock = intel_mtl_pll_disable_clock; 5367 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5368 if (intel_encoder_is_tc(encoder)) 5369 encoder->get_config = mtl_ddi_tc_phy_get_config; 5370 else 5371 encoder->get_config = mtl_ddi_non_tc_phy_get_config; 5372 } else if (DISPLAY_VER(display) >= 14) { 5373 encoder->enable_clock = intel_mtl_pll_enable_clock; 5374 encoder->disable_clock = intel_mtl_pll_disable_clock; 5375 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5376 if (intel_encoder_is_tc(encoder)) 5377 encoder->get_config = mtl_ddi_tc_phy_get_config; 5378 else 5379 encoder->get_config = mtl_ddi_non_tc_phy_get_config; 5380 } else if (display->platform.dg2) { 5381 encoder->get_config = dg2_ddi_get_config; 5382 } else if (display->platform.alderlake_s) { 5383 encoder->enable_clock = adls_ddi_enable_clock; 5384 encoder->disable_clock = adls_ddi_disable_clock; 5385 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5386 encoder->get_config = adls_ddi_get_config; 5387 } else if (display->platform.rocketlake) { 5388 encoder->enable_clock = rkl_ddi_enable_clock; 5389 encoder->disable_clock = rkl_ddi_disable_clock; 5390 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5391 encoder->get_config = rkl_ddi_get_config; 5392 } else if (display->platform.dg1) { 5393 encoder->enable_clock = dg1_ddi_enable_clock; 5394 encoder->disable_clock = dg1_ddi_disable_clock; 5395 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5396 encoder->get_config = dg1_ddi_get_config; 5397 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5398 if (intel_ddi_is_tc(display, port)) { 5399 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5400 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5401 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5402 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5403 encoder->get_config = icl_ddi_combo_get_config; 5404 } else { 5405 encoder->enable_clock = icl_ddi_combo_enable_clock; 5406 encoder->disable_clock = icl_ddi_combo_disable_clock; 5407 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5408 encoder->get_config = icl_ddi_combo_get_config; 5409 } 5410 } else if (DISPLAY_VER(display) >= 11) { 5411 if (intel_ddi_is_tc(display, port)) { 5412 encoder->enable_clock = icl_ddi_tc_enable_clock; 5413 encoder->disable_clock = icl_ddi_tc_disable_clock; 5414 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5415 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5416 encoder->get_config = icl_ddi_tc_get_config; 5417 } else { 5418 encoder->enable_clock = icl_ddi_combo_enable_clock; 5419 encoder->disable_clock = icl_ddi_combo_disable_clock; 5420 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5421 encoder->get_config = icl_ddi_combo_get_config; 5422 } 5423 } else if (display->platform.geminilake || display->platform.broxton) { 5424 /* BXT/GLK have fixed PLL->port mapping */ 5425 encoder->get_config = bxt_ddi_get_config; 5426 } else if (DISPLAY_VER(display) == 9) { 5427 encoder->enable_clock = skl_ddi_enable_clock; 5428 encoder->disable_clock = skl_ddi_disable_clock; 5429 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5430 encoder->get_config = skl_ddi_get_config; 5431 } else if (display->platform.broadwell || display->platform.haswell) { 5432 encoder->enable_clock = hsw_ddi_enable_clock; 5433 encoder->disable_clock = hsw_ddi_disable_clock; 5434 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5435 encoder->get_config = hsw_ddi_get_config; 5436 } 5437 5438 if (HAS_LT_PHY(display)) { 5439 encoder->set_signal_levels = intel_lt_phy_set_signal_levels; 5440 } else if (DISPLAY_VER(display) >= 14) { 5441 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5442 } else if (display->platform.dg2) { 5443 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5444 } else if (DISPLAY_VER(display) >= 12) { 5445 if (intel_encoder_is_combo(encoder)) 5446 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5447 else 5448 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5449 } else if (DISPLAY_VER(display) >= 11) { 5450 if (intel_encoder_is_combo(encoder)) 5451 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5452 else 5453 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5454 } else if (display->platform.geminilake || display->platform.broxton) { 5455 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5456 } else { 5457 encoder->set_signal_levels = hsw_set_signal_levels; 5458 } 5459 5460 intel_ddi_buf_trans_init(encoder); 5461 5462 if (DISPLAY_VER(display) >= 13) 5463 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5464 else if (display->platform.dg1) 5465 encoder->hpd_pin = dg1_hpd_pin(display, port); 5466 else if (display->platform.rocketlake) 5467 encoder->hpd_pin = rkl_hpd_pin(display, port); 5468 else if (DISPLAY_VER(display) >= 12) 5469 encoder->hpd_pin = tgl_hpd_pin(display, port); 5470 else if (display->platform.jasperlake || display->platform.elkhartlake) 5471 encoder->hpd_pin = ehl_hpd_pin(display, port); 5472 else if (DISPLAY_VER(display) == 11) 5473 encoder->hpd_pin = icl_hpd_pin(display, port); 5474 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5475 encoder->hpd_pin = skl_hpd_pin(display, port); 5476 else 5477 encoder->hpd_pin = intel_hpd_pin_default(port); 5478 5479 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5480 5481 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5482 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5483 5484 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5485 5486 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5487 5488 if (need_aux_ch(encoder, init_dp)) { 5489 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5490 if (dig_port->aux_ch == AUX_CH_NONE) 5491 goto err_aux_ch_init; 5492 } 5493 5494 /* 5495 * FIXME: We currently need to store dedicated_external because devdata 5496 * does not live long enough for when intel_encoder_is_tc() is called on 5497 * the unbind path. This needs to be fixed by making sure that the VBT 5498 * data is kept long enough, so that 5499 * intel_bios_encoder_is_dedicated_external() can be called directly 5500 * from intel_encoder_is_tc(). 5501 */ 5502 if (intel_bios_encoder_is_dedicated_external(devdata)) 5503 dig_port->dedicated_external = true; 5504 5505 if (intel_encoder_is_tc(encoder)) { 5506 bool is_legacy = 5507 !intel_bios_encoder_supports_typec_usb(devdata) && 5508 !intel_bios_encoder_supports_tbt(devdata); 5509 5510 if (!is_legacy && init_hdmi) { 5511 is_legacy = !init_dp; 5512 5513 drm_dbg_kms(display->drm, 5514 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5515 port_name(port), 5516 str_yes_no(init_dp), 5517 is_legacy ? "legacy" : "non-legacy"); 5518 } 5519 5520 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5521 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5522 5523 dig_port->lock = intel_tc_port_lock; 5524 dig_port->unlock = intel_tc_port_unlock; 5525 5526 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5527 goto err_aux_ch_init; 5528 } 5529 5530 drm_WARN_ON(display->drm, port > PORT_I); 5531 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5532 5533 if (DISPLAY_VER(display) >= 11) { 5534 if (intel_encoder_is_tc(encoder)) 5535 dig_port->connected = intel_tc_port_connected; 5536 else 5537 dig_port->connected = lpt_digital_port_connected; 5538 } else if (display->platform.geminilake || display->platform.broxton) { 5539 dig_port->connected = bdw_digital_port_connected; 5540 } else if (DISPLAY_VER(display) == 9) { 5541 dig_port->connected = lpt_digital_port_connected; 5542 } else if (display->platform.broadwell) { 5543 if (port == PORT_A) 5544 dig_port->connected = bdw_digital_port_connected; 5545 else 5546 dig_port->connected = lpt_digital_port_connected; 5547 } else if (display->platform.haswell) { 5548 if (port == PORT_A) 5549 dig_port->connected = hsw_digital_port_connected; 5550 else 5551 dig_port->connected = lpt_digital_port_connected; 5552 } 5553 5554 intel_infoframe_init(dig_port); 5555 5556 if (init_dp) { 5557 if (intel_ddi_init_dp_connector(dig_port)) 5558 goto err_dp_connector_init; 5559 5560 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5561 5562 if (dig_port->dp.mso_link_count) 5563 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5564 } 5565 5566 /* 5567 * In theory we don't need the encoder->type check, 5568 * but leave it just in case we have some really bad VBTs... 5569 */ 5570 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5571 if (intel_ddi_init_hdmi_connector(dig_port)) 5572 goto err_hdmi_connector_init; 5573 } 5574 5575 return; 5576 5577 err_hdmi_connector_init: 5578 if (init_dp) 5579 intel_ddi_cleanup_dp_connector(dig_port); 5580 err_dp_connector_init: 5581 if (intel_encoder_is_tc(encoder)) 5582 intel_tc_port_cleanup(dig_port); 5583 err_aux_ch_init: 5584 drm_encoder_cleanup(&encoder->base); 5585 kfree(dig_port); 5586 } 5587