1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2025 Intel Corporation
4 */
5 #include "intel_color.h"
6 #include "intel_colorop.h"
7 #include "intel_color_pipeline.h"
8 #include "intel_de.h"
9 #include "intel_display_types.h"
10 #include "skl_universal_plane.h"
11
12 #define MAX_COLOR_PIPELINES 1
13 #define PLANE_DEGAMMA_SIZE 128
14 #define PLANE_GAMMA_SIZE 32
15
16 static
_intel_color_pipeline_plane_init(struct drm_plane * plane,struct drm_prop_enum_list * list,enum pipe pipe)17 int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list,
18 enum pipe pipe)
19 {
20 struct drm_device *dev = plane->dev;
21 struct intel_display *display = to_intel_display(dev);
22 struct drm_colorop *prev_op;
23 struct intel_colorop *colorop;
24 int ret;
25
26 colorop = intel_colorop_create(INTEL_PLANE_CB_PRE_CSC_LUT);
27
28 ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
29 PLANE_DEGAMMA_SIZE,
30 DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
31 DRM_COLOROP_FLAG_ALLOW_BYPASS);
32
33 if (ret)
34 return ret;
35
36 list->type = colorop->base.base.id;
37 list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", colorop->base.base.id);
38
39 /* TODO: handle failures and clean up */
40 prev_op = &colorop->base;
41
42 if (DISPLAY_VER(display) >= 35 &&
43 intel_color_crtc_has_3dlut(display, pipe) &&
44 plane->type == DRM_PLANE_TYPE_PRIMARY) {
45 colorop = intel_colorop_create(INTEL_PLANE_CB_3DLUT);
46
47 ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane, 17,
48 DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
49 true);
50 if (ret)
51 return ret;
52
53 drm_colorop_set_next_property(prev_op, &colorop->base);
54
55 prev_op = &colorop->base;
56 }
57
58 colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
59 ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
60 DRM_COLOROP_FLAG_ALLOW_BYPASS);
61 if (ret)
62 return ret;
63
64 drm_colorop_set_next_property(prev_op, &colorop->base);
65 prev_op = &colorop->base;
66
67 colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT);
68 ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
69 PLANE_GAMMA_SIZE,
70 DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
71 DRM_COLOROP_FLAG_ALLOW_BYPASS);
72 if (ret)
73 return ret;
74
75 drm_colorop_set_next_property(prev_op, &colorop->base);
76
77 return 0;
78 }
79
intel_color_pipeline_plane_init(struct drm_plane * plane,enum pipe pipe)80 int intel_color_pipeline_plane_init(struct drm_plane *plane, enum pipe pipe)
81 {
82 struct drm_device *dev = plane->dev;
83 struct intel_display *display = to_intel_display(dev);
84 struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES];
85 int len = 0;
86 int ret;
87
88 /* Currently expose pipeline only for HDR planes */
89 if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
90 return 0;
91
92 /* Add pipeline consisting of transfer functions */
93 ret = _intel_color_pipeline_plane_init(plane, &pipelines[len], pipe);
94 if (ret)
95 return ret;
96 len++;
97
98 return drm_plane_create_color_pipeline_property(plane, pipelines, len);
99 }
100