1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel.vetter@ffwll.ch> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "i915_reg.h" 30 #include "intel_de.h" 31 #include "intel_display_irq.h" 32 #include "intel_display_trace.h" 33 #include "intel_display_types.h" 34 #include "intel_fbc.h" 35 #include "intel_fifo_underrun.h" 36 #include "intel_pch_display.h" 37 38 /** 39 * DOC: fifo underrun handling 40 * 41 * The i915 driver checks for display fifo underruns using the interrupt signals 42 * provided by the hardware. This is enabled by default and fairly useful to 43 * debug display issues, especially watermark settings. 44 * 45 * If an underrun is detected this is logged into dmesg. To avoid flooding logs 46 * and occupying the cpu underrun interrupts are disabled after the first 47 * occurrence until the next modeset on a given pipe. 48 * 49 * Note that underrun detection on gmch platforms is a bit more ugly since there 50 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe 51 * interrupt register). Also on some other platforms underrun interrupts are 52 * shared, which means that if we detect an underrun we need to disable underrun 53 * reporting on all pipes. 54 * 55 * The code also supports underrun detection on the PCH transcoder. 56 */ 57 58 static bool ivb_can_enable_err_int(struct drm_device *dev) 59 { 60 struct drm_i915_private *dev_priv = to_i915(dev); 61 struct intel_crtc *crtc; 62 enum pipe pipe; 63 64 lockdep_assert_held(&dev_priv->irq_lock); 65 66 for_each_pipe(dev_priv, pipe) { 67 crtc = intel_crtc_for_pipe(dev_priv, pipe); 68 69 if (crtc->cpu_fifo_underrun_disabled) 70 return false; 71 } 72 73 return true; 74 } 75 76 static bool cpt_can_enable_serr_int(struct drm_device *dev) 77 { 78 struct drm_i915_private *dev_priv = to_i915(dev); 79 enum pipe pipe; 80 struct intel_crtc *crtc; 81 82 lockdep_assert_held(&dev_priv->irq_lock); 83 84 for_each_pipe(dev_priv, pipe) { 85 crtc = intel_crtc_for_pipe(dev_priv, pipe); 86 87 if (crtc->pch_fifo_underrun_disabled) 88 return false; 89 } 90 91 return true; 92 } 93 94 static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) 95 { 96 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 97 i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe); 98 u32 enable_mask; 99 100 lockdep_assert_held(&dev_priv->irq_lock); 101 102 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) 103 return; 104 105 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); 106 intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); 107 intel_de_posting_read(dev_priv, reg); 108 109 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); 110 drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); 111 } 112 113 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, 114 enum pipe pipe, 115 bool enable, bool old) 116 { 117 struct drm_i915_private *dev_priv = to_i915(dev); 118 i915_reg_t reg = PIPESTAT(dev_priv, pipe); 119 120 lockdep_assert_held(&dev_priv->irq_lock); 121 122 if (enable) { 123 u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 124 125 intel_de_write(dev_priv, reg, 126 enable_mask | PIPE_FIFO_UNDERRUN_STATUS); 127 intel_de_posting_read(dev_priv, reg); 128 } else { 129 if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) 130 drm_err(&dev_priv->drm, "pipe %c underrun\n", 131 pipe_name(pipe)); 132 } 133 } 134 135 static void ilk_set_fifo_underrun_reporting(struct drm_device *dev, 136 enum pipe pipe, bool enable) 137 { 138 struct drm_i915_private *dev_priv = to_i915(dev); 139 u32 bit = (pipe == PIPE_A) ? 140 DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN; 141 142 if (enable) 143 ilk_enable_display_irq(dev_priv, bit); 144 else 145 ilk_disable_display_irq(dev_priv, bit); 146 } 147 148 static void ivb_check_fifo_underruns(struct intel_crtc *crtc) 149 { 150 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 151 enum pipe pipe = crtc->pipe; 152 u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); 153 154 lockdep_assert_held(&dev_priv->irq_lock); 155 156 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) 157 return; 158 159 intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 160 intel_de_posting_read(dev_priv, GEN7_ERR_INT); 161 162 trace_intel_cpu_fifo_underrun(dev_priv, pipe); 163 drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe)); 164 } 165 166 static void ivb_set_fifo_underrun_reporting(struct drm_device *dev, 167 enum pipe pipe, bool enable, 168 bool old) 169 { 170 struct drm_i915_private *dev_priv = to_i915(dev); 171 if (enable) { 172 intel_de_write(dev_priv, GEN7_ERR_INT, 173 ERR_INT_FIFO_UNDERRUN(pipe)); 174 175 if (!ivb_can_enable_err_int(dev)) 176 return; 177 178 ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB); 179 } else { 180 ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB); 181 182 if (old && 183 intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { 184 drm_err(&dev_priv->drm, 185 "uncleared fifo underrun on pipe %c\n", 186 pipe_name(pipe)); 187 } 188 } 189 } 190 191 static u32 192 icl_pipe_status_underrun_mask(struct drm_i915_private *dev_priv) 193 { 194 u32 mask = PIPE_STATUS_UNDERRUN; 195 196 if (DISPLAY_VER(dev_priv) >= 13) 197 mask |= PIPE_STATUS_SOFT_UNDERRUN_XELPD | 198 PIPE_STATUS_HARD_UNDERRUN_XELPD | 199 PIPE_STATUS_PORT_UNDERRUN_XELPD; 200 201 return mask; 202 } 203 204 static void bdw_set_fifo_underrun_reporting(struct drm_device *dev, 205 enum pipe pipe, bool enable) 206 { 207 struct drm_i915_private *dev_priv = to_i915(dev); 208 u32 mask = gen8_de_pipe_underrun_mask(dev_priv); 209 210 if (enable) { 211 if (DISPLAY_VER(dev_priv) >= 11) 212 intel_de_write(dev_priv, 213 ICL_PIPESTATUS(dev_priv, pipe), 214 icl_pipe_status_underrun_mask(dev_priv)); 215 216 bdw_enable_pipe_irq(dev_priv, pipe, mask); 217 } else { 218 bdw_disable_pipe_irq(dev_priv, pipe, mask); 219 } 220 } 221 222 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, 223 enum pipe pch_transcoder, 224 bool enable) 225 { 226 struct drm_i915_private *dev_priv = to_i915(dev); 227 u32 bit = (pch_transcoder == PIPE_A) ? 228 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; 229 230 if (enable) 231 ibx_enable_display_interrupt(dev_priv, bit); 232 else 233 ibx_disable_display_interrupt(dev_priv, bit); 234 } 235 236 static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) 237 { 238 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 239 enum pipe pch_transcoder = crtc->pipe; 240 u32 serr_int = intel_de_read(dev_priv, SERR_INT); 241 242 lockdep_assert_held(&dev_priv->irq_lock); 243 244 if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) 245 return; 246 247 intel_de_write(dev_priv, SERR_INT, 248 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 249 intel_de_posting_read(dev_priv, SERR_INT); 250 251 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); 252 drm_err(&dev_priv->drm, "pch fifo underrun on pch transcoder %c\n", 253 pipe_name(pch_transcoder)); 254 } 255 256 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, 257 enum pipe pch_transcoder, 258 bool enable, bool old) 259 { 260 struct drm_i915_private *dev_priv = to_i915(dev); 261 262 if (enable) { 263 intel_de_write(dev_priv, SERR_INT, 264 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 265 266 if (!cpt_can_enable_serr_int(dev)) 267 return; 268 269 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); 270 } else { 271 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); 272 273 if (old && intel_de_read(dev_priv, SERR_INT) & 274 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { 275 drm_err(&dev_priv->drm, 276 "uncleared pch fifo underrun on pch transcoder %c\n", 277 pipe_name(pch_transcoder)); 278 } 279 } 280 } 281 282 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 283 enum pipe pipe, bool enable) 284 { 285 struct drm_i915_private *dev_priv = to_i915(dev); 286 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 287 bool old; 288 289 lockdep_assert_held(&dev_priv->irq_lock); 290 291 old = !crtc->cpu_fifo_underrun_disabled; 292 crtc->cpu_fifo_underrun_disabled = !enable; 293 294 if (HAS_GMCH(dev_priv)) 295 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); 296 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) 297 ilk_set_fifo_underrun_reporting(dev, pipe, enable); 298 else if (DISPLAY_VER(dev_priv) == 7) 299 ivb_set_fifo_underrun_reporting(dev, pipe, enable, old); 300 else if (DISPLAY_VER(dev_priv) >= 8) 301 bdw_set_fifo_underrun_reporting(dev, pipe, enable); 302 303 return old; 304 } 305 306 /** 307 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state 308 * @dev_priv: i915 device instance 309 * @pipe: (CPU) pipe to set state for 310 * @enable: whether underruns should be reported or not 311 * 312 * This function sets the fifo underrun state for @pipe. It is used in the 313 * modeset code to avoid false positives since on many platforms underruns are 314 * expected when disabling or enabling the pipe. 315 * 316 * Notice that on some platforms disabling underrun reports for one pipe 317 * disables for all due to shared interrupts. Actual reporting is still per-pipe 318 * though. 319 * 320 * Returns the previous state of underrun reporting. 321 */ 322 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 323 enum pipe pipe, bool enable) 324 { 325 unsigned long flags; 326 bool ret; 327 328 spin_lock_irqsave(&dev_priv->irq_lock, flags); 329 ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe, 330 enable); 331 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 332 333 return ret; 334 } 335 336 /** 337 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state 338 * @dev_priv: i915 device instance 339 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 340 * @enable: whether underruns should be reported or not 341 * 342 * This function makes us disable or enable PCH fifo underruns for a specific 343 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO 344 * underrun reporting for one transcoder may also disable all the other PCH 345 * error interruts for the other transcoders, due to the fact that there's just 346 * one interrupt mask/enable bit for all the transcoders. 347 * 348 * Returns the previous state of underrun reporting. 349 */ 350 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 351 enum pipe pch_transcoder, 352 bool enable) 353 { 354 struct intel_crtc *crtc = 355 intel_crtc_for_pipe(dev_priv, pch_transcoder); 356 unsigned long flags; 357 bool old; 358 359 /* 360 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT 361 * has only one pch transcoder A that all pipes can use. To avoid racy 362 * pch transcoder -> pipe lookups from interrupt code simply store the 363 * underrun statistics in crtc A. Since we never expose this anywhere 364 * nor use it outside of the fifo underrun code here using the "wrong" 365 * crtc on LPT won't cause issues. 366 */ 367 368 spin_lock_irqsave(&dev_priv->irq_lock, flags); 369 370 old = !crtc->pch_fifo_underrun_disabled; 371 crtc->pch_fifo_underrun_disabled = !enable; 372 373 if (HAS_PCH_IBX(dev_priv)) 374 ibx_set_fifo_underrun_reporting(&dev_priv->drm, 375 pch_transcoder, 376 enable); 377 else 378 cpt_set_fifo_underrun_reporting(&dev_priv->drm, 379 pch_transcoder, 380 enable, old); 381 382 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 383 return old; 384 } 385 386 /** 387 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt 388 * @dev_priv: i915 device instance 389 * @pipe: (CPU) pipe to set state for 390 * 391 * This handles a CPU fifo underrun interrupt, generating an underrun warning 392 * into dmesg if underrun reporting is enabled and then disables the underrun 393 * interrupt to avoid an irq storm. 394 */ 395 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 396 enum pipe pipe) 397 { 398 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 399 u32 underruns = 0; 400 401 /* We may be called too early in init, thanks BIOS! */ 402 if (crtc == NULL) 403 return; 404 405 /* GMCH can't disable fifo underruns, filter them. */ 406 if (HAS_GMCH(dev_priv) && 407 crtc->cpu_fifo_underrun_disabled) 408 return; 409 410 /* 411 * Starting with display version 11, the PIPE_STAT register records 412 * whether an underrun has happened, and on XELPD+, it will also record 413 * whether the underrun was soft/hard and whether it was triggered by 414 * the downstream port logic. We should clear these bits (which use 415 * write-1-to-clear logic) too. 416 * 417 * Note that although the IIR gives us the same underrun and soft/hard 418 * information, PIPE_STAT is the only place we can find out whether 419 * the underrun was caused by the downstream port. 420 */ 421 if (DISPLAY_VER(dev_priv) >= 11) { 422 underruns = intel_de_read(dev_priv, 423 ICL_PIPESTATUS(dev_priv, pipe)) & 424 icl_pipe_status_underrun_mask(dev_priv); 425 intel_de_write(dev_priv, ICL_PIPESTATUS(dev_priv, pipe), 426 underruns); 427 } 428 429 if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { 430 trace_intel_cpu_fifo_underrun(dev_priv, pipe); 431 432 if (DISPLAY_VER(dev_priv) >= 11) 433 drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun: %s%s%s%s\n", 434 pipe_name(pipe), 435 underruns & PIPE_STATUS_SOFT_UNDERRUN_XELPD ? "soft," : "", 436 underruns & PIPE_STATUS_HARD_UNDERRUN_XELPD ? "hard," : "", 437 underruns & PIPE_STATUS_PORT_UNDERRUN_XELPD ? "port," : "", 438 underruns & PIPE_STATUS_UNDERRUN ? "transcoder," : ""); 439 else 440 drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); 441 } 442 443 intel_fbc_handle_fifo_underrun_irq(&dev_priv->display); 444 } 445 446 /** 447 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt 448 * @dev_priv: i915 device instance 449 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 450 * 451 * This handles a PCH fifo underrun interrupt, generating an underrun warning 452 * into dmesg if underrun reporting is enabled and then disables the underrun 453 * interrupt to avoid an irq storm. 454 */ 455 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 456 enum pipe pch_transcoder) 457 { 458 if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, 459 false)) { 460 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); 461 drm_err(&dev_priv->drm, "PCH transcoder %c FIFO underrun\n", 462 pipe_name(pch_transcoder)); 463 } 464 } 465 466 /** 467 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately 468 * @dev_priv: i915 device instance 469 * 470 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared 471 * error interrupt may have been disabled, and so CPU fifo underruns won't 472 * necessarily raise an interrupt, and on GMCH platforms where underruns never 473 * raise an interrupt. 474 */ 475 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) 476 { 477 struct intel_crtc *crtc; 478 479 spin_lock_irq(&dev_priv->irq_lock); 480 481 for_each_intel_crtc(&dev_priv->drm, crtc) { 482 if (crtc->cpu_fifo_underrun_disabled) 483 continue; 484 485 if (HAS_GMCH(dev_priv)) 486 i9xx_check_fifo_underruns(crtc); 487 else if (DISPLAY_VER(dev_priv) == 7) 488 ivb_check_fifo_underruns(crtc); 489 } 490 491 spin_unlock_irq(&dev_priv->irq_lock); 492 } 493 494 /** 495 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately 496 * @dev_priv: i915 device instance 497 * 498 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared 499 * error interrupt may have been disabled, and so PCH fifo underruns won't 500 * necessarily raise an interrupt. 501 */ 502 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv) 503 { 504 struct intel_crtc *crtc; 505 506 spin_lock_irq(&dev_priv->irq_lock); 507 508 for_each_intel_crtc(&dev_priv->drm, crtc) { 509 if (crtc->pch_fifo_underrun_disabled) 510 continue; 511 512 if (HAS_PCH_CPT(dev_priv)) 513 cpt_check_pch_fifo_underruns(crtc); 514 } 515 516 spin_unlock_irq(&dev_priv->irq_lock); 517 } 518 519 void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915, 520 struct intel_crtc *crtc, 521 bool enable) 522 { 523 crtc->cpu_fifo_underrun_disabled = !enable; 524 525 /* 526 * We track the PCH trancoder underrun reporting state 527 * within the crtc. With crtc for pipe A housing the underrun 528 * reporting state for PCH transcoder A, crtc for pipe B housing 529 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 530 * and marking underrun reporting as disabled for the non-existing 531 * PCH transcoders B and C would prevent enabling the south 532 * error interrupt (see cpt_can_enable_serr_int()). 533 */ 534 if (intel_has_pch_trancoder(i915, crtc->pipe)) 535 crtc->pch_fifo_underrun_disabled = !enable; 536 } 537