1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 #include <linux/iopoll.h> 26 #include <linux/time.h> 27 28 #include <drm/drm_fixed.h> 29 #include <drm/drm_print.h> 30 #include <drm/intel/intel_pcode_regs.h> 31 #include <drm/intel/pci_config.h> 32 #include <drm/intel/step.h> 33 34 #include "hsw_ips.h" 35 #include "intel_atomic.h" 36 #include "intel_audio.h" 37 #include "intel_cdclk.h" 38 #include "intel_crtc.h" 39 #include "intel_dbuf_bw.h" 40 #include "intel_de.h" 41 #include "intel_display_regs.h" 42 #include "intel_display_types.h" 43 #include "intel_display_utils.h" 44 #include "intel_display_wa.h" 45 #include "intel_dram.h" 46 #include "intel_mchbar.h" 47 #include "intel_parent.h" 48 #include "intel_plane.h" 49 #include "intel_psr.h" 50 #include "intel_vdsc.h" 51 #include "skl_watermark.h" 52 #include "skl_watermark_regs.h" 53 #include "vlv_clock.h" 54 #include "vlv_dsi.h" 55 #include "vlv_sideband.h" 56 57 /** 58 * DOC: CDCLK / RAWCLK 59 * 60 * The display engine uses several different clocks to do its work. There 61 * are two main clocks involved that aren't directly related to the actual 62 * pixel clock or any symbol/bit clock of the actual output port. These 63 * are the core display clock (CDCLK) and RAWCLK. 64 * 65 * CDCLK clocks most of the display pipe logic, and thus its frequency 66 * must be high enough to support the rate at which pixels are flowing 67 * through the pipes. Downscaling must also be accounted as that increases 68 * the effective pixel rate. 69 * 70 * On several platforms the CDCLK frequency can be changed dynamically 71 * to minimize power consumption for a given display configuration. 72 * Typically changes to the CDCLK frequency require all the display pipes 73 * to be shut down while the frequency is being changed. 74 * 75 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 76 * DMC will not change the active CDCLK frequency however, so that part 77 * will still be performed by the driver directly. 78 * 79 * There are multiple components involved in the generation of the CDCLK 80 * frequency: 81 * 82 * - We have the CDCLK PLL, which generates an output clock based on a 83 * reference clock and a ratio parameter. 84 * - The CD2X Divider, which divides the output of the PLL based on a 85 * divisor selected from a set of pre-defined choices. 86 * - The CD2X Squasher, which further divides the output based on a 87 * waveform represented as a sequence of bits where each zero 88 * "squashes out" a clock cycle. 89 * - And, finally, a fixed divider that divides the output frequency by 2. 90 * 91 * As such, the resulting CDCLK frequency can be calculated with the 92 * following formula: 93 * 94 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 95 * 96 * , where vco is the frequency generated by the PLL; cd2x_div 97 * represents the CD2X Divider; sq_len and sq_div are the bit length 98 * and the number of high bits for the CD2X Squasher waveform, respectively; 99 * and 2 represents the fixed divider. 100 * 101 * Note that some older platforms do not contain the CD2X Divider 102 * and/or CD2X Squasher, in which case we can ignore their respective 103 * factors in the formula above. 104 * 105 * Several methods exist to change the CDCLK frequency, which ones are 106 * supported depends on the platform: 107 * 108 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. 109 * - CD2X divider update. Single pipe can be active as the divider update 110 * can be synchronized with the pipe's start of vblank. 111 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. 112 * - Squash waveform update. Pipes can be active. 113 * - Crawl and squash can also be done back to back. Pipes can be active. 114 * 115 * RAWCLK is a fixed frequency clock, often used by various auxiliary 116 * blocks such as AUX CH or backlight PWM. Hence the only thing we 117 * really need to know about RAWCLK is its frequency so that various 118 * dividers can be programmed correctly. 119 */ 120 121 struct intel_cdclk_state { 122 struct intel_global_state base; 123 124 /* 125 * Logical configuration of cdclk (used for all scaling, 126 * watermark, etc. calculations and checks). This is 127 * computed as if all enabled crtcs were active. 128 */ 129 struct intel_cdclk_config logical; 130 131 /* 132 * Actual configuration of cdclk, can be different from the 133 * logical configuration only when all crtc's are DPMS off. 134 */ 135 struct intel_cdclk_config actual; 136 137 /* minimum acceptable cdclk to satisfy DBUF bandwidth requirements */ 138 int dbuf_bw_min_cdclk; 139 /* minimum acceptable cdclk for each pipe */ 140 int min_cdclk[I915_MAX_PIPES]; 141 /* minimum acceptable voltage level for each pipe */ 142 u8 min_voltage_level[I915_MAX_PIPES]; 143 144 /* pipe to which cd2x update is synchronized */ 145 enum pipe pipe; 146 147 /* forced minimum cdclk for glk+ audio w/a */ 148 int force_min_cdclk; 149 150 /* bitmask of enabled pipes */ 151 u8 enabled_pipes; 152 153 /* bitmask of active pipes */ 154 u8 active_pipes; 155 156 /* update cdclk with pipes disabled */ 157 bool disable_pipes; 158 }; 159 160 struct intel_cdclk_funcs { 161 void (*get_cdclk)(struct intel_display *display, 162 struct intel_cdclk_config *cdclk_config); 163 void (*set_cdclk)(struct intel_display *display, 164 const struct intel_cdclk_config *cdclk_config, 165 enum pipe pipe); 166 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 167 u8 (*calc_voltage_level)(int cdclk); 168 }; 169 170 void intel_cdclk_get_cdclk(struct intel_display *display, 171 struct intel_cdclk_config *cdclk_config) 172 { 173 display->cdclk.funcs->get_cdclk(display, cdclk_config); 174 } 175 176 static void intel_cdclk_set_cdclk(struct intel_display *display, 177 const struct intel_cdclk_config *cdclk_config, 178 enum pipe pipe) 179 { 180 display->cdclk.funcs->set_cdclk(display, cdclk_config, pipe); 181 } 182 183 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) 184 { 185 struct intel_display *display = to_intel_display(state); 186 187 return display->cdclk.funcs->modeset_calc_cdclk(state); 188 } 189 190 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, 191 int cdclk) 192 { 193 return display->cdclk.funcs->calc_voltage_level(cdclk); 194 } 195 196 static void fixed_133mhz_get_cdclk(struct intel_display *display, 197 struct intel_cdclk_config *cdclk_config) 198 { 199 cdclk_config->cdclk = 133333; 200 } 201 202 static void fixed_200mhz_get_cdclk(struct intel_display *display, 203 struct intel_cdclk_config *cdclk_config) 204 { 205 cdclk_config->cdclk = 200000; 206 } 207 208 static void fixed_266mhz_get_cdclk(struct intel_display *display, 209 struct intel_cdclk_config *cdclk_config) 210 { 211 cdclk_config->cdclk = 266667; 212 } 213 214 static void fixed_333mhz_get_cdclk(struct intel_display *display, 215 struct intel_cdclk_config *cdclk_config) 216 { 217 cdclk_config->cdclk = 333333; 218 } 219 220 static void fixed_400mhz_get_cdclk(struct intel_display *display, 221 struct intel_cdclk_config *cdclk_config) 222 { 223 cdclk_config->cdclk = 400000; 224 } 225 226 static void fixed_450mhz_get_cdclk(struct intel_display *display, 227 struct intel_cdclk_config *cdclk_config) 228 { 229 cdclk_config->cdclk = 450000; 230 } 231 232 static void i85x_get_cdclk(struct intel_display *display, 233 struct intel_cdclk_config *cdclk_config) 234 { 235 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 236 u16 hpllcc = 0; 237 238 /* 239 * 852GM/852GMV only supports 133 MHz and the HPLLCC 240 * encoding is different :( 241 * FIXME is this the right way to detect 852GM/852GMV? 242 */ 243 if (pdev->revision == 0x1) { 244 cdclk_config->cdclk = 133333; 245 return; 246 } 247 248 pci_bus_read_config_word(pdev->bus, 249 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 250 251 /* Assume that the hardware is in the high speed state. This 252 * should be the default. 253 */ 254 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 255 case GC_CLOCK_133_200: 256 case GC_CLOCK_133_200_2: 257 case GC_CLOCK_100_200: 258 cdclk_config->cdclk = 200000; 259 break; 260 case GC_CLOCK_166_250: 261 cdclk_config->cdclk = 250000; 262 break; 263 case GC_CLOCK_100_133: 264 cdclk_config->cdclk = 133333; 265 break; 266 case GC_CLOCK_133_266: 267 case GC_CLOCK_133_266_2: 268 case GC_CLOCK_166_266: 269 cdclk_config->cdclk = 266667; 270 break; 271 } 272 } 273 274 static void i915gm_get_cdclk(struct intel_display *display, 275 struct intel_cdclk_config *cdclk_config) 276 { 277 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 278 u16 gcfgc = 0; 279 280 pci_read_config_word(pdev, GCFGC, &gcfgc); 281 282 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 283 cdclk_config->cdclk = 133333; 284 return; 285 } 286 287 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 288 case GC_DISPLAY_CLOCK_333_320_MHZ: 289 cdclk_config->cdclk = 333333; 290 break; 291 default: 292 case GC_DISPLAY_CLOCK_190_200_MHZ: 293 cdclk_config->cdclk = 190000; 294 break; 295 } 296 } 297 298 static void i945gm_get_cdclk(struct intel_display *display, 299 struct intel_cdclk_config *cdclk_config) 300 { 301 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 302 u16 gcfgc = 0; 303 304 pci_read_config_word(pdev, GCFGC, &gcfgc); 305 306 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 307 cdclk_config->cdclk = 133333; 308 return; 309 } 310 311 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 312 case GC_DISPLAY_CLOCK_333_320_MHZ: 313 cdclk_config->cdclk = 320000; 314 break; 315 default: 316 case GC_DISPLAY_CLOCK_190_200_MHZ: 317 cdclk_config->cdclk = 200000; 318 break; 319 } 320 } 321 322 static unsigned int intel_hpll_vco(struct intel_display *display) 323 { 324 static const unsigned int blb_vco[8] = { 325 [0] = 3200000, 326 [1] = 4000000, 327 [2] = 5333333, 328 [3] = 4800000, 329 [4] = 6400000, 330 }; 331 static const unsigned int pnv_vco[8] = { 332 [0] = 3200000, 333 [1] = 4000000, 334 [2] = 5333333, 335 [3] = 4800000, 336 [4] = 2666667, 337 }; 338 static const unsigned int cl_vco[8] = { 339 [0] = 3200000, 340 [1] = 4000000, 341 [2] = 5333333, 342 [3] = 6400000, 343 [4] = 3333333, 344 [5] = 3566667, 345 [6] = 4266667, 346 }; 347 static const unsigned int elk_vco[8] = { 348 [0] = 3200000, 349 [1] = 4000000, 350 [2] = 5333333, 351 [3] = 4800000, 352 }; 353 static const unsigned int ctg_vco[8] = { 354 [0] = 3200000, 355 [1] = 4000000, 356 [2] = 5333333, 357 [3] = 6400000, 358 [4] = 2666667, 359 [5] = 4266667, 360 }; 361 const unsigned int *vco_table; 362 unsigned int vco; 363 u8 tmp = 0; 364 365 /* FIXME other chipsets? */ 366 if (display->platform.gm45) 367 vco_table = ctg_vco; 368 else if (display->platform.g45) 369 vco_table = elk_vco; 370 else if (display->platform.i965gm) 371 vco_table = cl_vco; 372 else if (display->platform.pineview) 373 vco_table = pnv_vco; 374 else if (display->platform.g33) 375 vco_table = blb_vco; 376 else 377 return 0; 378 379 tmp = intel_mchbar_read(display, display->platform.pineview || 380 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); 381 382 vco = vco_table[tmp & 0x7]; 383 if (vco == 0) 384 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 385 tmp); 386 else 387 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); 388 389 return vco; 390 } 391 392 static void g33_get_cdclk(struct intel_display *display, 393 struct intel_cdclk_config *cdclk_config) 394 { 395 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 396 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 397 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 398 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 399 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 400 const u8 *div_table; 401 unsigned int cdclk_sel; 402 u16 tmp = 0; 403 404 cdclk_config->vco = intel_hpll_vco(display); 405 406 pci_read_config_word(pdev, GCFGC, &tmp); 407 408 cdclk_sel = (tmp >> 4) & 0x7; 409 410 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 411 goto fail; 412 413 switch (cdclk_config->vco) { 414 case 3200000: 415 div_table = div_3200; 416 break; 417 case 4000000: 418 div_table = div_4000; 419 break; 420 case 4800000: 421 div_table = div_4800; 422 break; 423 case 5333333: 424 div_table = div_5333; 425 break; 426 default: 427 goto fail; 428 } 429 430 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 431 div_table[cdclk_sel]); 432 return; 433 434 fail: 435 drm_err(display->drm, 436 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 437 cdclk_config->vco, tmp); 438 cdclk_config->cdclk = 190476; 439 } 440 441 static void pnv_get_cdclk(struct intel_display *display, 442 struct intel_cdclk_config *cdclk_config) 443 { 444 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 445 u16 gcfgc = 0; 446 447 pci_read_config_word(pdev, GCFGC, &gcfgc); 448 449 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 450 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 451 cdclk_config->cdclk = 266667; 452 break; 453 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 454 cdclk_config->cdclk = 333333; 455 break; 456 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 457 cdclk_config->cdclk = 444444; 458 break; 459 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 460 cdclk_config->cdclk = 200000; 461 break; 462 default: 463 drm_err(display->drm, 464 "Unknown pnv display core clock 0x%04x\n", gcfgc); 465 fallthrough; 466 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 467 cdclk_config->cdclk = 133333; 468 break; 469 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 470 cdclk_config->cdclk = 166667; 471 break; 472 } 473 } 474 475 static void i965gm_get_cdclk(struct intel_display *display, 476 struct intel_cdclk_config *cdclk_config) 477 { 478 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 479 static const u8 div_3200[] = { 16, 10, 8 }; 480 static const u8 div_4000[] = { 20, 12, 10 }; 481 static const u8 div_5333[] = { 24, 16, 14 }; 482 const u8 *div_table; 483 unsigned int cdclk_sel; 484 u16 tmp = 0; 485 486 cdclk_config->vco = intel_hpll_vco(display); 487 488 pci_read_config_word(pdev, GCFGC, &tmp); 489 490 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 491 492 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 493 goto fail; 494 495 switch (cdclk_config->vco) { 496 case 3200000: 497 div_table = div_3200; 498 break; 499 case 4000000: 500 div_table = div_4000; 501 break; 502 case 5333333: 503 div_table = div_5333; 504 break; 505 default: 506 goto fail; 507 } 508 509 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 510 div_table[cdclk_sel]); 511 return; 512 513 fail: 514 drm_err(display->drm, 515 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 516 cdclk_config->vco, tmp); 517 cdclk_config->cdclk = 200000; 518 } 519 520 static void gm45_get_cdclk(struct intel_display *display, 521 struct intel_cdclk_config *cdclk_config) 522 { 523 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 524 unsigned int cdclk_sel; 525 u16 tmp = 0; 526 527 cdclk_config->vco = intel_hpll_vco(display); 528 529 pci_read_config_word(pdev, GCFGC, &tmp); 530 531 cdclk_sel = (tmp >> 12) & 0x1; 532 533 switch (cdclk_config->vco) { 534 case 2666667: 535 case 4000000: 536 case 5333333: 537 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 538 break; 539 case 3200000: 540 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 541 break; 542 default: 543 drm_err(display->drm, 544 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 545 cdclk_config->vco, tmp); 546 cdclk_config->cdclk = 222222; 547 break; 548 } 549 } 550 551 static void hsw_get_cdclk(struct intel_display *display, 552 struct intel_cdclk_config *cdclk_config) 553 { 554 u32 lcpll = intel_de_read(display, LCPLL_CTL); 555 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 556 557 if (lcpll & LCPLL_CD_SOURCE_FCLK) 558 cdclk_config->cdclk = 800000; 559 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 560 cdclk_config->cdclk = 450000; 561 else if (freq == LCPLL_CLK_FREQ_450) 562 cdclk_config->cdclk = 450000; 563 else if (display->platform.haswell_ult) 564 cdclk_config->cdclk = 337500; 565 else 566 cdclk_config->cdclk = 540000; 567 } 568 569 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) 570 { 571 int freq_320 = (vlv_clock_get_hpll_vco(display->drm) << 1) % 320000 != 0 ? 572 333333 : 320000; 573 574 /* 575 * We seem to get an unstable or solid color picture at 200MHz. 576 * Not sure what's wrong. For now use 200MHz only when all pipes 577 * are off. 578 */ 579 if (display->platform.valleyview && min_cdclk > freq_320) 580 return 400000; 581 else if (min_cdclk > 266667) 582 return freq_320; 583 else if (min_cdclk > 0) 584 return 266667; 585 else 586 return 200000; 587 } 588 589 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) 590 { 591 if (display->platform.valleyview) { 592 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 593 return 2; 594 else if (cdclk >= 266667) 595 return 1; 596 else 597 return 0; 598 } else { 599 /* 600 * Specs are full of misinformation, but testing on actual 601 * hardware has shown that we just need to write the desired 602 * CCK divider into the Punit register. 603 */ 604 return DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, cdclk) - 1; 605 } 606 } 607 608 static void vlv_get_cdclk(struct intel_display *display, 609 struct intel_cdclk_config *cdclk_config) 610 { 611 u32 val; 612 613 cdclk_config->vco = vlv_clock_get_hpll_vco(display->drm); 614 cdclk_config->cdclk = vlv_clock_get_cdclk(display->drm); 615 616 vlv_punit_get(display); 617 val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); 618 vlv_punit_put(display); 619 620 if (display->platform.valleyview) 621 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 622 DSPFREQGUAR_SHIFT; 623 else 624 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 625 DSPFREQGUAR_SHIFT_CHV; 626 } 627 628 static void vlv_program_pfi_credits(struct intel_display *display) 629 { 630 unsigned int credits, default_credits; 631 632 if (display->platform.cherryview) 633 default_credits = PFI_CREDIT(12); 634 else 635 default_credits = PFI_CREDIT(8); 636 637 if (display->cdclk.hw.cdclk >= vlv_clock_get_czclk(display->drm)) { 638 /* CHV suggested value is 31 or 63 */ 639 if (display->platform.cherryview) 640 credits = PFI_CREDIT_63; 641 else 642 credits = PFI_CREDIT(15); 643 } else { 644 credits = default_credits; 645 } 646 647 /* 648 * WA - write default credits before re-programming 649 * FIXME: should we also set the resend bit here? 650 */ 651 intel_de_write(display, GCI_CONTROL, 652 VGA_FAST_MODE_DISABLE | default_credits); 653 654 intel_de_write(display, GCI_CONTROL, 655 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 656 657 /* 658 * FIXME is this guaranteed to clear 659 * immediately or should we poll for it? 660 */ 661 drm_WARN_ON(display->drm, 662 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); 663 } 664 665 static void vlv_set_cdclk(struct intel_display *display, 666 const struct intel_cdclk_config *cdclk_config, 667 enum pipe pipe) 668 { 669 int cdclk = cdclk_config->cdclk; 670 u32 val, cmd = cdclk_config->voltage_level; 671 struct ref_tracker *wakeref; 672 int ret; 673 674 switch (cdclk) { 675 case 400000: 676 case 333333: 677 case 320000: 678 case 266667: 679 case 200000: 680 break; 681 default: 682 MISSING_CASE(cdclk); 683 return; 684 } 685 686 /* There are cases where we can end up here with power domains 687 * off and a CDCLK frequency other than the minimum, like when 688 * issuing a modeset without actually changing any display after 689 * a system suspend. So grab the display core domain, which covers 690 * the HW blocks needed for the following programming. 691 */ 692 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 693 694 intel_parent_vlv_iosf_get(display, 695 BIT(VLV_IOSF_SB_CCK) | 696 BIT(VLV_IOSF_SB_BUNIT) | 697 BIT(VLV_IOSF_SB_PUNIT)); 698 699 val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); 700 val &= ~DSPFREQGUAR_MASK; 701 val |= (cmd << DSPFREQGUAR_SHIFT); 702 vlv_punit_write(display, PUNIT_REG_DSPSSPM, val); 703 704 ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM), 705 (val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 706 500, 50 * 1000, false); 707 if (ret) 708 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 709 710 if (cdclk == 400000) { 711 u32 divider; 712 713 divider = DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, 714 cdclk) - 1; 715 716 /* adjust cdclk divider */ 717 val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL); 718 val &= ~CCK_FREQUENCY_VALUES; 719 val |= divider; 720 vlv_cck_write(display, CCK_DISPLAY_CLOCK_CONTROL, val); 721 722 ret = poll_timeout_us(val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL), 723 (val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 724 500, 50 * 1000, false); 725 if (ret) 726 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 727 } 728 729 /* adjust self-refresh exit latency value */ 730 val = vlv_bunit_read(display, BUNIT_REG_BISOC); 731 val &= ~0x7f; 732 733 /* 734 * For high bandwidth configs, we set a higher latency in the bunit 735 * so that the core display fetch happens in time to avoid underruns. 736 */ 737 if (cdclk == 400000) 738 val |= 4500 / 250; /* 4.5 usec */ 739 else 740 val |= 3000 / 250; /* 3.0 usec */ 741 vlv_bunit_write(display, BUNIT_REG_BISOC, val); 742 743 intel_parent_vlv_iosf_put(display, 744 BIT(VLV_IOSF_SB_CCK) | 745 BIT(VLV_IOSF_SB_BUNIT) | 746 BIT(VLV_IOSF_SB_PUNIT)); 747 748 intel_update_cdclk(display); 749 750 vlv_program_pfi_credits(display); 751 752 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 753 } 754 755 static void chv_set_cdclk(struct intel_display *display, 756 const struct intel_cdclk_config *cdclk_config, 757 enum pipe pipe) 758 { 759 int cdclk = cdclk_config->cdclk; 760 u32 val, cmd = cdclk_config->voltage_level; 761 struct ref_tracker *wakeref; 762 int ret; 763 764 switch (cdclk) { 765 case 333333: 766 case 320000: 767 case 266667: 768 case 200000: 769 break; 770 default: 771 MISSING_CASE(cdclk); 772 return; 773 } 774 775 /* There are cases where we can end up here with power domains 776 * off and a CDCLK frequency other than the minimum, like when 777 * issuing a modeset without actually changing any display after 778 * a system suspend. So grab the display core domain, which covers 779 * the HW blocks needed for the following programming. 780 */ 781 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 782 783 vlv_punit_get(display); 784 val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); 785 val &= ~DSPFREQGUAR_MASK_CHV; 786 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 787 vlv_punit_write(display, PUNIT_REG_DSPSSPM, val); 788 789 ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM), 790 (val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 791 500, 50 * 1000, false); 792 if (ret) 793 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 794 795 vlv_punit_put(display); 796 797 intel_update_cdclk(display); 798 799 vlv_program_pfi_credits(display); 800 801 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 802 } 803 804 static int bdw_calc_cdclk(int min_cdclk) 805 { 806 if (min_cdclk > 540000) 807 return 675000; 808 else if (min_cdclk > 450000) 809 return 540000; 810 else if (min_cdclk > 337500) 811 return 450000; 812 else 813 return 337500; 814 } 815 816 static u8 bdw_calc_voltage_level(int cdclk) 817 { 818 switch (cdclk) { 819 default: 820 case 337500: 821 return 2; 822 case 450000: 823 return 0; 824 case 540000: 825 return 1; 826 case 675000: 827 return 3; 828 } 829 } 830 831 static void bdw_get_cdclk(struct intel_display *display, 832 struct intel_cdclk_config *cdclk_config) 833 { 834 u32 lcpll = intel_de_read(display, LCPLL_CTL); 835 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 836 837 if (lcpll & LCPLL_CD_SOURCE_FCLK) 838 cdclk_config->cdclk = 800000; 839 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 840 cdclk_config->cdclk = 450000; 841 else if (freq == LCPLL_CLK_FREQ_450) 842 cdclk_config->cdclk = 450000; 843 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 844 cdclk_config->cdclk = 540000; 845 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 846 cdclk_config->cdclk = 337500; 847 else 848 cdclk_config->cdclk = 675000; 849 850 /* 851 * Can't read this out :( Let's assume it's 852 * at least what the CDCLK frequency requires. 853 */ 854 cdclk_config->voltage_level = 855 bdw_calc_voltage_level(cdclk_config->cdclk); 856 } 857 858 static u32 bdw_cdclk_freq_sel(int cdclk) 859 { 860 switch (cdclk) { 861 default: 862 MISSING_CASE(cdclk); 863 fallthrough; 864 case 337500: 865 return LCPLL_CLK_FREQ_337_5_BDW; 866 case 450000: 867 return LCPLL_CLK_FREQ_450; 868 case 540000: 869 return LCPLL_CLK_FREQ_54O_BDW; 870 case 675000: 871 return LCPLL_CLK_FREQ_675_BDW; 872 } 873 } 874 875 static void bdw_set_cdclk(struct intel_display *display, 876 const struct intel_cdclk_config *cdclk_config, 877 enum pipe pipe) 878 { 879 int cdclk = cdclk_config->cdclk; 880 int ret; 881 882 if (drm_WARN(display->drm, 883 (intel_de_read(display, LCPLL_CTL) & 884 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 885 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 886 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 887 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 888 "trying to change cdclk frequency with cdclk not enabled\n")) 889 return; 890 891 ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 892 if (ret) { 893 drm_err(display->drm, 894 "failed to inform pcode about cdclk change\n"); 895 return; 896 } 897 898 intel_de_rmw(display, LCPLL_CTL, 899 0, LCPLL_CD_SOURCE_FCLK); 900 901 /* 902 * According to the spec, it should be enough to poll for this 1 us. 903 * However, extensive testing shows that this can take longer. 904 */ 905 ret = intel_de_wait_for_set_us(display, LCPLL_CTL, 906 LCPLL_CD_SOURCE_FCLK_DONE, 100); 907 if (ret) 908 drm_err(display->drm, "Switching to FCLK failed\n"); 909 910 intel_de_rmw(display, LCPLL_CTL, 911 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 912 913 intel_de_rmw(display, LCPLL_CTL, 914 LCPLL_CD_SOURCE_FCLK, 0); 915 916 ret = intel_de_wait_for_clear_us(display, LCPLL_CTL, 917 LCPLL_CD_SOURCE_FCLK_DONE, 1); 918 if (ret) 919 drm_err(display->drm, "Switching back to LCPLL failed\n"); 920 921 intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ, 922 cdclk_config->voltage_level); 923 924 intel_de_write(display, CDCLK_FREQ, 925 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 926 927 intel_update_cdclk(display); 928 } 929 930 static int skl_calc_cdclk(int min_cdclk, int vco) 931 { 932 if (vco == 8640000) { 933 if (min_cdclk > 540000) 934 return 617143; 935 else if (min_cdclk > 432000) 936 return 540000; 937 else if (min_cdclk > 308571) 938 return 432000; 939 else 940 return 308571; 941 } else { 942 if (min_cdclk > 540000) 943 return 675000; 944 else if (min_cdclk > 450000) 945 return 540000; 946 else if (min_cdclk > 337500) 947 return 450000; 948 else 949 return 337500; 950 } 951 } 952 953 static u8 skl_calc_voltage_level(int cdclk) 954 { 955 if (cdclk > 540000) 956 return 3; 957 else if (cdclk > 450000) 958 return 2; 959 else if (cdclk > 337500) 960 return 1; 961 else 962 return 0; 963 } 964 965 static void skl_dpll0_update(struct intel_display *display, 966 struct intel_cdclk_config *cdclk_config) 967 { 968 u32 val; 969 970 cdclk_config->ref = 24000; 971 cdclk_config->vco = 0; 972 973 val = intel_de_read(display, LCPLL1_CTL); 974 if ((val & LCPLL_PLL_ENABLE) == 0) 975 return; 976 977 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) 978 return; 979 980 val = intel_de_read(display, DPLL_CTRL1); 981 982 if (drm_WARN_ON(display->drm, 983 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 984 DPLL_CTRL1_SSC(SKL_DPLL0) | 985 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 986 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 987 return; 988 989 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 990 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 991 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 992 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 993 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 994 cdclk_config->vco = 8100000; 995 break; 996 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 997 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 998 cdclk_config->vco = 8640000; 999 break; 1000 default: 1001 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 1002 break; 1003 } 1004 } 1005 1006 static void skl_get_cdclk(struct intel_display *display, 1007 struct intel_cdclk_config *cdclk_config) 1008 { 1009 u32 cdctl; 1010 1011 skl_dpll0_update(display, cdclk_config); 1012 1013 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 1014 1015 if (cdclk_config->vco == 0) 1016 goto out; 1017 1018 cdctl = intel_de_read(display, CDCLK_CTL); 1019 1020 if (cdclk_config->vco == 8640000) { 1021 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1022 case CDCLK_FREQ_450_432: 1023 cdclk_config->cdclk = 432000; 1024 break; 1025 case CDCLK_FREQ_337_308: 1026 cdclk_config->cdclk = 308571; 1027 break; 1028 case CDCLK_FREQ_540: 1029 cdclk_config->cdclk = 540000; 1030 break; 1031 case CDCLK_FREQ_675_617: 1032 cdclk_config->cdclk = 617143; 1033 break; 1034 default: 1035 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1036 break; 1037 } 1038 } else { 1039 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1040 case CDCLK_FREQ_450_432: 1041 cdclk_config->cdclk = 450000; 1042 break; 1043 case CDCLK_FREQ_337_308: 1044 cdclk_config->cdclk = 337500; 1045 break; 1046 case CDCLK_FREQ_540: 1047 cdclk_config->cdclk = 540000; 1048 break; 1049 case CDCLK_FREQ_675_617: 1050 cdclk_config->cdclk = 675000; 1051 break; 1052 default: 1053 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1054 break; 1055 } 1056 } 1057 1058 out: 1059 /* 1060 * Can't read this out :( Let's assume it's 1061 * at least what the CDCLK frequency requires. 1062 */ 1063 cdclk_config->voltage_level = 1064 skl_calc_voltage_level(cdclk_config->cdclk); 1065 } 1066 1067 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 1068 static int skl_cdclk_decimal(int cdclk) 1069 { 1070 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 1071 } 1072 1073 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) 1074 { 1075 bool changed = display->cdclk.skl_preferred_vco_freq != vco; 1076 1077 display->cdclk.skl_preferred_vco_freq = vco; 1078 1079 if (changed) 1080 intel_update_max_cdclk(display); 1081 } 1082 1083 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) 1084 { 1085 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 1086 1087 /* 1088 * We always enable DPLL0 with the lowest link rate possible, but still 1089 * taking into account the VCO required to operate the eDP panel at the 1090 * desired frequency. The usual DP link rates operate with a VCO of 1091 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1092 * The modeset code is responsible for the selection of the exact link 1093 * rate later on, with the constraint of choosing a frequency that 1094 * works with vco. 1095 */ 1096 if (vco == 8640000) 1097 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1098 else 1099 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1100 } 1101 1102 static void skl_dpll0_enable(struct intel_display *display, int vco) 1103 { 1104 intel_de_rmw(display, DPLL_CTRL1, 1105 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1106 DPLL_CTRL1_SSC(SKL_DPLL0) | 1107 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1108 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1109 skl_dpll0_link_rate(display, vco)); 1110 intel_de_posting_read(display, DPLL_CTRL1); 1111 1112 intel_de_rmw(display, LCPLL1_CTL, 1113 0, LCPLL_PLL_ENABLE); 1114 1115 if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1116 drm_err(display->drm, "DPLL0 not locked\n"); 1117 1118 display->cdclk.hw.vco = vco; 1119 1120 /* We'll want to keep using the current vco from now on. */ 1121 skl_set_preferred_cdclk_vco(display, vco); 1122 } 1123 1124 static void skl_dpll0_disable(struct intel_display *display) 1125 { 1126 intel_de_rmw(display, LCPLL1_CTL, 1127 LCPLL_PLL_ENABLE, 0); 1128 1129 if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1130 drm_err(display->drm, "Couldn't disable DPLL0\n"); 1131 1132 display->cdclk.hw.vco = 0; 1133 } 1134 1135 static u32 skl_cdclk_freq_sel(struct intel_display *display, 1136 int cdclk, int vco) 1137 { 1138 switch (cdclk) { 1139 default: 1140 drm_WARN_ON(display->drm, 1141 cdclk != display->cdclk.hw.bypass); 1142 drm_WARN_ON(display->drm, vco != 0); 1143 fallthrough; 1144 case 308571: 1145 case 337500: 1146 return CDCLK_FREQ_337_308; 1147 case 450000: 1148 case 432000: 1149 return CDCLK_FREQ_450_432; 1150 case 540000: 1151 return CDCLK_FREQ_540; 1152 case 617143: 1153 case 675000: 1154 return CDCLK_FREQ_675_617; 1155 } 1156 } 1157 1158 static void skl_set_cdclk(struct intel_display *display, 1159 const struct intel_cdclk_config *cdclk_config, 1160 enum pipe pipe) 1161 { 1162 int cdclk = cdclk_config->cdclk; 1163 int vco = cdclk_config->vco; 1164 u32 freq_select, cdclk_ctl; 1165 int ret; 1166 1167 /* 1168 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1169 * unsupported on SKL. In theory this should never happen since only 1170 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1171 * supported on SKL either, see the above WA. WARN whenever trying to 1172 * use the corresponding VCO freq as that always leads to using the 1173 * minimum 308MHz CDCLK. 1174 */ 1175 drm_WARN_ON_ONCE(display->drm, 1176 display->platform.skylake && vco == 8640000); 1177 1178 ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL, 1179 SKL_CDCLK_PREPARE_FOR_CHANGE, 1180 SKL_CDCLK_READY_FOR_CHANGE, 1181 SKL_CDCLK_READY_FOR_CHANGE, 3); 1182 if (ret) { 1183 drm_err(display->drm, 1184 "Failed to inform PCU about cdclk change (%d)\n", ret); 1185 return; 1186 } 1187 1188 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); 1189 1190 if (display->cdclk.hw.vco != 0 && 1191 display->cdclk.hw.vco != vco) 1192 skl_dpll0_disable(display); 1193 1194 cdclk_ctl = intel_de_read(display, CDCLK_CTL); 1195 1196 if (display->cdclk.hw.vco != vco) { 1197 /* Wa Display #1183: skl,kbl,cfl */ 1198 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1199 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1200 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1201 } 1202 1203 /* Wa Display #1183: skl,kbl,cfl */ 1204 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1205 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1206 intel_de_posting_read(display, CDCLK_CTL); 1207 1208 if (display->cdclk.hw.vco != vco) 1209 skl_dpll0_enable(display, vco); 1210 1211 /* Wa Display #1183: skl,kbl,cfl */ 1212 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1213 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1214 1215 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1216 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1217 1218 /* Wa Display #1183: skl,kbl,cfl */ 1219 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1220 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1221 intel_de_posting_read(display, CDCLK_CTL); 1222 1223 /* inform PCU of the change */ 1224 intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL, 1225 cdclk_config->voltage_level); 1226 1227 intel_update_cdclk(display); 1228 } 1229 1230 static void skl_sanitize_cdclk(struct intel_display *display) 1231 { 1232 u32 cdctl, expected; 1233 1234 /* 1235 * check if the pre-os initialized the display 1236 * There is SWF18 scratchpad register defined which is set by the 1237 * pre-os which can be used by the OS drivers to check the status 1238 */ 1239 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1240 goto sanitize; 1241 1242 intel_update_cdclk(display); 1243 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1244 1245 /* Is PLL enabled and locked ? */ 1246 if (display->cdclk.hw.vco == 0 || 1247 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 1248 goto sanitize; 1249 1250 /* DPLL okay; verify the cdclock 1251 * 1252 * Noticed in some instances that the freq selection is correct but 1253 * decimal part is programmed wrong from BIOS where pre-os does not 1254 * enable display. Verify the same as well. 1255 */ 1256 cdctl = intel_de_read(display, CDCLK_CTL); 1257 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1258 skl_cdclk_decimal(display->cdclk.hw.cdclk); 1259 1260 if (cdctl != expected) { 1261 cdctl &= ~CDCLK_FREQ_DECIMAL_MASK; 1262 cdctl |= expected & CDCLK_FREQ_DECIMAL_MASK; 1263 1264 if (cdctl != expected) 1265 goto sanitize; 1266 1267 drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n", 1268 intel_de_read(display, CDCLK_CTL), expected); 1269 1270 intel_de_write(display, CDCLK_CTL, expected); 1271 } 1272 1273 /* All well; nothing to sanitize */ 1274 return; 1275 1276 sanitize: 1277 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 1278 1279 /* force cdclk programming */ 1280 display->cdclk.hw.cdclk = 0; 1281 /* force full PLL disable + enable */ 1282 display->cdclk.hw.vco = ~0; 1283 } 1284 1285 static void skl_cdclk_init_hw(struct intel_display *display) 1286 { 1287 struct intel_cdclk_config cdclk_config; 1288 1289 skl_sanitize_cdclk(display); 1290 1291 if (display->cdclk.hw.cdclk != 0 && 1292 display->cdclk.hw.vco != 0) { 1293 /* 1294 * Use the current vco as our initial 1295 * guess as to what the preferred vco is. 1296 */ 1297 if (display->cdclk.skl_preferred_vco_freq == 0) 1298 skl_set_preferred_cdclk_vco(display, 1299 display->cdclk.hw.vco); 1300 return; 1301 } 1302 1303 cdclk_config = display->cdclk.hw; 1304 1305 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; 1306 if (cdclk_config.vco == 0) 1307 cdclk_config.vco = 8100000; 1308 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1309 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1310 1311 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1312 } 1313 1314 static void skl_cdclk_uninit_hw(struct intel_display *display) 1315 { 1316 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 1317 1318 cdclk_config.cdclk = cdclk_config.bypass; 1319 cdclk_config.vco = 0; 1320 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1321 1322 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1323 } 1324 1325 struct intel_cdclk_vals { 1326 u32 cdclk; 1327 u16 refclk; 1328 u16 waveform; 1329 u8 ratio; 1330 }; 1331 1332 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1333 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1334 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1335 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1336 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1337 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1338 {} 1339 }; 1340 1341 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1342 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1343 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1344 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1345 {} 1346 }; 1347 1348 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1349 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1350 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1351 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1352 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1353 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1354 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1355 1356 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1357 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1358 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1359 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1360 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1361 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1362 1363 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1364 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1365 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1366 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1367 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1368 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1369 {} 1370 }; 1371 1372 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1373 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1374 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1375 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1376 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1377 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1378 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1379 1380 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1381 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1382 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1383 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1384 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1385 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1386 1387 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1388 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1389 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1390 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1391 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1392 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1393 {} 1394 }; 1395 1396 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1397 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1398 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1399 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1400 1401 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1402 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1403 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1404 1405 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1406 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1407 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1408 {} 1409 }; 1410 1411 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1412 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1413 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1414 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1415 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1416 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1417 1418 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1419 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1420 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1421 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1422 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1423 1424 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1425 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1426 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1427 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1428 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1429 {} 1430 }; 1431 1432 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1433 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1434 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1435 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1436 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1437 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1438 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1439 1440 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1441 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1442 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1443 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1444 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1445 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1446 1447 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1448 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1449 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1450 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1451 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1452 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1453 {} 1454 }; 1455 1456 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1457 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1458 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1459 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1460 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1461 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1462 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1463 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1464 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1465 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1466 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1467 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1468 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1469 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1470 {} 1471 }; 1472 1473 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1474 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1475 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1476 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1477 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1478 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1479 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1480 {} 1481 }; 1482 1483 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { 1484 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1485 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1486 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1487 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1488 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1489 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1490 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1491 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1492 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1493 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1494 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1495 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1496 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1497 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1498 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1499 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1500 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1501 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1502 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1503 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1504 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1505 {} 1506 }; 1507 1508 /* 1509 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 1510 */ 1511 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 1512 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1513 {} 1514 }; 1515 1516 static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { 1517 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1518 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1519 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1520 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1521 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1522 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1523 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1524 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1525 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1526 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff }, 1527 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff }, 1528 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff }, 1529 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff }, 1530 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1531 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1532 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1533 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1534 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1535 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1536 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1537 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1538 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1539 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1540 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1541 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1542 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1543 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1544 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1545 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1546 {} 1547 }; 1548 1549 static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = { 1550 { .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 }, 1551 { .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 }, 1552 { .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa }, 1553 { .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a }, 1554 { .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 }, 1555 { .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 }, 1556 { .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee }, 1557 { .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de }, 1558 { .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe }, 1559 { .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe }, 1560 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1561 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1562 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1563 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1564 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1565 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1566 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1567 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1568 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1569 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1570 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1571 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1572 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1573 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1574 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1575 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1576 { .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff }, 1577 { .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff }, 1578 { .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff }, 1579 { .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff }, 1580 { .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff }, 1581 {} 1582 }; 1583 1584 static const int cdclk_squash_len = 16; 1585 1586 static int cdclk_squash_divider(u16 waveform) 1587 { 1588 return hweight16(waveform ?: 0xffff); 1589 } 1590 1591 static int cdclk_divider(int cdclk, int vco, u16 waveform) 1592 { 1593 /* 2 * cd2x divider */ 1594 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), 1595 cdclk * cdclk_squash_len); 1596 } 1597 1598 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) 1599 { 1600 const struct intel_cdclk_vals *table = display->cdclk.table; 1601 int i; 1602 1603 for (i = 0; table[i].refclk; i++) 1604 if (table[i].refclk == display->cdclk.hw.ref && 1605 table[i].cdclk >= min_cdclk) 1606 return table[i].cdclk; 1607 1608 drm_WARN(display->drm, 1, 1609 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1610 min_cdclk, display->cdclk.hw.ref); 1611 return display->cdclk.max_cdclk_freq; 1612 } 1613 1614 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) 1615 { 1616 const struct intel_cdclk_vals *table = display->cdclk.table; 1617 int i; 1618 1619 if (cdclk == display->cdclk.hw.bypass) 1620 return 0; 1621 1622 for (i = 0; table[i].refclk; i++) 1623 if (table[i].refclk == display->cdclk.hw.ref && 1624 table[i].cdclk == cdclk) 1625 return display->cdclk.hw.ref * table[i].ratio; 1626 1627 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1628 cdclk, display->cdclk.hw.ref); 1629 return 0; 1630 } 1631 1632 static u8 bxt_calc_voltage_level(int cdclk) 1633 { 1634 return DIV_ROUND_UP(cdclk, 25000); 1635 } 1636 1637 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1638 const int voltage_level_max_cdclk[]) 1639 { 1640 int voltage_level; 1641 1642 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1643 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1644 return voltage_level; 1645 } 1646 1647 MISSING_CASE(cdclk); 1648 return num_voltage_levels - 1; 1649 } 1650 1651 static u8 icl_calc_voltage_level(int cdclk) 1652 { 1653 static const int icl_voltage_level_max_cdclk[] = { 1654 [0] = 312000, 1655 [1] = 556800, 1656 [2] = 652800, 1657 }; 1658 1659 return calc_voltage_level(cdclk, 1660 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1661 icl_voltage_level_max_cdclk); 1662 } 1663 1664 static u8 ehl_calc_voltage_level(int cdclk) 1665 { 1666 static const int ehl_voltage_level_max_cdclk[] = { 1667 [0] = 180000, 1668 [1] = 312000, 1669 [2] = 326400, 1670 /* 1671 * Bspec lists the limit as 556.8 MHz, but some JSL 1672 * development boards (at least) boot with 652.8 MHz 1673 */ 1674 [3] = 652800, 1675 }; 1676 1677 return calc_voltage_level(cdclk, 1678 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1679 ehl_voltage_level_max_cdclk); 1680 } 1681 1682 static u8 tgl_calc_voltage_level(int cdclk) 1683 { 1684 static const int tgl_voltage_level_max_cdclk[] = { 1685 [0] = 312000, 1686 [1] = 326400, 1687 [2] = 556800, 1688 [3] = 652800, 1689 }; 1690 1691 return calc_voltage_level(cdclk, 1692 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1693 tgl_voltage_level_max_cdclk); 1694 } 1695 1696 static u8 rplu_calc_voltage_level(int cdclk) 1697 { 1698 static const int rplu_voltage_level_max_cdclk[] = { 1699 [0] = 312000, 1700 [1] = 480000, 1701 [2] = 556800, 1702 [3] = 652800, 1703 }; 1704 1705 return calc_voltage_level(cdclk, 1706 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1707 rplu_voltage_level_max_cdclk); 1708 } 1709 1710 static u8 xe3lpd_calc_voltage_level(int cdclk) 1711 { 1712 /* 1713 * Starting with xe3lpd power controller does not need the voltage 1714 * index when doing the modeset update. This function is best left 1715 * defined but returning 0 to the mask. 1716 */ 1717 return 0; 1718 } 1719 1720 static void icl_readout_refclk(struct intel_display *display, 1721 struct intel_cdclk_config *cdclk_config) 1722 { 1723 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1724 1725 switch (dssm) { 1726 default: 1727 MISSING_CASE(dssm); 1728 fallthrough; 1729 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1730 cdclk_config->ref = 24000; 1731 break; 1732 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1733 cdclk_config->ref = 19200; 1734 break; 1735 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1736 cdclk_config->ref = 38400; 1737 break; 1738 } 1739 } 1740 1741 static void bxt_de_pll_readout(struct intel_display *display, 1742 struct intel_cdclk_config *cdclk_config) 1743 { 1744 u32 val, ratio; 1745 1746 if (display->platform.dg2) 1747 cdclk_config->ref = 38400; 1748 else if (DISPLAY_VER(display) >= 11) 1749 icl_readout_refclk(display, cdclk_config); 1750 else 1751 cdclk_config->ref = 19200; 1752 1753 val = intel_de_read(display, BXT_DE_PLL_ENABLE); 1754 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1755 (val & BXT_DE_PLL_LOCK) == 0) { 1756 /* 1757 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1758 * setting it to zero is a way to signal that. 1759 */ 1760 cdclk_config->vco = 0; 1761 return; 1762 } 1763 1764 /* 1765 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1766 * gen9lp had it in a separate PLL control register. 1767 */ 1768 if (DISPLAY_VER(display) >= 11) 1769 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1770 else 1771 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1772 1773 cdclk_config->vco = ratio * cdclk_config->ref; 1774 } 1775 1776 static void bxt_get_cdclk(struct intel_display *display, 1777 struct intel_cdclk_config *cdclk_config) 1778 { 1779 u32 squash_ctl = 0; 1780 u32 divider; 1781 int div; 1782 1783 bxt_de_pll_readout(display, cdclk_config); 1784 1785 if (DISPLAY_VER(display) >= 12) 1786 cdclk_config->bypass = cdclk_config->ref / 2; 1787 else if (DISPLAY_VER(display) >= 11) 1788 cdclk_config->bypass = 50000; 1789 else 1790 cdclk_config->bypass = cdclk_config->ref; 1791 1792 if (cdclk_config->vco == 0) { 1793 cdclk_config->cdclk = cdclk_config->bypass; 1794 goto out; 1795 } 1796 1797 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1798 1799 switch (divider) { 1800 case BXT_CDCLK_CD2X_DIV_SEL_1: 1801 div = 2; 1802 break; 1803 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1804 div = 3; 1805 break; 1806 case BXT_CDCLK_CD2X_DIV_SEL_2: 1807 div = 4; 1808 break; 1809 case BXT_CDCLK_CD2X_DIV_SEL_4: 1810 div = 8; 1811 break; 1812 default: 1813 MISSING_CASE(divider); 1814 return; 1815 } 1816 1817 if (HAS_CDCLK_SQUASH(display)) 1818 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); 1819 1820 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1821 u16 waveform; 1822 int size; 1823 1824 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1825 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1826 1827 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1828 cdclk_config->vco, size * div); 1829 } else { 1830 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1831 } 1832 1833 out: 1834 if (DISPLAY_VER(display) >= 20) 1835 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 1836 /* 1837 * Can't read this out :( Let's assume it's 1838 * at least what the CDCLK frequency requires. 1839 */ 1840 cdclk_config->voltage_level = 1841 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); 1842 } 1843 1844 static void bxt_de_pll_disable(struct intel_display *display) 1845 { 1846 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); 1847 1848 /* Timeout 200us */ 1849 if (intel_de_wait_for_clear_ms(display, 1850 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1851 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); 1852 1853 display->cdclk.hw.vco = 0; 1854 } 1855 1856 static void bxt_de_pll_enable(struct intel_display *display, int vco) 1857 { 1858 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1859 1860 intel_de_rmw(display, BXT_DE_PLL_CTL, 1861 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1862 1863 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1864 1865 /* Timeout 200us */ 1866 if (intel_de_wait_for_set_ms(display, 1867 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1868 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); 1869 1870 display->cdclk.hw.vco = vco; 1871 } 1872 1873 static void icl_cdclk_pll_disable(struct intel_display *display) 1874 { 1875 /* 1876 * Wa_13012396614: 1877 * Fixes: A sporadic race condition between MDCLK selection and PLL 1878 * enabling. 1879 * Workaround: 1880 * Change programming of MDCLK source selection in CDCLK_CTL: 1881 * - When disabling the CDCLK PLL, first set MDCLK source to be CD2XCLK. 1882 * - When enabling the CDCLK PLL, update MDCLK source selection only 1883 * after the PLL is enabled (which is already done as part of the 1884 * normal flow of _bxt_set_cdclk()). 1885 */ 1886 if (intel_display_wa(display, INTEL_DISPLAY_WA_13012396614)) 1887 intel_de_rmw(display, CDCLK_CTL, MDCLK_SOURCE_SEL_MASK, MDCLK_SOURCE_SEL_CD2XCLK); 1888 1889 intel_de_rmw(display, BXT_DE_PLL_ENABLE, 1890 BXT_DE_PLL_PLL_ENABLE, 0); 1891 1892 /* Timeout 200us */ 1893 if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1894 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); 1895 1896 display->cdclk.hw.vco = 0; 1897 } 1898 1899 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) 1900 { 1901 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1902 u32 val; 1903 1904 val = ICL_CDCLK_PLL_RATIO(ratio); 1905 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1906 1907 val |= BXT_DE_PLL_PLL_ENABLE; 1908 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1909 1910 /* Timeout 200us */ 1911 if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1912 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); 1913 1914 display->cdclk.hw.vco = vco; 1915 } 1916 1917 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) 1918 { 1919 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1920 u32 val; 1921 1922 /* Write PLL ratio without disabling */ 1923 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1924 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1925 1926 /* Submit freq change request */ 1927 val |= BXT_DE_PLL_FREQ_REQ; 1928 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1929 1930 /* Timeout 200us */ 1931 if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, 1932 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1933 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); 1934 1935 val &= ~BXT_DE_PLL_FREQ_REQ; 1936 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1937 1938 display->cdclk.hw.vco = vco; 1939 } 1940 1941 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) 1942 { 1943 if (DISPLAY_VER(display) >= 12) { 1944 if (pipe == INVALID_PIPE) 1945 return TGL_CDCLK_CD2X_PIPE_NONE; 1946 else 1947 return TGL_CDCLK_CD2X_PIPE(pipe); 1948 } else if (DISPLAY_VER(display) >= 11) { 1949 if (pipe == INVALID_PIPE) 1950 return ICL_CDCLK_CD2X_PIPE_NONE; 1951 else 1952 return ICL_CDCLK_CD2X_PIPE(pipe); 1953 } else { 1954 if (pipe == INVALID_PIPE) 1955 return BXT_CDCLK_CD2X_PIPE_NONE; 1956 else 1957 return BXT_CDCLK_CD2X_PIPE(pipe); 1958 } 1959 } 1960 1961 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, 1962 int cdclk, int vco, u16 waveform) 1963 { 1964 u32 ret; 1965 1966 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1967 switch (cdclk_divider(cdclk, vco, waveform)) { 1968 default: 1969 drm_WARN_ON(display->drm, 1970 cdclk != display->cdclk.hw.bypass); 1971 drm_WARN_ON(display->drm, vco != 0); 1972 fallthrough; 1973 case 2: 1974 ret = BXT_CDCLK_CD2X_DIV_SEL_1; 1975 break; 1976 case 3: 1977 ret = BXT_CDCLK_CD2X_DIV_SEL_1_5; 1978 break; 1979 case 4: 1980 ret = BXT_CDCLK_CD2X_DIV_SEL_2; 1981 break; 1982 case 8: 1983 ret = BXT_CDCLK_CD2X_DIV_SEL_4; 1984 break; 1985 } 1986 1987 /* 1988 * On Xe3_LPD onward, the expectation is to always have 1989 * BXT_CDCLK_CD2X_DIV_SEL_1 as the default. 1990 */ 1991 if (DISPLAY_VER(display) >= 30) 1992 drm_WARN_ON(display->drm, ret != BXT_CDCLK_CD2X_DIV_SEL_1); 1993 1994 return ret; 1995 } 1996 1997 static u16 cdclk_squash_waveform(struct intel_display *display, 1998 int cdclk) 1999 { 2000 const struct intel_cdclk_vals *table = display->cdclk.table; 2001 int i; 2002 2003 if (cdclk == display->cdclk.hw.bypass) 2004 return 0; 2005 2006 for (i = 0; table[i].refclk; i++) 2007 if (table[i].refclk == display->cdclk.hw.ref && 2008 table[i].cdclk == cdclk) 2009 return table[i].waveform; 2010 2011 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 2012 cdclk, display->cdclk.hw.ref); 2013 2014 return 0xffff; 2015 } 2016 2017 static void icl_cdclk_pll_update(struct intel_display *display, int vco) 2018 { 2019 if (display->cdclk.hw.vco != 0 && 2020 display->cdclk.hw.vco != vco) 2021 icl_cdclk_pll_disable(display); 2022 2023 if (display->cdclk.hw.vco != vco) 2024 icl_cdclk_pll_enable(display, vco); 2025 } 2026 2027 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) 2028 { 2029 if (display->cdclk.hw.vco != 0 && 2030 display->cdclk.hw.vco != vco) 2031 bxt_de_pll_disable(display); 2032 2033 if (display->cdclk.hw.vco != vco) 2034 bxt_de_pll_enable(display, vco); 2035 } 2036 2037 static void dg2_cdclk_squash_program(struct intel_display *display, 2038 u16 waveform) 2039 { 2040 u32 squash_ctl = 0; 2041 2042 if (waveform) 2043 squash_ctl = CDCLK_SQUASH_ENABLE | 2044 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 2045 2046 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); 2047 } 2048 2049 static bool cdclk_pll_is_unknown(unsigned int vco) 2050 { 2051 /* 2052 * Ensure driver does not take the crawl path for the 2053 * case when the vco is set to ~0 in the 2054 * sanitize path. 2055 */ 2056 return vco == ~0; 2057 } 2058 2059 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) 2060 { 2061 return DISPLAY_VER(display) >= 20; 2062 } 2063 2064 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) 2065 { 2066 if (mdclk_source_is_cdclk_pll(display)) 2067 return MDCLK_SOURCE_SEL_CDCLK_PLL; 2068 2069 return MDCLK_SOURCE_SEL_CD2XCLK; 2070 } 2071 2072 int intel_mdclk_cdclk_ratio(struct intel_display *display, 2073 const struct intel_cdclk_config *cdclk_config) 2074 { 2075 if (mdclk_source_is_cdclk_pll(display)) 2076 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); 2077 2078 /* Otherwise, source for MDCLK is CD2XCLK. */ 2079 return 2; 2080 } 2081 2082 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, 2083 const struct intel_cdclk_config *cdclk_config) 2084 { 2085 intel_dbuf_mdclk_cdclk_ratio_update(display, 2086 intel_mdclk_cdclk_ratio(display, cdclk_config), 2087 cdclk_config->joined_mbus); 2088 } 2089 2090 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, 2091 const struct intel_cdclk_config *old_cdclk_config, 2092 const struct intel_cdclk_config *new_cdclk_config, 2093 struct intel_cdclk_config *mid_cdclk_config) 2094 { 2095 u16 old_waveform, new_waveform, mid_waveform; 2096 int old_div, new_div, mid_div; 2097 2098 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 2099 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 2100 return false; 2101 2102 /* Return if both Squash and Crawl are not present */ 2103 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2104 return false; 2105 2106 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); 2107 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); 2108 2109 /* Return if Squash only or Crawl only is the desired action */ 2110 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 2111 old_cdclk_config->vco == new_cdclk_config->vco || 2112 old_waveform == new_waveform) 2113 return false; 2114 2115 old_div = cdclk_divider(old_cdclk_config->cdclk, 2116 old_cdclk_config->vco, old_waveform); 2117 new_div = cdclk_divider(new_cdclk_config->cdclk, 2118 new_cdclk_config->vco, new_waveform); 2119 2120 /* 2121 * Should not happen currently. We might need more midpoint 2122 * transitions if we need to also change the cd2x divider. 2123 */ 2124 if (drm_WARN_ON(display->drm, old_div != new_div)) 2125 return false; 2126 2127 *mid_cdclk_config = *new_cdclk_config; 2128 2129 /* 2130 * Populate the mid_cdclk_config accordingly. 2131 * - If moving to a higher cdclk, the desired action is squashing. 2132 * The mid cdclk config should have the new (squash) waveform. 2133 * - If moving to a lower cdclk, the desired action is crawling. 2134 * The mid cdclk config should have the new vco. 2135 */ 2136 2137 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 2138 mid_cdclk_config->vco = old_cdclk_config->vco; 2139 mid_div = old_div; 2140 mid_waveform = new_waveform; 2141 } else { 2142 mid_cdclk_config->vco = new_cdclk_config->vco; 2143 mid_div = new_div; 2144 mid_waveform = old_waveform; 2145 } 2146 2147 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 2148 mid_cdclk_config->vco, 2149 cdclk_squash_len * mid_div); 2150 2151 /* make sure the mid clock came out sane */ 2152 2153 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < 2154 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 2155 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > 2156 display->cdclk.max_cdclk_freq); 2157 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != 2158 mid_waveform); 2159 2160 return true; 2161 } 2162 2163 static bool pll_enable_wa_needed(struct intel_display *display) 2164 { 2165 return (DISPLAY_VERx100(display) == 2000 || 2166 DISPLAY_VERx100(display) == 1400 || 2167 display->platform.dg2) && 2168 display->cdclk.hw.vco > 0; 2169 } 2170 2171 static u32 bxt_cdclk_ctl(struct intel_display *display, 2172 const struct intel_cdclk_config *cdclk_config, 2173 enum pipe pipe) 2174 { 2175 int cdclk = cdclk_config->cdclk; 2176 int vco = cdclk_config->vco; 2177 u16 waveform; 2178 u32 val; 2179 2180 waveform = cdclk_squash_waveform(display, cdclk); 2181 2182 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform); 2183 2184 if (DISPLAY_VER(display) < 30) 2185 val |= bxt_cdclk_cd2x_pipe(display, pipe); 2186 2187 /* 2188 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2189 * enable otherwise. 2190 */ 2191 if ((display->platform.geminilake || display->platform.broxton) && 2192 cdclk >= 500000) 2193 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2194 2195 if (DISPLAY_VER(display) >= 20) { 2196 /* 2197 * Wa_13012396614 requires selecting CD2XCLK as MDCLK source 2198 * prior to disabling the PLL, which is already handled by 2199 * icl_cdclk_pll_disable(). Here we are just making sure 2200 * we keep the expected value. 2201 */ 2202 if (intel_display_wa(display, INTEL_DISPLAY_WA_13012396614) && 2203 vco == 0) 2204 val |= MDCLK_SOURCE_SEL_CD2XCLK; 2205 else 2206 val |= xe2lpd_mdclk_source_sel(display); 2207 } else { 2208 val |= skl_cdclk_decimal(cdclk); 2209 } 2210 2211 return val; 2212 } 2213 2214 static void _bxt_set_cdclk(struct intel_display *display, 2215 const struct intel_cdclk_config *cdclk_config, 2216 enum pipe pipe) 2217 { 2218 int cdclk = cdclk_config->cdclk; 2219 int vco = cdclk_config->vco; 2220 2221 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && 2222 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { 2223 if (display->cdclk.hw.vco != vco) 2224 adlp_cdclk_pll_crawl(display, vco); 2225 } else if (DISPLAY_VER(display) >= 11) { 2226 /* wa_15010685871: dg2, mtl */ 2227 if (pll_enable_wa_needed(display)) 2228 dg2_cdclk_squash_program(display, 0); 2229 2230 icl_cdclk_pll_update(display, vco); 2231 } else { 2232 bxt_cdclk_pll_update(display, vco); 2233 } 2234 2235 if (HAS_CDCLK_SQUASH(display)) { 2236 u16 waveform = cdclk_squash_waveform(display, cdclk); 2237 2238 dg2_cdclk_squash_program(display, waveform); 2239 } 2240 2241 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); 2242 2243 if (pipe != INVALID_PIPE) 2244 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 2245 } 2246 2247 static void bxt_set_cdclk(struct intel_display *display, 2248 const struct intel_cdclk_config *cdclk_config, 2249 enum pipe pipe) 2250 { 2251 struct intel_cdclk_config mid_cdclk_config; 2252 int cdclk = cdclk_config->cdclk; 2253 int ret = 0; 2254 2255 /* 2256 * Inform power controller of upcoming frequency change. 2257 * Display versions 14 and beyond do not follow the PUnit 2258 * mailbox communication, skip 2259 * this step. 2260 */ 2261 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) 2262 ; /* NOOP */ 2263 else if (DISPLAY_VER(display) >= 11) 2264 ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL, 2265 SKL_CDCLK_PREPARE_FOR_CHANGE, 2266 SKL_CDCLK_READY_FOR_CHANGE, 2267 SKL_CDCLK_READY_FOR_CHANGE, 3); 2268 else 2269 /* 2270 * BSpec requires us to wait up to 150usec, but that leads to 2271 * timeouts; the 2ms used here is based on experiment. 2272 */ 2273 ret = intel_parent_pcode_write_timeout(display, 2274 HSW_PCODE_DE_WRITE_FREQ_REQ, 2275 0x80000000, 2); 2276 2277 if (ret) { 2278 drm_err(display->drm, 2279 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 2280 ret, cdclk); 2281 return; 2282 } 2283 2284 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) 2285 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2286 2287 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, 2288 cdclk_config, &mid_cdclk_config)) { 2289 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); 2290 _bxt_set_cdclk(display, cdclk_config, pipe); 2291 } else { 2292 _bxt_set_cdclk(display, cdclk_config, pipe); 2293 } 2294 2295 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) 2296 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2297 2298 if (DISPLAY_VER(display) >= 14) 2299 /* 2300 * NOOP - No Pcode communication needed for 2301 * Display versions 14 and beyond 2302 */; 2303 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) 2304 ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL, 2305 cdclk_config->voltage_level); 2306 if (DISPLAY_VER(display) < 11) { 2307 /* 2308 * The timeout isn't specified, the 2ms used here is based on 2309 * experiment. 2310 * FIXME: Waiting for the request completion could be delayed 2311 * until the next PCODE request based on BSpec. 2312 */ 2313 ret = intel_parent_pcode_write_timeout(display, 2314 HSW_PCODE_DE_WRITE_FREQ_REQ, 2315 cdclk_config->voltage_level, 2); 2316 } 2317 if (ret) { 2318 drm_err(display->drm, 2319 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2320 ret, cdclk); 2321 return; 2322 } 2323 2324 intel_update_cdclk(display); 2325 2326 if (DISPLAY_VER(display) >= 11) 2327 /* 2328 * Can't read out the voltage level :( 2329 * Let's just assume everything is as expected. 2330 */ 2331 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; 2332 } 2333 2334 static void bxt_sanitize_cdclk(struct intel_display *display) 2335 { 2336 u32 cdctl, expected; 2337 int cdclk, vco; 2338 2339 intel_update_cdclk(display); 2340 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 2341 2342 if (display->cdclk.hw.vco == 0 || 2343 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 2344 goto sanitize; 2345 2346 /* Make sure this is a legal cdclk value for the platform */ 2347 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); 2348 if (cdclk != display->cdclk.hw.cdclk) 2349 goto sanitize; 2350 2351 /* Make sure the VCO is correct for the cdclk */ 2352 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 2353 if (vco != display->cdclk.hw.vco) 2354 goto sanitize; 2355 2356 /* 2357 * Some BIOS versions leave an incorrect decimal frequency value and 2358 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2359 * so sanitize this register. 2360 */ 2361 cdctl = intel_de_read(display, CDCLK_CTL); 2362 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); 2363 2364 /* 2365 * Let's ignore the pipe field, since BIOS could have configured the 2366 * dividers both syncing to an active pipe, or asynchronously 2367 * (PIPE_NONE). 2368 */ 2369 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2370 cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2371 2372 if (cdctl != expected) { 2373 if (DISPLAY_VER(display) < 20) { 2374 cdctl &= ~CDCLK_FREQ_DECIMAL_MASK; 2375 cdctl |= expected & CDCLK_FREQ_DECIMAL_MASK; 2376 } 2377 2378 if (cdctl != expected) 2379 goto sanitize; 2380 2381 drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n", 2382 intel_de_read(display, CDCLK_CTL), expected); 2383 2384 intel_de_write(display, CDCLK_CTL, expected); 2385 } 2386 2387 /* All well; nothing to sanitize */ 2388 return; 2389 2390 sanitize: 2391 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 2392 2393 /* force cdclk programming */ 2394 display->cdclk.hw.cdclk = 0; 2395 2396 /* force full PLL disable + enable */ 2397 display->cdclk.hw.vco = ~0; 2398 } 2399 2400 static void bxt_cdclk_init_hw(struct intel_display *display) 2401 { 2402 struct intel_cdclk_config cdclk_config; 2403 2404 bxt_sanitize_cdclk(display); 2405 2406 if (display->cdclk.hw.cdclk != 0 && 2407 display->cdclk.hw.vco != 0) 2408 return; 2409 2410 cdclk_config = display->cdclk.hw; 2411 2412 /* 2413 * FIXME: 2414 * - The initial CDCLK needs to be read from VBT. 2415 * Need to make this change after VBT has changes for BXT. 2416 */ 2417 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); 2418 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); 2419 cdclk_config.voltage_level = 2420 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2421 2422 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2423 } 2424 2425 static void bxt_cdclk_uninit_hw(struct intel_display *display) 2426 { 2427 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 2428 2429 cdclk_config.cdclk = cdclk_config.bypass; 2430 cdclk_config.vco = 0; 2431 cdclk_config.voltage_level = 2432 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2433 2434 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2435 } 2436 2437 /** 2438 * intel_cdclk_init_hw - Initialize CDCLK hardware 2439 * @display: display instance 2440 * 2441 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and 2442 * sanitizing the state of the hardware if needed. This is generally done only 2443 * during the display core initialization sequence, after which the DMC will 2444 * take care of turning CDCLK off/on as needed. 2445 */ 2446 void intel_cdclk_init_hw(struct intel_display *display) 2447 { 2448 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2449 bxt_cdclk_init_hw(display); 2450 else if (DISPLAY_VER(display) == 9) 2451 skl_cdclk_init_hw(display); 2452 } 2453 2454 /** 2455 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2456 * @display: display instance 2457 * 2458 * Uninitialize CDCLK. This is done only during the display core 2459 * uninitialization sequence. 2460 */ 2461 void intel_cdclk_uninit_hw(struct intel_display *display) 2462 { 2463 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2464 bxt_cdclk_uninit_hw(display); 2465 else if (DISPLAY_VER(display) == 9) 2466 skl_cdclk_uninit_hw(display); 2467 } 2468 2469 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, 2470 const struct intel_cdclk_config *a, 2471 const struct intel_cdclk_config *b) 2472 { 2473 u16 old_waveform; 2474 u16 new_waveform; 2475 2476 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); 2477 2478 if (a->vco == 0 || b->vco == 0) 2479 return false; 2480 2481 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2482 return false; 2483 2484 old_waveform = cdclk_squash_waveform(display, a->cdclk); 2485 new_waveform = cdclk_squash_waveform(display, b->cdclk); 2486 2487 return a->vco != b->vco && 2488 old_waveform != new_waveform; 2489 } 2490 2491 static bool intel_cdclk_can_crawl(struct intel_display *display, 2492 const struct intel_cdclk_config *a, 2493 const struct intel_cdclk_config *b) 2494 { 2495 int a_div, b_div; 2496 2497 if (!HAS_CDCLK_CRAWL(display)) 2498 return false; 2499 2500 /* 2501 * The vco and cd2x divider will change independently 2502 * from each, so we disallow cd2x change when crawling. 2503 */ 2504 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2505 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2506 2507 return a->vco != 0 && b->vco != 0 && 2508 a->vco != b->vco && 2509 a_div == b_div && 2510 a->ref == b->ref; 2511 } 2512 2513 static bool intel_cdclk_can_squash(struct intel_display *display, 2514 const struct intel_cdclk_config *a, 2515 const struct intel_cdclk_config *b) 2516 { 2517 /* 2518 * FIXME should store a bit more state in intel_cdclk_config 2519 * to differentiate squasher vs. cd2x divider properly. For 2520 * the moment all platforms with squasher use a fixed cd2x 2521 * divider. 2522 */ 2523 if (!HAS_CDCLK_SQUASH(display)) 2524 return false; 2525 2526 return a->cdclk != b->cdclk && 2527 a->vco != 0 && 2528 a->vco == b->vco && 2529 a->ref == b->ref; 2530 } 2531 2532 /** 2533 * intel_cdclk_clock_changed - Check whether the clock changed 2534 * @a: first CDCLK configuration 2535 * @b: second CDCLK configuration 2536 * 2537 * Returns: 2538 * True if CDCLK changed in a way that requires re-programming and 2539 * False otherwise. 2540 */ 2541 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 2542 const struct intel_cdclk_config *b) 2543 { 2544 return a->cdclk != b->cdclk || 2545 a->vco != b->vco || 2546 a->ref != b->ref; 2547 } 2548 2549 /** 2550 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2551 * configurations requires only a cd2x divider update 2552 * @display: display instance 2553 * @a: first CDCLK configuration 2554 * @b: second CDCLK configuration 2555 * 2556 * Returns: 2557 * True if changing between the two CDCLK configurations 2558 * can be done with just a cd2x divider update, false if not. 2559 */ 2560 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, 2561 const struct intel_cdclk_config *a, 2562 const struct intel_cdclk_config *b) 2563 { 2564 /* Older hw doesn't have the capability */ 2565 if (DISPLAY_VER(display) < 10 && !display->platform.broxton) 2566 return false; 2567 2568 /* 2569 * FIXME should store a bit more state in intel_cdclk_config 2570 * to differentiate squasher vs. cd2x divider properly. For 2571 * the moment all platforms with squasher use a fixed cd2x 2572 * divider. 2573 */ 2574 if (HAS_CDCLK_SQUASH(display)) 2575 return false; 2576 2577 return a->cdclk != b->cdclk && 2578 a->vco != 0 && 2579 a->vco == b->vco && 2580 a->ref == b->ref; 2581 } 2582 2583 /** 2584 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2585 * @a: first CDCLK configuration 2586 * @b: second CDCLK configuration 2587 * 2588 * Returns: 2589 * True if the CDCLK configurations don't match, false if they do. 2590 */ 2591 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2592 const struct intel_cdclk_config *b) 2593 { 2594 return intel_cdclk_clock_changed(a, b) || 2595 a->voltage_level != b->voltage_level; 2596 } 2597 2598 void intel_cdclk_dump_config(struct intel_display *display, 2599 const struct intel_cdclk_config *cdclk_config, 2600 const char *context) 2601 { 2602 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2603 context, cdclk_config->cdclk, cdclk_config->vco, 2604 cdclk_config->ref, cdclk_config->bypass, 2605 cdclk_config->voltage_level); 2606 } 2607 2608 static void intel_pcode_notify(struct intel_display *display, 2609 u8 voltage_level, 2610 u8 active_pipe_count, 2611 u16 cdclk, 2612 bool cdclk_update_valid, 2613 bool pipe_count_update_valid) 2614 { 2615 int ret; 2616 u32 update_mask = 0; 2617 2618 if (!display->platform.dg2) 2619 return; 2620 2621 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2622 2623 if (cdclk_update_valid) 2624 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2625 2626 if (pipe_count_update_valid) 2627 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2628 2629 ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL, 2630 SKL_CDCLK_PREPARE_FOR_CHANGE | 2631 update_mask, 2632 SKL_CDCLK_READY_FOR_CHANGE, 2633 SKL_CDCLK_READY_FOR_CHANGE, 3); 2634 if (ret) 2635 drm_err(display->drm, 2636 "Failed to inform PCU about display config (err %d)\n", 2637 ret); 2638 } 2639 2640 static void intel_set_cdclk(struct intel_display *display, 2641 const struct intel_cdclk_config *cdclk_config, 2642 enum pipe pipe, const char *context) 2643 { 2644 struct intel_encoder *encoder; 2645 2646 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) 2647 return; 2648 2649 if (drm_WARN_ON_ONCE(display->drm, !display->cdclk.funcs->set_cdclk)) 2650 return; 2651 2652 intel_cdclk_dump_config(display, cdclk_config, context); 2653 2654 for_each_intel_encoder_with_psr(display->drm, encoder) { 2655 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2656 2657 intel_psr_pause(intel_dp); 2658 } 2659 2660 intel_audio_cdclk_change_pre(display); 2661 2662 /* 2663 * Lock aux/gmbus while we change cdclk in case those 2664 * functions use cdclk. Not all platforms/ports do, 2665 * but we'll lock them all for simplicity. 2666 */ 2667 mutex_lock(&display->gmbus.mutex); 2668 for_each_intel_dp(display->drm, encoder) { 2669 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2670 2671 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2672 &display->gmbus.mutex); 2673 } 2674 2675 intel_cdclk_set_cdclk(display, cdclk_config, pipe); 2676 2677 for_each_intel_dp(display->drm, encoder) { 2678 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2679 2680 mutex_unlock(&intel_dp->aux.hw_mutex); 2681 } 2682 mutex_unlock(&display->gmbus.mutex); 2683 2684 for_each_intel_encoder_with_psr(display->drm, encoder) { 2685 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2686 2687 intel_psr_resume(intel_dp); 2688 } 2689 2690 intel_audio_cdclk_change_post(display); 2691 2692 if (drm_WARN(display->drm, 2693 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), 2694 "cdclk state doesn't match!\n")) { 2695 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); 2696 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); 2697 } 2698 } 2699 2700 static bool dg2_power_well_count(struct intel_display *display, 2701 const struct intel_cdclk_state *cdclk_state) 2702 { 2703 return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0; 2704 } 2705 2706 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2707 { 2708 struct intel_display *display = to_intel_display(state); 2709 const struct intel_cdclk_state *old_cdclk_state = 2710 intel_atomic_get_old_cdclk_state(state); 2711 const struct intel_cdclk_state *new_cdclk_state = 2712 intel_atomic_get_new_cdclk_state(state); 2713 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2714 bool change_cdclk, update_pipe_count; 2715 2716 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2717 &new_cdclk_state->actual) && 2718 dg2_power_well_count(display, old_cdclk_state) == 2719 dg2_power_well_count(display, new_cdclk_state)) 2720 return; 2721 2722 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2723 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2724 2725 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2726 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) > 2727 dg2_power_well_count(display, old_cdclk_state); 2728 2729 /* 2730 * According to "Sequence Before Frequency Change", 2731 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2732 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2733 * which basically means we choose the maximum of old and new CDCLK, if we know both 2734 */ 2735 if (change_cdclk) 2736 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2737 2738 /* 2739 * According to "Sequence For Pipe Count Change", 2740 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2741 * (power well is enabled) 2742 * no action if it is decreasing, before the change 2743 */ 2744 if (update_pipe_count) 2745 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); 2746 2747 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2748 change_cdclk, update_pipe_count); 2749 } 2750 2751 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2752 { 2753 struct intel_display *display = to_intel_display(state); 2754 const struct intel_cdclk_state *new_cdclk_state = 2755 intel_atomic_get_new_cdclk_state(state); 2756 const struct intel_cdclk_state *old_cdclk_state = 2757 intel_atomic_get_old_cdclk_state(state); 2758 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2759 bool update_cdclk, update_pipe_count; 2760 2761 /* According to "Sequence After Frequency Change", set voltage to used level */ 2762 voltage_level = new_cdclk_state->actual.voltage_level; 2763 2764 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2765 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) < 2766 dg2_power_well_count(display, old_cdclk_state); 2767 2768 /* 2769 * According to "Sequence After Frequency Change", 2770 * set bits 25:16 to current CDCLK 2771 */ 2772 if (update_cdclk) 2773 cdclk = new_cdclk_state->actual.cdclk; 2774 2775 /* 2776 * According to "Sequence For Pipe Count Change", 2777 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2778 * after the change(power well is disabled) 2779 * no action if it is increasing, after the change 2780 */ 2781 if (update_pipe_count) 2782 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); 2783 2784 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2785 update_cdclk, update_pipe_count); 2786 } 2787 2788 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) 2789 { 2790 const struct intel_cdclk_state *old_cdclk_state = 2791 intel_atomic_get_old_cdclk_state(state); 2792 const struct intel_cdclk_state *new_cdclk_state = 2793 intel_atomic_get_new_cdclk_state(state); 2794 2795 return new_cdclk_state && !new_cdclk_state->disable_pipes && 2796 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; 2797 } 2798 2799 /** 2800 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2801 * @state: intel atomic state 2802 * 2803 * Program the hardware before updating the HW plane state based on the 2804 * new CDCLK state, if necessary. 2805 */ 2806 void 2807 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2808 { 2809 struct intel_display *display = to_intel_display(state); 2810 const struct intel_cdclk_state *old_cdclk_state = 2811 intel_atomic_get_old_cdclk_state(state); 2812 const struct intel_cdclk_state *new_cdclk_state = 2813 intel_atomic_get_new_cdclk_state(state); 2814 struct intel_cdclk_config cdclk_config; 2815 enum pipe pipe; 2816 2817 if (!new_cdclk_state) 2818 return; 2819 2820 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2821 &new_cdclk_state->actual)) 2822 return; 2823 2824 if (display->platform.dg2) 2825 intel_cdclk_pcode_pre_notify(state); 2826 2827 if (new_cdclk_state->disable_pipes) { 2828 cdclk_config = new_cdclk_state->actual; 2829 pipe = INVALID_PIPE; 2830 } else { 2831 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { 2832 cdclk_config = new_cdclk_state->actual; 2833 pipe = new_cdclk_state->pipe; 2834 } else { 2835 cdclk_config = old_cdclk_state->actual; 2836 pipe = INVALID_PIPE; 2837 } 2838 2839 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, 2840 old_cdclk_state->actual.voltage_level); 2841 } 2842 2843 /* 2844 * mbus joining will be changed later by 2845 * intel_dbuf_mbus_{pre,post}_ddb_update() 2846 */ 2847 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; 2848 2849 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2850 2851 intel_set_cdclk(display, &cdclk_config, pipe, 2852 "Pre changing CDCLK to"); 2853 } 2854 2855 /** 2856 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2857 * @state: intel atomic state 2858 * 2859 * Program the hardware after updating the HW plane state based on the 2860 * new CDCLK state, if necessary. 2861 */ 2862 void 2863 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2864 { 2865 struct intel_display *display = to_intel_display(state); 2866 const struct intel_cdclk_state *old_cdclk_state = 2867 intel_atomic_get_old_cdclk_state(state); 2868 const struct intel_cdclk_state *new_cdclk_state = 2869 intel_atomic_get_new_cdclk_state(state); 2870 enum pipe pipe; 2871 2872 if (!new_cdclk_state) 2873 return; 2874 2875 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2876 &new_cdclk_state->actual)) 2877 return; 2878 2879 if (display->platform.dg2) 2880 intel_cdclk_pcode_post_notify(state); 2881 2882 if (!new_cdclk_state->disable_pipes && 2883 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) 2884 pipe = new_cdclk_state->pipe; 2885 else 2886 pipe = INVALID_PIPE; 2887 2888 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2889 2890 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, 2891 "Post changing CDCLK to"); 2892 } 2893 2894 /* pixels per CDCLK */ 2895 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) 2896 { 2897 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; 2898 } 2899 2900 /* max pixel rate as % of CDCLK (not accounting for PPC) */ 2901 static int intel_cdclk_guardband(struct intel_display *display) 2902 { 2903 if (DISPLAY_VER(display) >= 9 || 2904 display->platform.broadwell || display->platform.haswell) 2905 return 100; 2906 else if (display->platform.cherryview) 2907 return 95; 2908 else 2909 return 90; 2910 } 2911 2912 static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate) 2913 { 2914 struct intel_display *display = to_intel_display(crtc_state); 2915 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 2916 int guardband = intel_cdclk_guardband(display); 2917 2918 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); 2919 } 2920 2921 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2922 { 2923 return _intel_pixel_rate_to_cdclk(crtc_state, crtc_state->pixel_rate); 2924 } 2925 2926 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2927 { 2928 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2929 struct intel_display *display = to_intel_display(crtc); 2930 struct intel_plane *plane; 2931 int min_cdclk = 0; 2932 2933 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 2934 min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]); 2935 2936 return min_cdclk; 2937 } 2938 2939 int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state) 2940 { 2941 int min_cdclk; 2942 2943 if (!crtc_state->hw.enable) 2944 return 0; 2945 2946 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2947 min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state)); 2948 min_cdclk = max(min_cdclk, intel_fbc_min_cdclk(crtc_state)); 2949 min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state)); 2950 min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state)); 2951 min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); 2952 min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state)); 2953 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2954 2955 return min_cdclk; 2956 } 2957 2958 static int intel_cdclk_update_crtc_min_cdclk(struct intel_atomic_state *state, 2959 struct intel_crtc *crtc, 2960 int old_min_cdclk, int new_min_cdclk, 2961 bool *need_cdclk_calc) 2962 { 2963 struct intel_display *display = to_intel_display(state); 2964 struct intel_cdclk_state *cdclk_state; 2965 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state); 2966 int ret; 2967 2968 if (new_min_cdclk == old_min_cdclk) 2969 return 0; 2970 2971 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 2972 return 0; 2973 2974 cdclk_state = intel_atomic_get_cdclk_state(state); 2975 if (IS_ERR(cdclk_state)) 2976 return PTR_ERR(cdclk_state); 2977 2978 old_min_cdclk = cdclk_state->min_cdclk[crtc->pipe]; 2979 2980 if (new_min_cdclk == old_min_cdclk) 2981 return 0; 2982 2983 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 2984 return 0; 2985 2986 cdclk_state->min_cdclk[crtc->pipe] = new_min_cdclk; 2987 2988 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2989 if (ret) 2990 return ret; 2991 2992 *need_cdclk_calc = true; 2993 2994 drm_dbg_kms(display->drm, 2995 "[CRTC:%d:%s] min cdclk: %d kHz -> %d kHz\n", 2996 crtc->base.base.id, crtc->base.name, 2997 old_min_cdclk, new_min_cdclk); 2998 2999 return 0; 3000 } 3001 3002 static int intel_cdclk_update_crtc_min_voltage_level(struct intel_atomic_state *state, 3003 struct intel_crtc *crtc, 3004 u8 old_min_voltage_level, 3005 u8 new_min_voltage_level, 3006 bool *need_cdclk_calc) 3007 { 3008 struct intel_display *display = to_intel_display(state); 3009 struct intel_cdclk_state *cdclk_state; 3010 bool allow_voltage_level_decrease = intel_any_crtc_needs_modeset(state); 3011 int ret; 3012 3013 if (new_min_voltage_level == old_min_voltage_level) 3014 return 0; 3015 3016 if (!allow_voltage_level_decrease && 3017 new_min_voltage_level < old_min_voltage_level) 3018 return 0; 3019 3020 cdclk_state = intel_atomic_get_cdclk_state(state); 3021 if (IS_ERR(cdclk_state)) 3022 return PTR_ERR(cdclk_state); 3023 3024 old_min_voltage_level = cdclk_state->min_voltage_level[crtc->pipe]; 3025 3026 if (new_min_voltage_level == old_min_voltage_level) 3027 return 0; 3028 3029 if (!allow_voltage_level_decrease && 3030 new_min_voltage_level < old_min_voltage_level) 3031 return 0; 3032 3033 cdclk_state->min_voltage_level[crtc->pipe] = new_min_voltage_level; 3034 3035 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3036 if (ret) 3037 return ret; 3038 3039 *need_cdclk_calc = true; 3040 3041 drm_dbg_kms(display->drm, 3042 "[CRTC:%d:%s] min voltage level: %d -> %d\n", 3043 crtc->base.base.id, crtc->base.name, 3044 old_min_voltage_level, new_min_voltage_level); 3045 3046 return 0; 3047 } 3048 3049 int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state, 3050 int old_min_cdclk, int new_min_cdclk, 3051 bool *need_cdclk_calc) 3052 { 3053 struct intel_display *display = to_intel_display(state); 3054 struct intel_cdclk_state *cdclk_state; 3055 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state); 3056 int ret; 3057 3058 if (new_min_cdclk == old_min_cdclk) 3059 return 0; 3060 3061 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 3062 return 0; 3063 3064 cdclk_state = intel_atomic_get_cdclk_state(state); 3065 if (IS_ERR(cdclk_state)) 3066 return PTR_ERR(cdclk_state); 3067 3068 old_min_cdclk = cdclk_state->dbuf_bw_min_cdclk; 3069 3070 if (new_min_cdclk == old_min_cdclk) 3071 return 0; 3072 3073 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 3074 return 0; 3075 3076 cdclk_state->dbuf_bw_min_cdclk = new_min_cdclk; 3077 3078 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3079 if (ret) 3080 return ret; 3081 3082 *need_cdclk_calc = true; 3083 3084 drm_dbg_kms(display->drm, 3085 "dbuf bandwidth min cdclk: %d kHz -> %d kHz\n", 3086 old_min_cdclk, new_min_cdclk); 3087 3088 return 0; 3089 } 3090 3091 static bool glk_cdclk_audio_wa_needed(struct intel_display *display, 3092 const struct intel_cdclk_state *cdclk_state) 3093 { 3094 return display->platform.geminilake && 3095 cdclk_state->enabled_pipes && 3096 !is_power_of_2(cdclk_state->enabled_pipes); 3097 } 3098 3099 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 3100 { 3101 struct intel_display *display = to_intel_display(state); 3102 struct intel_cdclk_state *cdclk_state = 3103 intel_atomic_get_new_cdclk_state(state); 3104 enum pipe pipe; 3105 int min_cdclk; 3106 3107 min_cdclk = cdclk_state->force_min_cdclk; 3108 min_cdclk = max(min_cdclk, cdclk_state->dbuf_bw_min_cdclk); 3109 for_each_pipe(display, pipe) 3110 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); 3111 3112 /* 3113 * Avoid glk_force_audio_cdclk() causing excessive screen 3114 * blinking when multiple pipes are active by making sure 3115 * CDCLK frequency is always high enough for audio. With a 3116 * single active pipe we can always change CDCLK frequency 3117 * by changing the cd2x divider (see glk_cdclk_table[]) and 3118 * thus a full modeset won't be needed then. 3119 */ 3120 if (glk_cdclk_audio_wa_needed(display, cdclk_state)) 3121 min_cdclk = max(min_cdclk, 2 * 96000); 3122 3123 if (min_cdclk > display->cdclk.max_cdclk_freq) { 3124 drm_dbg_kms(display->drm, 3125 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 3126 min_cdclk, display->cdclk.max_cdclk_freq); 3127 return -EINVAL; 3128 } 3129 3130 return min_cdclk; 3131 } 3132 3133 /* 3134 * Account for port clock min voltage level requirements. 3135 * This only really does something on DISPLA_VER >= 11 but can be 3136 * called on earlier platforms as well. 3137 * 3138 * Note that this functions assumes that 0 is 3139 * the lowest voltage value, and higher values 3140 * correspond to increasingly higher voltages. 3141 * 3142 * Should that relationship no longer hold on 3143 * future platforms this code will need to be 3144 * adjusted. 3145 */ 3146 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 3147 { 3148 struct intel_display *display = to_intel_display(state); 3149 struct intel_cdclk_state *cdclk_state = 3150 intel_atomic_get_new_cdclk_state(state); 3151 struct intel_crtc *crtc; 3152 struct intel_crtc_state *crtc_state; 3153 u8 min_voltage_level; 3154 enum pipe pipe; 3155 3156 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 3157 int ret; 3158 3159 if (crtc_state->hw.enable) 3160 min_voltage_level = crtc_state->min_voltage_level; 3161 else 3162 min_voltage_level = 0; 3163 3164 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 3165 continue; 3166 3167 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 3168 3169 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3170 if (ret) 3171 return ret; 3172 } 3173 3174 min_voltage_level = 0; 3175 for_each_pipe(display, pipe) 3176 min_voltage_level = max(min_voltage_level, 3177 cdclk_state->min_voltage_level[pipe]); 3178 3179 return min_voltage_level; 3180 } 3181 3182 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 3183 { 3184 struct intel_display *display = to_intel_display(state); 3185 struct intel_cdclk_state *cdclk_state = 3186 intel_atomic_get_new_cdclk_state(state); 3187 int min_cdclk, cdclk; 3188 3189 min_cdclk = intel_compute_min_cdclk(state); 3190 if (min_cdclk < 0) 3191 return min_cdclk; 3192 3193 cdclk = vlv_calc_cdclk(display, min_cdclk); 3194 3195 cdclk_state->logical.cdclk = cdclk; 3196 cdclk_state->logical.voltage_level = 3197 vlv_calc_voltage_level(display, cdclk); 3198 3199 if (!cdclk_state->active_pipes) { 3200 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); 3201 3202 cdclk_state->actual.cdclk = cdclk; 3203 cdclk_state->actual.voltage_level = 3204 vlv_calc_voltage_level(display, cdclk); 3205 } else { 3206 cdclk_state->actual = cdclk_state->logical; 3207 } 3208 3209 return 0; 3210 } 3211 3212 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 3213 { 3214 struct intel_cdclk_state *cdclk_state = 3215 intel_atomic_get_new_cdclk_state(state); 3216 int min_cdclk, cdclk; 3217 3218 min_cdclk = intel_compute_min_cdclk(state); 3219 if (min_cdclk < 0) 3220 return min_cdclk; 3221 3222 cdclk = bdw_calc_cdclk(min_cdclk); 3223 3224 cdclk_state->logical.cdclk = cdclk; 3225 cdclk_state->logical.voltage_level = 3226 bdw_calc_voltage_level(cdclk); 3227 3228 if (!cdclk_state->active_pipes) { 3229 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 3230 3231 cdclk_state->actual.cdclk = cdclk; 3232 cdclk_state->actual.voltage_level = 3233 bdw_calc_voltage_level(cdclk); 3234 } else { 3235 cdclk_state->actual = cdclk_state->logical; 3236 } 3237 3238 return 0; 3239 } 3240 3241 static int skl_dpll0_vco(struct intel_atomic_state *state) 3242 { 3243 struct intel_display *display = to_intel_display(state); 3244 struct intel_cdclk_state *cdclk_state = 3245 intel_atomic_get_new_cdclk_state(state); 3246 struct intel_crtc *crtc; 3247 struct intel_crtc_state *crtc_state; 3248 int vco; 3249 3250 vco = cdclk_state->logical.vco; 3251 if (!vco) 3252 vco = display->cdclk.skl_preferred_vco_freq; 3253 3254 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 3255 if (!crtc_state->hw.enable) 3256 continue; 3257 3258 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 3259 continue; 3260 3261 /* 3262 * DPLL0 VCO may need to be adjusted to get the correct 3263 * clock for eDP. This will affect cdclk as well. 3264 */ 3265 switch (crtc_state->port_clock / 2) { 3266 case 108000: 3267 case 216000: 3268 vco = 8640000; 3269 break; 3270 default: 3271 vco = 8100000; 3272 break; 3273 } 3274 } 3275 3276 return vco; 3277 } 3278 3279 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 3280 { 3281 struct intel_cdclk_state *cdclk_state = 3282 intel_atomic_get_new_cdclk_state(state); 3283 int min_cdclk, cdclk, vco; 3284 3285 min_cdclk = intel_compute_min_cdclk(state); 3286 if (min_cdclk < 0) 3287 return min_cdclk; 3288 3289 vco = skl_dpll0_vco(state); 3290 3291 cdclk = skl_calc_cdclk(min_cdclk, vco); 3292 3293 cdclk_state->logical.vco = vco; 3294 cdclk_state->logical.cdclk = cdclk; 3295 cdclk_state->logical.voltage_level = 3296 skl_calc_voltage_level(cdclk); 3297 3298 if (!cdclk_state->active_pipes) { 3299 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 3300 3301 cdclk_state->actual.vco = vco; 3302 cdclk_state->actual.cdclk = cdclk; 3303 cdclk_state->actual.voltage_level = 3304 skl_calc_voltage_level(cdclk); 3305 } else { 3306 cdclk_state->actual = cdclk_state->logical; 3307 } 3308 3309 return 0; 3310 } 3311 3312 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 3313 { 3314 struct intel_display *display = to_intel_display(state); 3315 struct intel_cdclk_state *cdclk_state = 3316 intel_atomic_get_new_cdclk_state(state); 3317 int min_cdclk, min_voltage_level, cdclk, vco; 3318 3319 min_cdclk = intel_compute_min_cdclk(state); 3320 if (min_cdclk < 0) 3321 return min_cdclk; 3322 3323 min_voltage_level = bxt_compute_min_voltage_level(state); 3324 if (min_voltage_level < 0) 3325 return min_voltage_level; 3326 3327 cdclk = bxt_calc_cdclk(display, min_cdclk); 3328 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3329 3330 cdclk_state->logical.vco = vco; 3331 cdclk_state->logical.cdclk = cdclk; 3332 cdclk_state->logical.voltage_level = 3333 max_t(int, min_voltage_level, 3334 intel_cdclk_calc_voltage_level(display, cdclk)); 3335 3336 if (!cdclk_state->active_pipes) { 3337 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); 3338 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3339 3340 cdclk_state->actual.vco = vco; 3341 cdclk_state->actual.cdclk = cdclk; 3342 cdclk_state->actual.voltage_level = 3343 intel_cdclk_calc_voltage_level(display, cdclk); 3344 } else { 3345 cdclk_state->actual = cdclk_state->logical; 3346 } 3347 3348 return 0; 3349 } 3350 3351 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) 3352 { 3353 int min_cdclk; 3354 3355 /* 3356 * We can't change the cdclk frequency, but we still want to 3357 * check that the required minimum frequency doesn't exceed 3358 * the actual cdclk frequency. 3359 */ 3360 min_cdclk = intel_compute_min_cdclk(state); 3361 if (min_cdclk < 0) 3362 return min_cdclk; 3363 3364 return 0; 3365 } 3366 3367 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3368 { 3369 struct intel_cdclk_state *cdclk_state; 3370 3371 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3372 if (!cdclk_state) 3373 return NULL; 3374 3375 cdclk_state->pipe = INVALID_PIPE; 3376 cdclk_state->disable_pipes = false; 3377 3378 return &cdclk_state->base; 3379 } 3380 3381 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3382 struct intel_global_state *state) 3383 { 3384 kfree(state); 3385 } 3386 3387 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3388 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3389 .atomic_destroy_state = intel_cdclk_destroy_state, 3390 }; 3391 3392 struct intel_cdclk_state * 3393 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3394 { 3395 struct intel_display *display = to_intel_display(state); 3396 struct intel_global_state *cdclk_state; 3397 3398 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); 3399 if (IS_ERR(cdclk_state)) 3400 return ERR_CAST(cdclk_state); 3401 3402 return to_intel_cdclk_state(cdclk_state); 3403 } 3404 3405 static int intel_cdclk_modeset_checks(struct intel_atomic_state *state, 3406 bool *need_cdclk_calc) 3407 { 3408 struct intel_display *display = to_intel_display(state); 3409 const struct intel_cdclk_state *old_cdclk_state; 3410 struct intel_cdclk_state *new_cdclk_state; 3411 int ret; 3412 3413 if (!intel_any_crtc_enable_changed(state) && 3414 !intel_any_crtc_active_changed(state)) 3415 return 0; 3416 3417 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3418 if (IS_ERR(new_cdclk_state)) 3419 return PTR_ERR(new_cdclk_state); 3420 3421 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3422 3423 new_cdclk_state->enabled_pipes = 3424 intel_calc_enabled_pipes(state, old_cdclk_state->enabled_pipes); 3425 3426 new_cdclk_state->active_pipes = 3427 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3428 3429 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3430 if (ret) 3431 return ret; 3432 3433 if (!old_cdclk_state->active_pipes != !new_cdclk_state->active_pipes) 3434 *need_cdclk_calc = true; 3435 3436 if (glk_cdclk_audio_wa_needed(display, old_cdclk_state) != 3437 glk_cdclk_audio_wa_needed(display, new_cdclk_state)) 3438 *need_cdclk_calc = true; 3439 3440 if (dg2_power_well_count(display, old_cdclk_state) != 3441 dg2_power_well_count(display, new_cdclk_state)) 3442 *need_cdclk_calc = true; 3443 3444 return 0; 3445 } 3446 3447 static int intel_crtcs_calc_min_cdclk(struct intel_atomic_state *state, 3448 bool *need_cdclk_calc) 3449 { 3450 const struct intel_crtc_state *old_crtc_state; 3451 const struct intel_crtc_state *new_crtc_state; 3452 struct intel_crtc *crtc; 3453 int ret; 3454 3455 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 3456 ret = intel_cdclk_update_crtc_min_cdclk(state, crtc, 3457 old_crtc_state->min_cdclk, 3458 new_crtc_state->min_cdclk, 3459 need_cdclk_calc); 3460 if (ret) 3461 return ret; 3462 3463 ret = intel_cdclk_update_crtc_min_voltage_level(state, crtc, 3464 old_crtc_state->min_voltage_level, 3465 new_crtc_state->min_voltage_level, 3466 need_cdclk_calc); 3467 if (ret) 3468 return ret; 3469 } 3470 3471 return 0; 3472 } 3473 3474 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) 3475 { 3476 struct intel_cdclk_state *cdclk_state; 3477 3478 cdclk_state = intel_atomic_get_cdclk_state(state); 3479 if (IS_ERR(cdclk_state)) 3480 return PTR_ERR(cdclk_state); 3481 3482 cdclk_state->actual.joined_mbus = joined_mbus; 3483 cdclk_state->logical.joined_mbus = joined_mbus; 3484 3485 return intel_atomic_lock_global_state(&cdclk_state->base); 3486 } 3487 3488 int intel_cdclk_init(struct intel_display *display) 3489 { 3490 struct intel_cdclk_state *cdclk_state; 3491 3492 cdclk_state = kzalloc_obj(*cdclk_state); 3493 if (!cdclk_state) 3494 return -ENOMEM; 3495 3496 intel_atomic_global_obj_init(display, &display->cdclk.obj, 3497 &cdclk_state->base, &intel_cdclk_funcs); 3498 3499 return 0; 3500 } 3501 3502 static bool intel_cdclk_need_serialize(struct intel_display *display, 3503 const struct intel_cdclk_state *old_cdclk_state, 3504 const struct intel_cdclk_state *new_cdclk_state) 3505 { 3506 /* 3507 * We need to poke hw for DG2, because we notify PCode if 3508 * pipe power well count changes. 3509 */ 3510 return intel_cdclk_changed(&old_cdclk_state->actual, 3511 &new_cdclk_state->actual) || 3512 dg2_power_well_count(display, old_cdclk_state) != 3513 dg2_power_well_count(display, new_cdclk_state); 3514 } 3515 3516 static int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3517 { 3518 struct intel_display *display = to_intel_display(state); 3519 const struct intel_cdclk_state *old_cdclk_state; 3520 struct intel_cdclk_state *new_cdclk_state; 3521 enum pipe pipe = INVALID_PIPE; 3522 int ret; 3523 3524 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3525 if (IS_ERR(new_cdclk_state)) 3526 return PTR_ERR(new_cdclk_state); 3527 3528 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3529 3530 ret = intel_cdclk_modeset_calc_cdclk(state); 3531 if (ret) 3532 return ret; 3533 3534 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { 3535 /* 3536 * Also serialize commits across all crtcs 3537 * if the actual hw needs to be poked. 3538 */ 3539 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3540 if (ret) 3541 return ret; 3542 } else if (intel_cdclk_changed(&old_cdclk_state->logical, 3543 &new_cdclk_state->logical)) { 3544 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3545 if (ret) 3546 return ret; 3547 } else { 3548 return 0; 3549 } 3550 3551 if (is_power_of_2(new_cdclk_state->active_pipes) && 3552 intel_cdclk_can_cd2x_update(display, 3553 &old_cdclk_state->actual, 3554 &new_cdclk_state->actual)) { 3555 struct intel_crtc *crtc; 3556 struct intel_crtc_state *crtc_state; 3557 3558 pipe = ilog2(new_cdclk_state->active_pipes); 3559 crtc = intel_crtc_for_pipe(display, pipe); 3560 3561 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3562 if (IS_ERR(crtc_state)) 3563 return PTR_ERR(crtc_state); 3564 3565 if (intel_crtc_needs_modeset(crtc_state)) 3566 pipe = INVALID_PIPE; 3567 } 3568 3569 if (intel_cdclk_can_crawl_and_squash(display, 3570 &old_cdclk_state->actual, 3571 &new_cdclk_state->actual)) { 3572 drm_dbg_kms(display->drm, 3573 "Can change cdclk via crawling and squashing\n"); 3574 } else if (intel_cdclk_can_squash(display, 3575 &old_cdclk_state->actual, 3576 &new_cdclk_state->actual)) { 3577 drm_dbg_kms(display->drm, 3578 "Can change cdclk via squashing\n"); 3579 } else if (intel_cdclk_can_crawl(display, 3580 &old_cdclk_state->actual, 3581 &new_cdclk_state->actual)) { 3582 drm_dbg_kms(display->drm, 3583 "Can change cdclk via crawling\n"); 3584 } else if (pipe != INVALID_PIPE) { 3585 new_cdclk_state->pipe = pipe; 3586 3587 drm_dbg_kms(display->drm, 3588 "Can change cdclk cd2x divider with pipe %c active\n", 3589 pipe_name(pipe)); 3590 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, 3591 &new_cdclk_state->actual)) { 3592 /* All pipes must be switched off while we change the cdclk. */ 3593 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3594 if (ret) 3595 return ret; 3596 3597 new_cdclk_state->disable_pipes = true; 3598 3599 drm_dbg_kms(display->drm, 3600 "Modeset required for cdclk change\n"); 3601 } 3602 3603 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != 3604 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { 3605 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); 3606 3607 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); 3608 if (ret) 3609 return ret; 3610 } 3611 3612 drm_dbg_kms(display->drm, 3613 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3614 new_cdclk_state->logical.cdclk, 3615 new_cdclk_state->actual.cdclk); 3616 drm_dbg_kms(display->drm, 3617 "New voltage level calculated to be logical %u, actual %u\n", 3618 new_cdclk_state->logical.voltage_level, 3619 new_cdclk_state->actual.voltage_level); 3620 3621 return 0; 3622 } 3623 3624 int intel_cdclk_atomic_check(struct intel_atomic_state *state) 3625 { 3626 const struct intel_cdclk_state *old_cdclk_state; 3627 struct intel_cdclk_state *new_cdclk_state; 3628 bool need_cdclk_calc = false; 3629 int ret; 3630 3631 ret = intel_cdclk_modeset_checks(state, &need_cdclk_calc); 3632 if (ret) 3633 return ret; 3634 3635 ret = intel_crtcs_calc_min_cdclk(state, &need_cdclk_calc); 3636 if (ret) 3637 return ret; 3638 3639 ret = intel_dbuf_bw_calc_min_cdclk(state, &need_cdclk_calc); 3640 if (ret) 3641 return ret; 3642 3643 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3644 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3645 3646 if (new_cdclk_state && 3647 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) { 3648 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3649 if (ret) 3650 return ret; 3651 3652 need_cdclk_calc = true; 3653 } 3654 3655 if (need_cdclk_calc) { 3656 ret = intel_modeset_calc_cdclk(state); 3657 if (ret) 3658 return ret; 3659 } 3660 3661 return 0; 3662 } 3663 3664 void intel_cdclk_update_hw_state(struct intel_display *display) 3665 { 3666 const struct intel_dbuf_bw_state *dbuf_bw_state = 3667 to_intel_dbuf_bw_state(display->dbuf_bw.obj.state); 3668 struct intel_cdclk_state *cdclk_state = 3669 to_intel_cdclk_state(display->cdclk.obj.state); 3670 struct intel_crtc *crtc; 3671 3672 cdclk_state->enabled_pipes = 0; 3673 cdclk_state->active_pipes = 0; 3674 3675 for_each_intel_crtc(display, crtc) { 3676 const struct intel_crtc_state *crtc_state = 3677 to_intel_crtc_state(crtc->base.state); 3678 enum pipe pipe = crtc->pipe; 3679 3680 if (crtc_state->hw.enable) 3681 cdclk_state->enabled_pipes |= BIT(pipe); 3682 if (crtc_state->hw.active) 3683 cdclk_state->active_pipes |= BIT(pipe); 3684 3685 cdclk_state->min_cdclk[pipe] = crtc_state->min_cdclk; 3686 cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level; 3687 } 3688 3689 cdclk_state->dbuf_bw_min_cdclk = intel_dbuf_bw_min_cdclk(display, dbuf_bw_state); 3690 } 3691 3692 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc) 3693 { 3694 struct intel_display *display = to_intel_display(crtc); 3695 3696 intel_cdclk_update_hw_state(display); 3697 } 3698 3699 static int intel_compute_max_dotclk(struct intel_display *display) 3700 { 3701 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); 3702 int guardband = intel_cdclk_guardband(display); 3703 int max_cdclk_freq = display->cdclk.max_cdclk_freq; 3704 3705 return ppc * max_cdclk_freq * guardband / 100; 3706 } 3707 3708 /** 3709 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3710 * @display: display instance 3711 * 3712 * Determine the maximum CDCLK frequency the platform supports, and also 3713 * derive the maximum dot clock frequency the maximum CDCLK frequency 3714 * allows. 3715 */ 3716 void intel_update_max_cdclk(struct intel_display *display) 3717 { 3718 if (DISPLAY_VER(display) >= 35) { 3719 display->cdclk.max_cdclk_freq = 787200; 3720 } else if (DISPLAY_VERx100(display) >= 3002) { 3721 display->cdclk.max_cdclk_freq = 480000; 3722 } else if (DISPLAY_VER(display) >= 30) { 3723 display->cdclk.max_cdclk_freq = 691200; 3724 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3725 if (display->cdclk.hw.ref == 24000) 3726 display->cdclk.max_cdclk_freq = 552000; 3727 else 3728 display->cdclk.max_cdclk_freq = 556800; 3729 } else if (DISPLAY_VER(display) >= 11) { 3730 if (display->cdclk.hw.ref == 24000) 3731 display->cdclk.max_cdclk_freq = 648000; 3732 else 3733 display->cdclk.max_cdclk_freq = 652800; 3734 } else if (display->platform.geminilake) { 3735 display->cdclk.max_cdclk_freq = 316800; 3736 } else if (display->platform.broxton) { 3737 display->cdclk.max_cdclk_freq = 624000; 3738 } else if (DISPLAY_VER(display) == 9) { 3739 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3740 int max_cdclk, vco; 3741 3742 vco = display->cdclk.skl_preferred_vco_freq; 3743 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 3744 3745 /* 3746 * Use the lower (vco 8640) cdclk values as a 3747 * first guess. skl_calc_cdclk() will correct it 3748 * if the preferred vco is 8100 instead. 3749 */ 3750 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3751 max_cdclk = 617143; 3752 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3753 max_cdclk = 540000; 3754 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3755 max_cdclk = 432000; 3756 else 3757 max_cdclk = 308571; 3758 3759 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3760 } else if (display->platform.broadwell) { 3761 /* 3762 * FIXME with extra cooling we can allow 3763 * 540 MHz for ULX and 675 Mhz for ULT. 3764 * How can we know if extra cooling is 3765 * available? PCI ID, VTB, something else? 3766 */ 3767 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3768 display->cdclk.max_cdclk_freq = 450000; 3769 else if (display->platform.broadwell_ulx) 3770 display->cdclk.max_cdclk_freq = 450000; 3771 else if (display->platform.broadwell_ult) 3772 display->cdclk.max_cdclk_freq = 540000; 3773 else 3774 display->cdclk.max_cdclk_freq = 675000; 3775 } else if (display->platform.cherryview) { 3776 display->cdclk.max_cdclk_freq = 320000; 3777 } else if (display->platform.valleyview) { 3778 display->cdclk.max_cdclk_freq = 400000; 3779 } else { 3780 /* otherwise assume cdclk is fixed */ 3781 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; 3782 } 3783 3784 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); 3785 3786 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", 3787 display->cdclk.max_cdclk_freq); 3788 3789 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", 3790 display->cdclk.max_dotclk_freq); 3791 } 3792 3793 /** 3794 * intel_update_cdclk - Determine the current CDCLK frequency 3795 * @display: display instance 3796 * 3797 * Determine the current CDCLK frequency. 3798 */ 3799 void intel_update_cdclk(struct intel_display *display) 3800 { 3801 intel_cdclk_get_cdclk(display, &display->cdclk.hw); 3802 3803 /* 3804 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3805 * Programmng [sic] note: bit[9:2] should be programmed to the number 3806 * of cdclk that generates 4MHz reference clock freq which is used to 3807 * generate GMBus clock. This will vary with the cdclk freq. 3808 */ 3809 if (display->platform.valleyview || display->platform.cherryview) 3810 intel_de_write(display, GMBUSFREQ_VLV, 3811 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); 3812 } 3813 3814 static int dg1_rawclk(struct intel_display *display) 3815 { 3816 /* 3817 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3818 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3819 */ 3820 intel_de_write(display, PCH_RAWCLK_FREQ, 3821 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3822 3823 return 38400; 3824 } 3825 3826 static int cnp_rawclk(struct intel_display *display) 3827 { 3828 int divider, fraction; 3829 u32 rawclk; 3830 3831 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3832 /* 24 MHz */ 3833 divider = 24000; 3834 fraction = 0; 3835 } else { 3836 /* 19.2 MHz */ 3837 divider = 19000; 3838 fraction = 200; 3839 } 3840 3841 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3842 if (fraction) { 3843 int numerator = 1; 3844 3845 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3846 fraction) - 1); 3847 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 3848 rawclk |= ICP_RAWCLK_NUM(numerator); 3849 } 3850 3851 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); 3852 return divider + fraction; 3853 } 3854 3855 static int pch_rawclk(struct intel_display *display) 3856 { 3857 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3858 } 3859 3860 static int i9xx_hrawclk(struct intel_display *display) 3861 { 3862 /* hrawclock is 1/4 the FSB frequency */ 3863 return DIV_ROUND_CLOSEST(intel_fsb_freq(display), 4); 3864 } 3865 3866 /** 3867 * intel_read_rawclk - Determine the current RAWCLK frequency 3868 * @display: display instance 3869 * 3870 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3871 * frequency clock so this needs to done only once. 3872 */ 3873 u32 intel_read_rawclk(struct intel_display *display) 3874 { 3875 u32 freq; 3876 3877 if (INTEL_PCH_TYPE(display) >= PCH_MTL) 3878 /* 3879 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3880 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3881 * not need to be programmed." 3882 */ 3883 freq = 38400; 3884 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 3885 freq = dg1_rawclk(display); 3886 else if (INTEL_PCH_TYPE(display) >= PCH_CNP) 3887 freq = cnp_rawclk(display); 3888 else if (HAS_PCH_SPLIT(display)) 3889 freq = pch_rawclk(display); 3890 else if (display->platform.valleyview || display->platform.cherryview) 3891 freq = vlv_clock_get_hrawclk(display->drm); 3892 else if (DISPLAY_VER(display) >= 3) 3893 freq = i9xx_hrawclk(display); 3894 else 3895 /* no rawclk on other platforms, or no need to know it */ 3896 return 0; 3897 3898 return freq; 3899 } 3900 3901 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3902 { 3903 struct intel_display *display = m->private; 3904 3905 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); 3906 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); 3907 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); 3908 3909 return 0; 3910 } 3911 3912 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3913 3914 void intel_cdclk_debugfs_register(struct intel_display *display) 3915 { 3916 debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root, 3917 display, &i915_cdclk_info_fops); 3918 } 3919 3920 static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { 3921 .get_cdclk = bxt_get_cdclk, 3922 .set_cdclk = bxt_set_cdclk, 3923 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3924 .calc_voltage_level = xe3lpd_calc_voltage_level, 3925 }; 3926 3927 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3928 .get_cdclk = bxt_get_cdclk, 3929 .set_cdclk = bxt_set_cdclk, 3930 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3931 .calc_voltage_level = rplu_calc_voltage_level, 3932 }; 3933 3934 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3935 .get_cdclk = bxt_get_cdclk, 3936 .set_cdclk = bxt_set_cdclk, 3937 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3938 .calc_voltage_level = tgl_calc_voltage_level, 3939 }; 3940 3941 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3942 .get_cdclk = bxt_get_cdclk, 3943 .set_cdclk = bxt_set_cdclk, 3944 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3945 .calc_voltage_level = ehl_calc_voltage_level, 3946 }; 3947 3948 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3949 .get_cdclk = bxt_get_cdclk, 3950 .set_cdclk = bxt_set_cdclk, 3951 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3952 .calc_voltage_level = icl_calc_voltage_level, 3953 }; 3954 3955 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3956 .get_cdclk = bxt_get_cdclk, 3957 .set_cdclk = bxt_set_cdclk, 3958 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3959 .calc_voltage_level = bxt_calc_voltage_level, 3960 }; 3961 3962 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3963 .get_cdclk = skl_get_cdclk, 3964 .set_cdclk = skl_set_cdclk, 3965 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3966 }; 3967 3968 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3969 .get_cdclk = bdw_get_cdclk, 3970 .set_cdclk = bdw_set_cdclk, 3971 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3972 }; 3973 3974 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3975 .get_cdclk = vlv_get_cdclk, 3976 .set_cdclk = chv_set_cdclk, 3977 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3978 }; 3979 3980 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3981 .get_cdclk = vlv_get_cdclk, 3982 .set_cdclk = vlv_set_cdclk, 3983 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3984 }; 3985 3986 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3987 .get_cdclk = hsw_get_cdclk, 3988 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3989 }; 3990 3991 /* SNB, IVB, 965G, 945G */ 3992 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3993 .get_cdclk = fixed_400mhz_get_cdclk, 3994 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3995 }; 3996 3997 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3998 .get_cdclk = fixed_450mhz_get_cdclk, 3999 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4000 }; 4001 4002 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 4003 .get_cdclk = gm45_get_cdclk, 4004 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4005 }; 4006 4007 /* G45 uses G33 */ 4008 4009 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 4010 .get_cdclk = i965gm_get_cdclk, 4011 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4012 }; 4013 4014 /* i965G uses fixed 400 */ 4015 4016 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 4017 .get_cdclk = pnv_get_cdclk, 4018 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4019 }; 4020 4021 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 4022 .get_cdclk = g33_get_cdclk, 4023 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4024 }; 4025 4026 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 4027 .get_cdclk = i945gm_get_cdclk, 4028 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4029 }; 4030 4031 /* i945G uses fixed 400 */ 4032 4033 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 4034 .get_cdclk = i915gm_get_cdclk, 4035 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4036 }; 4037 4038 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 4039 .get_cdclk = fixed_333mhz_get_cdclk, 4040 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4041 }; 4042 4043 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 4044 .get_cdclk = fixed_266mhz_get_cdclk, 4045 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4046 }; 4047 4048 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 4049 .get_cdclk = i85x_get_cdclk, 4050 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4051 }; 4052 4053 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 4054 .get_cdclk = fixed_200mhz_get_cdclk, 4055 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4056 }; 4057 4058 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 4059 .get_cdclk = fixed_133mhz_get_cdclk, 4060 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4061 }; 4062 4063 /** 4064 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 4065 * @display: display instance 4066 */ 4067 void intel_init_cdclk_hooks(struct intel_display *display) 4068 { 4069 if (DISPLAY_VER(display) >= 35) { 4070 display->cdclk.funcs = &xe3lpd_cdclk_funcs; 4071 display->cdclk.table = xe3p_lpd_cdclk_table; 4072 } else if (DISPLAY_VER(display) >= 30) { 4073 display->cdclk.funcs = &xe3lpd_cdclk_funcs; 4074 display->cdclk.table = xe3lpd_cdclk_table; 4075 } else if (DISPLAY_VER(display) >= 20) { 4076 display->cdclk.funcs = &rplu_cdclk_funcs; 4077 display->cdclk.table = xe2lpd_cdclk_table; 4078 } else if (DISPLAY_VERx100(display) >= 1401) { 4079 display->cdclk.funcs = &rplu_cdclk_funcs; 4080 display->cdclk.table = xe2hpd_cdclk_table; 4081 } else if (DISPLAY_VER(display) >= 14) { 4082 display->cdclk.funcs = &rplu_cdclk_funcs; 4083 display->cdclk.table = mtl_cdclk_table; 4084 } else if (display->platform.dg2) { 4085 display->cdclk.funcs = &tgl_cdclk_funcs; 4086 display->cdclk.table = dg2_cdclk_table; 4087 } else if (display->platform.alderlake_p) { 4088 /* Wa_22011320316:adl-p[a0] */ 4089 if (intel_display_wa(display, INTEL_DISPLAY_WA_22011320316)) { 4090 display->cdclk.table = adlp_a_step_cdclk_table; 4091 display->cdclk.funcs = &tgl_cdclk_funcs; 4092 } else if (display->platform.alderlake_p_raptorlake_u) { 4093 display->cdclk.table = rplu_cdclk_table; 4094 display->cdclk.funcs = &rplu_cdclk_funcs; 4095 } else { 4096 display->cdclk.table = adlp_cdclk_table; 4097 display->cdclk.funcs = &tgl_cdclk_funcs; 4098 } 4099 } else if (display->platform.rocketlake) { 4100 display->cdclk.funcs = &tgl_cdclk_funcs; 4101 display->cdclk.table = rkl_cdclk_table; 4102 } else if (DISPLAY_VER(display) >= 12) { 4103 display->cdclk.funcs = &tgl_cdclk_funcs; 4104 display->cdclk.table = icl_cdclk_table; 4105 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 4106 display->cdclk.funcs = &ehl_cdclk_funcs; 4107 display->cdclk.table = icl_cdclk_table; 4108 } else if (DISPLAY_VER(display) >= 11) { 4109 display->cdclk.funcs = &icl_cdclk_funcs; 4110 display->cdclk.table = icl_cdclk_table; 4111 } else if (display->platform.geminilake || display->platform.broxton) { 4112 display->cdclk.funcs = &bxt_cdclk_funcs; 4113 if (display->platform.geminilake) 4114 display->cdclk.table = glk_cdclk_table; 4115 else 4116 display->cdclk.table = bxt_cdclk_table; 4117 } else if (DISPLAY_VER(display) == 9) { 4118 display->cdclk.funcs = &skl_cdclk_funcs; 4119 } else if (display->platform.broadwell) { 4120 display->cdclk.funcs = &bdw_cdclk_funcs; 4121 } else if (display->platform.haswell) { 4122 display->cdclk.funcs = &hsw_cdclk_funcs; 4123 } else if (display->platform.cherryview) { 4124 display->cdclk.funcs = &chv_cdclk_funcs; 4125 } else if (display->platform.valleyview) { 4126 display->cdclk.funcs = &vlv_cdclk_funcs; 4127 } else if (display->platform.sandybridge || display->platform.ivybridge) { 4128 display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; 4129 } else if (display->platform.ironlake) { 4130 display->cdclk.funcs = &ilk_cdclk_funcs; 4131 } else if (display->platform.gm45) { 4132 display->cdclk.funcs = &gm45_cdclk_funcs; 4133 } else if (display->platform.g45) { 4134 display->cdclk.funcs = &g33_cdclk_funcs; 4135 } else if (display->platform.i965gm) { 4136 display->cdclk.funcs = &i965gm_cdclk_funcs; 4137 } else if (display->platform.i965g) { 4138 display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; 4139 } else if (display->platform.pineview) { 4140 display->cdclk.funcs = &pnv_cdclk_funcs; 4141 } else if (display->platform.g33) { 4142 display->cdclk.funcs = &g33_cdclk_funcs; 4143 } else if (display->platform.i945gm) { 4144 display->cdclk.funcs = &i945gm_cdclk_funcs; 4145 } else if (display->platform.i945g) { 4146 display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; 4147 } else if (display->platform.i915gm) { 4148 display->cdclk.funcs = &i915gm_cdclk_funcs; 4149 } else if (display->platform.i915g) { 4150 display->cdclk.funcs = &i915g_cdclk_funcs; 4151 } else if (display->platform.i865g) { 4152 display->cdclk.funcs = &i865g_cdclk_funcs; 4153 } else if (display->platform.i85x) { 4154 display->cdclk.funcs = &i85x_cdclk_funcs; 4155 } else if (display->platform.i845g) { 4156 display->cdclk.funcs = &i845g_cdclk_funcs; 4157 } else if (display->platform.i830) { 4158 display->cdclk.funcs = &i830_cdclk_funcs; 4159 } 4160 4161 if (drm_WARN(display->drm, !display->cdclk.funcs, 4162 "Unknown platform. Assuming i830\n")) 4163 display->cdclk.funcs = &i830_cdclk_funcs; 4164 } 4165 4166 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state) 4167 { 4168 return cdclk_state->logical.cdclk; 4169 } 4170 4171 int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state) 4172 { 4173 return cdclk_state->actual.cdclk; 4174 } 4175 4176 int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state) 4177 { 4178 return cdclk_state->actual.voltage_level; 4179 } 4180 4181 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe) 4182 { 4183 return cdclk_state->min_cdclk[pipe]; 4184 } 4185 4186 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state) 4187 { 4188 const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state; 4189 4190 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 4191 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 4192 4193 if (new_cdclk_state && 4194 (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk || 4195 new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level)) 4196 return true; 4197 4198 return false; 4199 } 4200 4201 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk) 4202 { 4203 cdclk_state->force_min_cdclk = force_min_cdclk; 4204 } 4205 4206 void intel_cdclk_read_hw(struct intel_display *display) 4207 { 4208 struct intel_cdclk_state *cdclk_state; 4209 4210 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); 4211 4212 intel_update_cdclk(display); 4213 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 4214 cdclk_state->actual = display->cdclk.hw; 4215 cdclk_state->logical = display->cdclk.hw; 4216 } 4217 4218 static int calc_cdclk(const struct intel_crtc_state *crtc_state, int min_cdclk) 4219 { 4220 struct intel_display *display = to_intel_display(crtc_state); 4221 4222 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) { 4223 return bxt_calc_cdclk(display, min_cdclk); 4224 } else if (DISPLAY_VER(display) == 9) { 4225 int vco; 4226 4227 vco = display->cdclk.skl_preferred_vco_freq; 4228 if (vco == 0) 4229 vco = 8100000; 4230 4231 return skl_calc_cdclk(min_cdclk, vco); 4232 } else if (display->platform.broadwell) { 4233 return bdw_calc_cdclk(min_cdclk); 4234 } else if (display->platform.cherryview || display->platform.valleyview) { 4235 return vlv_calc_cdclk(display, min_cdclk); 4236 } else { 4237 return display->cdclk.max_cdclk_freq; 4238 } 4239 } 4240 4241 static unsigned int _intel_cdclk_prefill_adj(const struct intel_crtc_state *crtc_state, 4242 int clock, int min_cdclk) 4243 { 4244 struct intel_display *display = to_intel_display(crtc_state); 4245 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 4246 int cdclk = calc_cdclk(crtc_state, min_cdclk); 4247 4248 return min(0x10000, DIV_ROUND_UP_ULL((u64)clock << 16, ppc * cdclk)); 4249 } 4250 4251 unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) 4252 { 4253 /* FIXME use the actual min_cdclk for the pipe here */ 4254 return intel_cdclk_prefill_adjustment_worst(crtc_state); 4255 } 4256 4257 unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state) 4258 { 4259 int clock = crtc_state->hw.pipe_mode.crtc_clock; 4260 int min_cdclk; 4261 4262 /* 4263 * FIXME could perhaps consider a few more of the factors 4264 * that go the per-crtc min_cdclk. Namely anything that 4265 * only changes during full modesets. 4266 * 4267 * FIXME this assumes 1:1 scaling, but the other _worst() stuff 4268 * assumes max downscaling, so the final result will be 4269 * unrealistically bad. Figure out where the actual maximum value 4270 * lies and use that to compute a more realistic worst case 4271 * estimate... 4272 */ 4273 min_cdclk = _intel_pixel_rate_to_cdclk(crtc_state, clock); 4274 4275 return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk); 4276 } 4277 4278 int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state, 4279 unsigned int prefill_lines_unadjusted, 4280 unsigned int prefill_lines_available) 4281 { 4282 struct intel_display *display = to_intel_display(crtc_state); 4283 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 4284 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 4285 4286 return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, prefill_lines_unadjusted), 4287 ppc * prefill_lines_available); 4288 } 4289