xref: /linux/drivers/gpu/drm/i915/display/intel_display.c (revision d34b59d5ba411e26ec13d71dda98ff40510feae0)
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *	Eric Anholt <eric@anholt.net>
25  */
26 
27 #include <linux/dma-resv.h>
28 #include <linux/i2c.h>
29 #include <linux/input.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/slab.h>
33 #include <linux/string_helpers.h>
34 
35 #include <drm/display/drm_dp_helper.h>
36 #include <drm/display/drm_dp_tunnel.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_atomic_helper.h>
39 #include <drm/drm_atomic_uapi.h>
40 #include <drm/drm_damage_helper.h>
41 #include <drm/drm_edid.h>
42 #include <drm/drm_fixed.h>
43 #include <drm/drm_fourcc.h>
44 #include <drm/drm_probe_helper.h>
45 #include <drm/drm_rect.h>
46 #include <drm/drm_vblank.h>
47 
48 #include "g4x_dp.h"
49 #include "g4x_hdmi.h"
50 #include "hsw_ips.h"
51 #include "i915_config.h"
52 #include "i915_drv.h"
53 #include "i915_reg.h"
54 #include "i915_utils.h"
55 #include "i9xx_plane.h"
56 #include "i9xx_plane_regs.h"
57 #include "i9xx_wm.h"
58 #include "intel_atomic.h"
59 #include "intel_atomic_plane.h"
60 #include "intel_audio.h"
61 #include "intel_bo.h"
62 #include "intel_bw.h"
63 #include "intel_cdclk.h"
64 #include "intel_clock_gating.h"
65 #include "intel_color.h"
66 #include "intel_crt.h"
67 #include "intel_crtc.h"
68 #include "intel_crtc_state_dump.h"
69 #include "intel_cursor_regs.h"
70 #include "intel_cx0_phy.h"
71 #include "intel_cursor.h"
72 #include "intel_ddi.h"
73 #include "intel_de.h"
74 #include "intel_display_driver.h"
75 #include "intel_display_power.h"
76 #include "intel_display_types.h"
77 #include "intel_dmc.h"
78 #include "intel_dp.h"
79 #include "intel_dp_link_training.h"
80 #include "intel_dp_mst.h"
81 #include "intel_dp_tunnel.h"
82 #include "intel_dpll.h"
83 #include "intel_dpll_mgr.h"
84 #include "intel_dpt.h"
85 #include "intel_dpt_common.h"
86 #include "intel_drrs.h"
87 #include "intel_dsb.h"
88 #include "intel_dsi.h"
89 #include "intel_dvo.h"
90 #include "intel_fb.h"
91 #include "intel_fbc.h"
92 #include "intel_fdi.h"
93 #include "intel_fifo_underrun.h"
94 #include "intel_frontbuffer.h"
95 #include "intel_hdmi.h"
96 #include "intel_hotplug.h"
97 #include "intel_link_bw.h"
98 #include "intel_lvds.h"
99 #include "intel_lvds_regs.h"
100 #include "intel_modeset_setup.h"
101 #include "intel_modeset_verify.h"
102 #include "intel_overlay.h"
103 #include "intel_panel.h"
104 #include "intel_pch_display.h"
105 #include "intel_pch_refclk.h"
106 #include "intel_pcode.h"
107 #include "intel_pfit.h"
108 #include "intel_pipe_crc.h"
109 #include "intel_plane_initial.h"
110 #include "intel_pmdemand.h"
111 #include "intel_pps.h"
112 #include "intel_psr.h"
113 #include "intel_psr_regs.h"
114 #include "intel_sdvo.h"
115 #include "intel_snps_phy.h"
116 #include "intel_tc.h"
117 #include "intel_tdf.h"
118 #include "intel_tv.h"
119 #include "intel_vblank.h"
120 #include "intel_vdsc.h"
121 #include "intel_vdsc_regs.h"
122 #include "intel_vga.h"
123 #include "intel_vrr.h"
124 #include "intel_wm.h"
125 #include "skl_scaler.h"
126 #include "skl_universal_plane.h"
127 #include "skl_watermark.h"
128 #include "vlv_dpio_phy_regs.h"
129 #include "vlv_dsi.h"
130 #include "vlv_dsi_pll.h"
131 #include "vlv_dsi_regs.h"
132 #include "vlv_sideband.h"
133 
134 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
135 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
136 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
137 static void bdw_set_pipe_misc(struct intel_dsb *dsb,
138 			      const struct intel_crtc_state *crtc_state);
139 
140 /* returns HPLL frequency in kHz */
141 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
142 {
143 	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144 
145 	/* Obtain SKU information */
146 	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
147 		CCK_FUSE_HPLL_FREQ_MASK;
148 
149 	return vco_freq[hpll_freq] * 1000;
150 }
151 
152 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
153 		      const char *name, u32 reg, int ref_freq)
154 {
155 	u32 val;
156 	int divider;
157 
158 	val = vlv_cck_read(dev_priv, reg);
159 	divider = val & CCK_FREQUENCY_VALUES;
160 
161 	drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
162 		 (divider << CCK_FREQUENCY_STATUS_SHIFT),
163 		 "%s change in progress\n", name);
164 
165 	return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
166 }
167 
168 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
169 			   const char *name, u32 reg)
170 {
171 	int hpll;
172 
173 	vlv_cck_get(dev_priv);
174 
175 	if (dev_priv->hpll_freq == 0)
176 		dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
177 
178 	hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
179 
180 	vlv_cck_put(dev_priv);
181 
182 	return hpll;
183 }
184 
185 void intel_update_czclk(struct intel_display *display)
186 {
187 	struct drm_i915_private *dev_priv = to_i915(display->drm);
188 
189 	if (!display->platform.valleyview && !display->platform.cherryview)
190 		return;
191 
192 	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
193 						      CCK_CZ_CLOCK_CONTROL);
194 
195 	drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
196 }
197 
198 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
199 {
200 	return (crtc_state->active_planes &
201 		~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
202 }
203 
204 /* WA Display #0827: Gen9:all */
205 static void
206 skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable)
207 {
208 	intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
209 		     DUPS1_GATING_DIS | DUPS2_GATING_DIS,
210 		     enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0);
211 }
212 
213 /* Wa_2006604312:icl,ehl */
214 static void
215 icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe,
216 		       bool enable)
217 {
218 	intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
219 		     DPFR_GATING_DIS,
220 		     enable ? DPFR_GATING_DIS : 0);
221 }
222 
223 /* Wa_1604331009:icl,jsl,ehl */
224 static void
225 icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe,
226 		       bool enable)
227 {
228 	intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
229 		     CURSOR_GATING_DIS,
230 		     enable ? CURSOR_GATING_DIS : 0);
231 }
232 
233 static bool
234 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
235 {
236 	return crtc_state->master_transcoder != INVALID_TRANSCODER;
237 }
238 
239 bool
240 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
241 {
242 	return crtc_state->sync_mode_slaves_mask != 0;
243 }
244 
245 bool
246 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
247 {
248 	return is_trans_port_sync_master(crtc_state) ||
249 		is_trans_port_sync_slave(crtc_state);
250 }
251 
252 static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)
253 {
254 	return ffs(crtc_state->joiner_pipes) - 1;
255 }
256 
257 /*
258  * The following helper functions, despite being named for bigjoiner,
259  * are applicable to both bigjoiner and uncompressed joiner configurations.
260  */
261 static bool is_bigjoiner(const struct intel_crtc_state *crtc_state)
262 {
263 	return hweight8(crtc_state->joiner_pipes) >= 2;
264 }
265 
266 static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
267 {
268 	if (!is_bigjoiner(crtc_state))
269 		return 0;
270 
271 	return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state));
272 }
273 
274 static unsigned int bigjoiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
275 {
276 	if (!is_bigjoiner(crtc_state))
277 		return 0;
278 
279 	return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state));
280 }
281 
282 bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state)
283 {
284 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
285 
286 	if (!is_bigjoiner(crtc_state))
287 		return false;
288 
289 	return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);
290 }
291 
292 bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state)
293 {
294 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
295 
296 	if (!is_bigjoiner(crtc_state))
297 		return false;
298 
299 	return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);
300 }
301 
302 u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state)
303 {
304 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
305 
306 	if (!is_bigjoiner(crtc_state))
307 		return BIT(crtc->pipe);
308 
309 	return bigjoiner_primary_pipes(crtc_state);
310 }
311 
312 u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state)
313 {
314 	return bigjoiner_secondary_pipes(crtc_state);
315 }
316 
317 bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state)
318 {
319 	return intel_crtc_num_joined_pipes(crtc_state) >= 4;
320 }
321 
322 static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
323 {
324 	if (!intel_crtc_is_ultrajoiner(crtc_state))
325 		return 0;
326 
327 	return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state));
328 }
329 
330 bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state)
331 {
332 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
333 
334 	return intel_crtc_is_ultrajoiner(crtc_state) &&
335 	       BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);
336 }
337 
338 /*
339  * The ultrajoiner enable bit doesn't seem to follow primary/secondary logic or
340  * any other logic, so lets just add helper function to
341  * at least hide this hassle..
342  */
343 static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state)
344 {
345 	if (!intel_crtc_is_ultrajoiner(crtc_state))
346 		return 0;
347 
348 	return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state));
349 }
350 
351 bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state)
352 {
353 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
354 
355 	return intel_crtc_is_ultrajoiner(crtc_state) &&
356 	       BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);
357 }
358 
359 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
360 {
361 	if (crtc_state->joiner_pipes)
362 		return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));
363 	else
364 		return 0;
365 }
366 
367 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
368 {
369 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
370 
371 	return crtc_state->joiner_pipes &&
372 		crtc->pipe != joiner_primary_pipe(crtc_state);
373 }
374 
375 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
376 {
377 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
378 
379 	return crtc_state->joiner_pipes &&
380 		crtc->pipe == joiner_primary_pipe(crtc_state);
381 }
382 
383 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state)
384 {
385 	return hweight8(intel_crtc_joined_pipe_mask(crtc_state));
386 }
387 
388 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
389 {
390 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
391 
392 	return BIT(crtc->pipe) | crtc_state->joiner_pipes;
393 }
394 
395 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
396 {
397 	struct intel_display *display = to_intel_display(crtc_state);
398 
399 	if (intel_crtc_is_joiner_secondary(crtc_state))
400 		return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state));
401 	else
402 		return to_intel_crtc(crtc_state->uapi.crtc);
403 }
404 
405 static void
406 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
407 {
408 	struct intel_display *display = to_intel_display(old_crtc_state);
409 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
410 
411 	if (DISPLAY_VER(display) >= 4) {
412 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
413 
414 		/* Wait for the Pipe State to go off */
415 		if (intel_de_wait_for_clear(display, TRANSCONF(display, cpu_transcoder),
416 					    TRANSCONF_STATE_ENABLE, 100))
417 			drm_WARN(display->drm, 1, "pipe_off wait timed out\n");
418 	} else {
419 		intel_wait_for_pipe_scanline_stopped(crtc);
420 	}
421 }
422 
423 void assert_transcoder(struct intel_display *display,
424 		       enum transcoder cpu_transcoder, bool state)
425 {
426 	bool cur_state;
427 	enum intel_display_power_domain power_domain;
428 	intel_wakeref_t wakeref;
429 
430 	/* we keep both pipes enabled on 830 */
431 	if (display->platform.i830)
432 		state = true;
433 
434 	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
435 	wakeref = intel_display_power_get_if_enabled(display, power_domain);
436 	if (wakeref) {
437 		u32 val = intel_de_read(display,
438 					TRANSCONF(display, cpu_transcoder));
439 		cur_state = !!(val & TRANSCONF_ENABLE);
440 
441 		intel_display_power_put(display, power_domain, wakeref);
442 	} else {
443 		cur_state = false;
444 	}
445 
446 	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
447 				 "transcoder %s assertion failure (expected %s, current %s)\n",
448 				 transcoder_name(cpu_transcoder), str_on_off(state),
449 				 str_on_off(cur_state));
450 }
451 
452 static void assert_plane(struct intel_plane *plane, bool state)
453 {
454 	struct intel_display *display = to_intel_display(plane->base.dev);
455 	enum pipe pipe;
456 	bool cur_state;
457 
458 	cur_state = plane->get_hw_state(plane, &pipe);
459 
460 	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
461 				 "%s assertion failure (expected %s, current %s)\n",
462 				 plane->base.name, str_on_off(state),
463 				 str_on_off(cur_state));
464 }
465 
466 #define assert_plane_enabled(p) assert_plane(p, true)
467 #define assert_plane_disabled(p) assert_plane(p, false)
468 
469 static void assert_planes_disabled(struct intel_crtc *crtc)
470 {
471 	struct intel_display *display = to_intel_display(crtc);
472 	struct intel_plane *plane;
473 
474 	for_each_intel_plane_on_crtc(display->drm, crtc, plane)
475 		assert_plane_disabled(plane);
476 }
477 
478 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
479 {
480 	struct intel_display *display = to_intel_display(new_crtc_state);
481 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
482 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
483 	enum pipe pipe = crtc->pipe;
484 	u32 val;
485 
486 	drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));
487 
488 	assert_planes_disabled(crtc);
489 
490 	/*
491 	 * A pipe without a PLL won't actually be able to drive bits from
492 	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
493 	 * need the check.
494 	 */
495 	if (HAS_GMCH(display)) {
496 		if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
497 			assert_dsi_pll_enabled(display);
498 		else
499 			assert_pll_enabled(display, pipe);
500 	} else {
501 		if (new_crtc_state->has_pch_encoder) {
502 			/* if driving the PCH, we need FDI enabled */
503 			assert_fdi_rx_pll_enabled(display,
504 						  intel_crtc_pch_transcoder(crtc));
505 			assert_fdi_tx_pll_enabled(display,
506 						  (enum pipe) cpu_transcoder);
507 		}
508 		/* FIXME: assert CPU port conditions for SNB+ */
509 	}
510 
511 	/* Wa_22012358565:adl-p */
512 	if (DISPLAY_VER(display) == 13)
513 		intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),
514 			     0, PIPE_ARB_USE_PROG_SLOTS);
515 
516 	if (DISPLAY_VER(display) >= 14) {
517 		u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
518 		u32 set = 0;
519 
520 		if (DISPLAY_VER(display) == 14)
521 			set |= DP_FEC_BS_JITTER_WA;
522 
523 		intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
524 			     clear, set);
525 	}
526 
527 	val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
528 	if (val & TRANSCONF_ENABLE) {
529 		/* we keep both pipes enabled on 830 */
530 		drm_WARN_ON(display->drm, !display->platform.i830);
531 		return;
532 	}
533 
534 	/* Wa_1409098942:adlp+ */
535 	if (DISPLAY_VER(display) >= 13 &&
536 	    new_crtc_state->dsc.compression_enable) {
537 		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
538 		val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
539 				      TRANSCONF_PIXEL_COUNT_SCALING_X4);
540 	}
541 
542 	intel_de_write(display, TRANSCONF(display, cpu_transcoder),
543 		       val | TRANSCONF_ENABLE);
544 	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
545 
546 	/*
547 	 * Until the pipe starts PIPEDSL reads will return a stale value,
548 	 * which causes an apparent vblank timestamp jump when PIPEDSL
549 	 * resets to its proper value. That also messes up the frame count
550 	 * when it's derived from the timestamps. So let's wait for the
551 	 * pipe to start properly before we call drm_crtc_vblank_on()
552 	 */
553 	if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
554 		intel_wait_for_pipe_scanline_moving(crtc);
555 }
556 
557 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
558 {
559 	struct intel_display *display = to_intel_display(old_crtc_state);
560 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
561 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
562 	enum pipe pipe = crtc->pipe;
563 	u32 val;
564 
565 	drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe));
566 
567 	/*
568 	 * Make sure planes won't keep trying to pump pixels to us,
569 	 * or we might hang the display.
570 	 */
571 	assert_planes_disabled(crtc);
572 
573 	val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
574 	if ((val & TRANSCONF_ENABLE) == 0)
575 		return;
576 
577 	/*
578 	 * Double wide has implications for planes
579 	 * so best keep it disabled when not needed.
580 	 */
581 	if (old_crtc_state->double_wide)
582 		val &= ~TRANSCONF_DOUBLE_WIDE;
583 
584 	/* Don't disable pipe or pipe PLLs if needed */
585 	if (!display->platform.i830)
586 		val &= ~TRANSCONF_ENABLE;
587 
588 	/* Wa_1409098942:adlp+ */
589 	if (DISPLAY_VER(display) >= 13 &&
590 	    old_crtc_state->dsc.compression_enable)
591 		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
592 
593 	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
594 
595 	if (DISPLAY_VER(display) >= 12)
596 		intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
597 			     FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
598 
599 	if ((val & TRANSCONF_ENABLE) == 0)
600 		intel_wait_for_pipe_off(old_crtc_state);
601 }
602 
603 u32 intel_plane_fb_max_stride(struct drm_device *drm,
604 			      u32 pixel_format, u64 modifier)
605 {
606 	struct intel_display *display = to_intel_display(drm);
607 	struct intel_crtc *crtc;
608 	struct intel_plane *plane;
609 
610 	if (!HAS_DISPLAY(display))
611 		return 0;
612 
613 	/*
614 	 * We assume the primary plane for pipe A has
615 	 * the highest stride limits of them all,
616 	 * if in case pipe A is disabled, use the first pipe from pipe_mask.
617 	 */
618 	crtc = intel_first_crtc(display);
619 	if (!crtc)
620 		return 0;
621 
622 	plane = to_intel_plane(crtc->base.primary);
623 
624 	return plane->max_stride(plane, pixel_format, modifier,
625 				 DRM_MODE_ROTATE_0);
626 }
627 
628 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
629 			     struct intel_plane_state *plane_state,
630 			     bool visible)
631 {
632 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
633 
634 	plane_state->uapi.visible = visible;
635 
636 	if (visible)
637 		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
638 	else
639 		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
640 }
641 
642 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
643 {
644 	struct intel_display *display = to_intel_display(crtc_state);
645 	struct drm_plane *plane;
646 
647 	/*
648 	 * Active_planes aliases if multiple "primary" or cursor planes
649 	 * have been used on the same (or wrong) pipe. plane_mask uses
650 	 * unique ids, hence we can use that to reconstruct active_planes.
651 	 */
652 	crtc_state->enabled_planes = 0;
653 	crtc_state->active_planes = 0;
654 
655 	drm_for_each_plane_mask(plane, display->drm,
656 				crtc_state->uapi.plane_mask) {
657 		crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
658 		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
659 	}
660 }
661 
662 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
663 				  struct intel_plane *plane)
664 {
665 	struct intel_display *display = to_intel_display(crtc);
666 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
667 	struct intel_crtc_state *crtc_state =
668 		to_intel_crtc_state(crtc->base.state);
669 	struct intel_plane_state *plane_state =
670 		to_intel_plane_state(plane->base.state);
671 
672 	drm_dbg_kms(display->drm,
673 		    "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
674 		    plane->base.base.id, plane->base.name,
675 		    crtc->base.base.id, crtc->base.name);
676 
677 	intel_plane_set_invisible(crtc_state, plane_state);
678 	intel_set_plane_visible(crtc_state, plane_state, false);
679 	intel_plane_fixup_bitmasks(crtc_state);
680 
681 	skl_wm_plane_disable_noatomic(crtc, plane);
682 
683 	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
684 	    hsw_ips_disable(crtc_state)) {
685 		crtc_state->ips_enabled = false;
686 		intel_plane_initial_vblank_wait(crtc);
687 	}
688 
689 	/*
690 	 * Vblank time updates from the shadow to live plane control register
691 	 * are blocked if the memory self-refresh mode is active at that
692 	 * moment. So to make sure the plane gets truly disabled, disable
693 	 * first the self-refresh mode. The self-refresh enable bit in turn
694 	 * will be checked/applied by the HW only at the next frame start
695 	 * event which is after the vblank start event, so we need to have a
696 	 * wait-for-vblank between disabling the plane and the pipe.
697 	 */
698 	if (HAS_GMCH(display) &&
699 	    intel_set_memory_cxsr(dev_priv, false))
700 		intel_plane_initial_vblank_wait(crtc);
701 
702 	/*
703 	 * Gen2 reports pipe underruns whenever all planes are disabled.
704 	 * So disable underrun reporting before all the planes get disabled.
705 	 */
706 	if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes)
707 		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false);
708 
709 	intel_plane_disable_arm(NULL, plane, crtc_state);
710 	intel_plane_initial_vblank_wait(crtc);
711 }
712 
713 unsigned int
714 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
715 {
716 	int x = 0, y = 0;
717 
718 	intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
719 					  plane_state->view.color_plane[0].offset, 0);
720 
721 	return y;
722 }
723 
724 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
725 {
726 	struct intel_display *display = to_intel_display(crtc_state);
727 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
728 	enum pipe pipe = crtc->pipe;
729 	u32 tmp;
730 
731 	tmp = intel_de_read(display, PIPE_CHICKEN(pipe));
732 
733 	/*
734 	 * Display WA #1153: icl
735 	 * enable hardware to bypass the alpha math
736 	 * and rounding for per-pixel values 00 and 0xff
737 	 */
738 	tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
739 	/*
740 	 * Display WA # 1605353570: icl
741 	 * Set the pixel rounding bit to 1 for allowing
742 	 * passthrough of Frame buffer pixels unmodified
743 	 * across pipe
744 	 */
745 	tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
746 
747 	/*
748 	 * Underrun recovery must always be disabled on display 13+.
749 	 * DG2 chicken bit meaning is inverted compared to other platforms.
750 	 */
751 	if (display->platform.dg2)
752 		tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
753 	else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30))
754 		tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
755 
756 	/* Wa_14010547955:dg2 */
757 	if (display->platform.dg2)
758 		tmp |= DG2_RENDER_CCSTAG_4_3_EN;
759 
760 	intel_de_write(display, PIPE_CHICKEN(pipe), tmp);
761 }
762 
763 bool intel_has_pending_fb_unpin(struct intel_display *display)
764 {
765 	struct drm_crtc *crtc;
766 	bool cleanup_done;
767 
768 	drm_for_each_crtc(crtc, display->drm) {
769 		struct drm_crtc_commit *commit;
770 		spin_lock(&crtc->commit_lock);
771 		commit = list_first_entry_or_null(&crtc->commit_list,
772 						  struct drm_crtc_commit, commit_entry);
773 		cleanup_done = commit ?
774 			try_wait_for_completion(&commit->cleanup_done) : true;
775 		spin_unlock(&crtc->commit_lock);
776 
777 		if (cleanup_done)
778 			continue;
779 
780 		intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
781 
782 		return true;
783 	}
784 
785 	return false;
786 }
787 
788 /*
789  * Finds the encoder associated with the given CRTC. This can only be
790  * used when we know that the CRTC isn't feeding multiple encoders!
791  */
792 struct intel_encoder *
793 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
794 			   const struct intel_crtc_state *crtc_state)
795 {
796 	const struct drm_connector_state *connector_state;
797 	const struct drm_connector *connector;
798 	struct intel_encoder *encoder = NULL;
799 	struct intel_crtc *primary_crtc;
800 	int num_encoders = 0;
801 	int i;
802 
803 	primary_crtc = intel_primary_crtc(crtc_state);
804 
805 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
806 		if (connector_state->crtc != &primary_crtc->base)
807 			continue;
808 
809 		encoder = to_intel_encoder(connector_state->best_encoder);
810 		num_encoders++;
811 	}
812 
813 	drm_WARN(state->base.dev, num_encoders != 1,
814 		 "%d encoders for pipe %c\n",
815 		 num_encoders, pipe_name(primary_crtc->pipe));
816 
817 	return encoder;
818 }
819 
820 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
821 {
822 	if (crtc->overlay)
823 		(void) intel_overlay_switch_off(crtc->overlay);
824 
825 	/* Let userspace switch the overlay on again. In most cases userspace
826 	 * has to recompute where to put it anyway.
827 	 */
828 }
829 
830 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
831 {
832 	struct intel_display *display = to_intel_display(crtc_state);
833 
834 	if (!crtc_state->nv12_planes)
835 		return false;
836 
837 	/* WA Display #0827: Gen9:all */
838 	if (DISPLAY_VER(display) == 9)
839 		return true;
840 
841 	return false;
842 }
843 
844 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
845 {
846 	struct intel_display *display = to_intel_display(crtc_state);
847 
848 	/* Wa_2006604312:icl,ehl */
849 	if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11)
850 		return true;
851 
852 	return false;
853 }
854 
855 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
856 {
857 	struct intel_display *display = to_intel_display(crtc_state);
858 
859 	/* Wa_1604331009:icl,jsl,ehl */
860 	if (is_hdr_mode(crtc_state) &&
861 	    crtc_state->active_planes & BIT(PLANE_CURSOR) &&
862 	    DISPLAY_VER(display) == 11)
863 		return true;
864 
865 	return false;
866 }
867 
868 static void intel_async_flip_vtd_wa(struct intel_display *display,
869 				    enum pipe pipe, bool enable)
870 {
871 	if (DISPLAY_VER(display) == 9) {
872 		/*
873 		 * "Plane N stretch max must be programmed to 11b (x1)
874 		 *  when Async flips are enabled on that plane."
875 		 */
876 		intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),
877 			     SKL_PLANE1_STRETCH_MAX_MASK,
878 			     enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
879 	} else {
880 		/* Also needed on HSW/BDW albeit undocumented */
881 		intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),
882 			     HSW_PRI_STRETCH_MAX_MASK,
883 			     enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
884 	}
885 }
886 
887 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
888 {
889 	struct intel_display *display = to_intel_display(crtc_state);
890 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
891 
892 	return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
893 		(DISPLAY_VER(display) == 9 || display->platform.broadwell ||
894 		 display->platform.haswell);
895 }
896 
897 static void intel_encoders_audio_enable(struct intel_atomic_state *state,
898 					struct intel_crtc *crtc)
899 {
900 	const struct intel_crtc_state *crtc_state =
901 		intel_atomic_get_new_crtc_state(state, crtc);
902 	const struct drm_connector_state *conn_state;
903 	struct drm_connector *conn;
904 	int i;
905 
906 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
907 		struct intel_encoder *encoder =
908 			to_intel_encoder(conn_state->best_encoder);
909 
910 		if (conn_state->crtc != &crtc->base)
911 			continue;
912 
913 		if (encoder->audio_enable)
914 			encoder->audio_enable(encoder, crtc_state, conn_state);
915 	}
916 }
917 
918 static void intel_encoders_audio_disable(struct intel_atomic_state *state,
919 					 struct intel_crtc *crtc)
920 {
921 	const struct intel_crtc_state *old_crtc_state =
922 		intel_atomic_get_old_crtc_state(state, crtc);
923 	const struct drm_connector_state *old_conn_state;
924 	struct drm_connector *conn;
925 	int i;
926 
927 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
928 		struct intel_encoder *encoder =
929 			to_intel_encoder(old_conn_state->best_encoder);
930 
931 		if (old_conn_state->crtc != &crtc->base)
932 			continue;
933 
934 		if (encoder->audio_disable)
935 			encoder->audio_disable(encoder, old_crtc_state, old_conn_state);
936 	}
937 }
938 
939 #define is_enabling(feature, old_crtc_state, new_crtc_state) \
940 	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
941 	 (new_crtc_state)->feature)
942 #define is_disabling(feature, old_crtc_state, new_crtc_state) \
943 	((old_crtc_state)->feature && \
944 	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
945 
946 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
947 			    const struct intel_crtc_state *new_crtc_state)
948 {
949 	if (!new_crtc_state->hw.active)
950 		return false;
951 
952 	return is_enabling(active_planes, old_crtc_state, new_crtc_state);
953 }
954 
955 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
956 			     const struct intel_crtc_state *new_crtc_state)
957 {
958 	if (!old_crtc_state->hw.active)
959 		return false;
960 
961 	return is_disabling(active_planes, old_crtc_state, new_crtc_state);
962 }
963 
964 static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
965 			       const struct intel_crtc_state *new_crtc_state)
966 {
967 	return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
968 		old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
969 		old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
970 		old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
971 		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
972 }
973 
974 static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
975 				const struct intel_crtc_state *new_crtc_state)
976 {
977 	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
978 		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
979 }
980 
981 static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
982 				    struct intel_crtc *crtc)
983 {
984 	const struct intel_crtc_state *old_crtc_state =
985 		intel_atomic_get_old_crtc_state(state, crtc);
986 	const struct intel_crtc_state *new_crtc_state =
987 		intel_atomic_get_new_crtc_state(state, crtc);
988 
989 	if (!new_crtc_state->hw.active)
990 		return false;
991 
992 	return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
993 		(new_crtc_state->vrr.enable &&
994 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
995 		  vrr_params_changed(old_crtc_state, new_crtc_state)));
996 }
997 
998 bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
999 			      struct intel_crtc *crtc)
1000 {
1001 	const struct intel_crtc_state *old_crtc_state =
1002 		intel_atomic_get_old_crtc_state(state, crtc);
1003 	const struct intel_crtc_state *new_crtc_state =
1004 		intel_atomic_get_new_crtc_state(state, crtc);
1005 
1006 	if (!old_crtc_state->hw.active)
1007 		return false;
1008 
1009 	return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
1010 		(old_crtc_state->vrr.enable &&
1011 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
1012 		  vrr_params_changed(old_crtc_state, new_crtc_state)));
1013 }
1014 
1015 static bool audio_enabling(const struct intel_crtc_state *old_crtc_state,
1016 			   const struct intel_crtc_state *new_crtc_state)
1017 {
1018 	if (!new_crtc_state->hw.active)
1019 		return false;
1020 
1021 	return is_enabling(has_audio, old_crtc_state, new_crtc_state) ||
1022 		(new_crtc_state->has_audio &&
1023 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
1024 }
1025 
1026 static bool audio_disabling(const struct intel_crtc_state *old_crtc_state,
1027 			    const struct intel_crtc_state *new_crtc_state)
1028 {
1029 	if (!old_crtc_state->hw.active)
1030 		return false;
1031 
1032 	return is_disabling(has_audio, old_crtc_state, new_crtc_state) ||
1033 		(old_crtc_state->has_audio &&
1034 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
1035 }
1036 
1037 #undef is_disabling
1038 #undef is_enabling
1039 
1040 static void intel_post_plane_update(struct intel_atomic_state *state,
1041 				    struct intel_crtc *crtc)
1042 {
1043 	struct intel_display *display = to_intel_display(state);
1044 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1045 	const struct intel_crtc_state *old_crtc_state =
1046 		intel_atomic_get_old_crtc_state(state, crtc);
1047 	const struct intel_crtc_state *new_crtc_state =
1048 		intel_atomic_get_new_crtc_state(state, crtc);
1049 	enum pipe pipe = crtc->pipe;
1050 
1051 	intel_psr_post_plane_update(state, crtc);
1052 
1053 	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
1054 
1055 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1056 		intel_update_watermarks(dev_priv);
1057 
1058 	intel_fbc_post_update(state, crtc);
1059 
1060 	if (needs_async_flip_vtd_wa(old_crtc_state) &&
1061 	    !needs_async_flip_vtd_wa(new_crtc_state))
1062 		intel_async_flip_vtd_wa(display, pipe, false);
1063 
1064 	if (needs_nv12_wa(old_crtc_state) &&
1065 	    !needs_nv12_wa(new_crtc_state))
1066 		skl_wa_827(display, pipe, false);
1067 
1068 	if (needs_scalerclk_wa(old_crtc_state) &&
1069 	    !needs_scalerclk_wa(new_crtc_state))
1070 		icl_wa_scalerclkgating(display, pipe, false);
1071 
1072 	if (needs_cursorclk_wa(old_crtc_state) &&
1073 	    !needs_cursorclk_wa(new_crtc_state))
1074 		icl_wa_cursorclkgating(display, pipe, false);
1075 
1076 	if (intel_crtc_needs_color_update(new_crtc_state))
1077 		intel_color_post_update(new_crtc_state);
1078 
1079 	if (audio_enabling(old_crtc_state, new_crtc_state))
1080 		intel_encoders_audio_enable(state, crtc);
1081 }
1082 
1083 static void intel_post_plane_update_after_readout(struct intel_atomic_state *state,
1084 						  struct intel_crtc *crtc)
1085 {
1086 	const struct intel_crtc_state *new_crtc_state =
1087 		intel_atomic_get_new_crtc_state(state, crtc);
1088 
1089 	/* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
1090 	hsw_ips_post_update(state, crtc);
1091 
1092 	/*
1093 	 * Activate DRRS after state readout to avoid
1094 	 * dp_m_n vs. dp_m2_n2 confusion on BDW+.
1095 	 */
1096 	intel_drrs_activate(new_crtc_state);
1097 }
1098 
1099 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1100 					struct intel_crtc *crtc)
1101 {
1102 	const struct intel_crtc_state *crtc_state =
1103 		intel_atomic_get_new_crtc_state(state, crtc);
1104 	u8 update_planes = crtc_state->update_planes;
1105 	const struct intel_plane_state __maybe_unused *plane_state;
1106 	struct intel_plane *plane;
1107 	int i;
1108 
1109 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1110 		if (plane->pipe == crtc->pipe &&
1111 		    update_planes & BIT(plane->id))
1112 			plane->enable_flip_done(plane);
1113 	}
1114 }
1115 
1116 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1117 					 struct intel_crtc *crtc)
1118 {
1119 	const struct intel_crtc_state *crtc_state =
1120 		intel_atomic_get_new_crtc_state(state, crtc);
1121 	u8 update_planes = crtc_state->update_planes;
1122 	const struct intel_plane_state __maybe_unused *plane_state;
1123 	struct intel_plane *plane;
1124 	int i;
1125 
1126 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1127 		if (plane->pipe == crtc->pipe &&
1128 		    update_planes & BIT(plane->id))
1129 			plane->disable_flip_done(plane);
1130 	}
1131 }
1132 
1133 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1134 					     struct intel_crtc *crtc)
1135 {
1136 	const struct intel_crtc_state *old_crtc_state =
1137 		intel_atomic_get_old_crtc_state(state, crtc);
1138 	const struct intel_crtc_state *new_crtc_state =
1139 		intel_atomic_get_new_crtc_state(state, crtc);
1140 	u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1141 				       ~new_crtc_state->async_flip_planes;
1142 	const struct intel_plane_state *old_plane_state;
1143 	struct intel_plane *plane;
1144 	bool need_vbl_wait = false;
1145 	int i;
1146 
1147 	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1148 		if (plane->need_async_flip_toggle_wa &&
1149 		    plane->pipe == crtc->pipe &&
1150 		    disable_async_flip_planes & BIT(plane->id)) {
1151 			/*
1152 			 * Apart from the async flip bit we want to
1153 			 * preserve the old state for the plane.
1154 			 */
1155 			intel_plane_async_flip(NULL, plane,
1156 					       old_crtc_state, old_plane_state, false);
1157 			need_vbl_wait = true;
1158 		}
1159 	}
1160 
1161 	if (need_vbl_wait)
1162 		intel_crtc_wait_for_next_vblank(crtc);
1163 }
1164 
1165 static void intel_pre_plane_update(struct intel_atomic_state *state,
1166 				   struct intel_crtc *crtc)
1167 {
1168 	struct intel_display *display = to_intel_display(state);
1169 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1170 	const struct intel_crtc_state *old_crtc_state =
1171 		intel_atomic_get_old_crtc_state(state, crtc);
1172 	const struct intel_crtc_state *new_crtc_state =
1173 		intel_atomic_get_new_crtc_state(state, crtc);
1174 	enum pipe pipe = crtc->pipe;
1175 
1176 	if (intel_crtc_vrr_disabling(state, crtc)) {
1177 		intel_vrr_disable(old_crtc_state);
1178 		intel_crtc_update_active_timings(old_crtc_state, false);
1179 	}
1180 
1181 	if (audio_disabling(old_crtc_state, new_crtc_state))
1182 		intel_encoders_audio_disable(state, crtc);
1183 
1184 	intel_drrs_deactivate(old_crtc_state);
1185 
1186 	intel_psr_pre_plane_update(state, crtc);
1187 
1188 	if (hsw_ips_pre_update(state, crtc))
1189 		intel_crtc_wait_for_next_vblank(crtc);
1190 
1191 	if (intel_fbc_pre_update(state, crtc))
1192 		intel_crtc_wait_for_next_vblank(crtc);
1193 
1194 	if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1195 	    needs_async_flip_vtd_wa(new_crtc_state))
1196 		intel_async_flip_vtd_wa(display, pipe, true);
1197 
1198 	/* Display WA 827 */
1199 	if (!needs_nv12_wa(old_crtc_state) &&
1200 	    needs_nv12_wa(new_crtc_state))
1201 		skl_wa_827(display, pipe, true);
1202 
1203 	/* Wa_2006604312:icl,ehl */
1204 	if (!needs_scalerclk_wa(old_crtc_state) &&
1205 	    needs_scalerclk_wa(new_crtc_state))
1206 		icl_wa_scalerclkgating(display, pipe, true);
1207 
1208 	/* Wa_1604331009:icl,jsl,ehl */
1209 	if (!needs_cursorclk_wa(old_crtc_state) &&
1210 	    needs_cursorclk_wa(new_crtc_state))
1211 		icl_wa_cursorclkgating(display, pipe, true);
1212 
1213 	/*
1214 	 * Vblank time updates from the shadow to live plane control register
1215 	 * are blocked if the memory self-refresh mode is active at that
1216 	 * moment. So to make sure the plane gets truly disabled, disable
1217 	 * first the self-refresh mode. The self-refresh enable bit in turn
1218 	 * will be checked/applied by the HW only at the next frame start
1219 	 * event which is after the vblank start event, so we need to have a
1220 	 * wait-for-vblank between disabling the plane and the pipe.
1221 	 */
1222 	if (HAS_GMCH(display) && old_crtc_state->hw.active &&
1223 	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1224 		intel_crtc_wait_for_next_vblank(crtc);
1225 
1226 	/*
1227 	 * IVB workaround: must disable low power watermarks for at least
1228 	 * one frame before enabling scaling.  LP watermarks can be re-enabled
1229 	 * when scaling is disabled.
1230 	 *
1231 	 * WaCxSRDisabledForSpriteScaling:ivb
1232 	 */
1233 	if (!HAS_GMCH(display) && old_crtc_state->hw.active &&
1234 	    new_crtc_state->disable_cxsr && ilk_disable_cxsr(dev_priv))
1235 		intel_crtc_wait_for_next_vblank(crtc);
1236 
1237 	/*
1238 	 * If we're doing a modeset we don't need to do any
1239 	 * pre-vblank watermark programming here.
1240 	 */
1241 	if (!intel_crtc_needs_modeset(new_crtc_state)) {
1242 		/*
1243 		 * For platforms that support atomic watermarks, program the
1244 		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1245 		 * will be the intermediate values that are safe for both pre- and
1246 		 * post- vblank; when vblank happens, the 'active' values will be set
1247 		 * to the final 'target' values and we'll do this again to get the
1248 		 * optimal watermarks.  For gen9+ platforms, the values we program here
1249 		 * will be the final target values which will get automatically latched
1250 		 * at vblank time; no further programming will be necessary.
1251 		 *
1252 		 * If a platform hasn't been transitioned to atomic watermarks yet,
1253 		 * we'll continue to update watermarks the old way, if flags tell
1254 		 * us to.
1255 		 */
1256 		if (!intel_initial_watermarks(state, crtc))
1257 			if (new_crtc_state->update_wm_pre)
1258 				intel_update_watermarks(dev_priv);
1259 	}
1260 
1261 	/*
1262 	 * Gen2 reports pipe underruns whenever all planes are disabled.
1263 	 * So disable underrun reporting before all the planes get disabled.
1264 	 *
1265 	 * We do this after .initial_watermarks() so that we have a
1266 	 * chance of catching underruns with the intermediate watermarks
1267 	 * vs. the old plane configuration.
1268 	 */
1269 	if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1270 		intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
1271 
1272 	/*
1273 	 * WA for platforms where async address update enable bit
1274 	 * is double buffered and only latched at start of vblank.
1275 	 */
1276 	if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1277 		intel_crtc_async_flip_disable_wa(state, crtc);
1278 }
1279 
1280 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1281 				      struct intel_crtc *crtc)
1282 {
1283 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1284 	const struct intel_crtc_state *new_crtc_state =
1285 		intel_atomic_get_new_crtc_state(state, crtc);
1286 	unsigned int update_mask = new_crtc_state->update_planes;
1287 	const struct intel_plane_state *old_plane_state;
1288 	struct intel_plane *plane;
1289 	unsigned fb_bits = 0;
1290 	int i;
1291 
1292 	intel_crtc_dpms_overlay_disable(crtc);
1293 
1294 	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1295 		if (crtc->pipe != plane->pipe ||
1296 		    !(update_mask & BIT(plane->id)))
1297 			continue;
1298 
1299 		intel_plane_disable_arm(NULL, plane, new_crtc_state);
1300 
1301 		if (old_plane_state->uapi.visible)
1302 			fb_bits |= plane->frontbuffer_bit;
1303 	}
1304 
1305 	intel_frontbuffer_flip(dev_priv, fb_bits);
1306 }
1307 
1308 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1309 {
1310 	struct intel_display *display = to_intel_display(state);
1311 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1312 	struct intel_crtc *crtc;
1313 	int i;
1314 
1315 	/*
1316 	 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1317 	 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1318 	 */
1319 	if (display->dpll.mgr) {
1320 		for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1321 			if (intel_crtc_needs_modeset(new_crtc_state))
1322 				continue;
1323 
1324 			new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1325 			new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1326 		}
1327 	}
1328 }
1329 
1330 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1331 					  struct intel_crtc *crtc)
1332 {
1333 	const struct intel_crtc_state *crtc_state =
1334 		intel_atomic_get_new_crtc_state(state, crtc);
1335 	const struct drm_connector_state *conn_state;
1336 	struct drm_connector *conn;
1337 	int i;
1338 
1339 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1340 		struct intel_encoder *encoder =
1341 			to_intel_encoder(conn_state->best_encoder);
1342 
1343 		if (conn_state->crtc != &crtc->base)
1344 			continue;
1345 
1346 		if (encoder->pre_pll_enable)
1347 			encoder->pre_pll_enable(state, encoder,
1348 						crtc_state, conn_state);
1349 	}
1350 }
1351 
1352 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1353 				      struct intel_crtc *crtc)
1354 {
1355 	const struct intel_crtc_state *crtc_state =
1356 		intel_atomic_get_new_crtc_state(state, crtc);
1357 	const struct drm_connector_state *conn_state;
1358 	struct drm_connector *conn;
1359 	int i;
1360 
1361 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1362 		struct intel_encoder *encoder =
1363 			to_intel_encoder(conn_state->best_encoder);
1364 
1365 		if (conn_state->crtc != &crtc->base)
1366 			continue;
1367 
1368 		if (encoder->pre_enable)
1369 			encoder->pre_enable(state, encoder,
1370 					    crtc_state, conn_state);
1371 	}
1372 }
1373 
1374 static void intel_encoders_enable(struct intel_atomic_state *state,
1375 				  struct intel_crtc *crtc)
1376 {
1377 	const struct intel_crtc_state *crtc_state =
1378 		intel_atomic_get_new_crtc_state(state, crtc);
1379 	const struct drm_connector_state *conn_state;
1380 	struct drm_connector *conn;
1381 	int i;
1382 
1383 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1384 		struct intel_encoder *encoder =
1385 			to_intel_encoder(conn_state->best_encoder);
1386 
1387 		if (conn_state->crtc != &crtc->base)
1388 			continue;
1389 
1390 		if (encoder->enable)
1391 			encoder->enable(state, encoder,
1392 					crtc_state, conn_state);
1393 		intel_opregion_notify_encoder(encoder, true);
1394 	}
1395 }
1396 
1397 static void intel_encoders_disable(struct intel_atomic_state *state,
1398 				   struct intel_crtc *crtc)
1399 {
1400 	const struct intel_crtc_state *old_crtc_state =
1401 		intel_atomic_get_old_crtc_state(state, crtc);
1402 	const struct drm_connector_state *old_conn_state;
1403 	struct drm_connector *conn;
1404 	int i;
1405 
1406 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1407 		struct intel_encoder *encoder =
1408 			to_intel_encoder(old_conn_state->best_encoder);
1409 
1410 		if (old_conn_state->crtc != &crtc->base)
1411 			continue;
1412 
1413 		intel_opregion_notify_encoder(encoder, false);
1414 		if (encoder->disable)
1415 			encoder->disable(state, encoder,
1416 					 old_crtc_state, old_conn_state);
1417 	}
1418 }
1419 
1420 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1421 					struct intel_crtc *crtc)
1422 {
1423 	const struct intel_crtc_state *old_crtc_state =
1424 		intel_atomic_get_old_crtc_state(state, crtc);
1425 	const struct drm_connector_state *old_conn_state;
1426 	struct drm_connector *conn;
1427 	int i;
1428 
1429 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1430 		struct intel_encoder *encoder =
1431 			to_intel_encoder(old_conn_state->best_encoder);
1432 
1433 		if (old_conn_state->crtc != &crtc->base)
1434 			continue;
1435 
1436 		if (encoder->post_disable)
1437 			encoder->post_disable(state, encoder,
1438 					      old_crtc_state, old_conn_state);
1439 	}
1440 }
1441 
1442 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1443 					    struct intel_crtc *crtc)
1444 {
1445 	const struct intel_crtc_state *old_crtc_state =
1446 		intel_atomic_get_old_crtc_state(state, crtc);
1447 	const struct drm_connector_state *old_conn_state;
1448 	struct drm_connector *conn;
1449 	int i;
1450 
1451 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1452 		struct intel_encoder *encoder =
1453 			to_intel_encoder(old_conn_state->best_encoder);
1454 
1455 		if (old_conn_state->crtc != &crtc->base)
1456 			continue;
1457 
1458 		if (encoder->post_pll_disable)
1459 			encoder->post_pll_disable(state, encoder,
1460 						  old_crtc_state, old_conn_state);
1461 	}
1462 }
1463 
1464 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1465 				       struct intel_crtc *crtc)
1466 {
1467 	const struct intel_crtc_state *crtc_state =
1468 		intel_atomic_get_new_crtc_state(state, crtc);
1469 	const struct drm_connector_state *conn_state;
1470 	struct drm_connector *conn;
1471 	int i;
1472 
1473 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1474 		struct intel_encoder *encoder =
1475 			to_intel_encoder(conn_state->best_encoder);
1476 
1477 		if (conn_state->crtc != &crtc->base)
1478 			continue;
1479 
1480 		if (encoder->update_pipe)
1481 			encoder->update_pipe(state, encoder,
1482 					     crtc_state, conn_state);
1483 	}
1484 }
1485 
1486 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1487 {
1488 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1489 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1490 
1491 	if (crtc_state->has_pch_encoder) {
1492 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1493 					       &crtc_state->fdi_m_n);
1494 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
1495 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1496 					       &crtc_state->dp_m_n);
1497 		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1498 					       &crtc_state->dp_m2_n2);
1499 	}
1500 
1501 	intel_set_transcoder_timings(crtc_state);
1502 
1503 	ilk_set_pipeconf(crtc_state);
1504 }
1505 
1506 static void ilk_crtc_enable(struct intel_atomic_state *state,
1507 			    struct intel_crtc *crtc)
1508 {
1509 	struct intel_display *display = to_intel_display(crtc);
1510 	const struct intel_crtc_state *new_crtc_state =
1511 		intel_atomic_get_new_crtc_state(state, crtc);
1512 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1513 	enum pipe pipe = crtc->pipe;
1514 
1515 	if (drm_WARN_ON(display->drm, crtc->active))
1516 		return;
1517 
1518 	/*
1519 	 * Sometimes spurious CPU pipe underruns happen during FDI
1520 	 * training, at least with VGA+HDMI cloning. Suppress them.
1521 	 *
1522 	 * On ILK we get an occasional spurious CPU pipe underruns
1523 	 * between eDP port A enable and vdd enable. Also PCH port
1524 	 * enable seems to result in the occasional CPU pipe underrun.
1525 	 *
1526 	 * Spurious PCH underruns also occur during PCH enabling.
1527 	 */
1528 	intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
1529 	intel_set_pch_fifo_underrun_reporting(display, pipe, false);
1530 
1531 	ilk_configure_cpu_transcoder(new_crtc_state);
1532 
1533 	intel_set_pipe_src_size(new_crtc_state);
1534 
1535 	crtc->active = true;
1536 
1537 	intel_encoders_pre_enable(state, crtc);
1538 
1539 	if (new_crtc_state->has_pch_encoder) {
1540 		ilk_pch_pre_enable(state, crtc);
1541 	} else {
1542 		assert_fdi_tx_disabled(display, pipe);
1543 		assert_fdi_rx_disabled(display, pipe);
1544 	}
1545 
1546 	ilk_pfit_enable(new_crtc_state);
1547 
1548 	/*
1549 	 * On ILK+ LUT must be loaded before the pipe is running but with
1550 	 * clocks enabled
1551 	 */
1552 	intel_color_modeset(new_crtc_state);
1553 
1554 	intel_initial_watermarks(state, crtc);
1555 	intel_enable_transcoder(new_crtc_state);
1556 
1557 	if (new_crtc_state->has_pch_encoder)
1558 		ilk_pch_enable(state, crtc);
1559 
1560 	intel_crtc_vblank_on(new_crtc_state);
1561 
1562 	intel_encoders_enable(state, crtc);
1563 
1564 	if (HAS_PCH_CPT(dev_priv))
1565 		intel_wait_for_pipe_scanline_moving(crtc);
1566 
1567 	/*
1568 	 * Must wait for vblank to avoid spurious PCH FIFO underruns.
1569 	 * And a second vblank wait is needed at least on ILK with
1570 	 * some interlaced HDMI modes. Let's do the double wait always
1571 	 * in case there are more corner cases we don't know about.
1572 	 */
1573 	if (new_crtc_state->has_pch_encoder) {
1574 		intel_crtc_wait_for_next_vblank(crtc);
1575 		intel_crtc_wait_for_next_vblank(crtc);
1576 	}
1577 	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
1578 	intel_set_pch_fifo_underrun_reporting(display, pipe, true);
1579 }
1580 
1581 /* Display WA #1180: WaDisableScalarClockGating: glk */
1582 static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state)
1583 {
1584 	struct intel_display *display = to_intel_display(crtc_state);
1585 
1586 	return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;
1587 }
1588 
1589 static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)
1590 {
1591 	struct intel_display *display = to_intel_display(crtc);
1592 	u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1593 
1594 	intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe),
1595 		     mask, enable ? mask : 0);
1596 }
1597 
1598 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1599 {
1600 	struct intel_display *display = to_intel_display(crtc_state);
1601 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1602 
1603 	intel_de_write(display, WM_LINETIME(crtc->pipe),
1604 		       HSW_LINETIME(crtc_state->linetime) |
1605 		       HSW_IPS_LINETIME(crtc_state->ips_linetime));
1606 }
1607 
1608 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1609 {
1610 	struct intel_display *display = to_intel_display(crtc_state);
1611 
1612 	intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),
1613 		     HSW_FRAME_START_DELAY_MASK,
1614 		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1615 }
1616 
1617 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1618 {
1619 	struct intel_display *display = to_intel_display(crtc_state);
1620 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1621 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1622 
1623 	if (crtc_state->has_pch_encoder) {
1624 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1625 					       &crtc_state->fdi_m_n);
1626 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
1627 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1628 					       &crtc_state->dp_m_n);
1629 		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1630 					       &crtc_state->dp_m2_n2);
1631 	}
1632 
1633 	intel_set_transcoder_timings(crtc_state);
1634 	if (HAS_VRR(display))
1635 		intel_vrr_set_transcoder_timings(crtc_state);
1636 
1637 	if (cpu_transcoder != TRANSCODER_EDP)
1638 		intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
1639 			       crtc_state->pixel_multiplier - 1);
1640 
1641 	hsw_set_frame_start_delay(crtc_state);
1642 
1643 	hsw_set_transconf(crtc_state);
1644 }
1645 
1646 static void hsw_crtc_enable(struct intel_atomic_state *state,
1647 			    struct intel_crtc *crtc)
1648 {
1649 	struct intel_display *display = to_intel_display(state);
1650 	const struct intel_crtc_state *new_crtc_state =
1651 		intel_atomic_get_new_crtc_state(state, crtc);
1652 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1653 	struct intel_crtc *pipe_crtc;
1654 	int i;
1655 
1656 	if (drm_WARN_ON(display->drm, crtc->active))
1657 		return;
1658 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i)
1659 		intel_dmc_enable_pipe(display, pipe_crtc->pipe);
1660 
1661 	intel_encoders_pre_pll_enable(state, crtc);
1662 
1663 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1664 		const struct intel_crtc_state *pipe_crtc_state =
1665 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
1666 
1667 		if (pipe_crtc_state->shared_dpll)
1668 			intel_enable_shared_dpll(pipe_crtc_state);
1669 	}
1670 
1671 	intel_encoders_pre_enable(state, crtc);
1672 
1673 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1674 		const struct intel_crtc_state *pipe_crtc_state =
1675 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
1676 
1677 		intel_dsc_enable(pipe_crtc_state);
1678 
1679 		if (HAS_UNCOMPRESSED_JOINER(display))
1680 			intel_uncompressed_joiner_enable(pipe_crtc_state);
1681 
1682 		intel_set_pipe_src_size(pipe_crtc_state);
1683 
1684 		if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)
1685 			bdw_set_pipe_misc(NULL, pipe_crtc_state);
1686 	}
1687 
1688 	if (!transcoder_is_dsi(cpu_transcoder))
1689 		hsw_configure_cpu_transcoder(new_crtc_state);
1690 
1691 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1692 		const struct intel_crtc_state *pipe_crtc_state =
1693 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
1694 
1695 		pipe_crtc->active = true;
1696 
1697 		if (glk_need_scaler_clock_gating_wa(pipe_crtc_state))
1698 			glk_pipe_scaler_clock_gating_wa(pipe_crtc, true);
1699 
1700 		if (DISPLAY_VER(display) >= 9)
1701 			skl_pfit_enable(pipe_crtc_state);
1702 		else
1703 			ilk_pfit_enable(pipe_crtc_state);
1704 
1705 		/*
1706 		 * On ILK+ LUT must be loaded before the pipe is running but with
1707 		 * clocks enabled
1708 		 */
1709 		intel_color_modeset(pipe_crtc_state);
1710 
1711 		hsw_set_linetime_wm(pipe_crtc_state);
1712 
1713 		if (DISPLAY_VER(display) >= 11)
1714 			icl_set_pipe_chicken(pipe_crtc_state);
1715 
1716 		intel_initial_watermarks(state, pipe_crtc);
1717 	}
1718 
1719 	intel_encoders_enable(state, crtc);
1720 
1721 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1722 		const struct intel_crtc_state *pipe_crtc_state =
1723 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
1724 		enum pipe hsw_workaround_pipe;
1725 
1726 		if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) {
1727 			intel_crtc_wait_for_next_vblank(pipe_crtc);
1728 			glk_pipe_scaler_clock_gating_wa(pipe_crtc, false);
1729 		}
1730 
1731 		/*
1732 		 * If we change the relative order between pipe/planes
1733 		 * enabling, we need to change the workaround.
1734 		 */
1735 		hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe;
1736 		if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) {
1737 			struct intel_crtc *wa_crtc =
1738 				intel_crtc_for_pipe(display, hsw_workaround_pipe);
1739 
1740 			intel_crtc_wait_for_next_vblank(wa_crtc);
1741 			intel_crtc_wait_for_next_vblank(wa_crtc);
1742 		}
1743 	}
1744 }
1745 
1746 static void ilk_crtc_disable(struct intel_atomic_state *state,
1747 			     struct intel_crtc *crtc)
1748 {
1749 	struct intel_display *display = to_intel_display(crtc);
1750 	const struct intel_crtc_state *old_crtc_state =
1751 		intel_atomic_get_old_crtc_state(state, crtc);
1752 	enum pipe pipe = crtc->pipe;
1753 
1754 	/*
1755 	 * Sometimes spurious CPU pipe underruns happen when the
1756 	 * pipe is already disabled, but FDI RX/TX is still enabled.
1757 	 * Happens at least with VGA+HDMI cloning. Suppress them.
1758 	 */
1759 	intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
1760 	intel_set_pch_fifo_underrun_reporting(display, pipe, false);
1761 
1762 	intel_encoders_disable(state, crtc);
1763 
1764 	intel_crtc_vblank_off(old_crtc_state);
1765 
1766 	intel_disable_transcoder(old_crtc_state);
1767 
1768 	ilk_pfit_disable(old_crtc_state);
1769 
1770 	if (old_crtc_state->has_pch_encoder)
1771 		ilk_pch_disable(state, crtc);
1772 
1773 	intel_encoders_post_disable(state, crtc);
1774 
1775 	if (old_crtc_state->has_pch_encoder)
1776 		ilk_pch_post_disable(state, crtc);
1777 
1778 	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
1779 	intel_set_pch_fifo_underrun_reporting(display, pipe, true);
1780 
1781 	intel_disable_shared_dpll(old_crtc_state);
1782 }
1783 
1784 static void hsw_crtc_disable(struct intel_atomic_state *state,
1785 			     struct intel_crtc *crtc)
1786 {
1787 	struct intel_display *display = to_intel_display(state);
1788 	const struct intel_crtc_state *old_crtc_state =
1789 		intel_atomic_get_old_crtc_state(state, crtc);
1790 	struct intel_crtc *pipe_crtc;
1791 	int i;
1792 
1793 	/*
1794 	 * FIXME collapse everything to one hook.
1795 	 * Need care with mst->ddi interactions.
1796 	 */
1797 	intel_encoders_disable(state, crtc);
1798 	intel_encoders_post_disable(state, crtc);
1799 
1800 	for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
1801 		const struct intel_crtc_state *old_pipe_crtc_state =
1802 			intel_atomic_get_old_crtc_state(state, pipe_crtc);
1803 
1804 		intel_disable_shared_dpll(old_pipe_crtc_state);
1805 	}
1806 
1807 	intel_encoders_post_pll_disable(state, crtc);
1808 
1809 	for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i)
1810 		intel_dmc_disable_pipe(display, pipe_crtc->pipe);
1811 }
1812 
1813 /* Prefer intel_encoder_is_combo() */
1814 bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
1815 {
1816 	if (phy == PHY_NONE)
1817 		return false;
1818 	else if (display->platform.alderlake_s)
1819 		return phy <= PHY_E;
1820 	else if (display->platform.dg1 || display->platform.rocketlake)
1821 		return phy <= PHY_D;
1822 	else if (display->platform.jasperlake || display->platform.elkhartlake)
1823 		return phy <= PHY_C;
1824 	else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12))
1825 		return phy <= PHY_B;
1826 	else
1827 		/*
1828 		 * DG2 outputs labelled as "combo PHY" in the bspec use
1829 		 * SNPS PHYs with completely different programming,
1830 		 * hence we always return false here.
1831 		 */
1832 		return false;
1833 }
1834 
1835 /* Prefer intel_encoder_is_tc() */
1836 bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
1837 {
1838 	/*
1839 	 * Discrete GPU phy's are not attached to FIA's to support TC
1840 	 * subsystem Legacy or non-legacy, and only support native DP/HDMI
1841 	 */
1842 	if (display->platform.dgfx)
1843 		return false;
1844 
1845 	if (DISPLAY_VER(display) >= 13)
1846 		return phy >= PHY_F && phy <= PHY_I;
1847 	else if (display->platform.tigerlake)
1848 		return phy >= PHY_D && phy <= PHY_I;
1849 	else if (display->platform.icelake)
1850 		return phy >= PHY_C && phy <= PHY_F;
1851 
1852 	return false;
1853 }
1854 
1855 /* Prefer intel_encoder_is_snps() */
1856 bool intel_phy_is_snps(struct intel_display *display, enum phy phy)
1857 {
1858 	/*
1859 	 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port
1860 	 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc().
1861 	 */
1862 	return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E;
1863 }
1864 
1865 /* Prefer intel_encoder_to_phy() */
1866 enum phy intel_port_to_phy(struct intel_display *display, enum port port)
1867 {
1868 	if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD)
1869 		return PHY_D + port - PORT_D_XELPD;
1870 	else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1)
1871 		return PHY_F + port - PORT_TC1;
1872 	else if (display->platform.alderlake_s && port >= PORT_TC1)
1873 		return PHY_B + port - PORT_TC1;
1874 	else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1)
1875 		return PHY_C + port - PORT_TC1;
1876 	else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
1877 		 port == PORT_D)
1878 		return PHY_A;
1879 
1880 	return PHY_A + port - PORT_A;
1881 }
1882 
1883 /* Prefer intel_encoder_to_tc() */
1884 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port)
1885 {
1886 	if (!intel_phy_is_tc(display, intel_port_to_phy(display, port)))
1887 		return TC_PORT_NONE;
1888 
1889 	if (DISPLAY_VER(display) >= 12)
1890 		return TC_PORT_1 + port - PORT_TC1;
1891 	else
1892 		return TC_PORT_1 + port - PORT_C;
1893 }
1894 
1895 enum phy intel_encoder_to_phy(struct intel_encoder *encoder)
1896 {
1897 	struct intel_display *display = to_intel_display(encoder);
1898 
1899 	return intel_port_to_phy(display, encoder->port);
1900 }
1901 
1902 bool intel_encoder_is_combo(struct intel_encoder *encoder)
1903 {
1904 	struct intel_display *display = to_intel_display(encoder);
1905 
1906 	return intel_phy_is_combo(display, intel_encoder_to_phy(encoder));
1907 }
1908 
1909 bool intel_encoder_is_snps(struct intel_encoder *encoder)
1910 {
1911 	struct intel_display *display = to_intel_display(encoder);
1912 
1913 	return intel_phy_is_snps(display, intel_encoder_to_phy(encoder));
1914 }
1915 
1916 bool intel_encoder_is_tc(struct intel_encoder *encoder)
1917 {
1918 	struct intel_display *display = to_intel_display(encoder);
1919 
1920 	return intel_phy_is_tc(display, intel_encoder_to_phy(encoder));
1921 }
1922 
1923 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder)
1924 {
1925 	struct intel_display *display = to_intel_display(encoder);
1926 
1927 	return intel_port_to_tc(display, encoder->port);
1928 }
1929 
1930 enum intel_display_power_domain
1931 intel_aux_power_domain(struct intel_digital_port *dig_port)
1932 {
1933 	struct intel_display *display = to_intel_display(dig_port);
1934 
1935 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
1936 		return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch);
1937 
1938 	return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);
1939 }
1940 
1941 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1942 				   struct intel_power_domain_mask *mask)
1943 {
1944 	struct intel_display *display = to_intel_display(crtc_state);
1945 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1946 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1947 	struct drm_encoder *encoder;
1948 	enum pipe pipe = crtc->pipe;
1949 
1950 	bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
1951 
1952 	if (!crtc_state->hw.active)
1953 		return;
1954 
1955 	set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
1956 	set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
1957 	if (crtc_state->pch_pfit.enabled ||
1958 	    crtc_state->pch_pfit.force_thru)
1959 		set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
1960 
1961 	drm_for_each_encoder_mask(encoder, display->drm,
1962 				  crtc_state->uapi.encoder_mask) {
1963 		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1964 
1965 		set_bit(intel_encoder->power_domain, mask->bits);
1966 	}
1967 
1968 	if (HAS_DDI(display) && crtc_state->has_audio)
1969 		set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
1970 
1971 	if (crtc_state->shared_dpll)
1972 		set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
1973 
1974 	if (crtc_state->dsc.compression_enable)
1975 		set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
1976 }
1977 
1978 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1979 					  struct intel_power_domain_mask *old_domains)
1980 {
1981 	struct intel_display *display = to_intel_display(crtc_state);
1982 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1983 	enum intel_display_power_domain domain;
1984 	struct intel_power_domain_mask domains, new_domains;
1985 
1986 	get_crtc_power_domains(crtc_state, &domains);
1987 
1988 	bitmap_andnot(new_domains.bits,
1989 		      domains.bits,
1990 		      crtc->enabled_power_domains.mask.bits,
1991 		      POWER_DOMAIN_NUM);
1992 	bitmap_andnot(old_domains->bits,
1993 		      crtc->enabled_power_domains.mask.bits,
1994 		      domains.bits,
1995 		      POWER_DOMAIN_NUM);
1996 
1997 	for_each_power_domain(domain, &new_domains)
1998 		intel_display_power_get_in_set(display,
1999 					       &crtc->enabled_power_domains,
2000 					       domain);
2001 }
2002 
2003 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
2004 					  struct intel_power_domain_mask *domains)
2005 {
2006 	struct intel_display *display = to_intel_display(crtc);
2007 
2008 	intel_display_power_put_mask_in_set(display,
2009 					    &crtc->enabled_power_domains,
2010 					    domains);
2011 }
2012 
2013 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2014 {
2015 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2016 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2017 
2018 	if (intel_crtc_has_dp_encoder(crtc_state)) {
2019 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2020 					       &crtc_state->dp_m_n);
2021 		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2022 					       &crtc_state->dp_m2_n2);
2023 	}
2024 
2025 	intel_set_transcoder_timings(crtc_state);
2026 
2027 	i9xx_set_pipeconf(crtc_state);
2028 }
2029 
2030 static void valleyview_crtc_enable(struct intel_atomic_state *state,
2031 				   struct intel_crtc *crtc)
2032 {
2033 	struct intel_display *display = to_intel_display(crtc);
2034 	const struct intel_crtc_state *new_crtc_state =
2035 		intel_atomic_get_new_crtc_state(state, crtc);
2036 	enum pipe pipe = crtc->pipe;
2037 
2038 	if (drm_WARN_ON(display->drm, crtc->active))
2039 		return;
2040 
2041 	i9xx_configure_cpu_transcoder(new_crtc_state);
2042 
2043 	intel_set_pipe_src_size(new_crtc_state);
2044 
2045 	intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0);
2046 
2047 	if (display->platform.cherryview && pipe == PIPE_B) {
2048 		intel_de_write(display, CHV_BLEND(display, pipe),
2049 			       CHV_BLEND_LEGACY);
2050 		intel_de_write(display, CHV_CANVAS(display, pipe), 0);
2051 	}
2052 
2053 	crtc->active = true;
2054 
2055 	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
2056 
2057 	intel_encoders_pre_pll_enable(state, crtc);
2058 
2059 	if (display->platform.cherryview)
2060 		chv_enable_pll(new_crtc_state);
2061 	else
2062 		vlv_enable_pll(new_crtc_state);
2063 
2064 	intel_encoders_pre_enable(state, crtc);
2065 
2066 	i9xx_pfit_enable(new_crtc_state);
2067 
2068 	intel_color_modeset(new_crtc_state);
2069 
2070 	intel_initial_watermarks(state, crtc);
2071 	intel_enable_transcoder(new_crtc_state);
2072 
2073 	intel_crtc_vblank_on(new_crtc_state);
2074 
2075 	intel_encoders_enable(state, crtc);
2076 }
2077 
2078 static void i9xx_crtc_enable(struct intel_atomic_state *state,
2079 			     struct intel_crtc *crtc)
2080 {
2081 	struct intel_display *display = to_intel_display(crtc);
2082 	const struct intel_crtc_state *new_crtc_state =
2083 		intel_atomic_get_new_crtc_state(state, crtc);
2084 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2085 	enum pipe pipe = crtc->pipe;
2086 
2087 	if (drm_WARN_ON(display->drm, crtc->active))
2088 		return;
2089 
2090 	i9xx_configure_cpu_transcoder(new_crtc_state);
2091 
2092 	intel_set_pipe_src_size(new_crtc_state);
2093 
2094 	crtc->active = true;
2095 
2096 	if (DISPLAY_VER(display) != 2)
2097 		intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
2098 
2099 	intel_encoders_pre_enable(state, crtc);
2100 
2101 	i9xx_enable_pll(new_crtc_state);
2102 
2103 	i9xx_pfit_enable(new_crtc_state);
2104 
2105 	intel_color_modeset(new_crtc_state);
2106 
2107 	if (!intel_initial_watermarks(state, crtc))
2108 		intel_update_watermarks(dev_priv);
2109 	intel_enable_transcoder(new_crtc_state);
2110 
2111 	intel_crtc_vblank_on(new_crtc_state);
2112 
2113 	intel_encoders_enable(state, crtc);
2114 
2115 	/* prevents spurious underruns */
2116 	if (DISPLAY_VER(display) == 2)
2117 		intel_crtc_wait_for_next_vblank(crtc);
2118 }
2119 
2120 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2121 			      struct intel_crtc *crtc)
2122 {
2123 	struct intel_display *display = to_intel_display(state);
2124 	struct drm_i915_private *dev_priv = to_i915(display->drm);
2125 	struct intel_crtc_state *old_crtc_state =
2126 		intel_atomic_get_old_crtc_state(state, crtc);
2127 	enum pipe pipe = crtc->pipe;
2128 
2129 	/*
2130 	 * On gen2 planes are double buffered but the pipe isn't, so we must
2131 	 * wait for planes to fully turn off before disabling the pipe.
2132 	 */
2133 	if (DISPLAY_VER(display) == 2)
2134 		intel_crtc_wait_for_next_vblank(crtc);
2135 
2136 	intel_encoders_disable(state, crtc);
2137 
2138 	intel_crtc_vblank_off(old_crtc_state);
2139 
2140 	intel_disable_transcoder(old_crtc_state);
2141 
2142 	i9xx_pfit_disable(old_crtc_state);
2143 
2144 	intel_encoders_post_disable(state, crtc);
2145 
2146 	if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2147 		if (display->platform.cherryview)
2148 			chv_disable_pll(dev_priv, pipe);
2149 		else if (display->platform.valleyview)
2150 			vlv_disable_pll(dev_priv, pipe);
2151 		else
2152 			i9xx_disable_pll(old_crtc_state);
2153 	}
2154 
2155 	intel_encoders_post_pll_disable(state, crtc);
2156 
2157 	if (DISPLAY_VER(display) != 2)
2158 		intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
2159 
2160 	if (!display->funcs.wm->initial_watermarks)
2161 		intel_update_watermarks(dev_priv);
2162 
2163 	/* clock the pipe down to 640x480@60 to potentially save power */
2164 	if (display->platform.i830)
2165 		i830_enable_pipe(display, pipe);
2166 }
2167 
2168 void intel_encoder_destroy(struct drm_encoder *encoder)
2169 {
2170 	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2171 
2172 	drm_encoder_cleanup(encoder);
2173 	kfree(intel_encoder);
2174 }
2175 
2176 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2177 {
2178 	struct intel_display *display = to_intel_display(crtc);
2179 
2180 	/* GDG double wide on either pipe, otherwise pipe A only */
2181 	return HAS_DOUBLE_WIDE(display) &&
2182 		(crtc->pipe == PIPE_A || display->platform.i915g);
2183 }
2184 
2185 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2186 {
2187 	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2188 	struct drm_rect src;
2189 
2190 	/*
2191 	 * We only use IF-ID interlacing. If we ever use
2192 	 * PF-ID we'll need to adjust the pixel_rate here.
2193 	 */
2194 
2195 	if (!crtc_state->pch_pfit.enabled)
2196 		return pixel_rate;
2197 
2198 	drm_rect_init(&src, 0, 0,
2199 		      drm_rect_width(&crtc_state->pipe_src) << 16,
2200 		      drm_rect_height(&crtc_state->pipe_src) << 16);
2201 
2202 	return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2203 				   pixel_rate);
2204 }
2205 
2206 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2207 					 const struct drm_display_mode *timings)
2208 {
2209 	mode->hdisplay = timings->crtc_hdisplay;
2210 	mode->htotal = timings->crtc_htotal;
2211 	mode->hsync_start = timings->crtc_hsync_start;
2212 	mode->hsync_end = timings->crtc_hsync_end;
2213 
2214 	mode->vdisplay = timings->crtc_vdisplay;
2215 	mode->vtotal = timings->crtc_vtotal;
2216 	mode->vsync_start = timings->crtc_vsync_start;
2217 	mode->vsync_end = timings->crtc_vsync_end;
2218 
2219 	mode->flags = timings->flags;
2220 	mode->type = DRM_MODE_TYPE_DRIVER;
2221 
2222 	mode->clock = timings->crtc_clock;
2223 
2224 	drm_mode_set_name(mode);
2225 }
2226 
2227 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2228 {
2229 	struct intel_display *display = to_intel_display(crtc_state);
2230 
2231 	if (HAS_GMCH(display))
2232 		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
2233 		crtc_state->pixel_rate =
2234 			crtc_state->hw.pipe_mode.crtc_clock;
2235 	else
2236 		crtc_state->pixel_rate =
2237 			ilk_pipe_pixel_rate(crtc_state);
2238 }
2239 
2240 static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2241 					struct drm_display_mode *mode)
2242 {
2243 	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2244 
2245 	if (num_pipes == 1)
2246 		return;
2247 
2248 	mode->crtc_clock /= num_pipes;
2249 	mode->crtc_hdisplay /= num_pipes;
2250 	mode->crtc_hblank_start /= num_pipes;
2251 	mode->crtc_hblank_end /= num_pipes;
2252 	mode->crtc_hsync_start /= num_pipes;
2253 	mode->crtc_hsync_end /= num_pipes;
2254 	mode->crtc_htotal /= num_pipes;
2255 }
2256 
2257 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2258 					  struct drm_display_mode *mode)
2259 {
2260 	int overlap = crtc_state->splitter.pixel_overlap;
2261 	int n = crtc_state->splitter.link_count;
2262 
2263 	if (!crtc_state->splitter.enable)
2264 		return;
2265 
2266 	/*
2267 	 * eDP MSO uses segment timings from EDID for transcoder
2268 	 * timings, but full mode for everything else.
2269 	 *
2270 	 * h_full = (h_segment - pixel_overlap) * link_count
2271 	 */
2272 	mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2273 	mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2274 	mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2275 	mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2276 	mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2277 	mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2278 	mode->crtc_clock *= n;
2279 }
2280 
2281 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2282 {
2283 	struct drm_display_mode *mode = &crtc_state->hw.mode;
2284 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2285 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2286 
2287 	/*
2288 	 * Start with the adjusted_mode crtc timings, which
2289 	 * have been filled with the transcoder timings.
2290 	 */
2291 	drm_mode_copy(pipe_mode, adjusted_mode);
2292 
2293 	/* Expand MSO per-segment transcoder timings to full */
2294 	intel_splitter_adjust_timings(crtc_state, pipe_mode);
2295 
2296 	/*
2297 	 * We want the full numbers in adjusted_mode normal timings,
2298 	 * adjusted_mode crtc timings are left with the raw transcoder
2299 	 * timings.
2300 	 */
2301 	intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2302 
2303 	/* Populate the "user" mode with full numbers */
2304 	drm_mode_copy(mode, pipe_mode);
2305 	intel_mode_from_crtc_timings(mode, mode);
2306 	mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2307 		intel_crtc_num_joined_pipes(crtc_state);
2308 	mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2309 
2310 	/* Derive per-pipe timings in case joiner is used */
2311 	intel_joiner_adjust_timings(crtc_state, pipe_mode);
2312 	intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2313 
2314 	intel_crtc_compute_pixel_rate(crtc_state);
2315 }
2316 
2317 void intel_encoder_get_config(struct intel_encoder *encoder,
2318 			      struct intel_crtc_state *crtc_state)
2319 {
2320 	encoder->get_config(encoder, crtc_state);
2321 
2322 	intel_crtc_readout_derived_state(crtc_state);
2323 }
2324 
2325 static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2326 {
2327 	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2328 	int width, height;
2329 
2330 	if (num_pipes == 1)
2331 		return;
2332 
2333 	width = drm_rect_width(&crtc_state->pipe_src);
2334 	height = drm_rect_height(&crtc_state->pipe_src);
2335 
2336 	drm_rect_init(&crtc_state->pipe_src, 0, 0,
2337 		      width / num_pipes, height);
2338 }
2339 
2340 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2341 {
2342 	struct intel_display *display = to_intel_display(crtc_state);
2343 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2344 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2345 
2346 	intel_joiner_compute_pipe_src(crtc_state);
2347 
2348 	/*
2349 	 * Pipe horizontal size must be even in:
2350 	 * - DVO ganged mode
2351 	 * - LVDS dual channel mode
2352 	 * - Double wide pipe
2353 	 */
2354 	if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2355 		if (crtc_state->double_wide) {
2356 			drm_dbg_kms(display->drm,
2357 				    "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2358 				    crtc->base.base.id, crtc->base.name);
2359 			return -EINVAL;
2360 		}
2361 
2362 		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2363 		    intel_is_dual_link_lvds(i915)) {
2364 			drm_dbg_kms(display->drm,
2365 				    "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2366 				    crtc->base.base.id, crtc->base.name);
2367 			return -EINVAL;
2368 		}
2369 	}
2370 
2371 	return 0;
2372 }
2373 
2374 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2375 {
2376 	struct intel_display *display = to_intel_display(crtc_state);
2377 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2378 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2379 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2380 	int clock_limit = display->cdclk.max_dotclk_freq;
2381 
2382 	/*
2383 	 * Start with the adjusted_mode crtc timings, which
2384 	 * have been filled with the transcoder timings.
2385 	 */
2386 	drm_mode_copy(pipe_mode, adjusted_mode);
2387 
2388 	/* Expand MSO per-segment transcoder timings to full */
2389 	intel_splitter_adjust_timings(crtc_state, pipe_mode);
2390 
2391 	/* Derive per-pipe timings in case joiner is used */
2392 	intel_joiner_adjust_timings(crtc_state, pipe_mode);
2393 	intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2394 
2395 	if (DISPLAY_VER(display) < 4) {
2396 		clock_limit = display->cdclk.max_cdclk_freq * 9 / 10;
2397 
2398 		/*
2399 		 * Enable double wide mode when the dot clock
2400 		 * is > 90% of the (display) core speed.
2401 		 */
2402 		if (intel_crtc_supports_double_wide(crtc) &&
2403 		    pipe_mode->crtc_clock > clock_limit) {
2404 			clock_limit = display->cdclk.max_dotclk_freq;
2405 			crtc_state->double_wide = true;
2406 		}
2407 	}
2408 
2409 	if (pipe_mode->crtc_clock > clock_limit) {
2410 		drm_dbg_kms(display->drm,
2411 			    "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2412 			    crtc->base.base.id, crtc->base.name,
2413 			    pipe_mode->crtc_clock, clock_limit,
2414 			    str_yes_no(crtc_state->double_wide));
2415 		return -EINVAL;
2416 	}
2417 
2418 	return 0;
2419 }
2420 
2421 static bool intel_crtc_needs_wa_14015401596(const struct intel_crtc_state *crtc_state)
2422 {
2423 	struct intel_display *display = to_intel_display(crtc_state);
2424 
2425 	return intel_vrr_possible(crtc_state) && crtc_state->has_psr &&
2426 		IS_DISPLAY_VER(display, 13, 14);
2427 }
2428 
2429 static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
2430 {
2431 	struct intel_display *display = to_intel_display(crtc_state);
2432 	int vblank_delay = 0;
2433 
2434 	if (!HAS_DSB(display))
2435 		return 0;
2436 
2437 	/* Wa_14015401596 */
2438 	if (intel_crtc_needs_wa_14015401596(crtc_state))
2439 		vblank_delay = max(vblank_delay, 1);
2440 
2441 	return vblank_delay;
2442 }
2443 
2444 static int intel_crtc_compute_vblank_delay(struct intel_atomic_state *state,
2445 					   struct intel_crtc *crtc)
2446 {
2447 	struct intel_display *display = to_intel_display(state);
2448 	struct intel_crtc_state *crtc_state =
2449 		intel_atomic_get_new_crtc_state(state, crtc);
2450 	struct drm_display_mode *adjusted_mode =
2451 		&crtc_state->hw.adjusted_mode;
2452 	int vblank_delay, max_vblank_delay;
2453 
2454 	vblank_delay = intel_crtc_vblank_delay(crtc_state);
2455 	max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1;
2456 
2457 	if (vblank_delay > max_vblank_delay) {
2458 		drm_dbg_kms(display->drm, "[CRTC:%d:%s] vblank delay (%d) exceeds max (%d)\n",
2459 			    crtc->base.base.id, crtc->base.name, vblank_delay, max_vblank_delay);
2460 		return -EINVAL;
2461 	}
2462 
2463 	adjusted_mode->crtc_vblank_start += vblank_delay;
2464 
2465 	return 0;
2466 }
2467 
2468 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2469 				     struct intel_crtc *crtc)
2470 {
2471 	struct intel_crtc_state *crtc_state =
2472 		intel_atomic_get_new_crtc_state(state, crtc);
2473 	int ret;
2474 
2475 	ret = intel_crtc_compute_vblank_delay(state, crtc);
2476 	if (ret)
2477 		return ret;
2478 
2479 	ret = intel_dpll_crtc_compute_clock(state, crtc);
2480 	if (ret)
2481 		return ret;
2482 
2483 	ret = intel_crtc_compute_pipe_src(crtc_state);
2484 	if (ret)
2485 		return ret;
2486 
2487 	ret = intel_crtc_compute_pipe_mode(crtc_state);
2488 	if (ret)
2489 		return ret;
2490 
2491 	intel_crtc_compute_pixel_rate(crtc_state);
2492 
2493 	if (crtc_state->has_pch_encoder)
2494 		return ilk_fdi_compute_config(crtc, crtc_state);
2495 
2496 	return 0;
2497 }
2498 
2499 static void
2500 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2501 {
2502 	while (*num > DATA_LINK_M_N_MASK ||
2503 	       *den > DATA_LINK_M_N_MASK) {
2504 		*num >>= 1;
2505 		*den >>= 1;
2506 	}
2507 }
2508 
2509 static void compute_m_n(u32 *ret_m, u32 *ret_n,
2510 			u32 m, u32 n, u32 constant_n)
2511 {
2512 	if (constant_n)
2513 		*ret_n = constant_n;
2514 	else
2515 		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2516 
2517 	*ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2518 	intel_reduce_m_n_ratio(ret_m, ret_n);
2519 }
2520 
2521 void
2522 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
2523 		       int pixel_clock, int link_clock,
2524 		       int bw_overhead,
2525 		       struct intel_link_m_n *m_n)
2526 {
2527 	u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
2528 	u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
2529 						  bw_overhead);
2530 	u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
2531 
2532 	/*
2533 	 * Windows/BIOS uses fixed M/N values always. Follow suit.
2534 	 *
2535 	 * Also several DP dongles in particular seem to be fussy
2536 	 * about too large link M/N values. Presumably the 20bit
2537 	 * value used by Windows/BIOS is acceptable to everyone.
2538 	 */
2539 	m_n->tu = 64;
2540 	compute_m_n(&m_n->data_m, &m_n->data_n,
2541 		    data_m, data_n,
2542 		    0x8000000);
2543 
2544 	compute_m_n(&m_n->link_m, &m_n->link_n,
2545 		    pixel_clock, link_symbol_clock,
2546 		    0x80000);
2547 }
2548 
2549 void intel_panel_sanitize_ssc(struct intel_display *display)
2550 {
2551 	struct drm_i915_private *dev_priv = to_i915(display->drm);
2552 
2553 	/*
2554 	 * There may be no VBT; and if the BIOS enabled SSC we can
2555 	 * just keep using it to avoid unnecessary flicker.  Whereas if the
2556 	 * BIOS isn't using it, don't assume it will work even if the VBT
2557 	 * indicates as much.
2558 	 */
2559 	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2560 		bool bios_lvds_use_ssc = intel_de_read(display,
2561 						       PCH_DREF_CONTROL) &
2562 			DREF_SSC1_ENABLE;
2563 
2564 		if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2565 			drm_dbg_kms(display->drm,
2566 				    "SSC %s by BIOS, overriding VBT which says %s\n",
2567 				    str_enabled_disabled(bios_lvds_use_ssc),
2568 				    str_enabled_disabled(display->vbt.lvds_use_ssc));
2569 			display->vbt.lvds_use_ssc = bios_lvds_use_ssc;
2570 		}
2571 	}
2572 }
2573 
2574 void intel_zero_m_n(struct intel_link_m_n *m_n)
2575 {
2576 	/* corresponds to 0 register value */
2577 	memset(m_n, 0, sizeof(*m_n));
2578 	m_n->tu = 1;
2579 }
2580 
2581 void intel_set_m_n(struct intel_display *display,
2582 		   const struct intel_link_m_n *m_n,
2583 		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2584 		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2585 {
2586 	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2587 	intel_de_write(display, data_n_reg, m_n->data_n);
2588 	intel_de_write(display, link_m_reg, m_n->link_m);
2589 	/*
2590 	 * On BDW+ writing LINK_N arms the double buffered update
2591 	 * of all the M/N registers, so it must be written last.
2592 	 */
2593 	intel_de_write(display, link_n_reg, m_n->link_n);
2594 }
2595 
2596 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
2597 				    enum transcoder transcoder)
2598 {
2599 	if (display->platform.haswell)
2600 		return transcoder == TRANSCODER_EDP;
2601 
2602 	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
2603 }
2604 
2605 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2606 				    enum transcoder transcoder,
2607 				    const struct intel_link_m_n *m_n)
2608 {
2609 	struct intel_display *display = to_intel_display(crtc);
2610 	enum pipe pipe = crtc->pipe;
2611 
2612 	if (DISPLAY_VER(display) >= 5)
2613 		intel_set_m_n(display, m_n,
2614 			      PIPE_DATA_M1(display, transcoder),
2615 			      PIPE_DATA_N1(display, transcoder),
2616 			      PIPE_LINK_M1(display, transcoder),
2617 			      PIPE_LINK_N1(display, transcoder));
2618 	else
2619 		intel_set_m_n(display, m_n,
2620 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2621 			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2622 }
2623 
2624 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2625 				    enum transcoder transcoder,
2626 				    const struct intel_link_m_n *m_n)
2627 {
2628 	struct intel_display *display = to_intel_display(crtc);
2629 
2630 	if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
2631 		return;
2632 
2633 	intel_set_m_n(display, m_n,
2634 		      PIPE_DATA_M2(display, transcoder),
2635 		      PIPE_DATA_N2(display, transcoder),
2636 		      PIPE_LINK_M2(display, transcoder),
2637 		      PIPE_LINK_N2(display, transcoder));
2638 }
2639 
2640 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2641 {
2642 	struct intel_display *display = to_intel_display(crtc_state);
2643 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2644 	enum pipe pipe = crtc->pipe;
2645 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2646 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2647 	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2648 	int vsyncshift = 0;
2649 
2650 	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
2651 
2652 	/* We need to be careful not to changed the adjusted mode, for otherwise
2653 	 * the hw state checker will get angry at the mismatch. */
2654 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2655 	crtc_vtotal = adjusted_mode->crtc_vtotal;
2656 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2657 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2658 
2659 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2660 		/* the chip adds 2 halflines automatically */
2661 		crtc_vtotal -= 1;
2662 		crtc_vblank_end -= 1;
2663 
2664 		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2665 			vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2666 		else
2667 			vsyncshift = adjusted_mode->crtc_hsync_start -
2668 				adjusted_mode->crtc_htotal / 2;
2669 		if (vsyncshift < 0)
2670 			vsyncshift += adjusted_mode->crtc_htotal;
2671 	}
2672 
2673 	/*
2674 	 * VBLANK_START no longer works on ADL+, instead we must use
2675 	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2676 	 */
2677 	if (DISPLAY_VER(display) >= 13) {
2678 		intel_de_write(display,
2679 			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
2680 			       crtc_vblank_start - crtc_vdisplay);
2681 
2682 		/*
2683 		 * VBLANK_START not used by hw, just clear it
2684 		 * to make it stand out in register dumps.
2685 		 */
2686 		crtc_vblank_start = 1;
2687 	}
2688 
2689 	if (DISPLAY_VER(display) >= 4)
2690 		intel_de_write(display,
2691 			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
2692 			       vsyncshift);
2693 
2694 	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
2695 		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2696 		       HTOTAL(adjusted_mode->crtc_htotal - 1));
2697 	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
2698 		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2699 		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2700 	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
2701 		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2702 		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2703 
2704 	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
2705 		       VACTIVE(crtc_vdisplay - 1) |
2706 		       VTOTAL(crtc_vtotal - 1));
2707 	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
2708 		       VBLANK_START(crtc_vblank_start - 1) |
2709 		       VBLANK_END(crtc_vblank_end - 1));
2710 	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
2711 		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2712 		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2713 
2714 	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2715 	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2716 	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
2717 	 * bits. */
2718 	if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&
2719 	    (pipe == PIPE_B || pipe == PIPE_C))
2720 		intel_de_write(display, TRANS_VTOTAL(display, pipe),
2721 			       VACTIVE(crtc_vdisplay - 1) |
2722 			       VTOTAL(crtc_vtotal - 1));
2723 }
2724 
2725 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
2726 {
2727 	struct intel_display *display = to_intel_display(crtc_state);
2728 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2729 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2730 	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2731 
2732 	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
2733 
2734 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2735 	crtc_vtotal = adjusted_mode->crtc_vtotal;
2736 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2737 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2738 
2739 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2740 		/* the chip adds 2 halflines automatically */
2741 		crtc_vtotal -= 1;
2742 		crtc_vblank_end -= 1;
2743 	}
2744 
2745 	if (DISPLAY_VER(display) >= 13) {
2746 		intel_de_write(display,
2747 			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
2748 			       crtc_vblank_start - crtc_vdisplay);
2749 
2750 		/*
2751 		 * VBLANK_START not used by hw, just clear it
2752 		 * to make it stand out in register dumps.
2753 		 */
2754 		crtc_vblank_start = 1;
2755 	}
2756 
2757 	/*
2758 	 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2759 	 * But let's write it anyway to keep the state checker happy.
2760 	 */
2761 	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
2762 		       VBLANK_START(crtc_vblank_start - 1) |
2763 		       VBLANK_END(crtc_vblank_end - 1));
2764 	/*
2765 	 * The double buffer latch point for TRANS_VTOTAL
2766 	 * is the transcoder's undelayed vblank.
2767 	 */
2768 	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
2769 		       VACTIVE(crtc_vdisplay - 1) |
2770 		       VTOTAL(crtc_vtotal - 1));
2771 }
2772 
2773 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2774 {
2775 	struct intel_display *display = to_intel_display(crtc_state);
2776 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2777 	int width = drm_rect_width(&crtc_state->pipe_src);
2778 	int height = drm_rect_height(&crtc_state->pipe_src);
2779 	enum pipe pipe = crtc->pipe;
2780 
2781 	/* pipesrc controls the size that is scaled from, which should
2782 	 * always be the user's requested size.
2783 	 */
2784 	intel_de_write(display, PIPESRC(display, pipe),
2785 		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2786 }
2787 
2788 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2789 {
2790 	struct intel_display *display = to_intel_display(crtc_state);
2791 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2792 
2793 	if (DISPLAY_VER(display) == 2)
2794 		return false;
2795 
2796 	if (DISPLAY_VER(display) >= 9 ||
2797 	    display->platform.broadwell || display->platform.haswell)
2798 		return intel_de_read(display,
2799 				     TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2800 	else
2801 		return intel_de_read(display,
2802 				     TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2803 }
2804 
2805 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2806 					 struct intel_crtc_state *pipe_config)
2807 {
2808 	struct intel_display *display = to_intel_display(crtc);
2809 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2810 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2811 	u32 tmp;
2812 
2813 	tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder));
2814 	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2815 	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2816 
2817 	if (!transcoder_is_dsi(cpu_transcoder)) {
2818 		tmp = intel_de_read(display,
2819 				    TRANS_HBLANK(display, cpu_transcoder));
2820 		adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2821 		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2822 	}
2823 
2824 	tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder));
2825 	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2826 	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2827 
2828 	tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
2829 	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2830 	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2831 
2832 	/* FIXME TGL+ DSI transcoders have this! */
2833 	if (!transcoder_is_dsi(cpu_transcoder)) {
2834 		tmp = intel_de_read(display,
2835 				    TRANS_VBLANK(display, cpu_transcoder));
2836 		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2837 		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2838 	}
2839 	tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder));
2840 	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2841 	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2842 
2843 	if (intel_pipe_is_interlaced(pipe_config)) {
2844 		adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2845 		adjusted_mode->crtc_vtotal += 1;
2846 		adjusted_mode->crtc_vblank_end += 1;
2847 	}
2848 
2849 	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder))
2850 		adjusted_mode->crtc_vblank_start =
2851 			adjusted_mode->crtc_vdisplay +
2852 			intel_de_read(display,
2853 				      TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));
2854 }
2855 
2856 static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2857 {
2858 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2859 	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2860 	enum pipe primary_pipe, pipe = crtc->pipe;
2861 	int width;
2862 
2863 	if (num_pipes == 1)
2864 		return;
2865 
2866 	primary_pipe = joiner_primary_pipe(crtc_state);
2867 	width = drm_rect_width(&crtc_state->pipe_src);
2868 
2869 	drm_rect_translate_to(&crtc_state->pipe_src,
2870 			      (pipe - primary_pipe) * width, 0);
2871 }
2872 
2873 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2874 				    struct intel_crtc_state *pipe_config)
2875 {
2876 	struct intel_display *display = to_intel_display(crtc);
2877 	u32 tmp;
2878 
2879 	tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));
2880 
2881 	drm_rect_init(&pipe_config->pipe_src, 0, 0,
2882 		      REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2883 		      REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2884 
2885 	intel_joiner_adjust_pipe_src(pipe_config);
2886 }
2887 
2888 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2889 {
2890 	struct intel_display *display = to_intel_display(crtc_state);
2891 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2892 	u32 val = 0;
2893 
2894 	/*
2895 	 * - We keep both pipes enabled on 830
2896 	 * - During modeset the pipe is still disabled and must remain so
2897 	 * - During fastset the pipe is already enabled and must remain so
2898 	 */
2899 	if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state))
2900 		val |= TRANSCONF_ENABLE;
2901 
2902 	if (crtc_state->double_wide)
2903 		val |= TRANSCONF_DOUBLE_WIDE;
2904 
2905 	/* only g4x and later have fancy bpc/dither controls */
2906 	if (display->platform.g4x || display->platform.valleyview ||
2907 	    display->platform.cherryview) {
2908 		/* Bspec claims that we can't use dithering for 30bpp pipes. */
2909 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2910 			val |= TRANSCONF_DITHER_EN |
2911 				TRANSCONF_DITHER_TYPE_SP;
2912 
2913 		switch (crtc_state->pipe_bpp) {
2914 		default:
2915 			/* Case prevented by intel_choose_pipe_bpp_dither. */
2916 			MISSING_CASE(crtc_state->pipe_bpp);
2917 			fallthrough;
2918 		case 18:
2919 			val |= TRANSCONF_BPC_6;
2920 			break;
2921 		case 24:
2922 			val |= TRANSCONF_BPC_8;
2923 			break;
2924 		case 30:
2925 			val |= TRANSCONF_BPC_10;
2926 			break;
2927 		}
2928 	}
2929 
2930 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2931 		if (DISPLAY_VER(display) < 4 ||
2932 		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2933 			val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2934 		else
2935 			val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2936 	} else {
2937 		val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2938 	}
2939 
2940 	if ((display->platform.valleyview || display->platform.cherryview) &&
2941 	    crtc_state->limited_color_range)
2942 		val |= TRANSCONF_COLOR_RANGE_SELECT;
2943 
2944 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2945 
2946 	if (crtc_state->wgc_enable)
2947 		val |= TRANSCONF_WGC_ENABLE;
2948 
2949 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2950 
2951 	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
2952 	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
2953 }
2954 
2955 static enum intel_output_format
2956 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
2957 {
2958 	struct intel_display *display = to_intel_display(crtc);
2959 	u32 tmp;
2960 
2961 	tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
2962 
2963 	if (tmp & PIPE_MISC_YUV420_ENABLE) {
2964 		/*
2965 		 * We support 4:2:0 in full blend mode only.
2966 		 * For xe3_lpd+ this is implied in YUV420 Enable bit.
2967 		 * Ensure the same for prior platforms in YUV420 Mode bit.
2968 		 */
2969 		if (DISPLAY_VER(display) < 30)
2970 			drm_WARN_ON(display->drm,
2971 				    (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
2972 
2973 		return INTEL_OUTPUT_FORMAT_YCBCR420;
2974 	} else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
2975 		return INTEL_OUTPUT_FORMAT_YCBCR444;
2976 	} else {
2977 		return INTEL_OUTPUT_FORMAT_RGB;
2978 	}
2979 }
2980 
2981 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
2982 				 struct intel_crtc_state *pipe_config)
2983 {
2984 	struct intel_display *display = to_intel_display(crtc);
2985 	enum intel_display_power_domain power_domain;
2986 	enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;
2987 	intel_wakeref_t wakeref;
2988 	bool ret = false;
2989 	u32 tmp;
2990 
2991 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
2992 	wakeref = intel_display_power_get_if_enabled(display, power_domain);
2993 	if (!wakeref)
2994 		return false;
2995 
2996 	tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
2997 	if (!(tmp & TRANSCONF_ENABLE))
2998 		goto out;
2999 
3000 	pipe_config->cpu_transcoder = cpu_transcoder;
3001 
3002 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3003 	pipe_config->sink_format = pipe_config->output_format;
3004 
3005 	if (display->platform.g4x || display->platform.valleyview ||
3006 	    display->platform.cherryview) {
3007 		switch (tmp & TRANSCONF_BPC_MASK) {
3008 		case TRANSCONF_BPC_6:
3009 			pipe_config->pipe_bpp = 18;
3010 			break;
3011 		case TRANSCONF_BPC_8:
3012 			pipe_config->pipe_bpp = 24;
3013 			break;
3014 		case TRANSCONF_BPC_10:
3015 			pipe_config->pipe_bpp = 30;
3016 			break;
3017 		default:
3018 			MISSING_CASE(tmp);
3019 			break;
3020 		}
3021 	}
3022 
3023 	if ((display->platform.valleyview || display->platform.cherryview) &&
3024 	    (tmp & TRANSCONF_COLOR_RANGE_SELECT))
3025 		pipe_config->limited_color_range = true;
3026 
3027 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
3028 
3029 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3030 
3031 	if ((display->platform.valleyview || display->platform.cherryview) &&
3032 	    (tmp & TRANSCONF_WGC_ENABLE))
3033 		pipe_config->wgc_enable = true;
3034 
3035 	intel_color_get_config(pipe_config);
3036 
3037 	if (HAS_DOUBLE_WIDE(display))
3038 		pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
3039 
3040 	intel_get_transcoder_timings(crtc, pipe_config);
3041 	intel_get_pipe_src_size(crtc, pipe_config);
3042 
3043 	i9xx_pfit_get_config(pipe_config);
3044 
3045 	i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);
3046 
3047 	if (DISPLAY_VER(display) >= 4) {
3048 		tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;
3049 		pipe_config->pixel_multiplier =
3050 			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3051 			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3052 	} else if (display->platform.i945g || display->platform.i945gm ||
3053 		   display->platform.g33 || display->platform.pineview) {
3054 		tmp = pipe_config->dpll_hw_state.i9xx.dpll;
3055 		pipe_config->pixel_multiplier =
3056 			((tmp & SDVO_MULTIPLIER_MASK)
3057 			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3058 	} else {
3059 		/* Note that on i915G/GM the pixel multiplier is in the sdvo
3060 		 * port and will be fixed up in the encoder->get_config
3061 		 * function. */
3062 		pipe_config->pixel_multiplier = 1;
3063 	}
3064 
3065 	if (display->platform.cherryview)
3066 		chv_crtc_clock_get(pipe_config);
3067 	else if (display->platform.valleyview)
3068 		vlv_crtc_clock_get(pipe_config);
3069 	else
3070 		i9xx_crtc_clock_get(pipe_config);
3071 
3072 	/*
3073 	 * Normally the dotclock is filled in by the encoder .get_config()
3074 	 * but in case the pipe is enabled w/o any ports we need a sane
3075 	 * default.
3076 	 */
3077 	pipe_config->hw.adjusted_mode.crtc_clock =
3078 		pipe_config->port_clock / pipe_config->pixel_multiplier;
3079 
3080 	ret = true;
3081 
3082 out:
3083 	intel_display_power_put(display, power_domain, wakeref);
3084 
3085 	return ret;
3086 }
3087 
3088 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3089 {
3090 	struct intel_display *display = to_intel_display(crtc_state);
3091 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3092 	u32 val = 0;
3093 
3094 	/*
3095 	 * - During modeset the pipe is still disabled and must remain so
3096 	 * - During fastset the pipe is already enabled and must remain so
3097 	 */
3098 	if (!intel_crtc_needs_modeset(crtc_state))
3099 		val |= TRANSCONF_ENABLE;
3100 
3101 	switch (crtc_state->pipe_bpp) {
3102 	default:
3103 		/* Case prevented by intel_choose_pipe_bpp_dither. */
3104 		MISSING_CASE(crtc_state->pipe_bpp);
3105 		fallthrough;
3106 	case 18:
3107 		val |= TRANSCONF_BPC_6;
3108 		break;
3109 	case 24:
3110 		val |= TRANSCONF_BPC_8;
3111 		break;
3112 	case 30:
3113 		val |= TRANSCONF_BPC_10;
3114 		break;
3115 	case 36:
3116 		val |= TRANSCONF_BPC_12;
3117 		break;
3118 	}
3119 
3120 	if (crtc_state->dither)
3121 		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3122 
3123 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3124 		val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3125 	else
3126 		val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3127 
3128 	/*
3129 	 * This would end up with an odd purple hue over
3130 	 * the entire display. Make sure we don't do it.
3131 	 */
3132 	drm_WARN_ON(display->drm, crtc_state->limited_color_range &&
3133 		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3134 
3135 	if (crtc_state->limited_color_range &&
3136 	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3137 		val |= TRANSCONF_COLOR_RANGE_SELECT;
3138 
3139 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3140 		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3141 
3142 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3143 
3144 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3145 	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3146 
3147 	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
3148 	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
3149 }
3150 
3151 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3152 {
3153 	struct intel_display *display = to_intel_display(crtc_state);
3154 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3155 	u32 val = 0;
3156 
3157 	/*
3158 	 * - During modeset the pipe is still disabled and must remain so
3159 	 * - During fastset the pipe is already enabled and must remain so
3160 	 */
3161 	if (!intel_crtc_needs_modeset(crtc_state))
3162 		val |= TRANSCONF_ENABLE;
3163 
3164 	if (display->platform.haswell && crtc_state->dither)
3165 		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3166 
3167 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3168 		val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3169 	else
3170 		val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3171 
3172 	if (display->platform.haswell &&
3173 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3174 		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3175 
3176 	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
3177 	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
3178 }
3179 
3180 static void bdw_set_pipe_misc(struct intel_dsb *dsb,
3181 			      const struct intel_crtc_state *crtc_state)
3182 {
3183 	struct intel_display *display = to_intel_display(crtc_state);
3184 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3185 	u32 val = 0;
3186 
3187 	switch (crtc_state->pipe_bpp) {
3188 	case 18:
3189 		val |= PIPE_MISC_BPC_6;
3190 		break;
3191 	case 24:
3192 		val |= PIPE_MISC_BPC_8;
3193 		break;
3194 	case 30:
3195 		val |= PIPE_MISC_BPC_10;
3196 		break;
3197 	case 36:
3198 		/* Port output 12BPC defined for ADLP+ */
3199 		if (DISPLAY_VER(display) >= 13)
3200 			val |= PIPE_MISC_BPC_12_ADLP;
3201 		break;
3202 	default:
3203 		MISSING_CASE(crtc_state->pipe_bpp);
3204 		break;
3205 	}
3206 
3207 	if (crtc_state->dither)
3208 		val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3209 
3210 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3211 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3212 		val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3213 
3214 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3215 		val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE :
3216 			PIPE_MISC_YUV420_ENABLE | PIPE_MISC_YUV420_MODE_FULL_BLEND;
3217 
3218 	if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state))
3219 		val |= PIPE_MISC_HDR_MODE_PRECISION;
3220 
3221 	if (DISPLAY_VER(display) >= 12)
3222 		val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3223 
3224 	/* allow PSR with sprite enabled */
3225 	if (display->platform.broadwell)
3226 		val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;
3227 
3228 	intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);
3229 }
3230 
3231 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3232 {
3233 	struct intel_display *display = to_intel_display(crtc);
3234 	u32 tmp;
3235 
3236 	tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
3237 
3238 	switch (tmp & PIPE_MISC_BPC_MASK) {
3239 	case PIPE_MISC_BPC_6:
3240 		return 18;
3241 	case PIPE_MISC_BPC_8:
3242 		return 24;
3243 	case PIPE_MISC_BPC_10:
3244 		return 30;
3245 	/*
3246 	 * PORT OUTPUT 12 BPC defined for ADLP+.
3247 	 *
3248 	 * TODO:
3249 	 * For previous platforms with DSI interface, bits 5:7
3250 	 * are used for storing pipe_bpp irrespective of dithering.
3251 	 * Since the value of 12 BPC is not defined for these bits
3252 	 * on older platforms, need to find a workaround for 12 BPC
3253 	 * MIPI DSI HW readout.
3254 	 */
3255 	case PIPE_MISC_BPC_12_ADLP:
3256 		if (DISPLAY_VER(display) >= 13)
3257 			return 36;
3258 		fallthrough;
3259 	default:
3260 		MISSING_CASE(tmp);
3261 		return 0;
3262 	}
3263 }
3264 
3265 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3266 {
3267 	/*
3268 	 * Account for spread spectrum to avoid
3269 	 * oversubscribing the link. Max center spread
3270 	 * is 2.5%; use 5% for safety's sake.
3271 	 */
3272 	u32 bps = target_clock * bpp * 21 / 20;
3273 	return DIV_ROUND_UP(bps, link_bw * 8);
3274 }
3275 
3276 void intel_get_m_n(struct intel_display *display,
3277 		   struct intel_link_m_n *m_n,
3278 		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3279 		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3280 {
3281 	m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
3282 	m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
3283 	m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
3284 	m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
3285 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
3286 }
3287 
3288 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3289 				    enum transcoder transcoder,
3290 				    struct intel_link_m_n *m_n)
3291 {
3292 	struct intel_display *display = to_intel_display(crtc);
3293 	enum pipe pipe = crtc->pipe;
3294 
3295 	if (DISPLAY_VER(display) >= 5)
3296 		intel_get_m_n(display, m_n,
3297 			      PIPE_DATA_M1(display, transcoder),
3298 			      PIPE_DATA_N1(display, transcoder),
3299 			      PIPE_LINK_M1(display, transcoder),
3300 			      PIPE_LINK_N1(display, transcoder));
3301 	else
3302 		intel_get_m_n(display, m_n,
3303 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3304 			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3305 }
3306 
3307 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3308 				    enum transcoder transcoder,
3309 				    struct intel_link_m_n *m_n)
3310 {
3311 	struct intel_display *display = to_intel_display(crtc);
3312 
3313 	if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
3314 		return;
3315 
3316 	intel_get_m_n(display, m_n,
3317 		      PIPE_DATA_M2(display, transcoder),
3318 		      PIPE_DATA_N2(display, transcoder),
3319 		      PIPE_LINK_M2(display, transcoder),
3320 		      PIPE_LINK_N2(display, transcoder));
3321 }
3322 
3323 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3324 				struct intel_crtc_state *pipe_config)
3325 {
3326 	struct intel_display *display = to_intel_display(crtc);
3327 	enum intel_display_power_domain power_domain;
3328 	enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;
3329 	intel_wakeref_t wakeref;
3330 	bool ret = false;
3331 	u32 tmp;
3332 
3333 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3334 	wakeref = intel_display_power_get_if_enabled(display, power_domain);
3335 	if (!wakeref)
3336 		return false;
3337 
3338 	tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
3339 	if (!(tmp & TRANSCONF_ENABLE))
3340 		goto out;
3341 
3342 	pipe_config->cpu_transcoder = cpu_transcoder;
3343 
3344 	switch (tmp & TRANSCONF_BPC_MASK) {
3345 	case TRANSCONF_BPC_6:
3346 		pipe_config->pipe_bpp = 18;
3347 		break;
3348 	case TRANSCONF_BPC_8:
3349 		pipe_config->pipe_bpp = 24;
3350 		break;
3351 	case TRANSCONF_BPC_10:
3352 		pipe_config->pipe_bpp = 30;
3353 		break;
3354 	case TRANSCONF_BPC_12:
3355 		pipe_config->pipe_bpp = 36;
3356 		break;
3357 	default:
3358 		break;
3359 	}
3360 
3361 	if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3362 		pipe_config->limited_color_range = true;
3363 
3364 	switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3365 	case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3366 	case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3367 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3368 		break;
3369 	default:
3370 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3371 		break;
3372 	}
3373 
3374 	pipe_config->sink_format = pipe_config->output_format;
3375 
3376 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3377 
3378 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3379 
3380 	pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3381 
3382 	intel_color_get_config(pipe_config);
3383 
3384 	pipe_config->pixel_multiplier = 1;
3385 
3386 	ilk_pch_get_config(pipe_config);
3387 
3388 	intel_get_transcoder_timings(crtc, pipe_config);
3389 	intel_get_pipe_src_size(crtc, pipe_config);
3390 
3391 	ilk_pfit_get_config(pipe_config);
3392 
3393 	ret = true;
3394 
3395 out:
3396 	intel_display_power_put(display, power_domain, wakeref);
3397 
3398 	return ret;
3399 }
3400 
3401 static u8 joiner_pipes(struct intel_display *display)
3402 {
3403 	u8 pipes;
3404 
3405 	if (DISPLAY_VER(display) >= 12)
3406 		pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3407 	else if (DISPLAY_VER(display) >= 11)
3408 		pipes = BIT(PIPE_B) | BIT(PIPE_C);
3409 	else
3410 		pipes = 0;
3411 
3412 	return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask;
3413 }
3414 
3415 static bool transcoder_ddi_func_is_enabled(struct intel_display *display,
3416 					   enum transcoder cpu_transcoder)
3417 {
3418 	enum intel_display_power_domain power_domain;
3419 	intel_wakeref_t wakeref;
3420 	u32 tmp = 0;
3421 
3422 	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3423 
3424 	with_intel_display_power_if_enabled(display, power_domain, wakeref)
3425 		tmp = intel_de_read(display,
3426 				    TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
3427 
3428 	return tmp & TRANS_DDI_FUNC_ENABLE;
3429 }
3430 
3431 static void enabled_uncompressed_joiner_pipes(struct intel_display *display,
3432 					      u8 *primary_pipes, u8 *secondary_pipes)
3433 {
3434 	struct intel_crtc *crtc;
3435 
3436 	*primary_pipes = 0;
3437 	*secondary_pipes = 0;
3438 
3439 	if (!HAS_UNCOMPRESSED_JOINER(display))
3440 		return;
3441 
3442 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3443 					 joiner_pipes(display)) {
3444 		enum intel_display_power_domain power_domain;
3445 		enum pipe pipe = crtc->pipe;
3446 		intel_wakeref_t wakeref;
3447 
3448 		power_domain = POWER_DOMAIN_PIPE(pipe);
3449 		with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3450 			u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3451 
3452 			if (tmp & UNCOMPRESSED_JOINER_PRIMARY)
3453 				*primary_pipes |= BIT(pipe);
3454 			if (tmp & UNCOMPRESSED_JOINER_SECONDARY)
3455 				*secondary_pipes |= BIT(pipe);
3456 		}
3457 	}
3458 }
3459 
3460 static void enabled_bigjoiner_pipes(struct intel_display *display,
3461 				    u8 *primary_pipes, u8 *secondary_pipes)
3462 {
3463 	struct intel_crtc *crtc;
3464 
3465 	*primary_pipes = 0;
3466 	*secondary_pipes = 0;
3467 
3468 	if (!HAS_BIGJOINER(display))
3469 		return;
3470 
3471 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3472 					 joiner_pipes(display)) {
3473 		enum intel_display_power_domain power_domain;
3474 		enum pipe pipe = crtc->pipe;
3475 		intel_wakeref_t wakeref;
3476 
3477 		power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe);
3478 		with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3479 			u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3480 
3481 			if (!(tmp & BIG_JOINER_ENABLE))
3482 				continue;
3483 
3484 			if (tmp & PRIMARY_BIG_JOINER_ENABLE)
3485 				*primary_pipes |= BIT(pipe);
3486 			else
3487 				*secondary_pipes |= BIT(pipe);
3488 		}
3489 	}
3490 }
3491 
3492 static u8 expected_secondary_pipes(u8 primary_pipes, int num_pipes)
3493 {
3494 	u8 secondary_pipes = 0;
3495 
3496 	for (int i = 1; i < num_pipes; i++)
3497 		secondary_pipes |= primary_pipes << i;
3498 
3499 	return secondary_pipes;
3500 }
3501 
3502 static u8 expected_uncompressed_joiner_secondary_pipes(u8 uncompjoiner_primary_pipes)
3503 {
3504 	return expected_secondary_pipes(uncompjoiner_primary_pipes, 2);
3505 }
3506 
3507 static u8 expected_bigjoiner_secondary_pipes(u8 bigjoiner_primary_pipes)
3508 {
3509 	return expected_secondary_pipes(bigjoiner_primary_pipes, 2);
3510 }
3511 
3512 static u8 get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes)
3513 {
3514 	primary_pipes &= GENMASK(pipe, 0);
3515 
3516 	return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0;
3517 }
3518 
3519 static u8 expected_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes)
3520 {
3521 	return expected_secondary_pipes(ultrajoiner_primary_pipes, 4);
3522 }
3523 
3524 static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes,
3525 					    u8 ultrajoiner_secondary_pipes)
3526 {
3527 	return ultrajoiner_secondary_pipes | ultrajoiner_primary_pipes << 3;
3528 }
3529 
3530 static void enabled_ultrajoiner_pipes(struct intel_display *display,
3531 				      u8 *primary_pipes, u8 *secondary_pipes)
3532 {
3533 	struct intel_crtc *crtc;
3534 
3535 	*primary_pipes = 0;
3536 	*secondary_pipes = 0;
3537 
3538 	if (!HAS_ULTRAJOINER(display))
3539 		return;
3540 
3541 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3542 					 joiner_pipes(display)) {
3543 		enum intel_display_power_domain power_domain;
3544 		enum pipe pipe = crtc->pipe;
3545 		intel_wakeref_t wakeref;
3546 
3547 		power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe);
3548 		with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3549 			u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3550 
3551 			if (!(tmp & ULTRA_JOINER_ENABLE))
3552 				continue;
3553 
3554 			if (tmp & PRIMARY_ULTRA_JOINER_ENABLE)
3555 				*primary_pipes |= BIT(pipe);
3556 			else
3557 				*secondary_pipes |= BIT(pipe);
3558 		}
3559 	}
3560 }
3561 
3562 static void enabled_joiner_pipes(struct intel_display *display,
3563 				 enum pipe pipe,
3564 				 u8 *primary_pipe, u8 *secondary_pipes)
3565 {
3566 	u8 primary_ultrajoiner_pipes;
3567 	u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes;
3568 	u8 secondary_ultrajoiner_pipes;
3569 	u8 secondary_uncompressed_joiner_pipes, secondary_bigjoiner_pipes;
3570 	u8 ultrajoiner_pipes;
3571 	u8 uncompressed_joiner_pipes, bigjoiner_pipes;
3572 
3573 	enabled_ultrajoiner_pipes(display, &primary_ultrajoiner_pipes,
3574 				  &secondary_ultrajoiner_pipes);
3575 	/*
3576 	 * For some strange reason the last pipe in the set of four
3577 	 * shouldn't have ultrajoiner enable bit set in hardware.
3578 	 * Set the bit anyway to make life easier.
3579 	 */
3580 	drm_WARN_ON(display->drm,
3581 		    expected_secondary_pipes(primary_ultrajoiner_pipes, 3) !=
3582 		    secondary_ultrajoiner_pipes);
3583 	secondary_ultrajoiner_pipes =
3584 		fixup_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes,
3585 						  secondary_ultrajoiner_pipes);
3586 
3587 	drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0);
3588 
3589 	enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes,
3590 					  &secondary_uncompressed_joiner_pipes);
3591 
3592 	drm_WARN_ON(display->drm,
3593 		    (primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0);
3594 
3595 	enabled_bigjoiner_pipes(display, &primary_bigjoiner_pipes,
3596 				&secondary_bigjoiner_pipes);
3597 
3598 	drm_WARN_ON(display->drm,
3599 		    (primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0);
3600 
3601 	ultrajoiner_pipes = primary_ultrajoiner_pipes | secondary_ultrajoiner_pipes;
3602 	uncompressed_joiner_pipes = primary_uncompressed_joiner_pipes |
3603 				    secondary_uncompressed_joiner_pipes;
3604 	bigjoiner_pipes = primary_bigjoiner_pipes | secondary_bigjoiner_pipes;
3605 
3606 	drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes,
3607 		 "Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x)\n",
3608 		 ultrajoiner_pipes, bigjoiner_pipes);
3609 
3610 	drm_WARN(display->drm, secondary_ultrajoiner_pipes !=
3611 		 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes),
3612 		 "Wrong secondary ultrajoiner pipes(expected %#x, current %#x)\n",
3613 		 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes),
3614 		 secondary_ultrajoiner_pipes);
3615 
3616 	drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0,
3617 		 "Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect\n",
3618 		 uncompressed_joiner_pipes, bigjoiner_pipes);
3619 
3620 	drm_WARN(display->drm, secondary_bigjoiner_pipes !=
3621 		 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes),
3622 		 "Wrong secondary bigjoiner pipes(expected %#x, current %#x)\n",
3623 		 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes),
3624 		 secondary_bigjoiner_pipes);
3625 
3626 	drm_WARN(display->drm, secondary_uncompressed_joiner_pipes !=
3627 		 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes),
3628 		 "Wrong secondary uncompressed joiner pipes(expected %#x, current %#x)\n",
3629 		 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes),
3630 		 secondary_uncompressed_joiner_pipes);
3631 
3632 	*primary_pipe = 0;
3633 	*secondary_pipes = 0;
3634 
3635 	if (ultrajoiner_pipes & BIT(pipe)) {
3636 		*primary_pipe = get_joiner_primary_pipe(pipe, primary_ultrajoiner_pipes);
3637 		*secondary_pipes = secondary_ultrajoiner_pipes &
3638 				   expected_ultrajoiner_secondary_pipes(*primary_pipe);
3639 
3640 		drm_WARN(display->drm,
3641 			 expected_ultrajoiner_secondary_pipes(*primary_pipe) !=
3642 			 *secondary_pipes,
3643 			 "Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3644 			 *primary_pipe,
3645 			 expected_ultrajoiner_secondary_pipes(*primary_pipe),
3646 			 *secondary_pipes);
3647 		return;
3648 	}
3649 
3650 	if (uncompressed_joiner_pipes & BIT(pipe)) {
3651 		*primary_pipe = get_joiner_primary_pipe(pipe, primary_uncompressed_joiner_pipes);
3652 		*secondary_pipes = secondary_uncompressed_joiner_pipes &
3653 				   expected_uncompressed_joiner_secondary_pipes(*primary_pipe);
3654 
3655 		drm_WARN(display->drm,
3656 			 expected_uncompressed_joiner_secondary_pipes(*primary_pipe) !=
3657 			 *secondary_pipes,
3658 			 "Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3659 			 *primary_pipe,
3660 			 expected_uncompressed_joiner_secondary_pipes(*primary_pipe),
3661 			 *secondary_pipes);
3662 		return;
3663 	}
3664 
3665 	if (bigjoiner_pipes & BIT(pipe)) {
3666 		*primary_pipe = get_joiner_primary_pipe(pipe, primary_bigjoiner_pipes);
3667 		*secondary_pipes = secondary_bigjoiner_pipes &
3668 				   expected_bigjoiner_secondary_pipes(*primary_pipe);
3669 
3670 		drm_WARN(display->drm,
3671 			 expected_bigjoiner_secondary_pipes(*primary_pipe) !=
3672 			 *secondary_pipes,
3673 			 "Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3674 			 *primary_pipe,
3675 			 expected_bigjoiner_secondary_pipes(*primary_pipe),
3676 			 *secondary_pipes);
3677 		return;
3678 	}
3679 }
3680 
3681 static u8 hsw_panel_transcoders(struct intel_display *display)
3682 {
3683 	u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3684 
3685 	if (DISPLAY_VER(display) >= 11)
3686 		panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3687 
3688 	return panel_transcoder_mask;
3689 }
3690 
3691 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3692 {
3693 	struct intel_display *display = to_intel_display(crtc);
3694 	u8 panel_transcoder_mask = hsw_panel_transcoders(display);
3695 	enum transcoder cpu_transcoder;
3696 	u8 primary_pipe, secondary_pipes;
3697 	u8 enabled_transcoders = 0;
3698 
3699 	/*
3700 	 * XXX: Do intel_display_power_get_if_enabled before reading this (for
3701 	 * consistency and less surprising code; it's in always on power).
3702 	 */
3703 	for_each_cpu_transcoder_masked(display, cpu_transcoder,
3704 				       panel_transcoder_mask) {
3705 		enum intel_display_power_domain power_domain;
3706 		intel_wakeref_t wakeref;
3707 		enum pipe trans_pipe;
3708 		u32 tmp = 0;
3709 
3710 		power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3711 		with_intel_display_power_if_enabled(display, power_domain, wakeref)
3712 			tmp = intel_de_read(display,
3713 					    TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
3714 
3715 		if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3716 			continue;
3717 
3718 		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3719 		default:
3720 			drm_WARN(display->drm, 1,
3721 				 "unknown pipe linked to transcoder %s\n",
3722 				 transcoder_name(cpu_transcoder));
3723 			fallthrough;
3724 		case TRANS_DDI_EDP_INPUT_A_ONOFF:
3725 		case TRANS_DDI_EDP_INPUT_A_ON:
3726 			trans_pipe = PIPE_A;
3727 			break;
3728 		case TRANS_DDI_EDP_INPUT_B_ONOFF:
3729 			trans_pipe = PIPE_B;
3730 			break;
3731 		case TRANS_DDI_EDP_INPUT_C_ONOFF:
3732 			trans_pipe = PIPE_C;
3733 			break;
3734 		case TRANS_DDI_EDP_INPUT_D_ONOFF:
3735 			trans_pipe = PIPE_D;
3736 			break;
3737 		}
3738 
3739 		if (trans_pipe == crtc->pipe)
3740 			enabled_transcoders |= BIT(cpu_transcoder);
3741 	}
3742 
3743 	/* single pipe or joiner primary */
3744 	cpu_transcoder = (enum transcoder) crtc->pipe;
3745 	if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))
3746 		enabled_transcoders |= BIT(cpu_transcoder);
3747 
3748 	/* joiner secondary -> consider the primary pipe's transcoder as well */
3749 	enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes);
3750 	if (secondary_pipes & BIT(crtc->pipe)) {
3751 		cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1;
3752 		if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))
3753 			enabled_transcoders |= BIT(cpu_transcoder);
3754 	}
3755 
3756 	return enabled_transcoders;
3757 }
3758 
3759 static bool has_edp_transcoders(u8 enabled_transcoders)
3760 {
3761 	return enabled_transcoders & BIT(TRANSCODER_EDP);
3762 }
3763 
3764 static bool has_dsi_transcoders(u8 enabled_transcoders)
3765 {
3766 	return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3767 				      BIT(TRANSCODER_DSI_1));
3768 }
3769 
3770 static bool has_pipe_transcoders(u8 enabled_transcoders)
3771 {
3772 	return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3773 				       BIT(TRANSCODER_DSI_0) |
3774 				       BIT(TRANSCODER_DSI_1));
3775 }
3776 
3777 static void assert_enabled_transcoders(struct intel_display *display,
3778 				       u8 enabled_transcoders)
3779 {
3780 	/* Only one type of transcoder please */
3781 	drm_WARN_ON(display->drm,
3782 		    has_edp_transcoders(enabled_transcoders) +
3783 		    has_dsi_transcoders(enabled_transcoders) +
3784 		    has_pipe_transcoders(enabled_transcoders) > 1);
3785 
3786 	/* Only DSI transcoders can be ganged */
3787 	drm_WARN_ON(display->drm,
3788 		    !has_dsi_transcoders(enabled_transcoders) &&
3789 		    !is_power_of_2(enabled_transcoders));
3790 }
3791 
3792 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3793 				     struct intel_crtc_state *pipe_config,
3794 				     struct intel_display_power_domain_set *power_domain_set)
3795 {
3796 	struct intel_display *display = to_intel_display(crtc);
3797 	unsigned long enabled_transcoders;
3798 	u32 tmp;
3799 
3800 	enabled_transcoders = hsw_enabled_transcoders(crtc);
3801 	if (!enabled_transcoders)
3802 		return false;
3803 
3804 	assert_enabled_transcoders(display, enabled_transcoders);
3805 
3806 	/*
3807 	 * With the exception of DSI we should only ever have
3808 	 * a single enabled transcoder. With DSI let's just
3809 	 * pick the first one.
3810 	 */
3811 	pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3812 
3813 	if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,
3814 						       POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3815 		return false;
3816 
3817 	if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) {
3818 		tmp = intel_de_read(display,
3819 				    TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder));
3820 
3821 		if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3822 			pipe_config->pch_pfit.force_thru = true;
3823 	}
3824 
3825 	tmp = intel_de_read(display,
3826 			    TRANSCONF(display, pipe_config->cpu_transcoder));
3827 
3828 	return tmp & TRANSCONF_ENABLE;
3829 }
3830 
3831 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3832 					 struct intel_crtc_state *pipe_config,
3833 					 struct intel_display_power_domain_set *power_domain_set)
3834 {
3835 	struct intel_display *display = to_intel_display(crtc);
3836 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3837 	enum transcoder cpu_transcoder;
3838 	enum port port;
3839 	u32 tmp;
3840 
3841 	for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3842 		if (port == PORT_A)
3843 			cpu_transcoder = TRANSCODER_DSI_A;
3844 		else
3845 			cpu_transcoder = TRANSCODER_DSI_C;
3846 
3847 		if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,
3848 							       POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3849 			continue;
3850 
3851 		/*
3852 		 * The PLL needs to be enabled with a valid divider
3853 		 * configuration, otherwise accessing DSI registers will hang
3854 		 * the machine. See BSpec North Display Engine
3855 		 * registers/MIPI[BXT]. We can break out here early, since we
3856 		 * need the same DSI PLL to be enabled for both DSI ports.
3857 		 */
3858 		if (!bxt_dsi_pll_is_enabled(dev_priv))
3859 			break;
3860 
3861 		/* XXX: this works for video mode only */
3862 		tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
3863 		if (!(tmp & DPI_ENABLE))
3864 			continue;
3865 
3866 		tmp = intel_de_read(display, MIPI_CTRL(display, port));
3867 		if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3868 			continue;
3869 
3870 		pipe_config->cpu_transcoder = cpu_transcoder;
3871 		break;
3872 	}
3873 
3874 	return transcoder_is_dsi(pipe_config->cpu_transcoder);
3875 }
3876 
3877 static void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
3878 {
3879 	struct intel_display *display = to_intel_display(crtc_state);
3880 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3881 	u8 primary_pipe, secondary_pipes;
3882 	enum pipe pipe = crtc->pipe;
3883 
3884 	enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes);
3885 
3886 	if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0)
3887 		return;
3888 
3889 	crtc_state->joiner_pipes = primary_pipe | secondary_pipes;
3890 }
3891 
3892 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3893 				struct intel_crtc_state *pipe_config)
3894 {
3895 	struct intel_display *display = to_intel_display(crtc);
3896 	bool active;
3897 	u32 tmp;
3898 
3899 	if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,
3900 						       POWER_DOMAIN_PIPE(crtc->pipe)))
3901 		return false;
3902 
3903 	active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
3904 
3905 	if ((display->platform.geminilake || display->platform.broxton) &&
3906 	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
3907 		drm_WARN_ON(display->drm, active);
3908 		active = true;
3909 	}
3910 
3911 	if (!active)
3912 		goto out;
3913 
3914 	intel_joiner_get_config(pipe_config);
3915 	intel_dsc_get_config(pipe_config);
3916 
3917 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
3918 	    DISPLAY_VER(display) >= 11)
3919 		intel_get_transcoder_timings(crtc, pipe_config);
3920 
3921 	if (HAS_VRR(display) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
3922 		intel_vrr_get_config(pipe_config);
3923 
3924 	intel_get_pipe_src_size(crtc, pipe_config);
3925 
3926 	if (display->platform.haswell) {
3927 		u32 tmp = intel_de_read(display,
3928 					TRANSCONF(display, pipe_config->cpu_transcoder));
3929 
3930 		if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3931 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3932 		else
3933 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3934 	} else {
3935 		pipe_config->output_format =
3936 			bdw_get_pipe_misc_output_format(crtc);
3937 	}
3938 
3939 	pipe_config->sink_format = pipe_config->output_format;
3940 
3941 	intel_color_get_config(pipe_config);
3942 
3943 	tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));
3944 	pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3945 	if (display->platform.broadwell || display->platform.haswell)
3946 		pipe_config->ips_linetime =
3947 			REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3948 
3949 	if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,
3950 						      POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
3951 		if (DISPLAY_VER(display) >= 9)
3952 			skl_scaler_get_config(pipe_config);
3953 		else
3954 			ilk_pfit_get_config(pipe_config);
3955 	}
3956 
3957 	hsw_ips_get_config(pipe_config);
3958 
3959 	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
3960 	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3961 		pipe_config->pixel_multiplier =
3962 			intel_de_read(display,
3963 				      TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1;
3964 	} else {
3965 		pipe_config->pixel_multiplier = 1;
3966 	}
3967 
3968 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3969 		tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
3970 
3971 		pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
3972 	} else {
3973 		/* no idea if this is correct */
3974 		pipe_config->framestart_delay = 1;
3975 	}
3976 
3977 out:
3978 	intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);
3979 
3980 	return active;
3981 }
3982 
3983 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
3984 {
3985 	struct intel_display *display = to_intel_display(crtc_state);
3986 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3987 
3988 	if (!display->funcs.display->get_pipe_config(crtc, crtc_state))
3989 		return false;
3990 
3991 	crtc_state->hw.active = true;
3992 
3993 	intel_crtc_readout_derived_state(crtc_state);
3994 
3995 	return true;
3996 }
3997 
3998 int intel_dotclock_calculate(int link_freq,
3999 			     const struct intel_link_m_n *m_n)
4000 {
4001 	/*
4002 	 * The calculation for the data clock -> pixel clock is:
4003 	 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4004 	 * But we want to avoid losing precision if possible, so:
4005 	 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4006 	 *
4007 	 * and for link freq (10kbs units) -> pixel clock it is:
4008 	 * link_symbol_clock = link_freq * 10 / link_symbol_size
4009 	 * pixel_clock = (m * link_symbol_clock) / n
4010 	 *    or for more precision:
4011 	 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size)
4012 	 */
4013 
4014 	if (!m_n->link_n)
4015 		return 0;
4016 
4017 	return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
4018 				m_n->link_n * intel_dp_link_symbol_size(link_freq));
4019 }
4020 
4021 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
4022 {
4023 	int dotclock;
4024 
4025 	if (intel_crtc_has_dp_encoder(pipe_config))
4026 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
4027 						    &pipe_config->dp_m_n);
4028 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
4029 		dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
4030 					     pipe_config->pipe_bpp);
4031 	else
4032 		dotclock = pipe_config->port_clock;
4033 
4034 	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
4035 	    !intel_crtc_has_dp_encoder(pipe_config))
4036 		dotclock *= 2;
4037 
4038 	if (pipe_config->pixel_multiplier)
4039 		dotclock /= pipe_config->pixel_multiplier;
4040 
4041 	return dotclock;
4042 }
4043 
4044 /* Returns the currently programmed mode of the given encoder. */
4045 struct drm_display_mode *
4046 intel_encoder_current_mode(struct intel_encoder *encoder)
4047 {
4048 	struct intel_display *display = to_intel_display(encoder);
4049 	struct intel_crtc_state *crtc_state;
4050 	struct drm_display_mode *mode;
4051 	struct intel_crtc *crtc;
4052 	enum pipe pipe;
4053 
4054 	if (!encoder->get_hw_state(encoder, &pipe))
4055 		return NULL;
4056 
4057 	crtc = intel_crtc_for_pipe(display, pipe);
4058 
4059 	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4060 	if (!mode)
4061 		return NULL;
4062 
4063 	crtc_state = intel_crtc_state_alloc(crtc);
4064 	if (!crtc_state) {
4065 		kfree(mode);
4066 		return NULL;
4067 	}
4068 
4069 	if (!intel_crtc_get_pipe_config(crtc_state)) {
4070 		intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4071 		kfree(mode);
4072 		return NULL;
4073 	}
4074 
4075 	intel_encoder_get_config(encoder, crtc_state);
4076 
4077 	intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4078 
4079 	intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4080 
4081 	return mode;
4082 }
4083 
4084 static bool encoders_cloneable(const struct intel_encoder *a,
4085 			       const struct intel_encoder *b)
4086 {
4087 	/* masks could be asymmetric, so check both ways */
4088 	return a == b || (a->cloneable & BIT(b->type) &&
4089 			  b->cloneable & BIT(a->type));
4090 }
4091 
4092 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4093 					 struct intel_crtc *crtc,
4094 					 struct intel_encoder *encoder)
4095 {
4096 	struct intel_encoder *source_encoder;
4097 	struct drm_connector *connector;
4098 	struct drm_connector_state *connector_state;
4099 	int i;
4100 
4101 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4102 		if (connector_state->crtc != &crtc->base)
4103 			continue;
4104 
4105 		source_encoder =
4106 			to_intel_encoder(connector_state->best_encoder);
4107 		if (!encoders_cloneable(encoder, source_encoder))
4108 			return false;
4109 	}
4110 
4111 	return true;
4112 }
4113 
4114 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4115 {
4116 	const struct drm_display_mode *pipe_mode =
4117 		&crtc_state->hw.pipe_mode;
4118 	int linetime_wm;
4119 
4120 	if (!crtc_state->hw.enable)
4121 		return 0;
4122 
4123 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4124 					pipe_mode->crtc_clock);
4125 
4126 	return min(linetime_wm, 0x1ff);
4127 }
4128 
4129 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4130 			       const struct intel_cdclk_state *cdclk_state)
4131 {
4132 	const struct drm_display_mode *pipe_mode =
4133 		&crtc_state->hw.pipe_mode;
4134 	int linetime_wm;
4135 
4136 	if (!crtc_state->hw.enable)
4137 		return 0;
4138 
4139 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4140 					cdclk_state->logical.cdclk);
4141 
4142 	return min(linetime_wm, 0x1ff);
4143 }
4144 
4145 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4146 {
4147 	struct intel_display *display = to_intel_display(crtc_state);
4148 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4149 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4150 	const struct drm_display_mode *pipe_mode =
4151 		&crtc_state->hw.pipe_mode;
4152 	int linetime_wm;
4153 
4154 	if (!crtc_state->hw.enable)
4155 		return 0;
4156 
4157 	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4158 				   crtc_state->pixel_rate);
4159 
4160 	/* Display WA #1135: BXT:ALL GLK:ALL */
4161 	if ((display->platform.geminilake || display->platform.broxton) &&
4162 	    skl_watermark_ipc_enabled(dev_priv))
4163 		linetime_wm /= 2;
4164 
4165 	return min(linetime_wm, 0x1ff);
4166 }
4167 
4168 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4169 				   struct intel_crtc *crtc)
4170 {
4171 	struct intel_display *display = to_intel_display(state);
4172 	struct intel_crtc_state *crtc_state =
4173 		intel_atomic_get_new_crtc_state(state, crtc);
4174 	const struct intel_cdclk_state *cdclk_state;
4175 
4176 	if (DISPLAY_VER(display) >= 9)
4177 		crtc_state->linetime = skl_linetime_wm(crtc_state);
4178 	else
4179 		crtc_state->linetime = hsw_linetime_wm(crtc_state);
4180 
4181 	if (!hsw_crtc_supports_ips(crtc))
4182 		return 0;
4183 
4184 	cdclk_state = intel_atomic_get_cdclk_state(state);
4185 	if (IS_ERR(cdclk_state))
4186 		return PTR_ERR(cdclk_state);
4187 
4188 	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4189 						       cdclk_state);
4190 
4191 	return 0;
4192 }
4193 
4194 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4195 				   struct intel_crtc *crtc)
4196 {
4197 	struct intel_display *display = to_intel_display(crtc);
4198 	struct intel_crtc_state *crtc_state =
4199 		intel_atomic_get_new_crtc_state(state, crtc);
4200 	int ret;
4201 
4202 	if (DISPLAY_VER(display) < 5 && !display->platform.g4x &&
4203 	    intel_crtc_needs_modeset(crtc_state) &&
4204 	    !crtc_state->hw.active)
4205 		crtc_state->update_wm_post = true;
4206 
4207 	if (intel_crtc_needs_modeset(crtc_state)) {
4208 		ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4209 		if (ret)
4210 			return ret;
4211 	}
4212 
4213 	ret = intel_color_check(state, crtc);
4214 	if (ret)
4215 		return ret;
4216 
4217 	ret = intel_wm_compute(state, crtc);
4218 	if (ret) {
4219 		drm_dbg_kms(display->drm,
4220 			    "[CRTC:%d:%s] watermarks are invalid\n",
4221 			    crtc->base.base.id, crtc->base.name);
4222 		return ret;
4223 	}
4224 
4225 	if (DISPLAY_VER(display) >= 9) {
4226 		if (intel_crtc_needs_modeset(crtc_state) ||
4227 		    intel_crtc_needs_fastset(crtc_state)) {
4228 			ret = skl_update_scaler_crtc(crtc_state);
4229 			if (ret)
4230 				return ret;
4231 		}
4232 
4233 		ret = intel_atomic_setup_scalers(state, crtc);
4234 		if (ret)
4235 			return ret;
4236 	}
4237 
4238 	if (HAS_IPS(display)) {
4239 		ret = hsw_ips_compute_config(state, crtc);
4240 		if (ret)
4241 			return ret;
4242 	}
4243 
4244 	if (DISPLAY_VER(display) >= 9 ||
4245 	    display->platform.broadwell || display->platform.haswell) {
4246 		ret = hsw_compute_linetime_wm(state, crtc);
4247 		if (ret)
4248 			return ret;
4249 
4250 	}
4251 
4252 	ret = intel_psr2_sel_fetch_update(state, crtc);
4253 	if (ret)
4254 		return ret;
4255 
4256 	return 0;
4257 }
4258 
4259 static int
4260 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4261 		      struct intel_crtc_state *crtc_state)
4262 {
4263 	struct intel_display *display = to_intel_display(crtc_state);
4264 	struct drm_connector *connector = conn_state->connector;
4265 	const struct drm_display_info *info = &connector->display_info;
4266 	int bpp;
4267 
4268 	switch (conn_state->max_bpc) {
4269 	case 6 ... 7:
4270 		bpp = 6 * 3;
4271 		break;
4272 	case 8 ... 9:
4273 		bpp = 8 * 3;
4274 		break;
4275 	case 10 ... 11:
4276 		bpp = 10 * 3;
4277 		break;
4278 	case 12 ... 16:
4279 		bpp = 12 * 3;
4280 		break;
4281 	default:
4282 		MISSING_CASE(conn_state->max_bpc);
4283 		return -EINVAL;
4284 	}
4285 
4286 	if (bpp < crtc_state->pipe_bpp) {
4287 		drm_dbg_kms(display->drm,
4288 			    "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4289 			    "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4290 			    connector->base.id, connector->name,
4291 			    bpp, 3 * info->bpc,
4292 			    3 * conn_state->max_requested_bpc,
4293 			    crtc_state->pipe_bpp);
4294 
4295 		crtc_state->pipe_bpp = bpp;
4296 	}
4297 
4298 	return 0;
4299 }
4300 
4301 static int
4302 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4303 			  struct intel_crtc *crtc)
4304 {
4305 	struct intel_display *display = to_intel_display(crtc);
4306 	struct intel_crtc_state *crtc_state =
4307 		intel_atomic_get_new_crtc_state(state, crtc);
4308 	struct drm_connector *connector;
4309 	struct drm_connector_state *connector_state;
4310 	int bpp, i;
4311 
4312 	if (display->platform.g4x || display->platform.valleyview ||
4313 	    display->platform.cherryview)
4314 		bpp = 10*3;
4315 	else if (DISPLAY_VER(display) >= 5)
4316 		bpp = 12*3;
4317 	else
4318 		bpp = 8*3;
4319 
4320 	crtc_state->pipe_bpp = bpp;
4321 
4322 	/* Clamp display bpp to connector max bpp */
4323 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4324 		int ret;
4325 
4326 		if (connector_state->crtc != &crtc->base)
4327 			continue;
4328 
4329 		ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4330 		if (ret)
4331 			return ret;
4332 	}
4333 
4334 	return 0;
4335 }
4336 
4337 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4338 {
4339 	struct intel_display *display = to_intel_display(state);
4340 	struct drm_connector *connector;
4341 	struct drm_connector_list_iter conn_iter;
4342 	unsigned int used_ports = 0;
4343 	unsigned int used_mst_ports = 0;
4344 	bool ret = true;
4345 
4346 	/*
4347 	 * We're going to peek into connector->state,
4348 	 * hence connection_mutex must be held.
4349 	 */
4350 	drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);
4351 
4352 	/*
4353 	 * Walk the connector list instead of the encoder
4354 	 * list to detect the problem on ddi platforms
4355 	 * where there's just one encoder per digital port.
4356 	 */
4357 	drm_connector_list_iter_begin(display->drm, &conn_iter);
4358 	drm_for_each_connector_iter(connector, &conn_iter) {
4359 		struct drm_connector_state *connector_state;
4360 		struct intel_encoder *encoder;
4361 
4362 		connector_state =
4363 			drm_atomic_get_new_connector_state(&state->base,
4364 							   connector);
4365 		if (!connector_state)
4366 			connector_state = connector->state;
4367 
4368 		if (!connector_state->best_encoder)
4369 			continue;
4370 
4371 		encoder = to_intel_encoder(connector_state->best_encoder);
4372 
4373 		drm_WARN_ON(display->drm, !connector_state->crtc);
4374 
4375 		switch (encoder->type) {
4376 		case INTEL_OUTPUT_DDI:
4377 			if (drm_WARN_ON(display->drm, !HAS_DDI(display)))
4378 				break;
4379 			fallthrough;
4380 		case INTEL_OUTPUT_DP:
4381 		case INTEL_OUTPUT_HDMI:
4382 		case INTEL_OUTPUT_EDP:
4383 			/* the same port mustn't appear more than once */
4384 			if (used_ports & BIT(encoder->port))
4385 				ret = false;
4386 
4387 			used_ports |= BIT(encoder->port);
4388 			break;
4389 		case INTEL_OUTPUT_DP_MST:
4390 			used_mst_ports |=
4391 				1 << encoder->port;
4392 			break;
4393 		default:
4394 			break;
4395 		}
4396 	}
4397 	drm_connector_list_iter_end(&conn_iter);
4398 
4399 	/* can't mix MST and SST/HDMI on the same port */
4400 	if (used_ports & used_mst_ports)
4401 		return false;
4402 
4403 	return ret;
4404 }
4405 
4406 static void
4407 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4408 					   struct intel_crtc *crtc)
4409 {
4410 	struct intel_crtc_state *crtc_state =
4411 		intel_atomic_get_new_crtc_state(state, crtc);
4412 
4413 	WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4414 
4415 	drm_property_replace_blob(&crtc_state->hw.degamma_lut,
4416 				  crtc_state->uapi.degamma_lut);
4417 	drm_property_replace_blob(&crtc_state->hw.gamma_lut,
4418 				  crtc_state->uapi.gamma_lut);
4419 	drm_property_replace_blob(&crtc_state->hw.ctm,
4420 				  crtc_state->uapi.ctm);
4421 }
4422 
4423 static void
4424 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4425 					 struct intel_crtc *crtc)
4426 {
4427 	struct intel_crtc_state *crtc_state =
4428 		intel_atomic_get_new_crtc_state(state, crtc);
4429 
4430 	WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4431 
4432 	crtc_state->hw.enable = crtc_state->uapi.enable;
4433 	crtc_state->hw.active = crtc_state->uapi.active;
4434 	drm_mode_copy(&crtc_state->hw.mode,
4435 		      &crtc_state->uapi.mode);
4436 	drm_mode_copy(&crtc_state->hw.adjusted_mode,
4437 		      &crtc_state->uapi.adjusted_mode);
4438 	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4439 
4440 	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4441 }
4442 
4443 static void
4444 copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4445 				 struct intel_crtc *secondary_crtc)
4446 {
4447 	struct intel_crtc_state *secondary_crtc_state =
4448 		intel_atomic_get_new_crtc_state(state, secondary_crtc);
4449 	struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state);
4450 	const struct intel_crtc_state *primary_crtc_state =
4451 		intel_atomic_get_new_crtc_state(state, primary_crtc);
4452 
4453 	drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut,
4454 				  primary_crtc_state->hw.degamma_lut);
4455 	drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut,
4456 				  primary_crtc_state->hw.gamma_lut);
4457 	drm_property_replace_blob(&secondary_crtc_state->hw.ctm,
4458 				  primary_crtc_state->hw.ctm);
4459 
4460 	secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;
4461 }
4462 
4463 static int
4464 copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
4465 			       struct intel_crtc *secondary_crtc)
4466 {
4467 	struct intel_crtc_state *secondary_crtc_state =
4468 		intel_atomic_get_new_crtc_state(state, secondary_crtc);
4469 	struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state);
4470 	const struct intel_crtc_state *primary_crtc_state =
4471 		intel_atomic_get_new_crtc_state(state, primary_crtc);
4472 	struct intel_crtc_state *saved_state;
4473 
4474 	WARN_ON(primary_crtc_state->joiner_pipes !=
4475 		secondary_crtc_state->joiner_pipes);
4476 
4477 	saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4478 	if (!saved_state)
4479 		return -ENOMEM;
4480 
4481 	/* preserve some things from the slave's original crtc state */
4482 	saved_state->uapi = secondary_crtc_state->uapi;
4483 	saved_state->scaler_state = secondary_crtc_state->scaler_state;
4484 	saved_state->shared_dpll = secondary_crtc_state->shared_dpll;
4485 	saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
4486 
4487 	intel_crtc_free_hw_state(secondary_crtc_state);
4488 	if (secondary_crtc_state->dp_tunnel_ref.tunnel)
4489 		drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref);
4490 	memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state));
4491 	kfree(saved_state);
4492 
4493 	/* Re-init hw state */
4494 	memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw));
4495 	secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;
4496 	secondary_crtc_state->hw.active = primary_crtc_state->hw.active;
4497 	drm_mode_copy(&secondary_crtc_state->hw.mode,
4498 		      &primary_crtc_state->hw.mode);
4499 	drm_mode_copy(&secondary_crtc_state->hw.pipe_mode,
4500 		      &primary_crtc_state->hw.pipe_mode);
4501 	drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode,
4502 		      &primary_crtc_state->hw.adjusted_mode);
4503 	secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter;
4504 
4505 	if (primary_crtc_state->dp_tunnel_ref.tunnel)
4506 		drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel,
4507 				      &secondary_crtc_state->dp_tunnel_ref);
4508 
4509 	copy_joiner_crtc_state_nomodeset(state, secondary_crtc);
4510 
4511 	secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed;
4512 	secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed;
4513 	secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed;
4514 
4515 	WARN_ON(primary_crtc_state->joiner_pipes !=
4516 		secondary_crtc_state->joiner_pipes);
4517 
4518 	return 0;
4519 }
4520 
4521 static int
4522 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4523 				 struct intel_crtc *crtc)
4524 {
4525 	struct intel_display *display = to_intel_display(state);
4526 	struct intel_crtc_state *crtc_state =
4527 		intel_atomic_get_new_crtc_state(state, crtc);
4528 	struct intel_crtc_state *saved_state;
4529 
4530 	saved_state = intel_crtc_state_alloc(crtc);
4531 	if (!saved_state)
4532 		return -ENOMEM;
4533 
4534 	/* free the old crtc_state->hw members */
4535 	intel_crtc_free_hw_state(crtc_state);
4536 
4537 	intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state);
4538 
4539 	/* FIXME: before the switch to atomic started, a new pipe_config was
4540 	 * kzalloc'd. Code that depends on any field being zero should be
4541 	 * fixed, so that the crtc_state can be safely duplicated. For now,
4542 	 * only fields that are know to not cause problems are preserved. */
4543 
4544 	saved_state->uapi = crtc_state->uapi;
4545 	saved_state->inherited = crtc_state->inherited;
4546 	saved_state->scaler_state = crtc_state->scaler_state;
4547 	saved_state->shared_dpll = crtc_state->shared_dpll;
4548 	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4549 	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
4550 	       sizeof(saved_state->icl_port_dplls));
4551 	saved_state->crc_enabled = crtc_state->crc_enabled;
4552 	if (display->platform.g4x ||
4553 	    display->platform.valleyview || display->platform.cherryview)
4554 		saved_state->wm = crtc_state->wm;
4555 
4556 	memcpy(crtc_state, saved_state, sizeof(*crtc_state));
4557 	kfree(saved_state);
4558 
4559 	intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4560 
4561 	return 0;
4562 }
4563 
4564 static int
4565 intel_modeset_pipe_config(struct intel_atomic_state *state,
4566 			  struct intel_crtc *crtc,
4567 			  const struct intel_link_bw_limits *limits)
4568 {
4569 	struct intel_display *display = to_intel_display(crtc);
4570 	struct intel_crtc_state *crtc_state =
4571 		intel_atomic_get_new_crtc_state(state, crtc);
4572 	struct drm_connector *connector;
4573 	struct drm_connector_state *connector_state;
4574 	int pipe_src_w, pipe_src_h;
4575 	int base_bpp, ret, i;
4576 
4577 	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4578 
4579 	crtc_state->framestart_delay = 1;
4580 
4581 	/*
4582 	 * Sanitize sync polarity flags based on requested ones. If neither
4583 	 * positive or negative polarity is requested, treat this as meaning
4584 	 * negative polarity.
4585 	 */
4586 	if (!(crtc_state->hw.adjusted_mode.flags &
4587 	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4588 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4589 
4590 	if (!(crtc_state->hw.adjusted_mode.flags &
4591 	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4592 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4593 
4594 	ret = compute_baseline_pipe_bpp(state, crtc);
4595 	if (ret)
4596 		return ret;
4597 
4598 	crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
4599 	crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
4600 
4601 	if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {
4602 		drm_dbg_kms(display->drm,
4603 			    "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n",
4604 			    crtc->base.base.id, crtc->base.name,
4605 			    FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));
4606 		crtc_state->bw_constrained = true;
4607 	}
4608 
4609 	base_bpp = crtc_state->pipe_bpp;
4610 
4611 	/*
4612 	 * Determine the real pipe dimensions. Note that stereo modes can
4613 	 * increase the actual pipe size due to the frame doubling and
4614 	 * insertion of additional space for blanks between the frame. This
4615 	 * is stored in the crtc timings. We use the requested mode to do this
4616 	 * computation to clearly distinguish it from the adjusted mode, which
4617 	 * can be changed by the connectors in the below retry loop.
4618 	 */
4619 	drm_mode_get_hv_timing(&crtc_state->hw.mode,
4620 			       &pipe_src_w, &pipe_src_h);
4621 	drm_rect_init(&crtc_state->pipe_src, 0, 0,
4622 		      pipe_src_w, pipe_src_h);
4623 
4624 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4625 		struct intel_encoder *encoder =
4626 			to_intel_encoder(connector_state->best_encoder);
4627 
4628 		if (connector_state->crtc != &crtc->base)
4629 			continue;
4630 
4631 		if (!check_single_encoder_cloning(state, crtc, encoder)) {
4632 			drm_dbg_kms(display->drm,
4633 				    "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4634 				    encoder->base.base.id, encoder->base.name);
4635 			return -EINVAL;
4636 		}
4637 
4638 		/*
4639 		 * Determine output_types before calling the .compute_config()
4640 		 * hooks so that the hooks can use this information safely.
4641 		 */
4642 		if (encoder->compute_output_type)
4643 			crtc_state->output_types |=
4644 				BIT(encoder->compute_output_type(encoder, crtc_state,
4645 								 connector_state));
4646 		else
4647 			crtc_state->output_types |= BIT(encoder->type);
4648 	}
4649 
4650 	/* Ensure the port clock defaults are reset when retrying. */
4651 	crtc_state->port_clock = 0;
4652 	crtc_state->pixel_multiplier = 1;
4653 
4654 	/* Fill in default crtc timings, allow encoders to overwrite them. */
4655 	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
4656 			      CRTC_STEREO_DOUBLE);
4657 
4658 	/* Pass our mode to the connectors and the CRTC to give them a chance to
4659 	 * adjust it according to limitations or connector properties, and also
4660 	 * a chance to reject the mode entirely.
4661 	 */
4662 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4663 		struct intel_encoder *encoder =
4664 			to_intel_encoder(connector_state->best_encoder);
4665 
4666 		if (connector_state->crtc != &crtc->base)
4667 			continue;
4668 
4669 		ret = encoder->compute_config(encoder, crtc_state,
4670 					      connector_state);
4671 		if (ret == -EDEADLK)
4672 			return ret;
4673 		if (ret < 0) {
4674 			drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n",
4675 				    encoder->base.base.id, encoder->base.name, ret);
4676 			return ret;
4677 		}
4678 	}
4679 
4680 	/* Set default port clock if not overwritten by the encoder. Needs to be
4681 	 * done afterwards in case the encoder adjusts the mode. */
4682 	if (!crtc_state->port_clock)
4683 		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
4684 			* crtc_state->pixel_multiplier;
4685 
4686 	ret = intel_crtc_compute_config(state, crtc);
4687 	if (ret == -EDEADLK)
4688 		return ret;
4689 	if (ret < 0) {
4690 		drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n",
4691 			    crtc->base.base.id, crtc->base.name, ret);
4692 		return ret;
4693 	}
4694 
4695 	/* Dithering seems to not pass-through bits correctly when it should, so
4696 	 * only enable it on 6bpc panels and when its not a compliance
4697 	 * test requesting 6bpc video pattern.
4698 	 */
4699 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
4700 		!crtc_state->dither_force_disable;
4701 	drm_dbg_kms(display->drm,
4702 		    "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4703 		    crtc->base.base.id, crtc->base.name,
4704 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
4705 
4706 	return 0;
4707 }
4708 
4709 static int
4710 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
4711 			       struct intel_crtc *crtc)
4712 {
4713 	struct intel_crtc_state *crtc_state =
4714 		intel_atomic_get_new_crtc_state(state, crtc);
4715 	struct drm_connector_state *conn_state;
4716 	struct drm_connector *connector;
4717 	int i;
4718 
4719 	intel_vrr_compute_config_late(crtc_state);
4720 
4721 	for_each_new_connector_in_state(&state->base, connector,
4722 					conn_state, i) {
4723 		struct intel_encoder *encoder =
4724 			to_intel_encoder(conn_state->best_encoder);
4725 		int ret;
4726 
4727 		if (conn_state->crtc != &crtc->base ||
4728 		    !encoder->compute_config_late)
4729 			continue;
4730 
4731 		ret = encoder->compute_config_late(encoder, crtc_state,
4732 						   conn_state);
4733 		if (ret)
4734 			return ret;
4735 	}
4736 
4737 	return 0;
4738 }
4739 
4740 bool intel_fuzzy_clock_check(int clock1, int clock2)
4741 {
4742 	int diff;
4743 
4744 	if (clock1 == clock2)
4745 		return true;
4746 
4747 	if (!clock1 || !clock2)
4748 		return false;
4749 
4750 	diff = abs(clock1 - clock2);
4751 
4752 	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
4753 		return true;
4754 
4755 	return false;
4756 }
4757 
4758 static bool
4759 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
4760 		       const struct intel_link_m_n *m2_n2)
4761 {
4762 	return m_n->tu == m2_n2->tu &&
4763 		m_n->data_m == m2_n2->data_m &&
4764 		m_n->data_n == m2_n2->data_n &&
4765 		m_n->link_m == m2_n2->link_m &&
4766 		m_n->link_n == m2_n2->link_n;
4767 }
4768 
4769 static bool
4770 intel_compare_infoframe(const union hdmi_infoframe *a,
4771 			const union hdmi_infoframe *b)
4772 {
4773 	return memcmp(a, b, sizeof(*a)) == 0;
4774 }
4775 
4776 static bool
4777 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
4778 			 const struct drm_dp_vsc_sdp *b)
4779 {
4780 	return a->pixelformat == b->pixelformat &&
4781 		a->colorimetry == b->colorimetry &&
4782 		a->bpc == b->bpc &&
4783 		a->dynamic_range == b->dynamic_range &&
4784 		a->content_type == b->content_type;
4785 }
4786 
4787 static bool
4788 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
4789 			const struct drm_dp_as_sdp *b)
4790 {
4791 	return a->vtotal == b->vtotal &&
4792 		a->target_rr == b->target_rr &&
4793 		a->duration_incr_ms == b->duration_incr_ms &&
4794 		a->duration_decr_ms == b->duration_decr_ms &&
4795 		a->mode == b->mode;
4796 }
4797 
4798 static bool
4799 intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
4800 {
4801 	return memcmp(a, b, len) == 0;
4802 }
4803 
4804 static void __printf(5, 6)
4805 pipe_config_mismatch(struct drm_printer *p, bool fastset,
4806 		     const struct intel_crtc *crtc,
4807 		     const char *name, const char *format, ...)
4808 {
4809 	struct va_format vaf;
4810 	va_list args;
4811 
4812 	va_start(args, format);
4813 	vaf.fmt = format;
4814 	vaf.va = &args;
4815 
4816 	if (fastset)
4817 		drm_printf(p, "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4818 			   crtc->base.base.id, crtc->base.name, name, &vaf);
4819 	else
4820 		drm_printf(p, "[CRTC:%d:%s] mismatch in %s %pV\n",
4821 			   crtc->base.base.id, crtc->base.name, name, &vaf);
4822 
4823 	va_end(args);
4824 }
4825 
4826 static void
4827 pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset,
4828 			       const struct intel_crtc *crtc,
4829 			       const char *name,
4830 			       const union hdmi_infoframe *a,
4831 			       const union hdmi_infoframe *b)
4832 {
4833 	struct intel_display *display = to_intel_display(crtc);
4834 	const char *loglevel;
4835 
4836 	if (fastset) {
4837 		if (!drm_debug_enabled(DRM_UT_KMS))
4838 			return;
4839 
4840 		loglevel = KERN_DEBUG;
4841 	} else {
4842 		loglevel = KERN_ERR;
4843 	}
4844 
4845 	pipe_config_mismatch(p, fastset, crtc, name, "infoframe");
4846 
4847 	drm_printf(p, "expected:\n");
4848 	hdmi_infoframe_log(loglevel, display->drm->dev, a);
4849 	drm_printf(p, "found:\n");
4850 	hdmi_infoframe_log(loglevel, display->drm->dev, b);
4851 }
4852 
4853 static void
4854 pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset,
4855 				const struct intel_crtc *crtc,
4856 				const char *name,
4857 				const struct drm_dp_vsc_sdp *a,
4858 				const struct drm_dp_vsc_sdp *b)
4859 {
4860 	pipe_config_mismatch(p, fastset, crtc, name, "dp vsc sdp");
4861 
4862 	drm_printf(p, "expected:\n");
4863 	drm_dp_vsc_sdp_log(p, a);
4864 	drm_printf(p, "found:\n");
4865 	drm_dp_vsc_sdp_log(p, b);
4866 }
4867 
4868 static void
4869 pipe_config_dp_as_sdp_mismatch(struct drm_printer *p, bool fastset,
4870 			       const struct intel_crtc *crtc,
4871 			       const char *name,
4872 			       const struct drm_dp_as_sdp *a,
4873 			       const struct drm_dp_as_sdp *b)
4874 {
4875 	pipe_config_mismatch(p, fastset, crtc, name, "dp as sdp");
4876 
4877 	drm_printf(p, "expected:\n");
4878 	drm_dp_as_sdp_log(p, a);
4879 	drm_printf(p, "found:\n");
4880 	drm_dp_as_sdp_log(p, b);
4881 }
4882 
4883 /* Returns the length up to and including the last differing byte */
4884 static size_t
4885 memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
4886 {
4887 	int i;
4888 
4889 	for (i = len - 1; i >= 0; i--) {
4890 		if (a[i] != b[i])
4891 			return i + 1;
4892 	}
4893 
4894 	return 0;
4895 }
4896 
4897 static void
4898 pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset,
4899 			    const struct intel_crtc *crtc,
4900 			    const char *name,
4901 			    const u8 *a, const u8 *b, size_t len)
4902 {
4903 	pipe_config_mismatch(p, fastset, crtc, name, "buffer");
4904 
4905 	/* only dump up to the last difference */
4906 	len = memcmp_diff_len(a, b, len);
4907 
4908 	drm_print_hex_dump(p, "expected: ", a, len);
4909 	drm_print_hex_dump(p, "found:    ", b, len);
4910 }
4911 
4912 static void
4913 pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
4914 			 const struct intel_crtc *crtc,
4915 			 const char *name,
4916 			 const struct intel_dpll_hw_state *a,
4917 			 const struct intel_dpll_hw_state *b)
4918 {
4919 	struct intel_display *display = to_intel_display(crtc);
4920 
4921 	pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */
4922 
4923 	drm_printf(p, "expected:\n");
4924 	intel_dpll_dump_hw_state(display, p, a);
4925 	drm_printf(p, "found:\n");
4926 	intel_dpll_dump_hw_state(display, p, b);
4927 }
4928 
4929 static void
4930 pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
4931 			    const struct intel_crtc *crtc,
4932 			    const char *name,
4933 			    const struct intel_cx0pll_state *a,
4934 			    const struct intel_cx0pll_state *b)
4935 {
4936 	struct intel_display *display = to_intel_display(crtc);
4937 	char *chipname = a->use_c10 ? "C10" : "C20";
4938 
4939 	pipe_config_mismatch(p, fastset, crtc, name, chipname);
4940 
4941 	drm_printf(p, "expected:\n");
4942 	intel_cx0pll_dump_hw_state(display, a);
4943 	drm_printf(p, "found:\n");
4944 	intel_cx0pll_dump_hw_state(display, b);
4945 }
4946 
4947 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
4948 {
4949 	struct intel_display *display = to_intel_display(old_crtc_state);
4950 
4951 	/*
4952 	 * Allow fastboot to fix up vblank delay (handled via LRR
4953 	 * codepaths), a bit dodgy as the registers aren't
4954 	 * double buffered but seems to be working more or less...
4955 	 */
4956 	return HAS_LRR(display) && old_crtc_state->inherited &&
4957 		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
4958 }
4959 
4960 bool
4961 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
4962 			  const struct intel_crtc_state *pipe_config,
4963 			  bool fastset)
4964 {
4965 	struct intel_display *display = to_intel_display(current_config);
4966 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4967 	struct drm_printer p;
4968 	u32 exclude_infoframes = 0;
4969 	bool ret = true;
4970 
4971 	if (fastset)
4972 		p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
4973 	else
4974 		p = drm_err_printer(display->drm, NULL);
4975 
4976 #define PIPE_CONF_CHECK_X(name) do { \
4977 	if (current_config->name != pipe_config->name) { \
4978 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
4979 				 __stringify(name) " is bool");	\
4980 		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
4981 				     "(expected 0x%08x, found 0x%08x)", \
4982 				     current_config->name, \
4983 				     pipe_config->name); \
4984 		ret = false; \
4985 	} \
4986 } while (0)
4987 
4988 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
4989 	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
4990 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
4991 				 __stringify(name) " is bool");	\
4992 		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
4993 				     "(expected 0x%08x, found 0x%08x)", \
4994 				     current_config->name & (mask), \
4995 				     pipe_config->name & (mask)); \
4996 		ret = false; \
4997 	} \
4998 } while (0)
4999 
5000 #define PIPE_CONF_CHECK_I(name) do { \
5001 	if (current_config->name != pipe_config->name) { \
5002 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5003 				 __stringify(name) " is bool");	\
5004 		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5005 				     "(expected %i, found %i)", \
5006 				     current_config->name, \
5007 				     pipe_config->name); \
5008 		ret = false; \
5009 	} \
5010 } while (0)
5011 
5012 #define PIPE_CONF_CHECK_LLI(name) do { \
5013 	if (current_config->name != pipe_config->name) { \
5014 		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5015 				     "(expected %lli, found %lli)", \
5016 				     current_config->name, \
5017 				     pipe_config->name); \
5018 		ret = false; \
5019 	} \
5020 } while (0)
5021 
5022 #define PIPE_CONF_CHECK_BOOL(name) do { \
5023 	if (current_config->name != pipe_config->name) { \
5024 		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
5025 				 __stringify(name) " is not bool");	\
5026 		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5027 				     "(expected %s, found %s)", \
5028 				     str_yes_no(current_config->name), \
5029 				     str_yes_no(pipe_config->name)); \
5030 		ret = false; \
5031 	} \
5032 } while (0)
5033 
5034 #define PIPE_CONF_CHECK_P(name) do { \
5035 	if (current_config->name != pipe_config->name) { \
5036 		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5037 				     "(expected %p, found %p)", \
5038 				     current_config->name, \
5039 				     pipe_config->name); \
5040 		ret = false; \
5041 	} \
5042 } while (0)
5043 
5044 #define PIPE_CONF_CHECK_M_N(name) do { \
5045 	if (!intel_compare_link_m_n(&current_config->name, \
5046 				    &pipe_config->name)) { \
5047 		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5048 				     "(expected tu %i data %i/%i link %i/%i, " \
5049 				     "found tu %i, data %i/%i link %i/%i)", \
5050 				     current_config->name.tu, \
5051 				     current_config->name.data_m, \
5052 				     current_config->name.data_n, \
5053 				     current_config->name.link_m, \
5054 				     current_config->name.link_n, \
5055 				     pipe_config->name.tu, \
5056 				     pipe_config->name.data_m, \
5057 				     pipe_config->name.data_n, \
5058 				     pipe_config->name.link_m, \
5059 				     pipe_config->name.link_n); \
5060 		ret = false; \
5061 	} \
5062 } while (0)
5063 
5064 #define PIPE_CONF_CHECK_PLL(name) do { \
5065 	if (!intel_dpll_compare_hw_state(display, &current_config->name, \
5066 					 &pipe_config->name)) { \
5067 		pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5068 					 &current_config->name, \
5069 					 &pipe_config->name); \
5070 		ret = false; \
5071 	} \
5072 } while (0)
5073 
5074 #define PIPE_CONF_CHECK_PLL_CX0(name) do { \
5075 	if (!intel_cx0pll_compare_hw_state(&current_config->name, \
5076 					   &pipe_config->name)) { \
5077 		pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \
5078 					    &current_config->name, \
5079 					    &pipe_config->name); \
5080 		ret = false; \
5081 	} \
5082 } while (0)
5083 
5084 #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
5085 	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5086 	PIPE_CONF_CHECK_I(name.crtc_htotal); \
5087 	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5088 	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5089 	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5090 	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5091 	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5092 	if (!fastset || !allow_vblank_delay_fastset(current_config)) \
5093 		PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5094 	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5095 	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5096 	if (!fastset || !pipe_config->update_lrr) { \
5097 		PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5098 		PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5099 	} \
5100 } while (0)
5101 
5102 #define PIPE_CONF_CHECK_RECT(name) do { \
5103 	PIPE_CONF_CHECK_I(name.x1); \
5104 	PIPE_CONF_CHECK_I(name.x2); \
5105 	PIPE_CONF_CHECK_I(name.y1); \
5106 	PIPE_CONF_CHECK_I(name.y2); \
5107 } while (0)
5108 
5109 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5110 	if ((current_config->name ^ pipe_config->name) & (mask)) { \
5111 		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5112 				     "(%x) (expected %i, found %i)", \
5113 				     (mask), \
5114 				     current_config->name & (mask), \
5115 				     pipe_config->name & (mask)); \
5116 		ret = false; \
5117 	} \
5118 } while (0)
5119 
5120 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5121 	if (!intel_compare_infoframe(&current_config->infoframes.name, \
5122 				     &pipe_config->infoframes.name)) { \
5123 		pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \
5124 					       &current_config->infoframes.name, \
5125 					       &pipe_config->infoframes.name); \
5126 		ret = false; \
5127 	} \
5128 } while (0)
5129 
5130 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5131 	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5132 				      &pipe_config->infoframes.name)) { \
5133 		pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
5134 						&current_config->infoframes.name, \
5135 						&pipe_config->infoframes.name); \
5136 		ret = false; \
5137 	} \
5138 } while (0)
5139 
5140 #define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
5141 	if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \
5142 				      &pipe_config->infoframes.name)) { \
5143 		pipe_config_dp_as_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
5144 						&current_config->infoframes.name, \
5145 						&pipe_config->infoframes.name); \
5146 		ret = false; \
5147 	} \
5148 } while (0)
5149 
5150 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5151 	BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5152 	BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5153 	if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5154 		pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \
5155 					    current_config->name, \
5156 					    pipe_config->name, \
5157 					    (len)); \
5158 		ret = false; \
5159 	} \
5160 } while (0)
5161 
5162 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5163 	if (current_config->gamma_mode == pipe_config->gamma_mode && \
5164 	    !intel_color_lut_equal(current_config, \
5165 				   current_config->lut, pipe_config->lut, \
5166 				   is_pre_csc_lut)) {	\
5167 		pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \
5168 				     "hw_state doesn't match sw_state"); \
5169 		ret = false; \
5170 	} \
5171 } while (0)
5172 
5173 #define PIPE_CONF_CHECK_CSC(name) do { \
5174 	PIPE_CONF_CHECK_X(name.preoff[0]); \
5175 	PIPE_CONF_CHECK_X(name.preoff[1]); \
5176 	PIPE_CONF_CHECK_X(name.preoff[2]); \
5177 	PIPE_CONF_CHECK_X(name.coeff[0]); \
5178 	PIPE_CONF_CHECK_X(name.coeff[1]); \
5179 	PIPE_CONF_CHECK_X(name.coeff[2]); \
5180 	PIPE_CONF_CHECK_X(name.coeff[3]); \
5181 	PIPE_CONF_CHECK_X(name.coeff[4]); \
5182 	PIPE_CONF_CHECK_X(name.coeff[5]); \
5183 	PIPE_CONF_CHECK_X(name.coeff[6]); \
5184 	PIPE_CONF_CHECK_X(name.coeff[7]); \
5185 	PIPE_CONF_CHECK_X(name.coeff[8]); \
5186 	PIPE_CONF_CHECK_X(name.postoff[0]); \
5187 	PIPE_CONF_CHECK_X(name.postoff[1]); \
5188 	PIPE_CONF_CHECK_X(name.postoff[2]); \
5189 } while (0)
5190 
5191 #define PIPE_CONF_QUIRK(quirk) \
5192 	((current_config->quirks | pipe_config->quirks) & (quirk))
5193 
5194 	PIPE_CONF_CHECK_BOOL(hw.enable);
5195 	PIPE_CONF_CHECK_BOOL(hw.active);
5196 
5197 	PIPE_CONF_CHECK_I(cpu_transcoder);
5198 	PIPE_CONF_CHECK_I(mst_master_transcoder);
5199 
5200 	PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5201 	PIPE_CONF_CHECK_I(fdi_lanes);
5202 	PIPE_CONF_CHECK_M_N(fdi_m_n);
5203 
5204 	PIPE_CONF_CHECK_I(lane_count);
5205 	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5206 
5207 	if (HAS_DOUBLE_BUFFERED_M_N(display)) {
5208 		if (!fastset || !pipe_config->update_m_n)
5209 			PIPE_CONF_CHECK_M_N(dp_m_n);
5210 	} else {
5211 		PIPE_CONF_CHECK_M_N(dp_m_n);
5212 		PIPE_CONF_CHECK_M_N(dp_m2_n2);
5213 	}
5214 
5215 	PIPE_CONF_CHECK_X(output_types);
5216 
5217 	PIPE_CONF_CHECK_I(framestart_delay);
5218 	PIPE_CONF_CHECK_I(msa_timing_delay);
5219 
5220 	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5221 	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5222 
5223 	PIPE_CONF_CHECK_I(pixel_multiplier);
5224 
5225 	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5226 			      DRM_MODE_FLAG_INTERLACE);
5227 
5228 	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5229 		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5230 				      DRM_MODE_FLAG_PHSYNC);
5231 		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5232 				      DRM_MODE_FLAG_NHSYNC);
5233 		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5234 				      DRM_MODE_FLAG_PVSYNC);
5235 		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5236 				      DRM_MODE_FLAG_NVSYNC);
5237 	}
5238 
5239 	PIPE_CONF_CHECK_I(output_format);
5240 	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5241 	if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) ||
5242 	    display->platform.valleyview || display->platform.cherryview)
5243 		PIPE_CONF_CHECK_BOOL(limited_color_range);
5244 
5245 	PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5246 	PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5247 	PIPE_CONF_CHECK_BOOL(has_infoframe);
5248 	PIPE_CONF_CHECK_BOOL(enhanced_framing);
5249 	PIPE_CONF_CHECK_BOOL(fec_enable);
5250 
5251 	if (!fastset) {
5252 		PIPE_CONF_CHECK_BOOL(has_audio);
5253 		PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5254 	}
5255 
5256 	PIPE_CONF_CHECK_X(gmch_pfit.control);
5257 	/* pfit ratios are autocomputed by the hw on gen4+ */
5258 	if (DISPLAY_VER(display) < 4)
5259 		PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5260 	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5261 
5262 	/*
5263 	 * Changing the EDP transcoder input mux
5264 	 * (A_ONOFF vs. A_ON) requires a full modeset.
5265 	 */
5266 	PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5267 
5268 	if (!fastset) {
5269 		PIPE_CONF_CHECK_RECT(pipe_src);
5270 
5271 		PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5272 		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5273 
5274 		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5275 		PIPE_CONF_CHECK_I(pixel_rate);
5276 
5277 		PIPE_CONF_CHECK_X(gamma_mode);
5278 		if (display->platform.cherryview)
5279 			PIPE_CONF_CHECK_X(cgm_mode);
5280 		else
5281 			PIPE_CONF_CHECK_X(csc_mode);
5282 		PIPE_CONF_CHECK_BOOL(gamma_enable);
5283 		PIPE_CONF_CHECK_BOOL(csc_enable);
5284 		PIPE_CONF_CHECK_BOOL(wgc_enable);
5285 
5286 		PIPE_CONF_CHECK_I(linetime);
5287 		PIPE_CONF_CHECK_I(ips_linetime);
5288 
5289 		PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5290 		PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5291 
5292 		PIPE_CONF_CHECK_CSC(csc);
5293 		PIPE_CONF_CHECK_CSC(output_csc);
5294 	}
5295 
5296 	PIPE_CONF_CHECK_BOOL(double_wide);
5297 
5298 	if (display->dpll.mgr)
5299 		PIPE_CONF_CHECK_P(shared_dpll);
5300 
5301 	/* FIXME convert everything over the dpll_mgr */
5302 	if (display->dpll.mgr || HAS_GMCH(display))
5303 		PIPE_CONF_CHECK_PLL(dpll_hw_state);
5304 
5305 	/* FIXME convert MTL+ platforms over to dpll_mgr */
5306 	if (DISPLAY_VER(display) >= 14)
5307 		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
5308 
5309 	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5310 	PIPE_CONF_CHECK_X(dsi_pll.div);
5311 
5312 	if (display->platform.g4x || DISPLAY_VER(display) >= 5)
5313 		PIPE_CONF_CHECK_I(pipe_bpp);
5314 
5315 	if (!fastset || !pipe_config->update_m_n) {
5316 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5317 		PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5318 	}
5319 	PIPE_CONF_CHECK_I(port_clock);
5320 
5321 	PIPE_CONF_CHECK_I(min_voltage_level);
5322 
5323 	if (current_config->has_psr || pipe_config->has_psr)
5324 		exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
5325 
5326 	if (current_config->vrr.enable || pipe_config->vrr.enable)
5327 		exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
5328 
5329 	PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, ~exclude_infoframes);
5330 	PIPE_CONF_CHECK_X(infoframes.gcp);
5331 	PIPE_CONF_CHECK_INFOFRAME(avi);
5332 	PIPE_CONF_CHECK_INFOFRAME(spd);
5333 	PIPE_CONF_CHECK_INFOFRAME(hdmi);
5334 	if (!fastset) {
5335 		PIPE_CONF_CHECK_INFOFRAME(drm);
5336 		PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
5337 	}
5338 	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5339 
5340 	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5341 	PIPE_CONF_CHECK_I(master_transcoder);
5342 	PIPE_CONF_CHECK_X(joiner_pipes);
5343 
5344 	PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
5345 	PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
5346 	PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
5347 	PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
5348 	PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
5349 	PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
5350 	PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
5351 	PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
5352 	PIPE_CONF_CHECK_I(dsc.config.pic_width);
5353 	PIPE_CONF_CHECK_I(dsc.config.pic_height);
5354 	PIPE_CONF_CHECK_I(dsc.config.slice_width);
5355 	PIPE_CONF_CHECK_I(dsc.config.slice_height);
5356 	PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
5357 	PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
5358 	PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
5359 	PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
5360 	PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
5361 	PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
5362 	PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
5363 	PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
5364 	PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
5365 	PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
5366 	PIPE_CONF_CHECK_I(dsc.config.initial_offset);
5367 	PIPE_CONF_CHECK_I(dsc.config.final_offset);
5368 	PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
5369 	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
5370 	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
5371 	PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
5372 	PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
5373 	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
5374 
5375 	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
5376 	PIPE_CONF_CHECK_I(dsc.num_streams);
5377 	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
5378 
5379 	PIPE_CONF_CHECK_BOOL(splitter.enable);
5380 	PIPE_CONF_CHECK_I(splitter.link_count);
5381 	PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5382 
5383 	if (!fastset) {
5384 		PIPE_CONF_CHECK_BOOL(vrr.enable);
5385 		PIPE_CONF_CHECK_I(vrr.vmin);
5386 		PIPE_CONF_CHECK_I(vrr.vmax);
5387 		PIPE_CONF_CHECK_I(vrr.flipline);
5388 		PIPE_CONF_CHECK_I(vrr.pipeline_full);
5389 		PIPE_CONF_CHECK_I(vrr.guardband);
5390 		PIPE_CONF_CHECK_I(vrr.vsync_start);
5391 		PIPE_CONF_CHECK_I(vrr.vsync_end);
5392 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
5393 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
5394 		PIPE_CONF_CHECK_BOOL(cmrr.enable);
5395 	}
5396 
5397 #undef PIPE_CONF_CHECK_X
5398 #undef PIPE_CONF_CHECK_I
5399 #undef PIPE_CONF_CHECK_LLI
5400 #undef PIPE_CONF_CHECK_BOOL
5401 #undef PIPE_CONF_CHECK_P
5402 #undef PIPE_CONF_CHECK_FLAGS
5403 #undef PIPE_CONF_CHECK_COLOR_LUT
5404 #undef PIPE_CONF_CHECK_TIMINGS
5405 #undef PIPE_CONF_CHECK_RECT
5406 #undef PIPE_CONF_QUIRK
5407 
5408 	return ret;
5409 }
5410 
5411 static void
5412 intel_verify_planes(struct intel_atomic_state *state)
5413 {
5414 	struct intel_plane *plane;
5415 	const struct intel_plane_state *plane_state;
5416 	int i;
5417 
5418 	for_each_new_intel_plane_in_state(state, plane,
5419 					  plane_state, i)
5420 		assert_plane(plane, plane_state->is_y_plane ||
5421 			     plane_state->uapi.visible);
5422 }
5423 
5424 static int intel_modeset_pipe(struct intel_atomic_state *state,
5425 			      struct intel_crtc_state *crtc_state,
5426 			      const char *reason)
5427 {
5428 	struct intel_display *display = to_intel_display(state);
5429 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5430 	int ret;
5431 
5432 	drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5433 		    crtc->base.base.id, crtc->base.name, reason);
5434 
5435 	ret = drm_atomic_add_affected_connectors(&state->base,
5436 						 &crtc->base);
5437 	if (ret)
5438 		return ret;
5439 
5440 	ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc);
5441 	if (ret)
5442 		return ret;
5443 
5444 	ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5445 	if (ret)
5446 		return ret;
5447 
5448 	ret = intel_atomic_add_affected_planes(state, crtc);
5449 	if (ret)
5450 		return ret;
5451 
5452 	crtc_state->uapi.mode_changed = true;
5453 
5454 	return 0;
5455 }
5456 
5457 /**
5458  * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5459  * @state: intel atomic state
5460  * @reason: the reason for the full modeset
5461  * @mask: mask of pipes to modeset
5462  *
5463  * Add pipes in @mask to @state and force a full modeset on the enabled ones
5464  * due to the description in @reason.
5465  * This function can be called only before new plane states are computed.
5466  *
5467  * Returns 0 in case of success, negative error code otherwise.
5468  */
5469 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
5470 				      const char *reason, u8 mask)
5471 {
5472 	struct intel_display *display = to_intel_display(state);
5473 	struct intel_crtc *crtc;
5474 
5475 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) {
5476 		struct intel_crtc_state *crtc_state;
5477 		int ret;
5478 
5479 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5480 		if (IS_ERR(crtc_state))
5481 			return PTR_ERR(crtc_state);
5482 
5483 		if (!crtc_state->hw.enable ||
5484 		    intel_crtc_needs_modeset(crtc_state))
5485 			continue;
5486 
5487 		ret = intel_modeset_pipe(state, crtc_state, reason);
5488 		if (ret)
5489 			return ret;
5490 	}
5491 
5492 	return 0;
5493 }
5494 
5495 static void
5496 intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state)
5497 {
5498 	crtc_state->uapi.mode_changed = true;
5499 
5500 	crtc_state->update_pipe = false;
5501 	crtc_state->update_m_n = false;
5502 	crtc_state->update_lrr = false;
5503 }
5504 
5505 /**
5506  * intel_modeset_all_pipes_late - force a full modeset on all pipes
5507  * @state: intel atomic state
5508  * @reason: the reason for the full modeset
5509  *
5510  * Add all pipes to @state and force a full modeset on the active ones due to
5511  * the description in @reason.
5512  * This function can be called only after new plane states are computed already.
5513  *
5514  * Returns 0 in case of success, negative error code otherwise.
5515  */
5516 int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
5517 				 const char *reason)
5518 {
5519 	struct intel_display *display = to_intel_display(state);
5520 	struct intel_crtc *crtc;
5521 
5522 	for_each_intel_crtc(display->drm, crtc) {
5523 		struct intel_crtc_state *crtc_state;
5524 		int ret;
5525 
5526 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5527 		if (IS_ERR(crtc_state))
5528 			return PTR_ERR(crtc_state);
5529 
5530 		if (!crtc_state->hw.active ||
5531 		    intel_crtc_needs_modeset(crtc_state))
5532 			continue;
5533 
5534 		ret = intel_modeset_pipe(state, crtc_state, reason);
5535 		if (ret)
5536 			return ret;
5537 
5538 		intel_crtc_flag_modeset(crtc_state);
5539 
5540 		crtc_state->update_planes |= crtc_state->active_planes;
5541 		crtc_state->async_flip_planes = 0;
5542 		crtc_state->do_async_flip = false;
5543 	}
5544 
5545 	return 0;
5546 }
5547 
5548 int intel_modeset_commit_pipes(struct intel_display *display,
5549 			       u8 pipe_mask,
5550 			       struct drm_modeset_acquire_ctx *ctx)
5551 {
5552 	struct drm_atomic_state *state;
5553 	struct intel_crtc *crtc;
5554 	int ret;
5555 
5556 	state = drm_atomic_state_alloc(display->drm);
5557 	if (!state)
5558 		return -ENOMEM;
5559 
5560 	state->acquire_ctx = ctx;
5561 	to_intel_atomic_state(state)->internal = true;
5562 
5563 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {
5564 		struct intel_crtc_state *crtc_state =
5565 			intel_atomic_get_crtc_state(state, crtc);
5566 
5567 		if (IS_ERR(crtc_state)) {
5568 			ret = PTR_ERR(crtc_state);
5569 			goto out;
5570 		}
5571 
5572 		crtc_state->uapi.connectors_changed = true;
5573 	}
5574 
5575 	ret = drm_atomic_commit(state);
5576 out:
5577 	drm_atomic_state_put(state);
5578 
5579 	return ret;
5580 }
5581 
5582 /*
5583  * This implements the workaround described in the "notes" section of the mode
5584  * set sequence documentation. When going from no pipes or single pipe to
5585  * multiple pipes, and planes are enabled after the pipe, we need to wait at
5586  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5587  */
5588 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5589 {
5590 	struct intel_crtc_state *crtc_state;
5591 	struct intel_crtc *crtc;
5592 	struct intel_crtc_state *first_crtc_state = NULL;
5593 	struct intel_crtc_state *other_crtc_state = NULL;
5594 	enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5595 	int i;
5596 
5597 	/* look at all crtc's that are going to be enabled in during modeset */
5598 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5599 		if (!crtc_state->hw.active ||
5600 		    !intel_crtc_needs_modeset(crtc_state))
5601 			continue;
5602 
5603 		if (first_crtc_state) {
5604 			other_crtc_state = crtc_state;
5605 			break;
5606 		} else {
5607 			first_crtc_state = crtc_state;
5608 			first_pipe = crtc->pipe;
5609 		}
5610 	}
5611 
5612 	/* No workaround needed? */
5613 	if (!first_crtc_state)
5614 		return 0;
5615 
5616 	/* w/a possibly needed, check how many crtc's are already enabled. */
5617 	for_each_intel_crtc(state->base.dev, crtc) {
5618 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5619 		if (IS_ERR(crtc_state))
5620 			return PTR_ERR(crtc_state);
5621 
5622 		crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5623 
5624 		if (!crtc_state->hw.active ||
5625 		    intel_crtc_needs_modeset(crtc_state))
5626 			continue;
5627 
5628 		/* 2 or more enabled crtcs means no need for w/a */
5629 		if (enabled_pipe != INVALID_PIPE)
5630 			return 0;
5631 
5632 		enabled_pipe = crtc->pipe;
5633 	}
5634 
5635 	if (enabled_pipe != INVALID_PIPE)
5636 		first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5637 	else if (other_crtc_state)
5638 		other_crtc_state->hsw_workaround_pipe = first_pipe;
5639 
5640 	return 0;
5641 }
5642 
5643 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5644 			   u8 active_pipes)
5645 {
5646 	const struct intel_crtc_state *crtc_state;
5647 	struct intel_crtc *crtc;
5648 	int i;
5649 
5650 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5651 		if (crtc_state->hw.active)
5652 			active_pipes |= BIT(crtc->pipe);
5653 		else
5654 			active_pipes &= ~BIT(crtc->pipe);
5655 	}
5656 
5657 	return active_pipes;
5658 }
5659 
5660 static int intel_modeset_checks(struct intel_atomic_state *state)
5661 {
5662 	struct intel_display *display = to_intel_display(state);
5663 
5664 	state->modeset = true;
5665 
5666 	if (display->platform.haswell)
5667 		return hsw_mode_set_planes_workaround(state);
5668 
5669 	return 0;
5670 }
5671 
5672 static bool lrr_params_changed(const struct drm_display_mode *old_adjusted_mode,
5673 			       const struct drm_display_mode *new_adjusted_mode)
5674 {
5675 	return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start ||
5676 		old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end ||
5677 		old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal;
5678 }
5679 
5680 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5681 				     struct intel_crtc_state *new_crtc_state)
5682 {
5683 	struct intel_display *display = to_intel_display(new_crtc_state);
5684 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5685 
5686 	/* only allow LRR when the timings stay within the VRR range */
5687 	if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
5688 		new_crtc_state->update_lrr = false;
5689 
5690 	if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {
5691 		drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",
5692 			    crtc->base.base.id, crtc->base.name);
5693 	} else {
5694 		if (allow_vblank_delay_fastset(old_crtc_state))
5695 			new_crtc_state->update_lrr = true;
5696 		new_crtc_state->uapi.mode_changed = false;
5697 	}
5698 
5699 	if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
5700 				   &new_crtc_state->dp_m_n))
5701 		new_crtc_state->update_m_n = false;
5702 
5703 	if (!lrr_params_changed(&old_crtc_state->hw.adjusted_mode,
5704 				&new_crtc_state->hw.adjusted_mode))
5705 		new_crtc_state->update_lrr = false;
5706 
5707 	if (intel_crtc_needs_modeset(new_crtc_state))
5708 		intel_crtc_flag_modeset(new_crtc_state);
5709 	else
5710 		new_crtc_state->update_pipe = true;
5711 }
5712 
5713 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
5714 {
5715 	struct intel_display *display = to_intel_display(state);
5716 	struct intel_crtc_state __maybe_unused *crtc_state;
5717 	struct intel_crtc *crtc;
5718 	int i;
5719 
5720 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5721 		int ret;
5722 
5723 		ret = intel_crtc_atomic_check(state, crtc);
5724 		if (ret) {
5725 			drm_dbg_atomic(display->drm,
5726 				       "[CRTC:%d:%s] atomic driver check failed\n",
5727 				       crtc->base.base.id, crtc->base.name);
5728 			return ret;
5729 		}
5730 	}
5731 
5732 	return 0;
5733 }
5734 
5735 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
5736 					       u8 transcoders)
5737 {
5738 	const struct intel_crtc_state *new_crtc_state;
5739 	struct intel_crtc *crtc;
5740 	int i;
5741 
5742 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5743 		if (new_crtc_state->hw.enable &&
5744 		    transcoders & BIT(new_crtc_state->cpu_transcoder) &&
5745 		    intel_crtc_needs_modeset(new_crtc_state))
5746 			return true;
5747 	}
5748 
5749 	return false;
5750 }
5751 
5752 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
5753 				     u8 pipes)
5754 {
5755 	const struct intel_crtc_state *new_crtc_state;
5756 	struct intel_crtc *crtc;
5757 	int i;
5758 
5759 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5760 		if (new_crtc_state->hw.enable &&
5761 		    pipes & BIT(crtc->pipe) &&
5762 		    intel_crtc_needs_modeset(new_crtc_state))
5763 			return true;
5764 	}
5765 
5766 	return false;
5767 }
5768 
5769 static int intel_atomic_check_joiner(struct intel_atomic_state *state,
5770 				     struct intel_crtc *primary_crtc)
5771 {
5772 	struct intel_display *display = to_intel_display(state);
5773 	struct intel_crtc_state *primary_crtc_state =
5774 		intel_atomic_get_new_crtc_state(state, primary_crtc);
5775 	struct intel_crtc *secondary_crtc;
5776 
5777 	if (!primary_crtc_state->joiner_pipes)
5778 		return 0;
5779 
5780 	/* sanity check */
5781 	if (drm_WARN_ON(display->drm,
5782 			primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))
5783 		return -EINVAL;
5784 
5785 	if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) {
5786 		drm_dbg_kms(display->drm,
5787 			    "[CRTC:%d:%s] Cannot act as joiner primary "
5788 			    "(need 0x%x as pipes, only 0x%x possible)\n",
5789 			    primary_crtc->base.base.id, primary_crtc->base.name,
5790 			    primary_crtc_state->joiner_pipes, joiner_pipes(display));
5791 		return -EINVAL;
5792 	}
5793 
5794 	for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
5795 					 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
5796 		struct intel_crtc_state *secondary_crtc_state;
5797 		int ret;
5798 
5799 		secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc);
5800 		if (IS_ERR(secondary_crtc_state))
5801 			return PTR_ERR(secondary_crtc_state);
5802 
5803 		/* primary being enabled, secondary was already configured? */
5804 		if (secondary_crtc_state->uapi.enable) {
5805 			drm_dbg_kms(display->drm,
5806 				    "[CRTC:%d:%s] secondary is enabled as normal CRTC, but "
5807 				    "[CRTC:%d:%s] claiming this CRTC for joiner.\n",
5808 				    secondary_crtc->base.base.id, secondary_crtc->base.name,
5809 				    primary_crtc->base.base.id, primary_crtc->base.name);
5810 			return -EINVAL;
5811 		}
5812 
5813 		/*
5814 		 * The state copy logic assumes the primary crtc gets processed
5815 		 * before the secondary crtc during the main compute_config loop.
5816 		 * This works because the crtcs are created in pipe order,
5817 		 * and the hardware requires primary pipe < secondary pipe as well.
5818 		 * Should that change we need to rethink the logic.
5819 		 */
5820 		if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
5821 			    drm_crtc_index(&secondary_crtc->base)))
5822 			return -EINVAL;
5823 
5824 		drm_dbg_kms(display->drm,
5825 			    "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n",
5826 			    secondary_crtc->base.base.id, secondary_crtc->base.name,
5827 			    primary_crtc->base.base.id, primary_crtc->base.name);
5828 
5829 		secondary_crtc_state->joiner_pipes =
5830 			primary_crtc_state->joiner_pipes;
5831 
5832 		ret = copy_joiner_crtc_state_modeset(state, secondary_crtc);
5833 		if (ret)
5834 			return ret;
5835 	}
5836 
5837 	return 0;
5838 }
5839 
5840 static void kill_joiner_secondaries(struct intel_atomic_state *state,
5841 				    struct intel_crtc *primary_crtc)
5842 {
5843 	struct intel_display *display = to_intel_display(state);
5844 	struct intel_crtc_state *primary_crtc_state =
5845 		intel_atomic_get_new_crtc_state(state, primary_crtc);
5846 	struct intel_crtc *secondary_crtc;
5847 
5848 	for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
5849 					 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
5850 		struct intel_crtc_state *secondary_crtc_state =
5851 			intel_atomic_get_new_crtc_state(state, secondary_crtc);
5852 
5853 		secondary_crtc_state->joiner_pipes = 0;
5854 
5855 		intel_crtc_copy_uapi_to_hw_state_modeset(state, secondary_crtc);
5856 	}
5857 
5858 	primary_crtc_state->joiner_pipes = 0;
5859 }
5860 
5861 /**
5862  * DOC: asynchronous flip implementation
5863  *
5864  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5865  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5866  * Correspondingly, support is currently added for primary plane only.
5867  *
5868  * Async flip can only change the plane surface address, so anything else
5869  * changing is rejected from the intel_async_flip_check_hw() function.
5870  * Once this check is cleared, flip done interrupt is enabled using
5871  * the intel_crtc_enable_flip_done() function.
5872  *
5873  * As soon as the surface address register is written, flip done interrupt is
5874  * generated and the requested events are sent to the userspace in the interrupt
5875  * handler itself. The timestamp and sequence sent during the flip done event
5876  * correspond to the last vblank and have no relation to the actual time when
5877  * the flip done event was sent.
5878  */
5879 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
5880 				       struct intel_crtc *crtc)
5881 {
5882 	struct intel_display *display = to_intel_display(state);
5883 	const struct intel_crtc_state *new_crtc_state =
5884 		intel_atomic_get_new_crtc_state(state, crtc);
5885 	const struct intel_plane_state *old_plane_state;
5886 	struct intel_plane_state *new_plane_state;
5887 	struct intel_plane *plane;
5888 	int i;
5889 
5890 	if (!new_crtc_state->uapi.async_flip)
5891 		return 0;
5892 
5893 	if (!new_crtc_state->uapi.active) {
5894 		drm_dbg_kms(display->drm,
5895 			    "[CRTC:%d:%s] not active\n",
5896 			    crtc->base.base.id, crtc->base.name);
5897 		return -EINVAL;
5898 	}
5899 
5900 	if (intel_crtc_needs_modeset(new_crtc_state)) {
5901 		drm_dbg_kms(display->drm,
5902 			    "[CRTC:%d:%s] modeset required\n",
5903 			    crtc->base.base.id, crtc->base.name);
5904 		return -EINVAL;
5905 	}
5906 
5907 	/*
5908 	 * FIXME: joiner+async flip is busted currently.
5909 	 * Remove this check once the issues are fixed.
5910 	 */
5911 	if (new_crtc_state->joiner_pipes) {
5912 		drm_dbg_kms(display->drm,
5913 			    "[CRTC:%d:%s] async flip disallowed with joiner\n",
5914 			    crtc->base.base.id, crtc->base.name);
5915 		return -EINVAL;
5916 	}
5917 
5918 	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
5919 					     new_plane_state, i) {
5920 		if (plane->pipe != crtc->pipe)
5921 			continue;
5922 
5923 		/*
5924 		 * TODO: Async flip is only supported through the page flip IOCTL
5925 		 * as of now. So support currently added for primary plane only.
5926 		 * Support for other planes on platforms on which supports
5927 		 * this(vlv/chv and icl+) should be added when async flip is
5928 		 * enabled in the atomic IOCTL path.
5929 		 */
5930 		if (!plane->async_flip) {
5931 			drm_dbg_kms(display->drm,
5932 				    "[PLANE:%d:%s] async flip not supported\n",
5933 				    plane->base.base.id, plane->base.name);
5934 			return -EINVAL;
5935 		}
5936 
5937 		if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
5938 			drm_dbg_kms(display->drm,
5939 				    "[PLANE:%d:%s] no old or new framebuffer\n",
5940 				    plane->base.base.id, plane->base.name);
5941 			return -EINVAL;
5942 		}
5943 	}
5944 
5945 	return 0;
5946 }
5947 
5948 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
5949 {
5950 	struct intel_display *display = to_intel_display(state);
5951 	const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
5952 	const struct intel_plane_state *new_plane_state, *old_plane_state;
5953 	struct intel_plane *plane;
5954 	int i;
5955 
5956 	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5957 	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5958 
5959 	if (!new_crtc_state->uapi.async_flip)
5960 		return 0;
5961 
5962 	if (!new_crtc_state->hw.active) {
5963 		drm_dbg_kms(display->drm,
5964 			    "[CRTC:%d:%s] not active\n",
5965 			    crtc->base.base.id, crtc->base.name);
5966 		return -EINVAL;
5967 	}
5968 
5969 	if (intel_crtc_needs_modeset(new_crtc_state)) {
5970 		drm_dbg_kms(display->drm,
5971 			    "[CRTC:%d:%s] modeset required\n",
5972 			    crtc->base.base.id, crtc->base.name);
5973 		return -EINVAL;
5974 	}
5975 
5976 	if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
5977 		drm_dbg_kms(display->drm,
5978 			    "[CRTC:%d:%s] Active planes cannot be in async flip\n",
5979 			    crtc->base.base.id, crtc->base.name);
5980 		return -EINVAL;
5981 	}
5982 
5983 	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
5984 					     new_plane_state, i) {
5985 		if (plane->pipe != crtc->pipe)
5986 			continue;
5987 
5988 		/*
5989 		 * Only async flip capable planes should be in the state
5990 		 * if we're really about to ask the hardware to perform
5991 		 * an async flip. We should never get this far otherwise.
5992 		 */
5993 		if (drm_WARN_ON(display->drm,
5994 				new_crtc_state->do_async_flip && !plane->async_flip))
5995 			return -EINVAL;
5996 
5997 		/*
5998 		 * Only check async flip capable planes other planes
5999 		 * may be involved in the initial commit due to
6000 		 * the wm0/ddb optimization.
6001 		 *
6002 		 * TODO maybe should track which planes actually
6003 		 * were requested to do the async flip...
6004 		 */
6005 		if (!plane->async_flip)
6006 			continue;
6007 
6008 		if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->modifier)) {
6009 			drm_dbg_kms(display->drm,
6010 				    "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
6011 				    plane->base.base.id, plane->base.name,
6012 				    new_plane_state->hw.fb->modifier);
6013 			return -EINVAL;
6014 		}
6015 
6016 		if (intel_format_info_is_yuv_semiplanar(new_plane_state->hw.fb->format,
6017 							new_plane_state->hw.fb->modifier)) {
6018 			drm_dbg_kms(display->drm,
6019 				    "[PLANE:%d:%s] Planar formats do not support async flips\n",
6020 				    plane->base.base.id, plane->base.name);
6021 			return -EINVAL;
6022 		}
6023 
6024 		/*
6025 		 * We turn the first async flip request into a sync flip
6026 		 * so that we can reconfigure the plane (eg. change modifier).
6027 		 */
6028 		if (!new_crtc_state->do_async_flip)
6029 			continue;
6030 
6031 		if (old_plane_state->view.color_plane[0].mapping_stride !=
6032 		    new_plane_state->view.color_plane[0].mapping_stride) {
6033 			drm_dbg_kms(display->drm,
6034 				    "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6035 				    plane->base.base.id, plane->base.name);
6036 			return -EINVAL;
6037 		}
6038 
6039 		if (old_plane_state->hw.fb->modifier !=
6040 		    new_plane_state->hw.fb->modifier) {
6041 			drm_dbg_kms(display->drm,
6042 				    "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6043 				    plane->base.base.id, plane->base.name);
6044 			return -EINVAL;
6045 		}
6046 
6047 		if (old_plane_state->hw.fb->format !=
6048 		    new_plane_state->hw.fb->format) {
6049 			drm_dbg_kms(display->drm,
6050 				    "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6051 				    plane->base.base.id, plane->base.name);
6052 			return -EINVAL;
6053 		}
6054 
6055 		if (old_plane_state->hw.rotation !=
6056 		    new_plane_state->hw.rotation) {
6057 			drm_dbg_kms(display->drm,
6058 				    "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6059 				    plane->base.base.id, plane->base.name);
6060 			return -EINVAL;
6061 		}
6062 
6063 		if (skl_plane_aux_dist(old_plane_state, 0) !=
6064 		    skl_plane_aux_dist(new_plane_state, 0)) {
6065 			drm_dbg_kms(display->drm,
6066 				    "[PLANE:%d:%s] AUX_DIST cannot be changed in async flip\n",
6067 				    plane->base.base.id, plane->base.name);
6068 			return -EINVAL;
6069 		}
6070 
6071 		if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6072 		    !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6073 			drm_dbg_kms(display->drm,
6074 				    "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6075 				    plane->base.base.id, plane->base.name);
6076 			return -EINVAL;
6077 		}
6078 
6079 		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6080 			drm_dbg_kms(display->drm,
6081 				    "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6082 				    plane->base.base.id, plane->base.name);
6083 			return -EINVAL;
6084 		}
6085 
6086 		if (old_plane_state->hw.pixel_blend_mode !=
6087 		    new_plane_state->hw.pixel_blend_mode) {
6088 			drm_dbg_kms(display->drm,
6089 				    "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6090 				    plane->base.base.id, plane->base.name);
6091 			return -EINVAL;
6092 		}
6093 
6094 		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6095 			drm_dbg_kms(display->drm,
6096 				    "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6097 				    plane->base.base.id, plane->base.name);
6098 			return -EINVAL;
6099 		}
6100 
6101 		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6102 			drm_dbg_kms(display->drm,
6103 				    "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6104 				    plane->base.base.id, plane->base.name);
6105 			return -EINVAL;
6106 		}
6107 
6108 		/* plane decryption is allow to change only in synchronous flips */
6109 		if (old_plane_state->decrypt != new_plane_state->decrypt) {
6110 			drm_dbg_kms(display->drm,
6111 				    "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6112 				    plane->base.base.id, plane->base.name);
6113 			return -EINVAL;
6114 		}
6115 	}
6116 
6117 	return 0;
6118 }
6119 
6120 static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
6121 {
6122 	struct intel_display *display = to_intel_display(state);
6123 	const struct intel_plane_state *plane_state;
6124 	struct intel_crtc_state *crtc_state;
6125 	struct intel_plane *plane;
6126 	struct intel_crtc *crtc;
6127 	u8 affected_pipes = 0;
6128 	u8 modeset_pipes = 0;
6129 	int i;
6130 
6131 	/*
6132 	 * Any plane which is in use by the joiner needs its crtc.
6133 	 * Pull those in first as this will not have happened yet
6134 	 * if the plane remains disabled according to uapi.
6135 	 */
6136 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6137 		crtc = to_intel_crtc(plane_state->hw.crtc);
6138 		if (!crtc)
6139 			continue;
6140 
6141 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6142 		if (IS_ERR(crtc_state))
6143 			return PTR_ERR(crtc_state);
6144 	}
6145 
6146 	/* Now pull in all joined crtcs */
6147 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6148 		affected_pipes |= crtc_state->joiner_pipes;
6149 		if (intel_crtc_needs_modeset(crtc_state))
6150 			modeset_pipes |= crtc_state->joiner_pipes;
6151 	}
6152 
6153 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) {
6154 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6155 		if (IS_ERR(crtc_state))
6156 			return PTR_ERR(crtc_state);
6157 	}
6158 
6159 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) {
6160 		int ret;
6161 
6162 		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6163 
6164 		crtc_state->uapi.mode_changed = true;
6165 
6166 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6167 		if (ret)
6168 			return ret;
6169 
6170 		ret = intel_atomic_add_affected_planes(state, crtc);
6171 		if (ret)
6172 			return ret;
6173 	}
6174 
6175 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6176 		/* Kill old joiner link, we may re-establish afterwards */
6177 		if (intel_crtc_needs_modeset(crtc_state) &&
6178 		    intel_crtc_is_joiner_primary(crtc_state))
6179 			kill_joiner_secondaries(state, crtc);
6180 	}
6181 
6182 	return 0;
6183 }
6184 
6185 static int intel_atomic_check_config(struct intel_atomic_state *state,
6186 				     struct intel_link_bw_limits *limits,
6187 				     enum pipe *failed_pipe)
6188 {
6189 	struct intel_display *display = to_intel_display(state);
6190 	struct intel_crtc_state *new_crtc_state;
6191 	struct intel_crtc *crtc;
6192 	int ret;
6193 	int i;
6194 
6195 	*failed_pipe = INVALID_PIPE;
6196 
6197 	ret = intel_joiner_add_affected_crtcs(state);
6198 	if (ret)
6199 		return ret;
6200 
6201 	ret = intel_fdi_add_affected_crtcs(state);
6202 	if (ret)
6203 		return ret;
6204 
6205 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6206 		if (!intel_crtc_needs_modeset(new_crtc_state)) {
6207 			if (intel_crtc_is_joiner_secondary(new_crtc_state))
6208 				copy_joiner_crtc_state_nomodeset(state, crtc);
6209 			else
6210 				intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6211 			continue;
6212 		}
6213 
6214 		if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6215 			continue;
6216 
6217 		ret = intel_crtc_prepare_cleared_state(state, crtc);
6218 		if (ret)
6219 			goto fail;
6220 
6221 		if (!new_crtc_state->hw.enable)
6222 			continue;
6223 
6224 		ret = intel_modeset_pipe_config(state, crtc, limits);
6225 		if (ret)
6226 			goto fail;
6227 	}
6228 
6229 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6230 		if (!intel_crtc_needs_modeset(new_crtc_state))
6231 			continue;
6232 
6233 		if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6234 			continue;
6235 
6236 		if (!new_crtc_state->hw.enable)
6237 			continue;
6238 
6239 		ret = intel_modeset_pipe_config_late(state, crtc);
6240 		if (ret)
6241 			goto fail;
6242 	}
6243 
6244 fail:
6245 	if (ret)
6246 		*failed_pipe = crtc->pipe;
6247 
6248 	return ret;
6249 }
6250 
6251 static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
6252 {
6253 	struct intel_link_bw_limits new_limits;
6254 	struct intel_link_bw_limits old_limits;
6255 	int ret;
6256 
6257 	intel_link_bw_init_limits(state, &new_limits);
6258 	old_limits = new_limits;
6259 
6260 	while (true) {
6261 		enum pipe failed_pipe;
6262 
6263 		ret = intel_atomic_check_config(state, &new_limits,
6264 						&failed_pipe);
6265 		if (ret) {
6266 			/*
6267 			 * The bpp limit for a pipe is below the minimum it supports, set the
6268 			 * limit to the minimum and recalculate the config.
6269 			 */
6270 			if (ret == -EINVAL &&
6271 			    intel_link_bw_set_bpp_limit_for_pipe(state,
6272 								 &old_limits,
6273 								 &new_limits,
6274 								 failed_pipe))
6275 				continue;
6276 
6277 			break;
6278 		}
6279 
6280 		old_limits = new_limits;
6281 
6282 		ret = intel_link_bw_atomic_check(state, &new_limits);
6283 		if (ret != -EAGAIN)
6284 			break;
6285 	}
6286 
6287 	return ret;
6288 }
6289 /**
6290  * intel_atomic_check - validate state object
6291  * @dev: drm device
6292  * @_state: state to validate
6293  */
6294 int intel_atomic_check(struct drm_device *dev,
6295 		       struct drm_atomic_state *_state)
6296 {
6297 	struct intel_display *display = to_intel_display(dev);
6298 	struct intel_atomic_state *state = to_intel_atomic_state(_state);
6299 	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6300 	struct intel_crtc *crtc;
6301 	int ret, i;
6302 	bool any_ms = false;
6303 
6304 	if (!intel_display_driver_check_access(display))
6305 		return -ENODEV;
6306 
6307 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6308 					    new_crtc_state, i) {
6309 		/*
6310 		 * crtc's state no longer considered to be inherited
6311 		 * after the first userspace/client initiated commit.
6312 		 */
6313 		if (!state->internal)
6314 			new_crtc_state->inherited = false;
6315 
6316 		if (new_crtc_state->inherited != old_crtc_state->inherited)
6317 			new_crtc_state->uapi.mode_changed = true;
6318 
6319 		if (new_crtc_state->uapi.scaling_filter !=
6320 		    old_crtc_state->uapi.scaling_filter)
6321 			new_crtc_state->uapi.mode_changed = true;
6322 	}
6323 
6324 	intel_vrr_check_modeset(state);
6325 
6326 	ret = drm_atomic_helper_check_modeset(dev, &state->base);
6327 	if (ret)
6328 		goto fail;
6329 
6330 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6331 		ret = intel_async_flip_check_uapi(state, crtc);
6332 		if (ret)
6333 			return ret;
6334 	}
6335 
6336 	ret = intel_atomic_check_config_and_link(state);
6337 	if (ret)
6338 		goto fail;
6339 
6340 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6341 		if (!intel_crtc_needs_modeset(new_crtc_state))
6342 			continue;
6343 
6344 		if (intel_crtc_is_joiner_secondary(new_crtc_state)) {
6345 			drm_WARN_ON(display->drm, new_crtc_state->uapi.enable);
6346 			continue;
6347 		}
6348 
6349 		ret = intel_atomic_check_joiner(state, crtc);
6350 		if (ret)
6351 			goto fail;
6352 	}
6353 
6354 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6355 					    new_crtc_state, i) {
6356 		if (!intel_crtc_needs_modeset(new_crtc_state))
6357 			continue;
6358 
6359 		intel_joiner_adjust_pipe_src(new_crtc_state);
6360 
6361 		intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6362 	}
6363 
6364 	/**
6365 	 * Check if fastset is allowed by external dependencies like other
6366 	 * pipes and transcoders.
6367 	 *
6368 	 * Right now it only forces a fullmodeset when the MST master
6369 	 * transcoder did not changed but the pipe of the master transcoder
6370 	 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6371 	 * in case of port synced crtcs, if one of the synced crtcs
6372 	 * needs a full modeset, all other synced crtcs should be
6373 	 * forced a full modeset.
6374 	 */
6375 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6376 		if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6377 			continue;
6378 
6379 		if (intel_dp_mst_crtc_needs_modeset(state, crtc))
6380 			intel_crtc_flag_modeset(new_crtc_state);
6381 
6382 		if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6383 			enum transcoder master = new_crtc_state->mst_master_transcoder;
6384 
6385 			if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
6386 				intel_crtc_flag_modeset(new_crtc_state);
6387 		}
6388 
6389 		if (is_trans_port_sync_mode(new_crtc_state)) {
6390 			u8 trans = new_crtc_state->sync_mode_slaves_mask;
6391 
6392 			if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6393 				trans |= BIT(new_crtc_state->master_transcoder);
6394 
6395 			if (intel_cpu_transcoders_need_modeset(state, trans))
6396 				intel_crtc_flag_modeset(new_crtc_state);
6397 		}
6398 
6399 		if (new_crtc_state->joiner_pipes) {
6400 			if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes))
6401 				intel_crtc_flag_modeset(new_crtc_state);
6402 		}
6403 	}
6404 
6405 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6406 					    new_crtc_state, i) {
6407 		if (!intel_crtc_needs_modeset(new_crtc_state))
6408 			continue;
6409 
6410 		any_ms = true;
6411 
6412 		intel_release_shared_dplls(state, crtc);
6413 	}
6414 
6415 	if (any_ms && !check_digital_port_conflicts(state)) {
6416 		drm_dbg_kms(display->drm,
6417 			    "rejecting conflicting digital port configuration\n");
6418 		ret = -EINVAL;
6419 		goto fail;
6420 	}
6421 
6422 	ret = intel_atomic_check_planes(state);
6423 	if (ret)
6424 		goto fail;
6425 
6426 	ret = intel_compute_global_watermarks(state);
6427 	if (ret)
6428 		goto fail;
6429 
6430 	ret = intel_bw_atomic_check(state);
6431 	if (ret)
6432 		goto fail;
6433 
6434 	ret = intel_cdclk_atomic_check(state, &any_ms);
6435 	if (ret)
6436 		goto fail;
6437 
6438 	if (intel_any_crtc_needs_modeset(state))
6439 		any_ms = true;
6440 
6441 	if (any_ms) {
6442 		ret = intel_modeset_checks(state);
6443 		if (ret)
6444 			goto fail;
6445 
6446 		ret = intel_modeset_calc_cdclk(state);
6447 		if (ret)
6448 			return ret;
6449 	}
6450 
6451 	ret = intel_pmdemand_atomic_check(state);
6452 	if (ret)
6453 		goto fail;
6454 
6455 	ret = intel_atomic_check_crtcs(state);
6456 	if (ret)
6457 		goto fail;
6458 
6459 	ret = intel_fbc_atomic_check(state);
6460 	if (ret)
6461 		goto fail;
6462 
6463 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6464 					    new_crtc_state, i) {
6465 		intel_color_assert_luts(new_crtc_state);
6466 
6467 		ret = intel_async_flip_check_hw(state, crtc);
6468 		if (ret)
6469 			goto fail;
6470 
6471 		/* Either full modeset or fastset (or neither), never both */
6472 		drm_WARN_ON(display->drm,
6473 			    intel_crtc_needs_modeset(new_crtc_state) &&
6474 			    intel_crtc_needs_fastset(new_crtc_state));
6475 
6476 		if (!intel_crtc_needs_modeset(new_crtc_state) &&
6477 		    !intel_crtc_needs_fastset(new_crtc_state))
6478 			continue;
6479 
6480 		intel_crtc_state_dump(new_crtc_state, state,
6481 				      intel_crtc_needs_modeset(new_crtc_state) ?
6482 				      "modeset" : "fastset");
6483 	}
6484 
6485 	return 0;
6486 
6487  fail:
6488 	if (ret == -EDEADLK)
6489 		return ret;
6490 
6491 	/*
6492 	 * FIXME would probably be nice to know which crtc specifically
6493 	 * caused the failure, in cases where we can pinpoint it.
6494 	 */
6495 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6496 					    new_crtc_state, i)
6497 		intel_crtc_state_dump(new_crtc_state, state, "failed");
6498 
6499 	return ret;
6500 }
6501 
6502 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6503 {
6504 	int ret;
6505 
6506 	ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6507 	if (ret < 0)
6508 		return ret;
6509 
6510 	return 0;
6511 }
6512 
6513 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6514 				  struct intel_crtc_state *crtc_state)
6515 {
6516 	struct intel_display *display = to_intel_display(crtc);
6517 
6518 	if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)
6519 		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);
6520 
6521 	if (crtc_state->has_pch_encoder) {
6522 		enum pipe pch_transcoder =
6523 			intel_crtc_pch_transcoder(crtc);
6524 
6525 		intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true);
6526 	}
6527 }
6528 
6529 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6530 			       const struct intel_crtc_state *new_crtc_state)
6531 {
6532 	struct intel_display *display = to_intel_display(new_crtc_state);
6533 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6534 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6535 
6536 	/*
6537 	 * Update pipe size and adjust fitter if needed: the reason for this is
6538 	 * that in compute_mode_changes we check the native mode (not the pfit
6539 	 * mode) to see if we can flip rather than do a full mode set. In the
6540 	 * fastboot case, we'll flip, but if we don't update the pipesrc and
6541 	 * pfit state, we'll end up with a big fb scanned out into the wrong
6542 	 * sized surface.
6543 	 */
6544 	intel_set_pipe_src_size(new_crtc_state);
6545 
6546 	/* on skylake this is done by detaching scalers */
6547 	if (DISPLAY_VER(display) >= 9) {
6548 		if (new_crtc_state->pch_pfit.enabled)
6549 			skl_pfit_enable(new_crtc_state);
6550 	} else if (HAS_PCH_SPLIT(dev_priv)) {
6551 		if (new_crtc_state->pch_pfit.enabled)
6552 			ilk_pfit_enable(new_crtc_state);
6553 		else if (old_crtc_state->pch_pfit.enabled)
6554 			ilk_pfit_disable(old_crtc_state);
6555 	}
6556 
6557 	/*
6558 	 * The register is supposedly single buffered so perhaps
6559 	 * not 100% correct to do this here. But SKL+ calculate
6560 	 * this based on the adjust pixel rate so pfit changes do
6561 	 * affect it and so it must be updated for fastsets.
6562 	 * HSW/BDW only really need this here for fastboot, after
6563 	 * that the value should not change without a full modeset.
6564 	 */
6565 	if (DISPLAY_VER(display) >= 9 ||
6566 	    display->platform.broadwell || display->platform.haswell)
6567 		hsw_set_linetime_wm(new_crtc_state);
6568 
6569 	if (new_crtc_state->update_m_n)
6570 		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
6571 					       &new_crtc_state->dp_m_n);
6572 
6573 	if (new_crtc_state->update_lrr)
6574 		intel_set_transcoder_timings_lrr(new_crtc_state);
6575 }
6576 
6577 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6578 				   struct intel_crtc *crtc)
6579 {
6580 	struct intel_display *display = to_intel_display(state);
6581 	const struct intel_crtc_state *old_crtc_state =
6582 		intel_atomic_get_old_crtc_state(state, crtc);
6583 	const struct intel_crtc_state *new_crtc_state =
6584 		intel_atomic_get_new_crtc_state(state, crtc);
6585 	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6586 
6587 	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
6588 
6589 	/*
6590 	 * During modesets pipe configuration was programmed as the
6591 	 * CRTC was enabled.
6592 	 */
6593 	if (!modeset) {
6594 		if (intel_crtc_needs_color_update(new_crtc_state))
6595 			intel_color_commit_arm(NULL, new_crtc_state);
6596 
6597 		if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)
6598 			bdw_set_pipe_misc(NULL, new_crtc_state);
6599 
6600 		if (intel_crtc_needs_fastset(new_crtc_state))
6601 			intel_pipe_fastset(old_crtc_state, new_crtc_state);
6602 	}
6603 
6604 	intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state);
6605 
6606 	intel_atomic_update_watermarks(state, crtc);
6607 }
6608 
6609 static void commit_pipe_post_planes(struct intel_atomic_state *state,
6610 				    struct intel_crtc *crtc)
6611 {
6612 	struct intel_display *display = to_intel_display(state);
6613 	const struct intel_crtc_state *new_crtc_state =
6614 		intel_atomic_get_new_crtc_state(state, crtc);
6615 
6616 	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
6617 
6618 	/*
6619 	 * Disable the scaler(s) after the plane(s) so that we don't
6620 	 * get a catastrophic underrun even if the two operations
6621 	 * end up happening in two different frames.
6622 	 */
6623 	if (DISPLAY_VER(display) >= 9 &&
6624 	    !intel_crtc_needs_modeset(new_crtc_state))
6625 		skl_detach_scalers(NULL, new_crtc_state);
6626 
6627 	if (intel_crtc_vrr_enabling(state, crtc))
6628 		intel_vrr_enable(new_crtc_state);
6629 }
6630 
6631 static void intel_enable_crtc(struct intel_atomic_state *state,
6632 			      struct intel_crtc *crtc)
6633 {
6634 	struct intel_display *display = to_intel_display(state);
6635 	const struct intel_crtc_state *new_crtc_state =
6636 		intel_atomic_get_new_crtc_state(state, crtc);
6637 	struct intel_crtc *pipe_crtc;
6638 
6639 	if (!intel_crtc_needs_modeset(new_crtc_state))
6640 		return;
6641 
6642 	for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc,
6643 						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
6644 		const struct intel_crtc_state *pipe_crtc_state =
6645 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
6646 
6647 		/* VRR will be enable later, if required */
6648 		intel_crtc_update_active_timings(pipe_crtc_state, false);
6649 	}
6650 
6651 	display->funcs.display->crtc_enable(state, crtc);
6652 
6653 	/* vblanks work again, re-enable pipe CRC. */
6654 	intel_crtc_enable_pipe_crc(crtc);
6655 }
6656 
6657 static void intel_pre_update_crtc(struct intel_atomic_state *state,
6658 				  struct intel_crtc *crtc)
6659 {
6660 	struct intel_display *display = to_intel_display(state);
6661 	const struct intel_crtc_state *old_crtc_state =
6662 		intel_atomic_get_old_crtc_state(state, crtc);
6663 	struct intel_crtc_state *new_crtc_state =
6664 		intel_atomic_get_new_crtc_state(state, crtc);
6665 	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6666 
6667 	if (old_crtc_state->inherited ||
6668 	    intel_crtc_needs_modeset(new_crtc_state)) {
6669 		if (HAS_DPT(display))
6670 			intel_dpt_configure(crtc);
6671 	}
6672 
6673 	if (!modeset) {
6674 		if (new_crtc_state->preload_luts &&
6675 		    intel_crtc_needs_color_update(new_crtc_state))
6676 			intel_color_load_luts(new_crtc_state);
6677 
6678 		intel_pre_plane_update(state, crtc);
6679 
6680 		if (intel_crtc_needs_fastset(new_crtc_state))
6681 			intel_encoders_update_pipe(state, crtc);
6682 
6683 		if (DISPLAY_VER(display) >= 11 &&
6684 		    intel_crtc_needs_fastset(new_crtc_state))
6685 			icl_set_pipe_chicken(new_crtc_state);
6686 
6687 		if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
6688 		    cmrr_params_changed(old_crtc_state, new_crtc_state))
6689 			intel_vrr_set_transcoder_timings(new_crtc_state);
6690 	}
6691 
6692 	intel_fbc_update(state, crtc);
6693 
6694 	drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF));
6695 
6696 	if (!modeset &&
6697 	    intel_crtc_needs_color_update(new_crtc_state) &&
6698 	    !new_crtc_state->use_dsb)
6699 		intel_color_commit_noarm(NULL, new_crtc_state);
6700 
6701 	if (!new_crtc_state->use_dsb)
6702 		intel_crtc_planes_update_noarm(NULL, state, crtc);
6703 }
6704 
6705 static void intel_update_crtc(struct intel_atomic_state *state,
6706 			      struct intel_crtc *crtc)
6707 {
6708 	const struct intel_crtc_state *old_crtc_state =
6709 		intel_atomic_get_old_crtc_state(state, crtc);
6710 	struct intel_crtc_state *new_crtc_state =
6711 		intel_atomic_get_new_crtc_state(state, crtc);
6712 
6713 	if (new_crtc_state->use_dsb) {
6714 		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event);
6715 
6716 		intel_dsb_commit(new_crtc_state->dsb_commit, false);
6717 	} else {
6718 		/* Perform vblank evasion around commit operation */
6719 		intel_pipe_update_start(state, crtc);
6720 
6721 		if (new_crtc_state->dsb_commit)
6722 			intel_dsb_commit(new_crtc_state->dsb_commit, false);
6723 
6724 		commit_pipe_pre_planes(state, crtc);
6725 
6726 		intel_crtc_planes_update_arm(NULL, state, crtc);
6727 
6728 		commit_pipe_post_planes(state, crtc);
6729 
6730 		intel_pipe_update_end(state, crtc);
6731 	}
6732 
6733 	/*
6734 	 * VRR/Seamless M/N update may need to update frame timings.
6735 	 *
6736 	 * FIXME Should be synchronized with the start of vblank somehow...
6737 	 */
6738 	if (intel_crtc_vrr_enabling(state, crtc) ||
6739 	    new_crtc_state->update_m_n || new_crtc_state->update_lrr)
6740 		intel_crtc_update_active_timings(new_crtc_state,
6741 						 new_crtc_state->vrr.enable);
6742 
6743 	/*
6744 	 * We usually enable FIFO underrun interrupts as part of the
6745 	 * CRTC enable sequence during modesets.  But when we inherit a
6746 	 * valid pipe configuration from the BIOS we need to take care
6747 	 * of enabling them on the CRTC's first fastset.
6748 	 */
6749 	if (intel_crtc_needs_fastset(new_crtc_state) &&
6750 	    old_crtc_state->inherited)
6751 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
6752 }
6753 
6754 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6755 					  struct intel_crtc *crtc)
6756 {
6757 	struct intel_display *display = to_intel_display(state);
6758 	const struct intel_crtc_state *old_crtc_state =
6759 		intel_atomic_get_old_crtc_state(state, crtc);
6760 	struct intel_crtc *pipe_crtc;
6761 
6762 	/*
6763 	 * We need to disable pipe CRC before disabling the pipe,
6764 	 * or we race against vblank off.
6765 	 */
6766 	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
6767 					 intel_crtc_joined_pipe_mask(old_crtc_state))
6768 		intel_crtc_disable_pipe_crc(pipe_crtc);
6769 
6770 	display->funcs.display->crtc_disable(state, crtc);
6771 
6772 	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
6773 					 intel_crtc_joined_pipe_mask(old_crtc_state)) {
6774 		const struct intel_crtc_state *new_pipe_crtc_state =
6775 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
6776 
6777 		pipe_crtc->active = false;
6778 		intel_fbc_disable(pipe_crtc);
6779 
6780 		if (!new_pipe_crtc_state->hw.active)
6781 			intel_initial_watermarks(state, pipe_crtc);
6782 	}
6783 }
6784 
6785 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6786 {
6787 	struct intel_display *display = to_intel_display(state);
6788 	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6789 	struct intel_crtc *crtc;
6790 	u8 disable_pipes = 0;
6791 	int i;
6792 
6793 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6794 					    new_crtc_state, i) {
6795 		if (!intel_crtc_needs_modeset(new_crtc_state))
6796 			continue;
6797 
6798 		/*
6799 		 * Needs to be done even for pipes
6800 		 * that weren't enabled previously.
6801 		 */
6802 		intel_pre_plane_update(state, crtc);
6803 
6804 		if (!old_crtc_state->hw.active)
6805 			continue;
6806 
6807 		disable_pipes |= BIT(crtc->pipe);
6808 	}
6809 
6810 	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6811 		if ((disable_pipes & BIT(crtc->pipe)) == 0)
6812 			continue;
6813 
6814 		intel_crtc_disable_planes(state, crtc);
6815 
6816 		drm_vblank_work_flush_all(&crtc->base);
6817 	}
6818 
6819 	/* Only disable port sync and MST slaves */
6820 	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6821 		if ((disable_pipes & BIT(crtc->pipe)) == 0)
6822 			continue;
6823 
6824 		if (intel_crtc_is_joiner_secondary(old_crtc_state))
6825 			continue;
6826 
6827 		/* In case of Transcoder port Sync master slave CRTCs can be
6828 		 * assigned in any order and we need to make sure that
6829 		 * slave CRTCs are disabled first and then master CRTC since
6830 		 * Slave vblanks are masked till Master Vblanks.
6831 		 */
6832 		if (!is_trans_port_sync_slave(old_crtc_state) &&
6833 		    !intel_dp_mst_is_slave_trans(old_crtc_state))
6834 			continue;
6835 
6836 		intel_old_crtc_state_disables(state, crtc);
6837 
6838 		disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
6839 	}
6840 
6841 	/* Disable everything else left on */
6842 	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6843 		if ((disable_pipes & BIT(crtc->pipe)) == 0)
6844 			continue;
6845 
6846 		if (intel_crtc_is_joiner_secondary(old_crtc_state))
6847 			continue;
6848 
6849 		intel_old_crtc_state_disables(state, crtc);
6850 
6851 		disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
6852 	}
6853 
6854 	drm_WARN_ON(display->drm, disable_pipes);
6855 }
6856 
6857 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
6858 {
6859 	struct intel_crtc_state *new_crtc_state;
6860 	struct intel_crtc *crtc;
6861 	int i;
6862 
6863 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6864 		if (!new_crtc_state->hw.active)
6865 			continue;
6866 
6867 		intel_enable_crtc(state, crtc);
6868 		intel_pre_update_crtc(state, crtc);
6869 	}
6870 
6871 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6872 		if (!new_crtc_state->hw.active)
6873 			continue;
6874 
6875 		intel_update_crtc(state, crtc);
6876 	}
6877 }
6878 
6879 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
6880 {
6881 	struct intel_display *display = to_intel_display(state);
6882 	struct intel_crtc *crtc;
6883 	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6884 	struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
6885 	u8 update_pipes = 0, modeset_pipes = 0;
6886 	int i;
6887 
6888 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6889 		enum pipe pipe = crtc->pipe;
6890 
6891 		if (!new_crtc_state->hw.active)
6892 			continue;
6893 
6894 		/* ignore allocations for crtc's that have been turned off. */
6895 		if (!intel_crtc_needs_modeset(new_crtc_state)) {
6896 			entries[pipe] = old_crtc_state->wm.skl.ddb;
6897 			update_pipes |= BIT(pipe);
6898 		} else {
6899 			modeset_pipes |= BIT(pipe);
6900 		}
6901 	}
6902 
6903 	/*
6904 	 * Whenever the number of active pipes changes, we need to make sure we
6905 	 * update the pipes in the right order so that their ddb allocations
6906 	 * never overlap with each other between CRTC updates. Otherwise we'll
6907 	 * cause pipe underruns and other bad stuff.
6908 	 *
6909 	 * So first lets enable all pipes that do not need a fullmodeset as
6910 	 * those don't have any external dependency.
6911 	 */
6912 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6913 		enum pipe pipe = crtc->pipe;
6914 
6915 		if ((update_pipes & BIT(pipe)) == 0)
6916 			continue;
6917 
6918 		intel_pre_update_crtc(state, crtc);
6919 	}
6920 
6921 	intel_dbuf_mbus_pre_ddb_update(state);
6922 
6923 	while (update_pipes) {
6924 		/*
6925 		 * Commit in reverse order to make joiner primary
6926 		 * send the uapi events after secondaries are done.
6927 		 */
6928 		for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
6929 							    new_crtc_state, i) {
6930 			enum pipe pipe = crtc->pipe;
6931 
6932 			if ((update_pipes & BIT(pipe)) == 0)
6933 				continue;
6934 
6935 			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
6936 							entries, I915_MAX_PIPES, pipe))
6937 				continue;
6938 
6939 			entries[pipe] = new_crtc_state->wm.skl.ddb;
6940 			update_pipes &= ~BIT(pipe);
6941 
6942 			intel_update_crtc(state, crtc);
6943 
6944 			/*
6945 			 * If this is an already active pipe, it's DDB changed,
6946 			 * and this isn't the last pipe that needs updating
6947 			 * then we need to wait for a vblank to pass for the
6948 			 * new ddb allocation to take effect.
6949 			 */
6950 			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
6951 						 &old_crtc_state->wm.skl.ddb) &&
6952 			    (update_pipes | modeset_pipes))
6953 				intel_crtc_wait_for_next_vblank(crtc);
6954 		}
6955 	}
6956 
6957 	intel_dbuf_mbus_post_ddb_update(state);
6958 
6959 	update_pipes = modeset_pipes;
6960 
6961 	/*
6962 	 * Enable all pipes that needs a modeset and do not depends on other
6963 	 * pipes
6964 	 */
6965 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6966 		enum pipe pipe = crtc->pipe;
6967 
6968 		if ((modeset_pipes & BIT(pipe)) == 0)
6969 			continue;
6970 
6971 		if (intel_crtc_is_joiner_secondary(new_crtc_state))
6972 			continue;
6973 
6974 		if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
6975 		    is_trans_port_sync_master(new_crtc_state))
6976 			continue;
6977 
6978 		modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
6979 
6980 		intel_enable_crtc(state, crtc);
6981 	}
6982 
6983 	/*
6984 	 * Then we enable all remaining pipes that depend on other
6985 	 * pipes: MST slaves and port sync masters
6986 	 */
6987 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6988 		enum pipe pipe = crtc->pipe;
6989 
6990 		if ((modeset_pipes & BIT(pipe)) == 0)
6991 			continue;
6992 
6993 		if (intel_crtc_is_joiner_secondary(new_crtc_state))
6994 			continue;
6995 
6996 		modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
6997 
6998 		intel_enable_crtc(state, crtc);
6999 	}
7000 
7001 	/*
7002 	 * Finally we do the plane updates/etc. for all pipes that got enabled.
7003 	 */
7004 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7005 		enum pipe pipe = crtc->pipe;
7006 
7007 		if ((update_pipes & BIT(pipe)) == 0)
7008 			continue;
7009 
7010 		intel_pre_update_crtc(state, crtc);
7011 	}
7012 
7013 	/*
7014 	 * Commit in reverse order to make joiner primary
7015 	 * send the uapi events after secondaries are done.
7016 	 */
7017 	for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) {
7018 		enum pipe pipe = crtc->pipe;
7019 
7020 		if ((update_pipes & BIT(pipe)) == 0)
7021 			continue;
7022 
7023 		drm_WARN_ON(display->drm,
7024 			    skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7025 							entries, I915_MAX_PIPES, pipe));
7026 
7027 		entries[pipe] = new_crtc_state->wm.skl.ddb;
7028 		update_pipes &= ~BIT(pipe);
7029 
7030 		intel_update_crtc(state, crtc);
7031 	}
7032 
7033 	drm_WARN_ON(display->drm, modeset_pipes);
7034 	drm_WARN_ON(display->drm, update_pipes);
7035 }
7036 
7037 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7038 {
7039 	struct drm_i915_private *i915 = to_i915(intel_state->base.dev);
7040 	struct drm_plane *plane;
7041 	struct drm_plane_state *new_plane_state;
7042 	int ret, i;
7043 
7044 	for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {
7045 		if (new_plane_state->fence) {
7046 			ret = dma_fence_wait_timeout(new_plane_state->fence, false,
7047 						     i915_fence_timeout(i915));
7048 			if (ret <= 0)
7049 				break;
7050 
7051 			dma_fence_put(new_plane_state->fence);
7052 			new_plane_state->fence = NULL;
7053 		}
7054 	}
7055 }
7056 
7057 static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state)
7058 {
7059 	if (crtc_state->dsb_commit)
7060 		intel_dsb_wait(crtc_state->dsb_commit);
7061 
7062 	intel_color_wait_commit(crtc_state);
7063 }
7064 
7065 static void intel_atomic_dsb_cleanup(struct intel_crtc_state *crtc_state)
7066 {
7067 	if (crtc_state->dsb_commit) {
7068 		intel_dsb_cleanup(crtc_state->dsb_commit);
7069 		crtc_state->dsb_commit = NULL;
7070 	}
7071 
7072 	intel_color_cleanup_commit(crtc_state);
7073 }
7074 
7075 static void intel_atomic_cleanup_work(struct work_struct *work)
7076 {
7077 	struct intel_atomic_state *state =
7078 		container_of(work, struct intel_atomic_state, cleanup_work);
7079 	struct intel_display *display = to_intel_display(state);
7080 	struct intel_crtc_state *old_crtc_state;
7081 	struct intel_crtc *crtc;
7082 	int i;
7083 
7084 	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
7085 		intel_atomic_dsb_cleanup(old_crtc_state);
7086 
7087 	drm_atomic_helper_cleanup_planes(display->drm, &state->base);
7088 	drm_atomic_helper_commit_cleanup_done(&state->base);
7089 	drm_atomic_state_put(&state->base);
7090 }
7091 
7092 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7093 {
7094 	struct intel_display *display = to_intel_display(state);
7095 	struct intel_plane *plane;
7096 	struct intel_plane_state *plane_state;
7097 	int i;
7098 
7099 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7100 		struct drm_framebuffer *fb = plane_state->hw.fb;
7101 		int cc_plane;
7102 		int ret;
7103 
7104 		if (!fb)
7105 			continue;
7106 
7107 		cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7108 		if (cc_plane < 0)
7109 			continue;
7110 
7111 		/*
7112 		 * The layout of the fast clear color value expected by HW
7113 		 * (the DRM ABI requiring this value to be located in fb at
7114 		 * offset 0 of cc plane, plane #2 previous generations or
7115 		 * plane #1 for flat ccs):
7116 		 * - 4 x 4 bytes per-channel value
7117 		 *   (in surface type specific float/int format provided by the fb user)
7118 		 * - 8 bytes native color value used by the display
7119 		 *   (converted/written by GPU during a fast clear operation using the
7120 		 *    above per-channel values)
7121 		 *
7122 		 * The commit's FB prepare hook already ensured that FB obj is pinned and the
7123 		 * caller made sure that the object is synced wrt. the related color clear value
7124 		 * GPU write on it.
7125 		 */
7126 		ret = intel_bo_read_from_page(intel_fb_bo(fb),
7127 					      fb->offsets[cc_plane] + 16,
7128 					      &plane_state->ccval,
7129 					      sizeof(plane_state->ccval));
7130 		/* The above could only fail if the FB obj has an unexpected backing store type. */
7131 		drm_WARN_ON(display->drm, ret);
7132 	}
7133 }
7134 
7135 static void intel_atomic_dsb_prepare(struct intel_atomic_state *state,
7136 				     struct intel_crtc *crtc)
7137 {
7138 	struct intel_display *display = to_intel_display(state);
7139 	struct intel_crtc_state *new_crtc_state =
7140 		intel_atomic_get_new_crtc_state(state, crtc);
7141 
7142 	if (!new_crtc_state->hw.active)
7143 		return;
7144 
7145 	if (state->base.legacy_cursor_update)
7146 		return;
7147 
7148 	/* FIXME deal with everything */
7149 	new_crtc_state->use_dsb =
7150 		!new_crtc_state->do_async_flip &&
7151 		(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
7152 		!intel_crtc_needs_modeset(new_crtc_state) &&
7153 		!intel_crtc_needs_fastset(new_crtc_state);
7154 
7155 	intel_color_prepare_commit(state, crtc);
7156 }
7157 
7158 static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
7159 				    struct intel_crtc *crtc)
7160 {
7161 	struct intel_display *display = to_intel_display(state);
7162 	struct intel_crtc_state *new_crtc_state =
7163 		intel_atomic_get_new_crtc_state(state, crtc);
7164 
7165 	if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank)
7166 		return;
7167 
7168 	/*
7169 	 * Rough estimate:
7170 	 * ~64 registers per each plane * 8 planes = 512
7171 	 * Double that for pipe stuff and other overhead.
7172 	 */
7173 	new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0,
7174 						       new_crtc_state->use_dsb ? 1024 : 16);
7175 	if (!new_crtc_state->dsb_commit) {
7176 		new_crtc_state->use_dsb = false;
7177 		intel_color_cleanup_commit(new_crtc_state);
7178 		return;
7179 	}
7180 
7181 	if (new_crtc_state->use_dsb) {
7182 		if (intel_crtc_needs_color_update(new_crtc_state))
7183 			intel_color_commit_noarm(new_crtc_state->dsb_commit,
7184 						 new_crtc_state);
7185 		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,
7186 					       state, crtc);
7187 
7188 		/*
7189 		 * Ensure we have "Frame Change" event when PSR state is
7190 		 * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank
7191 		 * evasion hangs as PIPEDSL is reading as 0.
7192 		 */
7193 		intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit,
7194 						     state, crtc);
7195 
7196 		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
7197 
7198 		if (intel_crtc_needs_color_update(new_crtc_state))
7199 			intel_color_commit_arm(new_crtc_state->dsb_commit,
7200 					       new_crtc_state);
7201 		bdw_set_pipe_misc(new_crtc_state->dsb_commit,
7202 				  new_crtc_state);
7203 		intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit,
7204 						     new_crtc_state);
7205 		intel_crtc_planes_update_arm(new_crtc_state->dsb_commit,
7206 					     state, crtc);
7207 
7208 		if (DISPLAY_VER(display) >= 9)
7209 			skl_detach_scalers(new_crtc_state->dsb_commit,
7210 					   new_crtc_state);
7211 
7212 		if (!new_crtc_state->dsb_color_vblank) {
7213 			intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
7214 
7215 			intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
7216 			intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
7217 			intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state);
7218 			intel_dsb_interrupt(new_crtc_state->dsb_commit);
7219 		}
7220 	}
7221 
7222 	if (new_crtc_state->dsb_color_vblank)
7223 		intel_dsb_chain(state, new_crtc_state->dsb_commit,
7224 				new_crtc_state->dsb_color_vblank, true);
7225 
7226 	intel_dsb_finish(new_crtc_state->dsb_commit);
7227 }
7228 
7229 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7230 {
7231 	struct intel_display *display = to_intel_display(state);
7232 	struct drm_i915_private *dev_priv = to_i915(display->drm);
7233 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7234 	struct intel_crtc *crtc;
7235 	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7236 	intel_wakeref_t wakeref = NULL;
7237 	int i;
7238 
7239 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7240 		intel_atomic_dsb_prepare(state, crtc);
7241 
7242 	intel_atomic_commit_fence_wait(state);
7243 
7244 	intel_td_flush(display);
7245 
7246 	intel_atomic_prepare_plane_clear_colors(state);
7247 
7248 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7249 		intel_fbc_prepare_dirty_rect(state, crtc);
7250 
7251 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7252 		intel_atomic_dsb_finish(state, crtc);
7253 
7254 	drm_atomic_helper_wait_for_dependencies(&state->base);
7255 	drm_dp_mst_atomic_wait_for_dependencies(&state->base);
7256 	intel_atomic_global_state_wait_for_dependencies(state);
7257 
7258 	/*
7259 	 * During full modesets we write a lot of registers, wait
7260 	 * for PLLs, etc. Doing that while DC states are enabled
7261 	 * is not a good idea.
7262 	 *
7263 	 * During fastsets and other updates we also need to
7264 	 * disable DC states due to the following scenario:
7265 	 * 1. DC5 exit and PSR exit happen
7266 	 * 2. Some or all _noarm() registers are written
7267 	 * 3. Due to some long delay PSR is re-entered
7268 	 * 4. DC5 entry -> DMC saves the already written new
7269 	 *    _noarm() registers and the old not yet written
7270 	 *    _arm() registers
7271 	 * 5. DC5 exit -> DMC restores a mixture of old and
7272 	 *    new register values and arms the update
7273 	 * 6. PSR exit -> hardware latches a mixture of old and
7274 	 *    new register values -> corrupted frame, or worse
7275 	 * 7. New _arm() registers are finally written
7276 	 * 8. Hardware finally latches a complete set of new
7277 	 *    register values, and subsequent frames will be OK again
7278 	 *
7279 	 * Also note that due to the pipe CSC hardware issues on
7280 	 * SKL/GLK DC states must remain off until the pipe CSC
7281 	 * state readout has happened. Otherwise we risk corrupting
7282 	 * the CSC latched register values with the readout (see
7283 	 * skl_read_csc() and skl_color_commit_noarm()).
7284 	 */
7285 	wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);
7286 
7287 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7288 					    new_crtc_state, i) {
7289 		if (intel_crtc_needs_modeset(new_crtc_state) ||
7290 		    intel_crtc_needs_fastset(new_crtc_state))
7291 			intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7292 	}
7293 
7294 	intel_commit_modeset_disables(state);
7295 
7296 	intel_dp_tunnel_atomic_alloc_bw(state);
7297 
7298 	/* FIXME: Eventually get rid of our crtc->config pointer */
7299 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7300 		crtc->config = new_crtc_state;
7301 
7302 	/*
7303 	 * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7304 	 * plls, cdclk frequency, QGV point selection parameter etc. Voltage
7305 	 * index, cdclk/ddiclk frequencies are supposed to be configured before
7306 	 * the cdclk config is set.
7307 	 */
7308 	intel_pmdemand_pre_plane_update(state);
7309 
7310 	if (state->modeset) {
7311 		drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base);
7312 
7313 		intel_set_cdclk_pre_plane_update(state);
7314 
7315 		intel_modeset_verify_disabled(state);
7316 	}
7317 
7318 	intel_sagv_pre_plane_update(state);
7319 
7320 	/* Complete the events for pipes that have now been disabled */
7321 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7322 		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7323 
7324 		/* Complete events for now disable pipes here. */
7325 		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7326 			spin_lock_irq(&display->drm->event_lock);
7327 			drm_crtc_send_vblank_event(&crtc->base,
7328 						   new_crtc_state->uapi.event);
7329 			spin_unlock_irq(&display->drm->event_lock);
7330 
7331 			new_crtc_state->uapi.event = NULL;
7332 		}
7333 	}
7334 
7335 	intel_encoders_update_prepare(state);
7336 
7337 	intel_dbuf_pre_plane_update(state);
7338 
7339 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7340 		if (new_crtc_state->do_async_flip)
7341 			intel_crtc_enable_flip_done(state, crtc);
7342 	}
7343 
7344 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
7345 	display->funcs.display->commit_modeset_enables(state);
7346 
7347 	intel_program_dpkgc_latency(state);
7348 
7349 	intel_wait_for_vblank_workers(state);
7350 
7351 	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7352 	 * already, but still need the state for the delayed optimization. To
7353 	 * fix this:
7354 	 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7355 	 * - schedule that vblank worker _before_ calling hw_done
7356 	 * - at the start of commit_tail, cancel it _synchrously
7357 	 * - switch over to the vblank wait helper in the core after that since
7358 	 *   we don't need out special handling any more.
7359 	 */
7360 	drm_atomic_helper_wait_for_flip_done(display->drm, &state->base);
7361 
7362 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7363 		if (new_crtc_state->do_async_flip)
7364 			intel_crtc_disable_flip_done(state, crtc);
7365 
7366 		intel_atomic_dsb_wait_commit(new_crtc_state);
7367 
7368 		if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb)
7369 			intel_vrr_check_push_sent(NULL, new_crtc_state);
7370 	}
7371 
7372 	/*
7373 	 * Now that the vblank has passed, we can go ahead and program the
7374 	 * optimal watermarks on platforms that need two-step watermark
7375 	 * programming.
7376 	 *
7377 	 * TODO: Move this (and other cleanup) to an async worker eventually.
7378 	 */
7379 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7380 					    new_crtc_state, i) {
7381 		/*
7382 		 * Gen2 reports pipe underruns whenever all planes are disabled.
7383 		 * So re-enable underrun reporting after some planes get enabled.
7384 		 *
7385 		 * We do this before .optimize_watermarks() so that we have a
7386 		 * chance of catching underruns with the intermediate watermarks
7387 		 * vs. the new plane configuration.
7388 		 */
7389 		if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7390 			intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);
7391 
7392 		intel_optimize_watermarks(state, crtc);
7393 	}
7394 
7395 	intel_dbuf_post_plane_update(state);
7396 
7397 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7398 		intel_post_plane_update(state, crtc);
7399 
7400 		intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7401 
7402 		intel_modeset_verify_crtc(state, crtc);
7403 
7404 		intel_post_plane_update_after_readout(state, crtc);
7405 
7406 		/*
7407 		 * DSB cleanup is done in cleanup_work aligning with framebuffer
7408 		 * cleanup. So copy and reset the dsb structure to sync with
7409 		 * commit_done and later do dsb cleanup in cleanup_work.
7410 		 *
7411 		 * FIXME get rid of this funny new->old swapping
7412 		 */
7413 		old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank);
7414 		old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit);
7415 	}
7416 
7417 	/* Underruns don't always raise interrupts, so check manually */
7418 	intel_check_cpu_fifo_underruns(display);
7419 	intel_check_pch_fifo_underruns(display);
7420 
7421 	if (state->modeset)
7422 		intel_verify_planes(state);
7423 
7424 	intel_sagv_post_plane_update(state);
7425 	if (state->modeset)
7426 		intel_set_cdclk_post_plane_update(state);
7427 	intel_pmdemand_post_plane_update(state);
7428 
7429 	drm_atomic_helper_commit_hw_done(&state->base);
7430 	intel_atomic_global_state_commit_done(state);
7431 
7432 	if (state->modeset) {
7433 		/* As one of the primary mmio accessors, KMS has a high
7434 		 * likelihood of triggering bugs in unclaimed access. After we
7435 		 * finish modesetting, see if an error has been flagged, and if
7436 		 * so enable debugging for the next modeset - and hope we catch
7437 		 * the culprit.
7438 		 */
7439 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7440 	}
7441 	/*
7442 	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
7443 	 * toggling overhead at and above 60 FPS.
7444 	 */
7445 	intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17);
7446 	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7447 
7448 	/*
7449 	 * Defer the cleanup of the old state to a separate worker to not
7450 	 * impede the current task (userspace for blocking modesets) that
7451 	 * are executed inline. For out-of-line asynchronous modesets/flips,
7452 	 * deferring to a new worker seems overkill, but we would place a
7453 	 * schedule point (cond_resched()) here anyway to keep latencies
7454 	 * down.
7455 	 */
7456 	INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work);
7457 	queue_work(display->wq.cleanup, &state->cleanup_work);
7458 }
7459 
7460 static void intel_atomic_commit_work(struct work_struct *work)
7461 {
7462 	struct intel_atomic_state *state =
7463 		container_of(work, struct intel_atomic_state, base.commit_work);
7464 
7465 	intel_atomic_commit_tail(state);
7466 }
7467 
7468 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7469 {
7470 	struct intel_plane_state *old_plane_state, *new_plane_state;
7471 	struct intel_plane *plane;
7472 	int i;
7473 
7474 	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7475 					     new_plane_state, i)
7476 		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7477 					to_intel_frontbuffer(new_plane_state->hw.fb),
7478 					plane->frontbuffer_bit);
7479 }
7480 
7481 static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock)
7482 {
7483 	int ret;
7484 
7485 	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7486 	if (ret)
7487 		return ret;
7488 
7489 	ret = intel_atomic_global_state_setup_commit(state);
7490 	if (ret)
7491 		return ret;
7492 
7493 	return 0;
7494 }
7495 
7496 static int intel_atomic_swap_state(struct intel_atomic_state *state)
7497 {
7498 	int ret;
7499 
7500 	ret = drm_atomic_helper_swap_state(&state->base, true);
7501 	if (ret)
7502 		return ret;
7503 
7504 	intel_atomic_swap_global_state(state);
7505 
7506 	intel_shared_dpll_swap_state(state);
7507 
7508 	intel_atomic_track_fbs(state);
7509 
7510 	return 0;
7511 }
7512 
7513 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
7514 			bool nonblock)
7515 {
7516 	struct intel_display *display = to_intel_display(dev);
7517 	struct intel_atomic_state *state = to_intel_atomic_state(_state);
7518 	struct drm_i915_private *dev_priv = to_i915(dev);
7519 	int ret = 0;
7520 
7521 	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7522 
7523 	/*
7524 	 * The intel_legacy_cursor_update() fast path takes care
7525 	 * of avoiding the vblank waits for simple cursor
7526 	 * movement and flips. For cursor on/off and size changes,
7527 	 * we want to perform the vblank waits so that watermark
7528 	 * updates happen during the correct frames. Gen9+ have
7529 	 * double buffered watermarks and so shouldn't need this.
7530 	 *
7531 	 * Unset state->legacy_cursor_update before the call to
7532 	 * drm_atomic_helper_setup_commit() because otherwise
7533 	 * drm_atomic_helper_wait_for_flip_done() is a noop and
7534 	 * we get FIFO underruns because we didn't wait
7535 	 * for vblank.
7536 	 *
7537 	 * FIXME doing watermarks and fb cleanup from a vblank worker
7538 	 * (assuming we had any) would solve these problems.
7539 	 */
7540 	if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) {
7541 		struct intel_crtc_state *new_crtc_state;
7542 		struct intel_crtc *crtc;
7543 		int i;
7544 
7545 		for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7546 			if (new_crtc_state->wm.need_postvbl_update ||
7547 			    new_crtc_state->update_wm_post)
7548 				state->base.legacy_cursor_update = false;
7549 	}
7550 
7551 	ret = intel_atomic_prepare_commit(state);
7552 	if (ret) {
7553 		drm_dbg_atomic(display->drm,
7554 			       "Preparing state failed with %i\n", ret);
7555 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7556 		return ret;
7557 	}
7558 
7559 	ret = intel_atomic_setup_commit(state, nonblock);
7560 	if (!ret)
7561 		ret = intel_atomic_swap_state(state);
7562 
7563 	if (ret) {
7564 		drm_atomic_helper_unprepare_planes(dev, &state->base);
7565 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7566 		return ret;
7567 	}
7568 
7569 	drm_atomic_state_get(&state->base);
7570 	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7571 
7572 	if (nonblock && state->modeset) {
7573 		queue_work(display->wq.modeset, &state->base.commit_work);
7574 	} else if (nonblock) {
7575 		queue_work(display->wq.flip, &state->base.commit_work);
7576 	} else {
7577 		if (state->modeset)
7578 			flush_workqueue(display->wq.modeset);
7579 		intel_atomic_commit_tail(state);
7580 	}
7581 
7582 	return 0;
7583 }
7584 
7585 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7586 {
7587 	struct intel_display *display = to_intel_display(encoder);
7588 	struct intel_encoder *source_encoder;
7589 	u32 possible_clones = 0;
7590 
7591 	for_each_intel_encoder(display->drm, source_encoder) {
7592 		if (encoders_cloneable(encoder, source_encoder))
7593 			possible_clones |= drm_encoder_mask(&source_encoder->base);
7594 	}
7595 
7596 	return possible_clones;
7597 }
7598 
7599 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7600 {
7601 	struct intel_display *display = to_intel_display(encoder);
7602 	struct intel_crtc *crtc;
7603 	u32 possible_crtcs = 0;
7604 
7605 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask)
7606 		possible_crtcs |= drm_crtc_mask(&crtc->base);
7607 
7608 	return possible_crtcs;
7609 }
7610 
7611 static bool ilk_has_edp_a(struct intel_display *display)
7612 {
7613 	if (!display->platform.mobile)
7614 		return false;
7615 
7616 	if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0)
7617 		return false;
7618 
7619 	if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7620 		return false;
7621 
7622 	return true;
7623 }
7624 
7625 static bool intel_ddi_crt_present(struct intel_display *display)
7626 {
7627 	struct drm_i915_private *dev_priv = to_i915(display->drm);
7628 
7629 	if (DISPLAY_VER(display) >= 9)
7630 		return false;
7631 
7632 	if (display->platform.haswell_ult || display->platform.broadwell_ult)
7633 		return false;
7634 
7635 	if (HAS_PCH_LPT_H(dev_priv) &&
7636 	    intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7637 		return false;
7638 
7639 	/* DDI E can't be used if DDI A requires 4 lanes */
7640 	if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7641 		return false;
7642 
7643 	if (!display->vbt.int_crt_support)
7644 		return false;
7645 
7646 	return true;
7647 }
7648 
7649 bool assert_port_valid(struct intel_display *display, enum port port)
7650 {
7651 	return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),
7652 			 "Platform does not support port %c\n", port_name(port));
7653 }
7654 
7655 void intel_setup_outputs(struct intel_display *display)
7656 {
7657 	struct drm_i915_private *dev_priv = to_i915(display->drm);
7658 	struct intel_encoder *encoder;
7659 	bool dpd_is_edp = false;
7660 
7661 	intel_pps_unlock_regs_wa(display);
7662 
7663 	if (!HAS_DISPLAY(display))
7664 		return;
7665 
7666 	if (HAS_DDI(display)) {
7667 		if (intel_ddi_crt_present(display))
7668 			intel_crt_init(display);
7669 
7670 		intel_bios_for_each_encoder(display, intel_ddi_init);
7671 
7672 		if (display->platform.geminilake || display->platform.broxton)
7673 			vlv_dsi_init(dev_priv);
7674 	} else if (HAS_PCH_SPLIT(dev_priv)) {
7675 		int found;
7676 
7677 		/*
7678 		 * intel_edp_init_connector() depends on this completing first,
7679 		 * to prevent the registration of both eDP and LVDS and the
7680 		 * incorrect sharing of the PPS.
7681 		 */
7682 		intel_lvds_init(dev_priv);
7683 		intel_crt_init(display);
7684 
7685 		dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);
7686 
7687 		if (ilk_has_edp_a(display))
7688 			g4x_dp_init(display, DP_A, PORT_A);
7689 
7690 		if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) {
7691 			/* PCH SDVOB multiplex with HDMIB */
7692 			found = intel_sdvo_init(display, PCH_SDVOB, PORT_B);
7693 			if (!found)
7694 				g4x_hdmi_init(display, PCH_HDMIB, PORT_B);
7695 			if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED))
7696 				g4x_dp_init(display, PCH_DP_B, PORT_B);
7697 		}
7698 
7699 		if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED)
7700 			g4x_hdmi_init(display, PCH_HDMIC, PORT_C);
7701 
7702 		if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED)
7703 			g4x_hdmi_init(display, PCH_HDMID, PORT_D);
7704 
7705 		if (intel_de_read(display, PCH_DP_C) & DP_DETECTED)
7706 			g4x_dp_init(display, PCH_DP_C, PORT_C);
7707 
7708 		if (intel_de_read(display, PCH_DP_D) & DP_DETECTED)
7709 			g4x_dp_init(display, PCH_DP_D, PORT_D);
7710 	} else if (display->platform.valleyview || display->platform.cherryview) {
7711 		bool has_edp, has_port;
7712 
7713 		if (display->platform.valleyview && display->vbt.int_crt_support)
7714 			intel_crt_init(display);
7715 
7716 		/*
7717 		 * The DP_DETECTED bit is the latched state of the DDC
7718 		 * SDA pin at boot. However since eDP doesn't require DDC
7719 		 * (no way to plug in a DP->HDMI dongle) the DDC pins for
7720 		 * eDP ports may have been muxed to an alternate function.
7721 		 * Thus we can't rely on the DP_DETECTED bit alone to detect
7722 		 * eDP ports. Consult the VBT as well as DP_DETECTED to
7723 		 * detect eDP ports.
7724 		 *
7725 		 * Sadly the straps seem to be missing sometimes even for HDMI
7726 		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7727 		 * and VBT for the presence of the port. Additionally we can't
7728 		 * trust the port type the VBT declares as we've seen at least
7729 		 * HDMI ports that the VBT claim are DP or eDP.
7730 		 */
7731 		has_edp = intel_dp_is_port_edp(display, PORT_B);
7732 		has_port = intel_bios_is_port_present(display, PORT_B);
7733 		if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port)
7734 			has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B);
7735 		if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7736 			g4x_hdmi_init(display, VLV_HDMIB, PORT_B);
7737 
7738 		has_edp = intel_dp_is_port_edp(display, PORT_C);
7739 		has_port = intel_bios_is_port_present(display, PORT_C);
7740 		if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port)
7741 			has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C);
7742 		if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7743 			g4x_hdmi_init(display, VLV_HDMIC, PORT_C);
7744 
7745 		if (display->platform.cherryview) {
7746 			/*
7747 			 * eDP not supported on port D,
7748 			 * so no need to worry about it
7749 			 */
7750 			has_port = intel_bios_is_port_present(display, PORT_D);
7751 			if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port)
7752 				g4x_dp_init(display, CHV_DP_D, PORT_D);
7753 			if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port)
7754 				g4x_hdmi_init(display, CHV_HDMID, PORT_D);
7755 		}
7756 
7757 		vlv_dsi_init(dev_priv);
7758 	} else if (display->platform.pineview) {
7759 		intel_lvds_init(dev_priv);
7760 		intel_crt_init(display);
7761 	} else if (IS_DISPLAY_VER(display, 3, 4)) {
7762 		bool found = false;
7763 
7764 		if (display->platform.mobile)
7765 			intel_lvds_init(dev_priv);
7766 
7767 		intel_crt_init(display);
7768 
7769 		if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
7770 			drm_dbg_kms(display->drm, "probing SDVOB\n");
7771 			found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B);
7772 			if (!found && display->platform.g4x) {
7773 				drm_dbg_kms(display->drm,
7774 					    "probing HDMI on SDVOB\n");
7775 				g4x_hdmi_init(display, GEN4_HDMIB, PORT_B);
7776 			}
7777 
7778 			if (!found && display->platform.g4x)
7779 				g4x_dp_init(display, DP_B, PORT_B);
7780 		}
7781 
7782 		/* Before G4X SDVOC doesn't have its own detect register */
7783 
7784 		if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
7785 			drm_dbg_kms(display->drm, "probing SDVOC\n");
7786 			found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C);
7787 		}
7788 
7789 		if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) {
7790 
7791 			if (display->platform.g4x) {
7792 				drm_dbg_kms(display->drm,
7793 					    "probing HDMI on SDVOC\n");
7794 				g4x_hdmi_init(display, GEN4_HDMIC, PORT_C);
7795 			}
7796 			if (display->platform.g4x)
7797 				g4x_dp_init(display, DP_C, PORT_C);
7798 		}
7799 
7800 		if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))
7801 			g4x_dp_init(display, DP_D, PORT_D);
7802 
7803 		if (SUPPORTS_TV(display))
7804 			intel_tv_init(display);
7805 	} else if (DISPLAY_VER(display) == 2) {
7806 		if (display->platform.i85x)
7807 			intel_lvds_init(dev_priv);
7808 
7809 		intel_crt_init(display);
7810 		intel_dvo_init(dev_priv);
7811 	}
7812 
7813 	for_each_intel_encoder(display->drm, encoder) {
7814 		encoder->base.possible_crtcs =
7815 			intel_encoder_possible_crtcs(encoder);
7816 		encoder->base.possible_clones =
7817 			intel_encoder_possible_clones(encoder);
7818 	}
7819 
7820 	intel_init_pch_refclk(dev_priv);
7821 
7822 	drm_helper_move_panel_connectors_to_head(display->drm);
7823 }
7824 
7825 static int max_dotclock(struct intel_display *display)
7826 {
7827 	int max_dotclock = display->cdclk.max_dotclk_freq;
7828 
7829 	if (HAS_ULTRAJOINER(display))
7830 		max_dotclock *= 4;
7831 	else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display))
7832 		max_dotclock *= 2;
7833 
7834 	return max_dotclock;
7835 }
7836 
7837 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
7838 				      const struct drm_display_mode *mode)
7839 {
7840 	struct intel_display *display = to_intel_display(dev);
7841 	int hdisplay_max, htotal_max;
7842 	int vdisplay_max, vtotal_max;
7843 
7844 	/*
7845 	 * Can't reject DBLSCAN here because Xorg ddxen can add piles
7846 	 * of DBLSCAN modes to the output's mode list when they detect
7847 	 * the scaling mode property on the connector. And they don't
7848 	 * ask the kernel to validate those modes in any way until
7849 	 * modeset time at which point the client gets a protocol error.
7850 	 * So in order to not upset those clients we silently ignore the
7851 	 * DBLSCAN flag on such connectors. For other connectors we will
7852 	 * reject modes with the DBLSCAN flag in encoder->compute_config().
7853 	 * And we always reject DBLSCAN modes in connector->mode_valid()
7854 	 * as we never want such modes on the connector's mode list.
7855 	 */
7856 
7857 	if (mode->vscan > 1)
7858 		return MODE_NO_VSCAN;
7859 
7860 	if (mode->flags & DRM_MODE_FLAG_HSKEW)
7861 		return MODE_H_ILLEGAL;
7862 
7863 	if (mode->flags & (DRM_MODE_FLAG_CSYNC |
7864 			   DRM_MODE_FLAG_NCSYNC |
7865 			   DRM_MODE_FLAG_PCSYNC))
7866 		return MODE_HSYNC;
7867 
7868 	if (mode->flags & (DRM_MODE_FLAG_BCAST |
7869 			   DRM_MODE_FLAG_PIXMUX |
7870 			   DRM_MODE_FLAG_CLKDIV2))
7871 		return MODE_BAD;
7872 
7873 	/*
7874 	 * Reject clearly excessive dotclocks early to
7875 	 * avoid having to worry about huge integers later.
7876 	 */
7877 	if (mode->clock > max_dotclock(display))
7878 		return MODE_CLOCK_HIGH;
7879 
7880 	/* Transcoder timing limits */
7881 	if (DISPLAY_VER(display) >= 11) {
7882 		hdisplay_max = 16384;
7883 		vdisplay_max = 8192;
7884 		htotal_max = 16384;
7885 		vtotal_max = 8192;
7886 	} else if (DISPLAY_VER(display) >= 9 ||
7887 		   display->platform.broadwell || display->platform.haswell) {
7888 		hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
7889 		vdisplay_max = 4096;
7890 		htotal_max = 8192;
7891 		vtotal_max = 8192;
7892 	} else if (DISPLAY_VER(display) >= 3) {
7893 		hdisplay_max = 4096;
7894 		vdisplay_max = 4096;
7895 		htotal_max = 8192;
7896 		vtotal_max = 8192;
7897 	} else {
7898 		hdisplay_max = 2048;
7899 		vdisplay_max = 2048;
7900 		htotal_max = 4096;
7901 		vtotal_max = 4096;
7902 	}
7903 
7904 	if (mode->hdisplay > hdisplay_max ||
7905 	    mode->hsync_start > htotal_max ||
7906 	    mode->hsync_end > htotal_max ||
7907 	    mode->htotal > htotal_max)
7908 		return MODE_H_ILLEGAL;
7909 
7910 	if (mode->vdisplay > vdisplay_max ||
7911 	    mode->vsync_start > vtotal_max ||
7912 	    mode->vsync_end > vtotal_max ||
7913 	    mode->vtotal > vtotal_max)
7914 		return MODE_V_ILLEGAL;
7915 
7916 	return MODE_OK;
7917 }
7918 
7919 enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display,
7920 						     const struct drm_display_mode *mode)
7921 {
7922 	/*
7923 	 * Additional transcoder timing limits,
7924 	 * excluding BXT/GLK DSI transcoders.
7925 	 */
7926 	if (DISPLAY_VER(display) >= 5) {
7927 		if (mode->hdisplay < 64 ||
7928 		    mode->htotal - mode->hdisplay < 32)
7929 			return MODE_H_ILLEGAL;
7930 
7931 		if (mode->vtotal - mode->vdisplay < 5)
7932 			return MODE_V_ILLEGAL;
7933 	} else {
7934 		if (mode->htotal - mode->hdisplay < 32)
7935 			return MODE_H_ILLEGAL;
7936 
7937 		if (mode->vtotal - mode->vdisplay < 3)
7938 			return MODE_V_ILLEGAL;
7939 	}
7940 
7941 	/*
7942 	 * Cantiga+ cannot handle modes with a hsync front porch of 0.
7943 	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7944 	 */
7945 	if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) &&
7946 	    mode->hsync_start == mode->hdisplay)
7947 		return MODE_H_ILLEGAL;
7948 
7949 	return MODE_OK;
7950 }
7951 
7952 enum drm_mode_status
7953 intel_mode_valid_max_plane_size(struct intel_display *display,
7954 				const struct drm_display_mode *mode,
7955 				int num_joined_pipes)
7956 {
7957 	int plane_width_max, plane_height_max;
7958 
7959 	/*
7960 	 * intel_mode_valid() should be
7961 	 * sufficient on older platforms.
7962 	 */
7963 	if (DISPLAY_VER(display) < 9)
7964 		return MODE_OK;
7965 
7966 	/*
7967 	 * Most people will probably want a fullscreen
7968 	 * plane so let's not advertize modes that are
7969 	 * too big for that.
7970 	 */
7971 	if (DISPLAY_VER(display) >= 30) {
7972 		plane_width_max = 6144 * num_joined_pipes;
7973 		plane_height_max = 4800;
7974 	} else if (DISPLAY_VER(display) >= 11) {
7975 		plane_width_max = 5120 * num_joined_pipes;
7976 		plane_height_max = 4320;
7977 	} else {
7978 		plane_width_max = 5120;
7979 		plane_height_max = 4096;
7980 	}
7981 
7982 	if (mode->hdisplay > plane_width_max)
7983 		return MODE_H_ILLEGAL;
7984 
7985 	if (mode->vdisplay > plane_height_max)
7986 		return MODE_V_ILLEGAL;
7987 
7988 	return MODE_OK;
7989 }
7990 
7991 static const struct intel_display_funcs skl_display_funcs = {
7992 	.get_pipe_config = hsw_get_pipe_config,
7993 	.crtc_enable = hsw_crtc_enable,
7994 	.crtc_disable = hsw_crtc_disable,
7995 	.commit_modeset_enables = skl_commit_modeset_enables,
7996 	.get_initial_plane_config = skl_get_initial_plane_config,
7997 	.fixup_initial_plane_config = skl_fixup_initial_plane_config,
7998 };
7999 
8000 static const struct intel_display_funcs ddi_display_funcs = {
8001 	.get_pipe_config = hsw_get_pipe_config,
8002 	.crtc_enable = hsw_crtc_enable,
8003 	.crtc_disable = hsw_crtc_disable,
8004 	.commit_modeset_enables = intel_commit_modeset_enables,
8005 	.get_initial_plane_config = i9xx_get_initial_plane_config,
8006 	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8007 };
8008 
8009 static const struct intel_display_funcs pch_split_display_funcs = {
8010 	.get_pipe_config = ilk_get_pipe_config,
8011 	.crtc_enable = ilk_crtc_enable,
8012 	.crtc_disable = ilk_crtc_disable,
8013 	.commit_modeset_enables = intel_commit_modeset_enables,
8014 	.get_initial_plane_config = i9xx_get_initial_plane_config,
8015 	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8016 };
8017 
8018 static const struct intel_display_funcs vlv_display_funcs = {
8019 	.get_pipe_config = i9xx_get_pipe_config,
8020 	.crtc_enable = valleyview_crtc_enable,
8021 	.crtc_disable = i9xx_crtc_disable,
8022 	.commit_modeset_enables = intel_commit_modeset_enables,
8023 	.get_initial_plane_config = i9xx_get_initial_plane_config,
8024 	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8025 };
8026 
8027 static const struct intel_display_funcs i9xx_display_funcs = {
8028 	.get_pipe_config = i9xx_get_pipe_config,
8029 	.crtc_enable = i9xx_crtc_enable,
8030 	.crtc_disable = i9xx_crtc_disable,
8031 	.commit_modeset_enables = intel_commit_modeset_enables,
8032 	.get_initial_plane_config = i9xx_get_initial_plane_config,
8033 	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8034 };
8035 
8036 /**
8037  * intel_init_display_hooks - initialize the display modesetting hooks
8038  * @display: display device private
8039  */
8040 void intel_init_display_hooks(struct intel_display *display)
8041 {
8042 	struct drm_i915_private *dev_priv = to_i915(display->drm);
8043 
8044 	if (DISPLAY_VER(display) >= 9) {
8045 		display->funcs.display = &skl_display_funcs;
8046 	} else if (HAS_DDI(display)) {
8047 		display->funcs.display = &ddi_display_funcs;
8048 	} else if (HAS_PCH_SPLIT(dev_priv)) {
8049 		display->funcs.display = &pch_split_display_funcs;
8050 	} else if (display->platform.cherryview ||
8051 		   display->platform.valleyview) {
8052 		display->funcs.display = &vlv_display_funcs;
8053 	} else {
8054 		display->funcs.display = &i9xx_display_funcs;
8055 	}
8056 }
8057 
8058 int intel_initial_commit(struct intel_display *display)
8059 {
8060 	struct drm_atomic_state *state = NULL;
8061 	struct drm_modeset_acquire_ctx ctx;
8062 	struct intel_crtc *crtc;
8063 	int ret = 0;
8064 
8065 	state = drm_atomic_state_alloc(display->drm);
8066 	if (!state)
8067 		return -ENOMEM;
8068 
8069 	drm_modeset_acquire_init(&ctx, 0);
8070 
8071 	state->acquire_ctx = &ctx;
8072 	to_intel_atomic_state(state)->internal = true;
8073 
8074 retry:
8075 	for_each_intel_crtc(display->drm, crtc) {
8076 		struct intel_crtc_state *crtc_state =
8077 			intel_atomic_get_crtc_state(state, crtc);
8078 
8079 		if (IS_ERR(crtc_state)) {
8080 			ret = PTR_ERR(crtc_state);
8081 			goto out;
8082 		}
8083 
8084 		if (crtc_state->hw.active) {
8085 			struct intel_encoder *encoder;
8086 
8087 			ret = drm_atomic_add_affected_planes(state, &crtc->base);
8088 			if (ret)
8089 				goto out;
8090 
8091 			/*
8092 			 * FIXME hack to force a LUT update to avoid the
8093 			 * plane update forcing the pipe gamma on without
8094 			 * having a proper LUT loaded. Remove once we
8095 			 * have readout for pipe gamma enable.
8096 			 */
8097 			crtc_state->uapi.color_mgmt_changed = true;
8098 
8099 			for_each_intel_encoder_mask(display->drm, encoder,
8100 						    crtc_state->uapi.encoder_mask) {
8101 				if (encoder->initial_fastset_check &&
8102 				    !encoder->initial_fastset_check(encoder, crtc_state)) {
8103 					ret = drm_atomic_add_affected_connectors(state,
8104 										 &crtc->base);
8105 					if (ret)
8106 						goto out;
8107 				}
8108 			}
8109 		}
8110 	}
8111 
8112 	ret = drm_atomic_commit(state);
8113 
8114 out:
8115 	if (ret == -EDEADLK) {
8116 		drm_atomic_state_clear(state);
8117 		drm_modeset_backoff(&ctx);
8118 		goto retry;
8119 	}
8120 
8121 	drm_atomic_state_put(state);
8122 
8123 	drm_modeset_drop_locks(&ctx);
8124 	drm_modeset_acquire_fini(&ctx);
8125 
8126 	return ret;
8127 }
8128 
8129 void i830_enable_pipe(struct intel_display *display, enum pipe pipe)
8130 {
8131 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
8132 	enum transcoder cpu_transcoder = (enum transcoder)pipe;
8133 	/* 640x480@60Hz, ~25175 kHz */
8134 	struct dpll clock = {
8135 		.m1 = 18,
8136 		.m2 = 7,
8137 		.p1 = 13,
8138 		.p2 = 4,
8139 		.n = 2,
8140 	};
8141 	u32 dpll, fp;
8142 	int i;
8143 
8144 	drm_WARN_ON(display->drm,
8145 		    i9xx_calc_dpll_params(48000, &clock) != 25154);
8146 
8147 	drm_dbg_kms(display->drm,
8148 		    "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8149 		    pipe_name(pipe), clock.vco, clock.dot);
8150 
8151 	fp = i9xx_dpll_compute_fp(&clock);
8152 	dpll = DPLL_DVO_2X_MODE |
8153 		DPLL_VGA_MODE_DIS |
8154 		((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8155 		PLL_P2_DIVIDE_BY_4 |
8156 		PLL_REF_INPUT_DREFCLK |
8157 		DPLL_VCO_ENABLE;
8158 
8159 	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
8160 		       HACTIVE(640 - 1) | HTOTAL(800 - 1));
8161 	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
8162 		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8163 	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
8164 		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8165 	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
8166 		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
8167 	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
8168 		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8169 	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
8170 		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8171 	intel_de_write(display, PIPESRC(display, pipe),
8172 		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8173 
8174 	intel_de_write(display, FP0(pipe), fp);
8175 	intel_de_write(display, FP1(pipe), fp);
8176 
8177 	/*
8178 	 * Apparently we need to have VGA mode enabled prior to changing
8179 	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8180 	 * dividers, even though the register value does change.
8181 	 */
8182 	intel_de_write(display, DPLL(display, pipe),
8183 		       dpll & ~DPLL_VGA_MODE_DIS);
8184 	intel_de_write(display, DPLL(display, pipe), dpll);
8185 
8186 	/* Wait for the clocks to stabilize. */
8187 	intel_de_posting_read(display, DPLL(display, pipe));
8188 	udelay(150);
8189 
8190 	/* The pixel multiplier can only be updated once the
8191 	 * DPLL is enabled and the clocks are stable.
8192 	 *
8193 	 * So write it again.
8194 	 */
8195 	intel_de_write(display, DPLL(display, pipe), dpll);
8196 
8197 	/* We do this three times for luck */
8198 	for (i = 0; i < 3 ; i++) {
8199 		intel_de_write(display, DPLL(display, pipe), dpll);
8200 		intel_de_posting_read(display, DPLL(display, pipe));
8201 		udelay(150); /* wait for warmup */
8202 	}
8203 
8204 	intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);
8205 	intel_de_posting_read(display, TRANSCONF(display, pipe));
8206 
8207 	intel_wait_for_pipe_scanline_moving(crtc);
8208 }
8209 
8210 void i830_disable_pipe(struct intel_display *display, enum pipe pipe)
8211 {
8212 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
8213 
8214 	drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",
8215 		    pipe_name(pipe));
8216 
8217 	drm_WARN_ON(display->drm,
8218 		    intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);
8219 	drm_WARN_ON(display->drm,
8220 		    intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);
8221 	drm_WARN_ON(display->drm,
8222 		    intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);
8223 	drm_WARN_ON(display->drm,
8224 		    intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);
8225 	drm_WARN_ON(display->drm,
8226 		    intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);
8227 
8228 	intel_de_write(display, TRANSCONF(display, pipe), 0);
8229 	intel_de_posting_read(display, TRANSCONF(display, pipe));
8230 
8231 	intel_wait_for_pipe_scanline_stopped(crtc);
8232 
8233 	intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);
8234 	intel_de_posting_read(display, DPLL(display, pipe));
8235 }
8236 
8237 bool intel_scanout_needs_vtd_wa(struct intel_display *display)
8238 {
8239 	struct drm_i915_private *i915 = to_i915(display->drm);
8240 
8241 	return IS_DISPLAY_VER(display, 6, 11) && i915_vtd_active(i915);
8242 }
8243