1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/display/drm_dp_tunnel.h> 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_atomic_uapi.h> 40 #include <drm/drm_damage_helper.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_fixed.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_print.h> 45 #include <drm/drm_probe_helper.h> 46 #include <drm/drm_rect.h> 47 #include <drm/drm_vblank.h> 48 49 #include "g4x_dp.h" 50 #include "g4x_hdmi.h" 51 #include "hsw_ips.h" 52 #include "i915_config.h" 53 #include "i915_reg.h" 54 #include "i9xx_plane.h" 55 #include "i9xx_plane_regs.h" 56 #include "i9xx_wm.h" 57 #include "intel_alpm.h" 58 #include "intel_atomic.h" 59 #include "intel_audio.h" 60 #include "intel_bo.h" 61 #include "intel_bw.h" 62 #include "intel_casf.h" 63 #include "intel_cdclk.h" 64 #include "intel_clock_gating.h" 65 #include "intel_color.h" 66 #include "intel_crt.h" 67 #include "intel_crtc.h" 68 #include "intel_crtc_state_dump.h" 69 #include "intel_cursor.h" 70 #include "intel_cursor_regs.h" 71 #include "intel_cx0_phy.h" 72 #include "intel_ddi.h" 73 #include "intel_de.h" 74 #include "intel_display_driver.h" 75 #include "intel_display_power.h" 76 #include "intel_display_regs.h" 77 #include "intel_display_rpm.h" 78 #include "intel_display_types.h" 79 #include "intel_display_utils.h" 80 #include "intel_display_wa.h" 81 #include "intel_dmc.h" 82 #include "intel_dp.h" 83 #include "intel_dp_link_training.h" 84 #include "intel_dp_mst.h" 85 #include "intel_dp_tunnel.h" 86 #include "intel_dpll.h" 87 #include "intel_dpll_mgr.h" 88 #include "intel_dpt.h" 89 #include "intel_dpt_common.h" 90 #include "intel_drrs.h" 91 #include "intel_dsb.h" 92 #include "intel_dsi.h" 93 #include "intel_dvo.h" 94 #include "intel_fb.h" 95 #include "intel_fbc.h" 96 #include "intel_fdi.h" 97 #include "intel_fifo_underrun.h" 98 #include "intel_flipq.h" 99 #include "intel_frontbuffer.h" 100 #include "intel_hdmi.h" 101 #include "intel_hotplug.h" 102 #include "intel_initial_plane.h" 103 #include "intel_link_bw.h" 104 #include "intel_lt_phy.h" 105 #include "intel_lvds.h" 106 #include "intel_lvds_regs.h" 107 #include "intel_modeset_setup.h" 108 #include "intel_modeset_verify.h" 109 #include "intel_overlay.h" 110 #include "intel_panel.h" 111 #include "intel_pch_display.h" 112 #include "intel_pch_refclk.h" 113 #include "intel_pfit.h" 114 #include "intel_pipe_crc.h" 115 #include "intel_plane.h" 116 #include "intel_pmdemand.h" 117 #include "intel_pps.h" 118 #include "intel_psr.h" 119 #include "intel_psr_regs.h" 120 #include "intel_sdvo.h" 121 #include "intel_snps_phy.h" 122 #include "intel_tc.h" 123 #include "intel_tdf.h" 124 #include "intel_tv.h" 125 #include "intel_vblank.h" 126 #include "intel_vdsc.h" 127 #include "intel_vdsc_regs.h" 128 #include "intel_vga.h" 129 #include "intel_vrr.h" 130 #include "intel_wm.h" 131 #include "skl_scaler.h" 132 #include "skl_universal_plane.h" 133 #include "skl_watermark.h" 134 #include "vlv_dsi.h" 135 #include "vlv_dsi_pll.h" 136 #include "vlv_dsi_regs.h" 137 138 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 139 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 140 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 141 static void bdw_set_pipe_misc(struct intel_dsb *dsb, 142 const struct intel_crtc_state *crtc_state); 143 144 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 145 { 146 return (crtc_state->active_planes & 147 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 148 } 149 150 /* WA Display #0827: Gen9:all */ 151 static void 152 skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable) 153 { 154 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 155 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 156 enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0); 157 } 158 159 /* Wa_2006604312:icl,ehl */ 160 static void 161 icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe, 162 bool enable) 163 { 164 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 165 DPFR_GATING_DIS, 166 enable ? DPFR_GATING_DIS : 0); 167 } 168 169 /* Wa_1604331009:icl,jsl,ehl */ 170 static void 171 icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe, 172 bool enable) 173 { 174 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 175 CURSOR_GATING_DIS, 176 enable ? CURSOR_GATING_DIS : 0); 177 } 178 179 static bool 180 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 181 { 182 return crtc_state->master_transcoder != INVALID_TRANSCODER; 183 } 184 185 bool 186 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 187 { 188 return crtc_state->sync_mode_slaves_mask != 0; 189 } 190 191 bool 192 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 193 { 194 return is_trans_port_sync_master(crtc_state) || 195 is_trans_port_sync_slave(crtc_state); 196 } 197 198 static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state) 199 { 200 return ffs(crtc_state->joiner_pipes) - 1; 201 } 202 203 /* 204 * The following helper functions, despite being named for bigjoiner, 205 * are applicable to both bigjoiner and uncompressed joiner configurations. 206 */ 207 static bool is_bigjoiner(const struct intel_crtc_state *crtc_state) 208 { 209 return hweight8(crtc_state->joiner_pipes) >= 2; 210 } 211 212 static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state) 213 { 214 if (!is_bigjoiner(crtc_state)) 215 return 0; 216 217 return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state)); 218 } 219 220 static unsigned int bigjoiner_secondary_pipes(const struct intel_crtc_state *crtc_state) 221 { 222 if (!is_bigjoiner(crtc_state)) 223 return 0; 224 225 return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state)); 226 } 227 228 bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state) 229 { 230 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 231 232 if (!is_bigjoiner(crtc_state)) 233 return false; 234 235 return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state); 236 } 237 238 bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state) 239 { 240 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 241 242 if (!is_bigjoiner(crtc_state)) 243 return false; 244 245 return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state); 246 } 247 248 u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state) 249 { 250 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 251 252 if (!is_bigjoiner(crtc_state)) 253 return BIT(crtc->pipe); 254 255 return bigjoiner_primary_pipes(crtc_state); 256 } 257 258 u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state) 259 { 260 return bigjoiner_secondary_pipes(crtc_state); 261 } 262 263 bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state) 264 { 265 return intel_crtc_num_joined_pipes(crtc_state) >= 4; 266 } 267 268 static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state) 269 { 270 if (!intel_crtc_is_ultrajoiner(crtc_state)) 271 return 0; 272 273 return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state)); 274 } 275 276 bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state) 277 { 278 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 279 280 return intel_crtc_is_ultrajoiner(crtc_state) && 281 BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state); 282 } 283 284 /* 285 * The ultrajoiner enable bit doesn't seem to follow primary/secondary logic or 286 * any other logic, so lets just add helper function to 287 * at least hide this hassle.. 288 */ 289 static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state) 290 { 291 if (!intel_crtc_is_ultrajoiner(crtc_state)) 292 return 0; 293 294 return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state)); 295 } 296 297 bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state) 298 { 299 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 300 301 return intel_crtc_is_ultrajoiner(crtc_state) && 302 BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state); 303 } 304 305 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state) 306 { 307 if (crtc_state->joiner_pipes) 308 return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state)); 309 else 310 return 0; 311 } 312 313 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state) 314 { 315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 316 317 return crtc_state->joiner_pipes && 318 crtc->pipe != joiner_primary_pipe(crtc_state); 319 } 320 321 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state) 322 { 323 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 324 325 return crtc_state->joiner_pipes && 326 crtc->pipe == joiner_primary_pipe(crtc_state); 327 } 328 329 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state) 330 { 331 return hweight8(intel_crtc_joined_pipe_mask(crtc_state)); 332 } 333 334 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state) 335 { 336 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 337 338 return BIT(crtc->pipe) | crtc_state->joiner_pipes; 339 } 340 341 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) 342 { 343 struct intel_display *display = to_intel_display(crtc_state); 344 345 if (intel_crtc_is_joiner_secondary(crtc_state)) 346 return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state)); 347 else 348 return to_intel_crtc(crtc_state->uapi.crtc); 349 } 350 351 static void 352 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 353 { 354 struct intel_display *display = to_intel_display(old_crtc_state); 355 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 356 357 if (DISPLAY_VER(display) >= 4) { 358 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 359 360 /* Wait for the Pipe State to go off */ 361 if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, cpu_transcoder), 362 TRANSCONF_STATE_ENABLE, 100)) 363 drm_WARN(display->drm, 1, "pipe_off wait timed out\n"); 364 } else { 365 intel_wait_for_pipe_scanline_stopped(crtc); 366 } 367 } 368 369 void assert_transcoder(struct intel_display *display, 370 enum transcoder cpu_transcoder, bool state) 371 { 372 bool cur_state; 373 enum intel_display_power_domain power_domain; 374 struct ref_tracker *wakeref; 375 376 /* we keep both pipes enabled on 830 */ 377 if (display->platform.i830) 378 state = true; 379 380 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 381 wakeref = intel_display_power_get_if_enabled(display, power_domain); 382 if (wakeref) { 383 u32 val = intel_de_read(display, 384 TRANSCONF(display, cpu_transcoder)); 385 cur_state = !!(val & TRANSCONF_ENABLE); 386 387 intel_display_power_put(display, power_domain, wakeref); 388 } else { 389 cur_state = false; 390 } 391 392 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 393 "transcoder %s assertion failure (expected %s, current %s)\n", 394 transcoder_name(cpu_transcoder), str_on_off(state), 395 str_on_off(cur_state)); 396 } 397 398 static void assert_plane(struct intel_plane *plane, bool state) 399 { 400 struct intel_display *display = to_intel_display(plane->base.dev); 401 enum pipe pipe; 402 bool cur_state; 403 404 cur_state = plane->get_hw_state(plane, &pipe); 405 406 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 407 "%s assertion failure (expected %s, current %s)\n", 408 plane->base.name, str_on_off(state), 409 str_on_off(cur_state)); 410 } 411 412 #define assert_plane_enabled(p) assert_plane(p, true) 413 #define assert_plane_disabled(p) assert_plane(p, false) 414 415 static void assert_planes_disabled(struct intel_crtc *crtc) 416 { 417 struct intel_display *display = to_intel_display(crtc); 418 struct intel_plane *plane; 419 420 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 421 assert_plane_disabled(plane); 422 } 423 424 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 425 { 426 struct intel_display *display = to_intel_display(new_crtc_state); 427 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 428 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 429 enum pipe pipe = crtc->pipe; 430 u32 val; 431 432 drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe)); 433 434 assert_planes_disabled(crtc); 435 436 /* 437 * A pipe without a PLL won't actually be able to drive bits from 438 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 439 * need the check. 440 */ 441 if (HAS_GMCH(display)) { 442 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 443 assert_dsi_pll_enabled(display); 444 else 445 assert_pll_enabled(display, pipe); 446 } else { 447 if (new_crtc_state->has_pch_encoder) { 448 /* if driving the PCH, we need FDI enabled */ 449 assert_fdi_rx_pll_enabled(display, 450 intel_crtc_pch_transcoder(crtc)); 451 assert_fdi_tx_pll_enabled(display, 452 (enum pipe) cpu_transcoder); 453 } 454 /* FIXME: assert CPU port conditions for SNB+ */ 455 } 456 457 /* Wa_22012358565:adl-p */ 458 if (DISPLAY_VER(display) == 13) 459 intel_de_rmw(display, PIPE_ARB_CTL(display, pipe), 460 0, PIPE_ARB_USE_PROG_SLOTS); 461 462 if (DISPLAY_VER(display) >= 14) { 463 u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA; 464 u32 set = 0; 465 466 if (DISPLAY_VER(display) == 14) 467 set |= DP_FEC_BS_JITTER_WA; 468 469 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 470 clear, set); 471 } 472 473 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 474 if (val & TRANSCONF_ENABLE) { 475 /* we keep both pipes enabled on 830 */ 476 drm_WARN_ON(display->drm, !display->platform.i830); 477 return; 478 } 479 480 /* Wa_1409098942:adlp+ */ 481 if (DISPLAY_VER(display) >= 13 && 482 new_crtc_state->dsc.compression_enable) { 483 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; 484 val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK, 485 TRANSCONF_PIXEL_COUNT_SCALING_X4); 486 } 487 488 intel_de_write(display, TRANSCONF(display, cpu_transcoder), 489 val | TRANSCONF_ENABLE); 490 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 491 492 /* 493 * Until the pipe starts PIPEDSL reads will return a stale value, 494 * which causes an apparent vblank timestamp jump when PIPEDSL 495 * resets to its proper value. That also messes up the frame count 496 * when it's derived from the timestamps. So let's wait for the 497 * pipe to start properly before we call drm_crtc_vblank_on() 498 */ 499 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 500 intel_wait_for_pipe_scanline_moving(crtc); 501 } 502 503 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 504 { 505 struct intel_display *display = to_intel_display(old_crtc_state); 506 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 507 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 508 enum pipe pipe = crtc->pipe; 509 u32 val; 510 511 drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe)); 512 513 /* 514 * Make sure planes won't keep trying to pump pixels to us, 515 * or we might hang the display. 516 */ 517 assert_planes_disabled(crtc); 518 519 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 520 if ((val & TRANSCONF_ENABLE) == 0) 521 return; 522 523 /* 524 * Double wide has implications for planes 525 * so best keep it disabled when not needed. 526 */ 527 if (old_crtc_state->double_wide) 528 val &= ~TRANSCONF_DOUBLE_WIDE; 529 530 /* Don't disable pipe or pipe PLLs if needed */ 531 if (!display->platform.i830) 532 val &= ~TRANSCONF_ENABLE; 533 534 /* Wa_1409098942:adlp+ */ 535 if (DISPLAY_VER(display) >= 13 && 536 old_crtc_state->dsc.compression_enable) 537 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; 538 539 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 540 541 if (DISPLAY_VER(display) >= 12) 542 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 543 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 544 545 if ((val & TRANSCONF_ENABLE) == 0) 546 intel_wait_for_pipe_off(old_crtc_state); 547 } 548 549 u32 intel_plane_fb_max_stride(struct intel_display *display, 550 const struct drm_format_info *info, 551 u64 modifier) 552 { 553 struct intel_crtc *crtc; 554 struct intel_plane *plane; 555 556 /* 557 * We assume the primary plane for pipe A has 558 * the highest stride limits of them all, 559 * if in case pipe A is disabled, use the first pipe from pipe_mask. 560 */ 561 crtc = intel_first_crtc(display); 562 if (!crtc) 563 return 0; 564 565 plane = to_intel_plane(crtc->base.primary); 566 567 return plane->max_stride(plane, info, modifier, 568 DRM_MODE_ROTATE_0); 569 } 570 571 u32 intel_dumb_fb_max_stride(struct drm_device *drm, 572 u32 pixel_format, u64 modifier) 573 { 574 struct intel_display *display = to_intel_display(drm); 575 576 if (!HAS_DISPLAY(display)) 577 return 0; 578 579 return intel_plane_fb_max_stride(display, 580 drm_get_format_info(drm, pixel_format, modifier), 581 modifier); 582 } 583 584 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 585 struct intel_plane_state *plane_state, 586 bool visible) 587 { 588 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 589 590 plane_state->uapi.visible = visible; 591 592 if (visible) 593 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 594 else 595 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 596 } 597 598 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 599 { 600 struct intel_display *display = to_intel_display(crtc_state); 601 struct drm_plane *plane; 602 603 /* 604 * Active_planes aliases if multiple "primary" or cursor planes 605 * have been used on the same (or wrong) pipe. plane_mask uses 606 * unique ids, hence we can use that to reconstruct active_planes. 607 */ 608 crtc_state->enabled_planes = 0; 609 crtc_state->active_planes = 0; 610 611 drm_for_each_plane_mask(plane, display->drm, 612 crtc_state->uapi.plane_mask) { 613 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 614 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 615 } 616 } 617 618 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 619 struct intel_plane *plane) 620 { 621 struct intel_display *display = to_intel_display(crtc); 622 struct intel_crtc_state *crtc_state = 623 to_intel_crtc_state(crtc->base.state); 624 struct intel_plane_state *plane_state = 625 to_intel_plane_state(plane->base.state); 626 627 drm_dbg_kms(display->drm, 628 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 629 plane->base.base.id, plane->base.name, 630 crtc->base.base.id, crtc->base.name); 631 632 intel_plane_set_invisible(crtc_state, plane_state); 633 intel_set_plane_visible(crtc_state, plane_state, false); 634 intel_plane_fixup_bitmasks(crtc_state); 635 636 skl_wm_plane_disable_noatomic(crtc, plane); 637 638 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 639 hsw_ips_disable(crtc_state)) { 640 crtc_state->ips_enabled = false; 641 intel_initial_plane_vblank_wait(crtc); 642 } 643 644 /* 645 * Vblank time updates from the shadow to live plane control register 646 * are blocked if the memory self-refresh mode is active at that 647 * moment. So to make sure the plane gets truly disabled, disable 648 * first the self-refresh mode. The self-refresh enable bit in turn 649 * will be checked/applied by the HW only at the next frame start 650 * event which is after the vblank start event, so we need to have a 651 * wait-for-vblank between disabling the plane and the pipe. 652 */ 653 if (HAS_GMCH(display) && 654 intel_set_memory_cxsr(display, false)) 655 intel_initial_plane_vblank_wait(crtc); 656 657 /* 658 * Gen2 reports pipe underruns whenever all planes are disabled. 659 * So disable underrun reporting before all the planes get disabled. 660 */ 661 if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes) 662 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false); 663 664 intel_plane_disable_arm(NULL, plane, crtc_state); 665 intel_initial_plane_vblank_wait(crtc); 666 } 667 668 unsigned int 669 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 670 { 671 int x = 0, y = 0; 672 673 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 674 plane_state->view.color_plane[0].offset, 0); 675 676 return y; 677 } 678 679 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 680 { 681 struct intel_display *display = to_intel_display(crtc_state); 682 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 683 enum pipe pipe = crtc->pipe; 684 u32 tmp; 685 686 tmp = intel_de_read(display, PIPE_CHICKEN(pipe)); 687 688 /* 689 * Display WA #1153: icl 690 * enable hardware to bypass the alpha math 691 * and rounding for per-pixel values 00 and 0xff 692 */ 693 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 694 /* 695 * Display WA # 1605353570: icl 696 * Set the pixel rounding bit to 1 for allowing 697 * passthrough of Frame buffer pixels unmodified 698 * across pipe 699 */ 700 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 701 702 /* 703 * Underrun recovery must always be disabled on display 13+. 704 * DG2 chicken bit meaning is inverted compared to other platforms. 705 */ 706 if (display->platform.dg2) 707 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 708 else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30)) 709 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 710 711 /* Wa_14010547955:dg2 */ 712 if (display->platform.dg2) 713 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 714 715 intel_de_write(display, PIPE_CHICKEN(pipe), tmp); 716 } 717 718 bool intel_has_pending_fb_unpin(struct intel_display *display) 719 { 720 struct drm_crtc *crtc; 721 bool cleanup_done; 722 723 drm_for_each_crtc(crtc, display->drm) { 724 struct drm_crtc_commit *commit; 725 spin_lock(&crtc->commit_lock); 726 commit = list_first_entry_or_null(&crtc->commit_list, 727 struct drm_crtc_commit, commit_entry); 728 cleanup_done = commit ? 729 try_wait_for_completion(&commit->cleanup_done) : true; 730 spin_unlock(&crtc->commit_lock); 731 732 if (cleanup_done) 733 continue; 734 735 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 736 737 return true; 738 } 739 740 return false; 741 } 742 743 /* 744 * Finds the encoder associated with the given CRTC. This can only be 745 * used when we know that the CRTC isn't feeding multiple encoders! 746 */ 747 struct intel_encoder * 748 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 749 const struct intel_crtc_state *crtc_state) 750 { 751 const struct drm_connector_state *connector_state; 752 const struct drm_connector *connector; 753 struct intel_encoder *encoder = NULL; 754 struct intel_crtc *primary_crtc; 755 int num_encoders = 0; 756 int i; 757 758 primary_crtc = intel_primary_crtc(crtc_state); 759 760 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 761 if (connector_state->crtc != &primary_crtc->base) 762 continue; 763 764 encoder = to_intel_encoder(connector_state->best_encoder); 765 num_encoders++; 766 } 767 768 drm_WARN(state->base.dev, num_encoders != 1, 769 "%d encoders for pipe %c\n", 770 num_encoders, pipe_name(primary_crtc->pipe)); 771 772 return encoder; 773 } 774 775 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 776 { 777 if (crtc->overlay) 778 (void) intel_overlay_switch_off(crtc->overlay); 779 780 /* Let userspace switch the overlay on again. In most cases userspace 781 * has to recompute where to put it anyway. 782 */ 783 } 784 785 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 786 { 787 struct intel_display *display = to_intel_display(crtc_state); 788 789 if (!crtc_state->nv12_planes) 790 return false; 791 792 /* WA Display #0827: Gen9:all */ 793 if (DISPLAY_VER(display) == 9) 794 return true; 795 796 return false; 797 } 798 799 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 800 { 801 struct intel_display *display = to_intel_display(crtc_state); 802 803 /* Wa_2006604312:icl,ehl */ 804 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11) 805 return true; 806 807 return false; 808 } 809 810 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 811 { 812 struct intel_display *display = to_intel_display(crtc_state); 813 814 /* Wa_1604331009:icl,jsl,ehl */ 815 if (is_hdr_mode(crtc_state) && 816 crtc_state->active_planes & BIT(PLANE_CURSOR) && 817 DISPLAY_VER(display) == 11) 818 return true; 819 820 return false; 821 } 822 823 static void intel_async_flip_vtd_wa(struct intel_display *display, 824 enum pipe pipe, bool enable) 825 { 826 if (DISPLAY_VER(display) == 9) { 827 /* 828 * "Plane N stretch max must be programmed to 11b (x1) 829 * when Async flips are enabled on that plane." 830 */ 831 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 832 SKL_PLANE1_STRETCH_MAX_MASK, 833 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 834 } else { 835 /* Also needed on HSW/BDW albeit undocumented */ 836 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 837 HSW_PRI_STRETCH_MAX_MASK, 838 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 839 } 840 } 841 842 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 843 { 844 struct intel_display *display = to_intel_display(crtc_state); 845 846 return crtc_state->uapi.async_flip && intel_display_vtd_active(display) && 847 (DISPLAY_VER(display) == 9 || display->platform.broadwell || 848 display->platform.haswell); 849 } 850 851 static void intel_encoders_audio_enable(struct intel_atomic_state *state, 852 struct intel_crtc *crtc) 853 { 854 const struct intel_crtc_state *crtc_state = 855 intel_atomic_get_new_crtc_state(state, crtc); 856 const struct drm_connector_state *conn_state; 857 struct drm_connector *conn; 858 int i; 859 860 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 861 struct intel_encoder *encoder = 862 to_intel_encoder(conn_state->best_encoder); 863 864 if (conn_state->crtc != &crtc->base) 865 continue; 866 867 if (encoder->audio_enable) 868 encoder->audio_enable(encoder, crtc_state, conn_state); 869 } 870 } 871 872 static void intel_encoders_audio_disable(struct intel_atomic_state *state, 873 struct intel_crtc *crtc) 874 { 875 const struct intel_crtc_state *old_crtc_state = 876 intel_atomic_get_old_crtc_state(state, crtc); 877 const struct drm_connector_state *old_conn_state; 878 struct drm_connector *conn; 879 int i; 880 881 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 882 struct intel_encoder *encoder = 883 to_intel_encoder(old_conn_state->best_encoder); 884 885 if (old_conn_state->crtc != &crtc->base) 886 continue; 887 888 if (encoder->audio_disable) 889 encoder->audio_disable(encoder, old_crtc_state, old_conn_state); 890 } 891 } 892 893 #define is_enabling(feature, old_crtc_state, new_crtc_state) \ 894 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \ 895 (new_crtc_state)->feature) 896 #define is_disabling(feature, old_crtc_state, new_crtc_state) \ 897 ((old_crtc_state)->feature && \ 898 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state))) 899 900 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 901 const struct intel_crtc_state *new_crtc_state) 902 { 903 if (!new_crtc_state->hw.active) 904 return false; 905 906 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 907 } 908 909 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 910 const struct intel_crtc_state *new_crtc_state) 911 { 912 if (!old_crtc_state->hw.active) 913 return false; 914 915 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 916 } 917 918 static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, 919 const struct intel_crtc_state *new_crtc_state) 920 { 921 return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline || 922 old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin || 923 old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax || 924 old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband || 925 old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full || 926 old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start || 927 old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end; 928 } 929 930 static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, 931 const struct intel_crtc_state *new_crtc_state) 932 { 933 return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || 934 old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; 935 } 936 937 static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state, 938 struct intel_crtc *crtc) 939 { 940 const struct intel_crtc_state *old_crtc_state = 941 intel_atomic_get_old_crtc_state(state, crtc); 942 const struct intel_crtc_state *new_crtc_state = 943 intel_atomic_get_new_crtc_state(state, crtc); 944 945 if (!new_crtc_state->hw.active) 946 return false; 947 948 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) || 949 (new_crtc_state->vrr.enable && 950 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || 951 vrr_params_changed(old_crtc_state, new_crtc_state))); 952 } 953 954 bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, 955 struct intel_crtc *crtc) 956 { 957 const struct intel_crtc_state *old_crtc_state = 958 intel_atomic_get_old_crtc_state(state, crtc); 959 const struct intel_crtc_state *new_crtc_state = 960 intel_atomic_get_new_crtc_state(state, crtc); 961 962 if (!old_crtc_state->hw.active) 963 return false; 964 965 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) || 966 (old_crtc_state->vrr.enable && 967 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || 968 vrr_params_changed(old_crtc_state, new_crtc_state))); 969 } 970 971 static bool audio_enabling(const struct intel_crtc_state *old_crtc_state, 972 const struct intel_crtc_state *new_crtc_state) 973 { 974 if (!new_crtc_state->hw.active) 975 return false; 976 977 return is_enabling(has_audio, old_crtc_state, new_crtc_state) || 978 (new_crtc_state->has_audio && 979 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); 980 } 981 982 static bool audio_disabling(const struct intel_crtc_state *old_crtc_state, 983 const struct intel_crtc_state *new_crtc_state) 984 { 985 if (!old_crtc_state->hw.active) 986 return false; 987 988 return is_disabling(has_audio, old_crtc_state, new_crtc_state) || 989 (old_crtc_state->has_audio && 990 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); 991 } 992 993 static bool intel_casf_enabling(const struct intel_crtc_state *new_crtc_state, 994 const struct intel_crtc_state *old_crtc_state) 995 { 996 if (!new_crtc_state->hw.active) 997 return false; 998 999 return is_enabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state); 1000 } 1001 1002 static bool intel_casf_disabling(const struct intel_crtc_state *old_crtc_state, 1003 const struct intel_crtc_state *new_crtc_state) 1004 { 1005 if (!new_crtc_state->hw.active) 1006 return false; 1007 1008 return is_disabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state); 1009 } 1010 1011 #undef is_disabling 1012 #undef is_enabling 1013 1014 static void intel_post_plane_update(struct intel_atomic_state *state, 1015 struct intel_crtc *crtc) 1016 { 1017 struct intel_display *display = to_intel_display(state); 1018 const struct intel_crtc_state *old_crtc_state = 1019 intel_atomic_get_old_crtc_state(state, crtc); 1020 const struct intel_crtc_state *new_crtc_state = 1021 intel_atomic_get_new_crtc_state(state, crtc); 1022 enum pipe pipe = crtc->pipe; 1023 1024 intel_frontbuffer_flip(display, new_crtc_state->fb_bits); 1025 1026 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1027 intel_update_watermarks(display); 1028 1029 intel_fbc_post_update(state, crtc); 1030 1031 if (needs_async_flip_vtd_wa(old_crtc_state) && 1032 !needs_async_flip_vtd_wa(new_crtc_state)) 1033 intel_async_flip_vtd_wa(display, pipe, false); 1034 1035 if (needs_nv12_wa(old_crtc_state) && 1036 !needs_nv12_wa(new_crtc_state)) 1037 skl_wa_827(display, pipe, false); 1038 1039 if (needs_scalerclk_wa(old_crtc_state) && 1040 !needs_scalerclk_wa(new_crtc_state)) 1041 icl_wa_scalerclkgating(display, pipe, false); 1042 1043 if (needs_cursorclk_wa(old_crtc_state) && 1044 !needs_cursorclk_wa(new_crtc_state)) 1045 icl_wa_cursorclkgating(display, pipe, false); 1046 1047 if (intel_crtc_needs_color_update(new_crtc_state)) 1048 intel_color_post_update(new_crtc_state); 1049 1050 if (audio_enabling(old_crtc_state, new_crtc_state)) 1051 intel_encoders_audio_enable(state, crtc); 1052 1053 if (intel_display_wa(display, 14011503117)) { 1054 if (old_crtc_state->pch_pfit.enabled != new_crtc_state->pch_pfit.enabled) 1055 adl_scaler_ecc_unmask(new_crtc_state); 1056 } 1057 1058 intel_alpm_post_plane_update(state, crtc); 1059 1060 intel_psr_post_plane_update(state, crtc); 1061 } 1062 1063 static void intel_post_plane_update_after_readout(struct intel_atomic_state *state, 1064 struct intel_crtc *crtc) 1065 { 1066 const struct intel_crtc_state *new_crtc_state = 1067 intel_atomic_get_new_crtc_state(state, crtc); 1068 1069 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 1070 hsw_ips_post_update(state, crtc); 1071 1072 /* 1073 * Activate DRRS after state readout to avoid 1074 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 1075 */ 1076 intel_drrs_activate(new_crtc_state); 1077 } 1078 1079 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1080 struct intel_crtc *crtc) 1081 { 1082 const struct intel_crtc_state *crtc_state = 1083 intel_atomic_get_new_crtc_state(state, crtc); 1084 u8 update_planes = crtc_state->update_planes; 1085 const struct intel_plane_state __maybe_unused *plane_state; 1086 struct intel_plane *plane; 1087 int i; 1088 1089 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1090 if (plane->pipe == crtc->pipe && 1091 update_planes & BIT(plane->id)) 1092 plane->enable_flip_done(plane); 1093 } 1094 } 1095 1096 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1097 struct intel_crtc *crtc) 1098 { 1099 const struct intel_crtc_state *crtc_state = 1100 intel_atomic_get_new_crtc_state(state, crtc); 1101 u8 update_planes = crtc_state->update_planes; 1102 const struct intel_plane_state __maybe_unused *plane_state; 1103 struct intel_plane *plane; 1104 int i; 1105 1106 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1107 if (plane->pipe == crtc->pipe && 1108 update_planes & BIT(plane->id)) 1109 plane->disable_flip_done(plane); 1110 } 1111 } 1112 1113 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1114 struct intel_crtc *crtc) 1115 { 1116 const struct intel_crtc_state *old_crtc_state = 1117 intel_atomic_get_old_crtc_state(state, crtc); 1118 const struct intel_crtc_state *new_crtc_state = 1119 intel_atomic_get_new_crtc_state(state, crtc); 1120 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1121 ~new_crtc_state->async_flip_planes; 1122 const struct intel_plane_state *old_plane_state; 1123 struct intel_plane *plane; 1124 bool need_vbl_wait = false; 1125 int i; 1126 1127 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1128 if (plane->need_async_flip_toggle_wa && 1129 plane->pipe == crtc->pipe && 1130 disable_async_flip_planes & BIT(plane->id)) { 1131 /* 1132 * Apart from the async flip bit we want to 1133 * preserve the old state for the plane. 1134 */ 1135 intel_plane_async_flip(NULL, plane, 1136 old_crtc_state, old_plane_state, false); 1137 need_vbl_wait = true; 1138 } 1139 } 1140 1141 if (need_vbl_wait) 1142 intel_crtc_wait_for_next_vblank(crtc); 1143 } 1144 1145 static void intel_pre_plane_update(struct intel_atomic_state *state, 1146 struct intel_crtc *crtc) 1147 { 1148 struct intel_display *display = to_intel_display(state); 1149 const struct intel_crtc_state *old_crtc_state = 1150 intel_atomic_get_old_crtc_state(state, crtc); 1151 const struct intel_crtc_state *new_crtc_state = 1152 intel_atomic_get_new_crtc_state(state, crtc); 1153 enum pipe pipe = crtc->pipe; 1154 1155 intel_alpm_pre_plane_update(state, crtc); 1156 intel_psr_pre_plane_update(state, crtc); 1157 1158 if (intel_crtc_vrr_disabling(state, crtc)) { 1159 intel_vrr_disable(old_crtc_state); 1160 intel_vrr_dcb_reset(old_crtc_state, crtc); 1161 intel_crtc_update_active_timings(old_crtc_state, false); 1162 } 1163 1164 if (audio_disabling(old_crtc_state, new_crtc_state)) 1165 intel_encoders_audio_disable(state, crtc); 1166 1167 if (intel_casf_disabling(old_crtc_state, new_crtc_state)) 1168 intel_casf_disable(new_crtc_state); 1169 1170 intel_drrs_deactivate(old_crtc_state); 1171 1172 if (hsw_ips_pre_update(state, crtc)) 1173 intel_crtc_wait_for_next_vblank(crtc); 1174 1175 if (intel_fbc_pre_update(state, crtc)) 1176 intel_crtc_wait_for_next_vblank(crtc); 1177 1178 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1179 needs_async_flip_vtd_wa(new_crtc_state)) 1180 intel_async_flip_vtd_wa(display, pipe, true); 1181 1182 /* Display WA 827 */ 1183 if (!needs_nv12_wa(old_crtc_state) && 1184 needs_nv12_wa(new_crtc_state)) 1185 skl_wa_827(display, pipe, true); 1186 1187 /* Wa_2006604312:icl,ehl */ 1188 if (!needs_scalerclk_wa(old_crtc_state) && 1189 needs_scalerclk_wa(new_crtc_state)) 1190 icl_wa_scalerclkgating(display, pipe, true); 1191 1192 /* Wa_1604331009:icl,jsl,ehl */ 1193 if (!needs_cursorclk_wa(old_crtc_state) && 1194 needs_cursorclk_wa(new_crtc_state)) 1195 icl_wa_cursorclkgating(display, pipe, true); 1196 1197 /* 1198 * Vblank time updates from the shadow to live plane control register 1199 * are blocked if the memory self-refresh mode is active at that 1200 * moment. So to make sure the plane gets truly disabled, disable 1201 * first the self-refresh mode. The self-refresh enable bit in turn 1202 * will be checked/applied by the HW only at the next frame start 1203 * event which is after the vblank start event, so we need to have a 1204 * wait-for-vblank between disabling the plane and the pipe. 1205 */ 1206 if (HAS_GMCH(display) && old_crtc_state->hw.active && 1207 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false)) 1208 intel_crtc_wait_for_next_vblank(crtc); 1209 1210 /* 1211 * IVB workaround: must disable low power watermarks for at least 1212 * one frame before enabling scaling. LP watermarks can be re-enabled 1213 * when scaling is disabled. 1214 * 1215 * WaCxSRDisabledForSpriteScaling:ivb 1216 */ 1217 if (!HAS_GMCH(display) && old_crtc_state->hw.active && 1218 new_crtc_state->disable_cxsr && ilk_disable_cxsr(display)) 1219 intel_crtc_wait_for_next_vblank(crtc); 1220 1221 /* 1222 * If we're doing a modeset we don't need to do any 1223 * pre-vblank watermark programming here. 1224 */ 1225 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1226 /* 1227 * For platforms that support atomic watermarks, program the 1228 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1229 * will be the intermediate values that are safe for both pre- and 1230 * post- vblank; when vblank happens, the 'active' values will be set 1231 * to the final 'target' values and we'll do this again to get the 1232 * optimal watermarks. For gen9+ platforms, the values we program here 1233 * will be the final target values which will get automatically latched 1234 * at vblank time; no further programming will be necessary. 1235 * 1236 * If a platform hasn't been transitioned to atomic watermarks yet, 1237 * we'll continue to update watermarks the old way, if flags tell 1238 * us to. 1239 */ 1240 if (!intel_initial_watermarks(state, crtc)) 1241 if (new_crtc_state->update_wm_pre) 1242 intel_update_watermarks(display); 1243 } 1244 1245 /* 1246 * Gen2 reports pipe underruns whenever all planes are disabled. 1247 * So disable underrun reporting before all the planes get disabled. 1248 * 1249 * We do this after .initial_watermarks() so that we have a 1250 * chance of catching underruns with the intermediate watermarks 1251 * vs. the old plane configuration. 1252 */ 1253 if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1254 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1255 1256 /* 1257 * WA for platforms where async address update enable bit 1258 * is double buffered and only latched at start of vblank. 1259 */ 1260 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1261 intel_crtc_async_flip_disable_wa(state, crtc); 1262 } 1263 1264 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1265 struct intel_crtc *crtc) 1266 { 1267 struct intel_display *display = to_intel_display(state); 1268 const struct intel_crtc_state *new_crtc_state = 1269 intel_atomic_get_new_crtc_state(state, crtc); 1270 unsigned int update_mask = new_crtc_state->update_planes; 1271 const struct intel_plane_state *old_plane_state; 1272 struct intel_plane *plane; 1273 unsigned fb_bits = 0; 1274 int i; 1275 1276 intel_crtc_dpms_overlay_disable(crtc); 1277 1278 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1279 if (crtc->pipe != plane->pipe || 1280 !(update_mask & BIT(plane->id))) 1281 continue; 1282 1283 intel_plane_disable_arm(NULL, plane, new_crtc_state); 1284 1285 if (old_plane_state->uapi.visible) 1286 fb_bits |= plane->frontbuffer_bit; 1287 } 1288 1289 intel_frontbuffer_flip(display, fb_bits); 1290 } 1291 1292 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1293 { 1294 struct intel_display *display = to_intel_display(state); 1295 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1296 struct intel_crtc *crtc; 1297 int i; 1298 1299 /* 1300 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1301 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1302 */ 1303 if (display->dpll.mgr) { 1304 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1305 if (intel_crtc_needs_modeset(new_crtc_state)) 1306 continue; 1307 1308 new_crtc_state->intel_dpll = old_crtc_state->intel_dpll; 1309 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1310 } 1311 } 1312 } 1313 1314 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1315 struct intel_crtc *crtc) 1316 { 1317 const struct intel_crtc_state *crtc_state = 1318 intel_atomic_get_new_crtc_state(state, crtc); 1319 const struct drm_connector_state *conn_state; 1320 struct drm_connector *conn; 1321 int i; 1322 1323 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1324 struct intel_encoder *encoder = 1325 to_intel_encoder(conn_state->best_encoder); 1326 1327 if (conn_state->crtc != &crtc->base) 1328 continue; 1329 1330 if (encoder->pre_pll_enable) 1331 encoder->pre_pll_enable(state, encoder, 1332 crtc_state, conn_state); 1333 } 1334 } 1335 1336 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1337 struct intel_crtc *crtc) 1338 { 1339 const struct intel_crtc_state *crtc_state = 1340 intel_atomic_get_new_crtc_state(state, crtc); 1341 const struct drm_connector_state *conn_state; 1342 struct drm_connector *conn; 1343 int i; 1344 1345 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1346 struct intel_encoder *encoder = 1347 to_intel_encoder(conn_state->best_encoder); 1348 1349 if (conn_state->crtc != &crtc->base) 1350 continue; 1351 1352 if (encoder->pre_enable) 1353 encoder->pre_enable(state, encoder, 1354 crtc_state, conn_state); 1355 } 1356 } 1357 1358 static void intel_encoders_enable(struct intel_atomic_state *state, 1359 struct intel_crtc *crtc) 1360 { 1361 const struct intel_crtc_state *crtc_state = 1362 intel_atomic_get_new_crtc_state(state, crtc); 1363 const struct drm_connector_state *conn_state; 1364 struct drm_connector *conn; 1365 int i; 1366 1367 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1368 struct intel_encoder *encoder = 1369 to_intel_encoder(conn_state->best_encoder); 1370 1371 if (conn_state->crtc != &crtc->base) 1372 continue; 1373 1374 if (encoder->enable) 1375 encoder->enable(state, encoder, 1376 crtc_state, conn_state); 1377 intel_opregion_notify_encoder(encoder, true); 1378 } 1379 } 1380 1381 static void intel_encoders_disable(struct intel_atomic_state *state, 1382 struct intel_crtc *crtc) 1383 { 1384 const struct intel_crtc_state *old_crtc_state = 1385 intel_atomic_get_old_crtc_state(state, crtc); 1386 const struct drm_connector_state *old_conn_state; 1387 struct drm_connector *conn; 1388 int i; 1389 1390 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1391 struct intel_encoder *encoder = 1392 to_intel_encoder(old_conn_state->best_encoder); 1393 1394 if (old_conn_state->crtc != &crtc->base) 1395 continue; 1396 1397 intel_opregion_notify_encoder(encoder, false); 1398 if (encoder->disable) 1399 encoder->disable(state, encoder, 1400 old_crtc_state, old_conn_state); 1401 } 1402 } 1403 1404 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1405 struct intel_crtc *crtc) 1406 { 1407 const struct intel_crtc_state *old_crtc_state = 1408 intel_atomic_get_old_crtc_state(state, crtc); 1409 const struct drm_connector_state *old_conn_state; 1410 struct drm_connector *conn; 1411 int i; 1412 1413 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1414 struct intel_encoder *encoder = 1415 to_intel_encoder(old_conn_state->best_encoder); 1416 1417 if (old_conn_state->crtc != &crtc->base) 1418 continue; 1419 1420 if (encoder->post_disable) 1421 encoder->post_disable(state, encoder, 1422 old_crtc_state, old_conn_state); 1423 } 1424 } 1425 1426 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1427 struct intel_crtc *crtc) 1428 { 1429 const struct intel_crtc_state *old_crtc_state = 1430 intel_atomic_get_old_crtc_state(state, crtc); 1431 const struct drm_connector_state *old_conn_state; 1432 struct drm_connector *conn; 1433 int i; 1434 1435 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1436 struct intel_encoder *encoder = 1437 to_intel_encoder(old_conn_state->best_encoder); 1438 1439 if (old_conn_state->crtc != &crtc->base) 1440 continue; 1441 1442 if (encoder->post_pll_disable) 1443 encoder->post_pll_disable(state, encoder, 1444 old_crtc_state, old_conn_state); 1445 } 1446 } 1447 1448 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1449 struct intel_crtc *crtc) 1450 { 1451 const struct intel_crtc_state *crtc_state = 1452 intel_atomic_get_new_crtc_state(state, crtc); 1453 const struct drm_connector_state *conn_state; 1454 struct drm_connector *conn; 1455 int i; 1456 1457 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1458 struct intel_encoder *encoder = 1459 to_intel_encoder(conn_state->best_encoder); 1460 1461 if (conn_state->crtc != &crtc->base) 1462 continue; 1463 1464 if (encoder->update_pipe) 1465 encoder->update_pipe(state, encoder, 1466 crtc_state, conn_state); 1467 } 1468 } 1469 1470 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1471 { 1472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1473 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1474 1475 if (crtc_state->has_pch_encoder) { 1476 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1477 &crtc_state->fdi_m_n); 1478 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1479 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1480 &crtc_state->dp_m_n); 1481 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1482 &crtc_state->dp_m2_n2); 1483 } 1484 1485 intel_set_transcoder_timings(crtc_state); 1486 1487 ilk_set_pipeconf(crtc_state); 1488 } 1489 1490 static void ilk_crtc_enable(struct intel_atomic_state *state, 1491 struct intel_crtc *crtc) 1492 { 1493 struct intel_display *display = to_intel_display(crtc); 1494 const struct intel_crtc_state *new_crtc_state = 1495 intel_atomic_get_new_crtc_state(state, crtc); 1496 enum pipe pipe = crtc->pipe; 1497 1498 if (drm_WARN_ON(display->drm, crtc->active)) 1499 return; 1500 1501 /* 1502 * Sometimes spurious CPU pipe underruns happen during FDI 1503 * training, at least with VGA+HDMI cloning. Suppress them. 1504 * 1505 * On ILK we get an occasional spurious CPU pipe underruns 1506 * between eDP port A enable and vdd enable. Also PCH port 1507 * enable seems to result in the occasional CPU pipe underrun. 1508 * 1509 * Spurious PCH underruns also occur during PCH enabling. 1510 */ 1511 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1512 intel_set_pch_fifo_underrun_reporting(display, pipe, false); 1513 1514 ilk_configure_cpu_transcoder(new_crtc_state); 1515 1516 intel_set_pipe_src_size(new_crtc_state); 1517 1518 crtc->active = true; 1519 1520 intel_encoders_pre_enable(state, crtc); 1521 1522 if (new_crtc_state->has_pch_encoder) { 1523 ilk_pch_pre_enable(state, crtc); 1524 } else { 1525 assert_fdi_tx_disabled(display, pipe); 1526 assert_fdi_rx_disabled(display, pipe); 1527 } 1528 1529 ilk_pfit_enable(new_crtc_state); 1530 1531 /* 1532 * On ILK+ LUT must be loaded before the pipe is running but with 1533 * clocks enabled 1534 */ 1535 intel_color_modeset(new_crtc_state); 1536 1537 intel_initial_watermarks(state, crtc); 1538 intel_enable_transcoder(new_crtc_state); 1539 1540 if (new_crtc_state->has_pch_encoder) 1541 ilk_pch_enable(state, crtc); 1542 1543 intel_crtc_vblank_on(new_crtc_state); 1544 1545 intel_encoders_enable(state, crtc); 1546 1547 if (HAS_PCH_CPT(display)) 1548 intel_wait_for_pipe_scanline_moving(crtc); 1549 1550 /* 1551 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1552 * And a second vblank wait is needed at least on ILK with 1553 * some interlaced HDMI modes. Let's do the double wait always 1554 * in case there are more corner cases we don't know about. 1555 */ 1556 if (new_crtc_state->has_pch_encoder) { 1557 intel_crtc_wait_for_next_vblank(crtc); 1558 intel_crtc_wait_for_next_vblank(crtc); 1559 } 1560 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 1561 intel_set_pch_fifo_underrun_reporting(display, pipe, true); 1562 } 1563 1564 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1565 static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state) 1566 { 1567 struct intel_display *display = to_intel_display(crtc_state); 1568 1569 return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled; 1570 } 1571 1572 static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable) 1573 { 1574 struct intel_display *display = to_intel_display(crtc); 1575 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1576 1577 intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe), 1578 mask, enable ? mask : 0); 1579 } 1580 1581 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1582 { 1583 struct intel_display *display = to_intel_display(crtc_state); 1584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1585 1586 intel_de_write(display, WM_LINETIME(crtc->pipe), 1587 HSW_LINETIME(crtc_state->linetime) | 1588 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1589 } 1590 1591 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1592 { 1593 struct intel_display *display = to_intel_display(crtc_state); 1594 1595 intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder), 1596 HSW_FRAME_START_DELAY_MASK, 1597 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1598 } 1599 1600 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1601 { 1602 struct intel_display *display = to_intel_display(crtc_state); 1603 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1604 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1605 1606 if (crtc_state->has_pch_encoder) { 1607 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1608 &crtc_state->fdi_m_n); 1609 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1610 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1611 &crtc_state->dp_m_n); 1612 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1613 &crtc_state->dp_m2_n2); 1614 } 1615 1616 intel_set_transcoder_timings(crtc_state); 1617 1618 if (cpu_transcoder != TRANSCODER_EDP) 1619 intel_de_write(display, TRANS_MULT(display, cpu_transcoder), 1620 crtc_state->pixel_multiplier - 1); 1621 1622 hsw_set_frame_start_delay(crtc_state); 1623 1624 hsw_set_transconf(crtc_state); 1625 } 1626 1627 static void hsw_crtc_enable(struct intel_atomic_state *state, 1628 struct intel_crtc *crtc) 1629 { 1630 struct intel_display *display = to_intel_display(state); 1631 const struct intel_crtc_state *new_crtc_state = 1632 intel_atomic_get_new_crtc_state(state, crtc); 1633 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1634 struct intel_crtc *pipe_crtc; 1635 int i; 1636 1637 if (drm_WARN_ON(display->drm, crtc->active)) 1638 return; 1639 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { 1640 const struct intel_crtc_state *new_pipe_crtc_state = 1641 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1642 1643 intel_dmc_enable_pipe(new_pipe_crtc_state); 1644 } 1645 1646 intel_encoders_pre_pll_enable(state, crtc); 1647 1648 if (new_crtc_state->intel_dpll) 1649 intel_dpll_enable(new_crtc_state); 1650 1651 intel_encoders_pre_enable(state, crtc); 1652 1653 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { 1654 const struct intel_crtc_state *pipe_crtc_state = 1655 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1656 1657 intel_dsc_enable(pipe_crtc_state); 1658 1659 if (HAS_UNCOMPRESSED_JOINER(display)) 1660 intel_uncompressed_joiner_enable(pipe_crtc_state); 1661 1662 intel_set_pipe_src_size(pipe_crtc_state); 1663 1664 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) 1665 bdw_set_pipe_misc(NULL, pipe_crtc_state); 1666 } 1667 1668 if (!transcoder_is_dsi(cpu_transcoder)) 1669 hsw_configure_cpu_transcoder(new_crtc_state); 1670 1671 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { 1672 const struct intel_crtc_state *pipe_crtc_state = 1673 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1674 1675 pipe_crtc->active = true; 1676 1677 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) 1678 glk_pipe_scaler_clock_gating_wa(pipe_crtc, true); 1679 1680 if (DISPLAY_VER(display) >= 9) 1681 skl_pfit_enable(pipe_crtc_state); 1682 else 1683 ilk_pfit_enable(pipe_crtc_state); 1684 1685 /* 1686 * On ILK+ LUT must be loaded before the pipe is running but with 1687 * clocks enabled 1688 */ 1689 intel_color_modeset(pipe_crtc_state); 1690 1691 hsw_set_linetime_wm(pipe_crtc_state); 1692 1693 if (DISPLAY_VER(display) >= 11) 1694 icl_set_pipe_chicken(pipe_crtc_state); 1695 1696 intel_initial_watermarks(state, pipe_crtc); 1697 } 1698 1699 intel_encoders_enable(state, crtc); 1700 1701 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { 1702 const struct intel_crtc_state *pipe_crtc_state = 1703 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1704 enum pipe hsw_workaround_pipe; 1705 1706 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) { 1707 intel_crtc_wait_for_next_vblank(pipe_crtc); 1708 glk_pipe_scaler_clock_gating_wa(pipe_crtc, false); 1709 } 1710 1711 /* 1712 * If we change the relative order between pipe/planes 1713 * enabling, we need to change the workaround. 1714 */ 1715 hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe; 1716 if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) { 1717 struct intel_crtc *wa_crtc = 1718 intel_crtc_for_pipe(display, hsw_workaround_pipe); 1719 1720 intel_crtc_wait_for_next_vblank(wa_crtc); 1721 intel_crtc_wait_for_next_vblank(wa_crtc); 1722 } 1723 } 1724 } 1725 1726 static void ilk_crtc_disable(struct intel_atomic_state *state, 1727 struct intel_crtc *crtc) 1728 { 1729 struct intel_display *display = to_intel_display(crtc); 1730 const struct intel_crtc_state *old_crtc_state = 1731 intel_atomic_get_old_crtc_state(state, crtc); 1732 enum pipe pipe = crtc->pipe; 1733 1734 /* 1735 * Sometimes spurious CPU pipe underruns happen when the 1736 * pipe is already disabled, but FDI RX/TX is still enabled. 1737 * Happens at least with VGA+HDMI cloning. Suppress them. 1738 */ 1739 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1740 intel_set_pch_fifo_underrun_reporting(display, pipe, false); 1741 1742 intel_encoders_disable(state, crtc); 1743 1744 intel_crtc_vblank_off(old_crtc_state); 1745 1746 intel_disable_transcoder(old_crtc_state); 1747 1748 ilk_pfit_disable(old_crtc_state); 1749 1750 if (old_crtc_state->has_pch_encoder) 1751 ilk_pch_disable(state, crtc); 1752 1753 intel_encoders_post_disable(state, crtc); 1754 1755 if (old_crtc_state->has_pch_encoder) 1756 ilk_pch_post_disable(state, crtc); 1757 1758 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 1759 intel_set_pch_fifo_underrun_reporting(display, pipe, true); 1760 } 1761 1762 static void hsw_crtc_disable(struct intel_atomic_state *state, 1763 struct intel_crtc *crtc) 1764 { 1765 struct intel_display *display = to_intel_display(state); 1766 const struct intel_crtc_state *old_crtc_state = 1767 intel_atomic_get_old_crtc_state(state, crtc); 1768 struct intel_crtc *pipe_crtc; 1769 int i; 1770 1771 /* 1772 * FIXME collapse everything to one hook. 1773 * Need care with mst->ddi interactions. 1774 */ 1775 intel_encoders_disable(state, crtc); 1776 intel_encoders_post_disable(state, crtc); 1777 1778 intel_dpll_disable(old_crtc_state); 1779 1780 intel_encoders_post_pll_disable(state, crtc); 1781 1782 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 1783 const struct intel_crtc_state *old_pipe_crtc_state = 1784 intel_atomic_get_old_crtc_state(state, pipe_crtc); 1785 1786 intel_dmc_disable_pipe(old_pipe_crtc_state); 1787 } 1788 } 1789 1790 /* Prefer intel_encoder_is_combo() */ 1791 bool intel_phy_is_combo(struct intel_display *display, enum phy phy) 1792 { 1793 if (phy == PHY_NONE) 1794 return false; 1795 else if (display->platform.alderlake_s) 1796 return phy <= PHY_E; 1797 else if (display->platform.dg1 || display->platform.rocketlake) 1798 return phy <= PHY_D; 1799 else if (display->platform.jasperlake || display->platform.elkhartlake) 1800 return phy <= PHY_C; 1801 else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12)) 1802 return phy <= PHY_B; 1803 else 1804 /* 1805 * DG2 outputs labelled as "combo PHY" in the bspec use 1806 * SNPS PHYs with completely different programming, 1807 * hence we always return false here. 1808 */ 1809 return false; 1810 } 1811 1812 /* 1813 * This function returns true if the DDI port respective to the PHY enumeration 1814 * is a Type-C capable port. 1815 * 1816 * Depending on the VBT, the port might be configured 1817 * as a "dedicated external" port, meaning that actual physical PHY is outside 1818 * of the Type-C subsystem and, as such, not really a "Type-C PHY". 1819 * 1820 * Prefer intel_encoder_is_tc(), especially if you really need to know if we 1821 * are dealing with Type-C connections. 1822 */ 1823 bool intel_phy_is_tc(struct intel_display *display, enum phy phy) 1824 { 1825 /* 1826 * Discrete GPU phy's are not attached to FIA's to support TC 1827 * subsystem Legacy or non-legacy, and only support native DP/HDMI 1828 */ 1829 if (display->platform.dgfx) 1830 return false; 1831 1832 if (DISPLAY_VER(display) >= 13) 1833 return phy >= PHY_F && phy <= PHY_I; 1834 else if (display->platform.tigerlake) 1835 return phy >= PHY_D && phy <= PHY_I; 1836 else if (display->platform.icelake) 1837 return phy >= PHY_C && phy <= PHY_F; 1838 1839 return false; 1840 } 1841 1842 /* Prefer intel_encoder_is_snps() */ 1843 bool intel_phy_is_snps(struct intel_display *display, enum phy phy) 1844 { 1845 /* 1846 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port 1847 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc(). 1848 */ 1849 return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E; 1850 } 1851 1852 /* Prefer intel_encoder_to_phy() */ 1853 enum phy intel_port_to_phy(struct intel_display *display, enum port port) 1854 { 1855 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) 1856 return PHY_D + port - PORT_D_XELPD; 1857 else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1) 1858 return PHY_F + port - PORT_TC1; 1859 else if (display->platform.alderlake_s && port >= PORT_TC1) 1860 return PHY_B + port - PORT_TC1; 1861 else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1) 1862 return PHY_C + port - PORT_TC1; 1863 else if ((display->platform.jasperlake || display->platform.elkhartlake) && 1864 port == PORT_D) 1865 return PHY_A; 1866 1867 return PHY_A + port - PORT_A; 1868 } 1869 1870 /* Prefer intel_encoder_to_tc() */ 1871 /* 1872 * Return TC_PORT_1..I915_MAX_TC_PORTS for any TypeC DDI port. The function 1873 * can be also called for TypeC DDI ports not connected to a TypeC PHY such as 1874 * the PORT_TC1..4 ports on RKL/ADLS/BMG. 1875 */ 1876 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port) 1877 { 1878 if (DISPLAY_VER(display) >= 12) 1879 return TC_PORT_1 + port - PORT_TC1; 1880 else 1881 return TC_PORT_1 + port - PORT_C; 1882 } 1883 1884 /* 1885 * Return TC_PORT_1..I915_MAX_TC_PORTS for TypeC DDI ports connected to a TypeC PHY. 1886 * Note that on RKL, ADLS, BMG the PORT_TC1..4 ports are connected to a non-TypeC 1887 * PHY, so on those platforms the function returns TC_PORT_NONE. 1888 */ 1889 enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port) 1890 { 1891 if (!intel_phy_is_tc(display, intel_port_to_phy(display, port))) 1892 return TC_PORT_NONE; 1893 1894 return intel_port_to_tc(display, port); 1895 } 1896 1897 enum phy intel_encoder_to_phy(struct intel_encoder *encoder) 1898 { 1899 struct intel_display *display = to_intel_display(encoder); 1900 1901 return intel_port_to_phy(display, encoder->port); 1902 } 1903 1904 bool intel_encoder_is_combo(struct intel_encoder *encoder) 1905 { 1906 struct intel_display *display = to_intel_display(encoder); 1907 1908 return intel_phy_is_combo(display, intel_encoder_to_phy(encoder)); 1909 } 1910 1911 bool intel_encoder_is_snps(struct intel_encoder *encoder) 1912 { 1913 struct intel_display *display = to_intel_display(encoder); 1914 1915 return intel_phy_is_snps(display, intel_encoder_to_phy(encoder)); 1916 } 1917 1918 bool intel_encoder_is_tc(struct intel_encoder *encoder) 1919 { 1920 struct intel_display *display = to_intel_display(encoder); 1921 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1922 1923 if (dig_port && dig_port->dedicated_external) 1924 return false; 1925 1926 return intel_phy_is_tc(display, intel_encoder_to_phy(encoder)); 1927 } 1928 1929 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder) 1930 { 1931 struct intel_display *display = to_intel_display(encoder); 1932 1933 return intel_tc_phy_port_to_tc(display, encoder->port); 1934 } 1935 1936 enum intel_display_power_domain 1937 intel_aux_power_domain(struct intel_digital_port *dig_port) 1938 { 1939 struct intel_display *display = to_intel_display(dig_port); 1940 1941 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 1942 return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch); 1943 1944 return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch); 1945 } 1946 1947 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1948 struct intel_power_domain_mask *mask) 1949 { 1950 struct intel_display *display = to_intel_display(crtc_state); 1951 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1952 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1953 struct drm_encoder *encoder; 1954 enum pipe pipe = crtc->pipe; 1955 1956 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 1957 1958 if (!crtc_state->hw.active) 1959 return; 1960 1961 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 1962 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 1963 if (crtc_state->pch_pfit.enabled || 1964 crtc_state->pch_pfit.force_thru) 1965 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 1966 1967 drm_for_each_encoder_mask(encoder, display->drm, 1968 crtc_state->uapi.encoder_mask) { 1969 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1970 1971 set_bit(intel_encoder->power_domain, mask->bits); 1972 } 1973 1974 if (HAS_DDI(display) && crtc_state->has_audio) 1975 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 1976 1977 if (crtc_state->intel_dpll) 1978 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 1979 1980 if (crtc_state->dsc.compression_enable) 1981 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 1982 } 1983 1984 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1985 struct intel_power_domain_mask *old_domains) 1986 { 1987 struct intel_display *display = to_intel_display(crtc_state); 1988 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1989 enum intel_display_power_domain domain; 1990 struct intel_power_domain_mask domains, new_domains; 1991 1992 get_crtc_power_domains(crtc_state, &domains); 1993 1994 bitmap_andnot(new_domains.bits, 1995 domains.bits, 1996 crtc->enabled_power_domains.mask.bits, 1997 POWER_DOMAIN_NUM); 1998 bitmap_andnot(old_domains->bits, 1999 crtc->enabled_power_domains.mask.bits, 2000 domains.bits, 2001 POWER_DOMAIN_NUM); 2002 2003 for_each_power_domain(domain, &new_domains) 2004 intel_display_power_get_in_set(display, 2005 &crtc->enabled_power_domains, 2006 domain); 2007 } 2008 2009 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2010 struct intel_power_domain_mask *domains) 2011 { 2012 struct intel_display *display = to_intel_display(crtc); 2013 2014 intel_display_power_put_mask_in_set(display, 2015 &crtc->enabled_power_domains, 2016 domains); 2017 } 2018 2019 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2020 { 2021 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2022 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2023 2024 if (intel_crtc_has_dp_encoder(crtc_state)) { 2025 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2026 &crtc_state->dp_m_n); 2027 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2028 &crtc_state->dp_m2_n2); 2029 } 2030 2031 intel_set_transcoder_timings(crtc_state); 2032 2033 i9xx_set_pipeconf(crtc_state); 2034 } 2035 2036 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2037 struct intel_crtc *crtc) 2038 { 2039 struct intel_display *display = to_intel_display(crtc); 2040 const struct intel_crtc_state *new_crtc_state = 2041 intel_atomic_get_new_crtc_state(state, crtc); 2042 enum pipe pipe = crtc->pipe; 2043 2044 if (drm_WARN_ON(display->drm, crtc->active)) 2045 return; 2046 2047 i9xx_configure_cpu_transcoder(new_crtc_state); 2048 2049 intel_set_pipe_src_size(new_crtc_state); 2050 2051 intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0); 2052 2053 if (display->platform.cherryview && pipe == PIPE_B) { 2054 intel_de_write(display, CHV_BLEND(display, pipe), 2055 CHV_BLEND_LEGACY); 2056 intel_de_write(display, CHV_CANVAS(display, pipe), 0); 2057 } 2058 2059 crtc->active = true; 2060 2061 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 2062 2063 intel_encoders_pre_pll_enable(state, crtc); 2064 2065 if (display->platform.cherryview) 2066 chv_enable_pll(new_crtc_state); 2067 else 2068 vlv_enable_pll(new_crtc_state); 2069 2070 intel_encoders_pre_enable(state, crtc); 2071 2072 i9xx_pfit_enable(new_crtc_state); 2073 2074 intel_color_modeset(new_crtc_state); 2075 2076 intel_initial_watermarks(state, crtc); 2077 intel_enable_transcoder(new_crtc_state); 2078 2079 intel_crtc_vblank_on(new_crtc_state); 2080 2081 intel_encoders_enable(state, crtc); 2082 } 2083 2084 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2085 struct intel_crtc *crtc) 2086 { 2087 struct intel_display *display = to_intel_display(crtc); 2088 const struct intel_crtc_state *new_crtc_state = 2089 intel_atomic_get_new_crtc_state(state, crtc); 2090 enum pipe pipe = crtc->pipe; 2091 2092 if (drm_WARN_ON(display->drm, crtc->active)) 2093 return; 2094 2095 i9xx_configure_cpu_transcoder(new_crtc_state); 2096 2097 intel_set_pipe_src_size(new_crtc_state); 2098 2099 crtc->active = true; 2100 2101 if (DISPLAY_VER(display) != 2) 2102 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 2103 2104 intel_encoders_pre_enable(state, crtc); 2105 2106 i9xx_enable_pll(new_crtc_state); 2107 2108 i9xx_pfit_enable(new_crtc_state); 2109 2110 intel_color_modeset(new_crtc_state); 2111 2112 if (!intel_initial_watermarks(state, crtc)) 2113 intel_update_watermarks(display); 2114 intel_enable_transcoder(new_crtc_state); 2115 2116 intel_crtc_vblank_on(new_crtc_state); 2117 2118 intel_encoders_enable(state, crtc); 2119 2120 /* prevents spurious underruns */ 2121 if (DISPLAY_VER(display) == 2) 2122 intel_crtc_wait_for_next_vblank(crtc); 2123 } 2124 2125 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2126 struct intel_crtc *crtc) 2127 { 2128 struct intel_display *display = to_intel_display(state); 2129 struct intel_crtc_state *old_crtc_state = 2130 intel_atomic_get_old_crtc_state(state, crtc); 2131 enum pipe pipe = crtc->pipe; 2132 2133 /* 2134 * On gen2 planes are double buffered but the pipe isn't, so we must 2135 * wait for planes to fully turn off before disabling the pipe. 2136 */ 2137 if (DISPLAY_VER(display) == 2) 2138 intel_crtc_wait_for_next_vblank(crtc); 2139 2140 intel_encoders_disable(state, crtc); 2141 2142 intel_crtc_vblank_off(old_crtc_state); 2143 2144 intel_disable_transcoder(old_crtc_state); 2145 2146 i9xx_pfit_disable(old_crtc_state); 2147 2148 intel_encoders_post_disable(state, crtc); 2149 2150 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2151 if (display->platform.cherryview) 2152 chv_disable_pll(display, pipe); 2153 else if (display->platform.valleyview) 2154 vlv_disable_pll(display, pipe); 2155 else 2156 i9xx_disable_pll(old_crtc_state); 2157 } 2158 2159 intel_encoders_post_pll_disable(state, crtc); 2160 2161 if (DISPLAY_VER(display) != 2) 2162 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 2163 2164 if (!display->funcs.wm->initial_watermarks) 2165 intel_update_watermarks(display); 2166 2167 /* clock the pipe down to 640x480@60 to potentially save power */ 2168 if (display->platform.i830) 2169 i830_enable_pipe(display, pipe); 2170 } 2171 2172 void intel_encoder_destroy(struct drm_encoder *encoder) 2173 { 2174 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2175 2176 drm_encoder_cleanup(encoder); 2177 kfree(intel_encoder); 2178 } 2179 2180 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2181 { 2182 struct intel_display *display = to_intel_display(crtc); 2183 2184 /* GDG double wide on either pipe, otherwise pipe A only */ 2185 return HAS_DOUBLE_WIDE(display) && 2186 (crtc->pipe == PIPE_A || display->platform.i915g); 2187 } 2188 2189 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2190 { 2191 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2192 struct drm_rect src; 2193 2194 /* 2195 * We only use IF-ID interlacing. If we ever use 2196 * PF-ID we'll need to adjust the pixel_rate here. 2197 */ 2198 2199 if (!crtc_state->pch_pfit.enabled) 2200 return pixel_rate; 2201 2202 drm_rect_init(&src, 0, 0, 2203 drm_rect_width(&crtc_state->pipe_src) << 16, 2204 drm_rect_height(&crtc_state->pipe_src) << 16); 2205 2206 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2207 pixel_rate); 2208 } 2209 2210 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2211 const struct drm_display_mode *timings) 2212 { 2213 mode->hdisplay = timings->crtc_hdisplay; 2214 mode->htotal = timings->crtc_htotal; 2215 mode->hsync_start = timings->crtc_hsync_start; 2216 mode->hsync_end = timings->crtc_hsync_end; 2217 2218 mode->vdisplay = timings->crtc_vdisplay; 2219 mode->vtotal = timings->crtc_vtotal; 2220 mode->vsync_start = timings->crtc_vsync_start; 2221 mode->vsync_end = timings->crtc_vsync_end; 2222 2223 mode->flags = timings->flags; 2224 mode->type = DRM_MODE_TYPE_DRIVER; 2225 2226 mode->clock = timings->crtc_clock; 2227 2228 drm_mode_set_name(mode); 2229 } 2230 2231 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2232 { 2233 struct intel_display *display = to_intel_display(crtc_state); 2234 2235 if (HAS_GMCH(display)) 2236 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2237 crtc_state->pixel_rate = 2238 crtc_state->hw.pipe_mode.crtc_clock; 2239 else 2240 crtc_state->pixel_rate = 2241 ilk_pipe_pixel_rate(crtc_state); 2242 } 2243 2244 static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2245 struct drm_display_mode *mode) 2246 { 2247 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2248 2249 if (num_pipes == 1) 2250 return; 2251 2252 mode->crtc_clock /= num_pipes; 2253 mode->crtc_hdisplay /= num_pipes; 2254 mode->crtc_hblank_start /= num_pipes; 2255 mode->crtc_hblank_end /= num_pipes; 2256 mode->crtc_hsync_start /= num_pipes; 2257 mode->crtc_hsync_end /= num_pipes; 2258 mode->crtc_htotal /= num_pipes; 2259 } 2260 2261 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2262 struct drm_display_mode *mode) 2263 { 2264 int overlap = crtc_state->splitter.pixel_overlap; 2265 int n = crtc_state->splitter.link_count; 2266 2267 if (!crtc_state->splitter.enable) 2268 return; 2269 2270 /* 2271 * eDP MSO uses segment timings from EDID for transcoder 2272 * timings, but full mode for everything else. 2273 * 2274 * h_full = (h_segment - pixel_overlap) * link_count 2275 */ 2276 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2277 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2278 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2279 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2280 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2281 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2282 mode->crtc_clock *= n; 2283 } 2284 2285 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2286 { 2287 struct drm_display_mode *mode = &crtc_state->hw.mode; 2288 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2289 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2290 2291 /* 2292 * Start with the adjusted_mode crtc timings, which 2293 * have been filled with the transcoder timings. 2294 */ 2295 drm_mode_copy(pipe_mode, adjusted_mode); 2296 2297 /* Expand MSO per-segment transcoder timings to full */ 2298 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2299 2300 /* 2301 * We want the full numbers in adjusted_mode normal timings, 2302 * adjusted_mode crtc timings are left with the raw transcoder 2303 * timings. 2304 */ 2305 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2306 2307 /* Populate the "user" mode with full numbers */ 2308 drm_mode_copy(mode, pipe_mode); 2309 intel_mode_from_crtc_timings(mode, mode); 2310 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2311 intel_crtc_num_joined_pipes(crtc_state); 2312 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2313 2314 /* Derive per-pipe timings in case joiner is used */ 2315 intel_joiner_adjust_timings(crtc_state, pipe_mode); 2316 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2317 2318 intel_crtc_compute_pixel_rate(crtc_state); 2319 } 2320 2321 void intel_encoder_get_config(struct intel_encoder *encoder, 2322 struct intel_crtc_state *crtc_state) 2323 { 2324 encoder->get_config(encoder, crtc_state); 2325 2326 intel_crtc_readout_derived_state(crtc_state); 2327 } 2328 2329 static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2330 { 2331 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2332 int width, height; 2333 2334 if (num_pipes == 1) 2335 return; 2336 2337 width = drm_rect_width(&crtc_state->pipe_src); 2338 height = drm_rect_height(&crtc_state->pipe_src); 2339 2340 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2341 width / num_pipes, height); 2342 } 2343 2344 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2345 { 2346 struct intel_display *display = to_intel_display(crtc_state); 2347 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2348 2349 intel_joiner_compute_pipe_src(crtc_state); 2350 2351 /* 2352 * Pipe horizontal size must be even in: 2353 * - DVO ganged mode 2354 * - LVDS dual channel mode 2355 * - Double wide pipe 2356 */ 2357 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2358 if (crtc_state->double_wide) { 2359 drm_dbg_kms(display->drm, 2360 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2361 crtc->base.base.id, crtc->base.name); 2362 return -EINVAL; 2363 } 2364 2365 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2366 intel_is_dual_link_lvds(display)) { 2367 drm_dbg_kms(display->drm, 2368 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2369 crtc->base.base.id, crtc->base.name); 2370 return -EINVAL; 2371 } 2372 } 2373 2374 return 0; 2375 } 2376 2377 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2378 { 2379 struct intel_display *display = to_intel_display(crtc_state); 2380 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2381 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2382 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2383 int clock_limit = display->cdclk.max_dotclk_freq; 2384 2385 /* 2386 * Start with the adjusted_mode crtc timings, which 2387 * have been filled with the transcoder timings. 2388 */ 2389 drm_mode_copy(pipe_mode, adjusted_mode); 2390 2391 /* Expand MSO per-segment transcoder timings to full */ 2392 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2393 2394 /* Derive per-pipe timings in case joiner is used */ 2395 intel_joiner_adjust_timings(crtc_state, pipe_mode); 2396 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2397 2398 if (DISPLAY_VER(display) < 4) { 2399 clock_limit = display->cdclk.max_cdclk_freq * 9 / 10; 2400 2401 /* 2402 * Enable double wide mode when the dot clock 2403 * is > 90% of the (display) core speed. 2404 */ 2405 if (intel_crtc_supports_double_wide(crtc) && 2406 pipe_mode->crtc_clock > clock_limit) { 2407 clock_limit = display->cdclk.max_dotclk_freq; 2408 crtc_state->double_wide = true; 2409 } 2410 } 2411 2412 if (pipe_mode->crtc_clock > clock_limit) { 2413 drm_dbg_kms(display->drm, 2414 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2415 crtc->base.base.id, crtc->base.name, 2416 pipe_mode->crtc_clock, clock_limit, 2417 str_yes_no(crtc_state->double_wide)); 2418 return -EINVAL; 2419 } 2420 2421 return 0; 2422 } 2423 2424 static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state) 2425 { 2426 struct intel_display *display = to_intel_display(crtc_state); 2427 int set_context_latency = 0; 2428 2429 if (!HAS_DSB(display)) 2430 return 0; 2431 2432 set_context_latency = max(set_context_latency, 2433 intel_psr_min_set_context_latency(crtc_state)); 2434 2435 return set_context_latency; 2436 } 2437 2438 static int intel_crtc_compute_set_context_latency(struct intel_atomic_state *state, 2439 struct intel_crtc *crtc) 2440 { 2441 struct intel_display *display = to_intel_display(state); 2442 struct intel_crtc_state *crtc_state = 2443 intel_atomic_get_new_crtc_state(state, crtc); 2444 struct drm_display_mode *adjusted_mode = 2445 &crtc_state->hw.adjusted_mode; 2446 int set_context_latency, max_vblank_delay; 2447 2448 set_context_latency = intel_crtc_set_context_latency(crtc_state); 2449 2450 max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1; 2451 2452 if (set_context_latency > max_vblank_delay) { 2453 drm_dbg_kms(display->drm, "[CRTC:%d:%s] set context latency (%d) exceeds max (%d)\n", 2454 crtc->base.base.id, crtc->base.name, 2455 set_context_latency, 2456 max_vblank_delay); 2457 return -EINVAL; 2458 } 2459 2460 crtc_state->set_context_latency = set_context_latency; 2461 adjusted_mode->crtc_vblank_start += set_context_latency; 2462 2463 return 0; 2464 } 2465 2466 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2467 struct intel_crtc *crtc) 2468 { 2469 struct intel_crtc_state *crtc_state = 2470 intel_atomic_get_new_crtc_state(state, crtc); 2471 int ret; 2472 2473 ret = intel_dpll_crtc_compute_clock(state, crtc); 2474 if (ret) 2475 return ret; 2476 2477 ret = intel_crtc_compute_set_context_latency(state, crtc); 2478 if (ret) 2479 return ret; 2480 2481 ret = intel_crtc_compute_pipe_src(crtc_state); 2482 if (ret) 2483 return ret; 2484 2485 ret = intel_crtc_compute_pipe_mode(crtc_state); 2486 if (ret) 2487 return ret; 2488 2489 intel_crtc_compute_pixel_rate(crtc_state); 2490 2491 if (crtc_state->has_pch_encoder) 2492 return ilk_fdi_compute_config(crtc, crtc_state); 2493 2494 intel_vrr_compute_guardband(crtc_state); 2495 2496 return 0; 2497 } 2498 2499 static void 2500 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2501 { 2502 while (*num > DATA_LINK_M_N_MASK || 2503 *den > DATA_LINK_M_N_MASK) { 2504 *num >>= 1; 2505 *den >>= 1; 2506 } 2507 } 2508 2509 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2510 u32 m, u32 n, u32 constant_n) 2511 { 2512 if (constant_n) 2513 *ret_n = constant_n; 2514 else 2515 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2516 2517 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2518 intel_reduce_m_n_ratio(ret_m, ret_n); 2519 } 2520 2521 void 2522 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, 2523 int pixel_clock, int link_clock, 2524 int bw_overhead, 2525 struct intel_link_m_n *m_n) 2526 { 2527 u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock); 2528 u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16, 2529 bw_overhead); 2530 u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes); 2531 2532 /* 2533 * Windows/BIOS uses fixed M/N values always. Follow suit. 2534 * 2535 * Also several DP dongles in particular seem to be fussy 2536 * about too large link M/N values. Presumably the 20bit 2537 * value used by Windows/BIOS is acceptable to everyone. 2538 */ 2539 m_n->tu = 64; 2540 compute_m_n(&m_n->data_m, &m_n->data_n, 2541 data_m, data_n, 2542 0x8000000); 2543 2544 compute_m_n(&m_n->link_m, &m_n->link_n, 2545 pixel_clock, link_symbol_clock, 2546 0x80000); 2547 } 2548 2549 void intel_panel_sanitize_ssc(struct intel_display *display) 2550 { 2551 /* 2552 * There may be no VBT; and if the BIOS enabled SSC we can 2553 * just keep using it to avoid unnecessary flicker. Whereas if the 2554 * BIOS isn't using it, don't assume it will work even if the VBT 2555 * indicates as much. 2556 */ 2557 if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) { 2558 bool bios_lvds_use_ssc = intel_de_read(display, 2559 PCH_DREF_CONTROL) & 2560 DREF_SSC1_ENABLE; 2561 2562 if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2563 drm_dbg_kms(display->drm, 2564 "SSC %s by BIOS, overriding VBT which says %s\n", 2565 str_enabled_disabled(bios_lvds_use_ssc), 2566 str_enabled_disabled(display->vbt.lvds_use_ssc)); 2567 display->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2568 } 2569 } 2570 } 2571 2572 void intel_zero_m_n(struct intel_link_m_n *m_n) 2573 { 2574 /* corresponds to 0 register value */ 2575 memset(m_n, 0, sizeof(*m_n)); 2576 m_n->tu = 1; 2577 } 2578 2579 void intel_set_m_n(struct intel_display *display, 2580 const struct intel_link_m_n *m_n, 2581 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2582 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2583 { 2584 intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2585 intel_de_write(display, data_n_reg, m_n->data_n); 2586 intel_de_write(display, link_m_reg, m_n->link_m); 2587 /* 2588 * On BDW+ writing LINK_N arms the double buffered update 2589 * of all the M/N registers, so it must be written last. 2590 */ 2591 intel_de_write(display, link_n_reg, m_n->link_n); 2592 } 2593 2594 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, 2595 enum transcoder transcoder) 2596 { 2597 if (display->platform.haswell) 2598 return transcoder == TRANSCODER_EDP; 2599 2600 return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview; 2601 } 2602 2603 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2604 enum transcoder transcoder, 2605 const struct intel_link_m_n *m_n) 2606 { 2607 struct intel_display *display = to_intel_display(crtc); 2608 enum pipe pipe = crtc->pipe; 2609 2610 if (DISPLAY_VER(display) >= 5) 2611 intel_set_m_n(display, m_n, 2612 PIPE_DATA_M1(display, transcoder), 2613 PIPE_DATA_N1(display, transcoder), 2614 PIPE_LINK_M1(display, transcoder), 2615 PIPE_LINK_N1(display, transcoder)); 2616 else 2617 intel_set_m_n(display, m_n, 2618 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2619 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2620 } 2621 2622 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2623 enum transcoder transcoder, 2624 const struct intel_link_m_n *m_n) 2625 { 2626 struct intel_display *display = to_intel_display(crtc); 2627 2628 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) 2629 return; 2630 2631 intel_set_m_n(display, m_n, 2632 PIPE_DATA_M2(display, transcoder), 2633 PIPE_DATA_N2(display, transcoder), 2634 PIPE_LINK_M2(display, transcoder), 2635 PIPE_LINK_N2(display, transcoder)); 2636 } 2637 2638 static bool 2639 transcoder_has_vrr(const struct intel_crtc_state *crtc_state) 2640 { 2641 struct intel_display *display = to_intel_display(crtc_state); 2642 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2643 2644 return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder); 2645 } 2646 2647 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2648 { 2649 struct intel_display *display = to_intel_display(crtc_state); 2650 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2651 enum pipe pipe = crtc->pipe; 2652 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2653 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2654 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2655 int vsyncshift = 0; 2656 2657 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 2658 2659 /* We need to be careful not to changed the adjusted mode, for otherwise 2660 * the hw state checker will get angry at the mismatch. */ 2661 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2662 crtc_vtotal = adjusted_mode->crtc_vtotal; 2663 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2664 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2665 2666 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2667 /* the chip adds 2 halflines automatically */ 2668 crtc_vtotal -= 1; 2669 crtc_vblank_end -= 1; 2670 2671 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2672 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2673 else 2674 vsyncshift = adjusted_mode->crtc_hsync_start - 2675 adjusted_mode->crtc_htotal / 2; 2676 if (vsyncshift < 0) 2677 vsyncshift += adjusted_mode->crtc_htotal; 2678 } 2679 2680 /* 2681 * VBLANK_START no longer works on ADL+, instead we must use 2682 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2683 */ 2684 if (DISPLAY_VER(display) >= 13) { 2685 intel_de_write(display, 2686 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder), 2687 crtc_state->set_context_latency); 2688 2689 /* 2690 * VBLANK_START not used by hw, just clear it 2691 * to make it stand out in register dumps. 2692 */ 2693 crtc_vblank_start = 1; 2694 } else if (DISPLAY_VER(display) == 12) { 2695 /* VBLANK_START - VACTIVE defines SCL on TGL */ 2696 crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency; 2697 } 2698 2699 if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35) 2700 intel_de_write(display, 2701 TRANS_VSYNCSHIFT(display, cpu_transcoder), 2702 vsyncshift); 2703 2704 intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), 2705 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2706 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2707 intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), 2708 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2709 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2710 intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), 2711 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2712 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2713 2714 /* 2715 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal 2716 * bits are not required. Since the support for these bits is going to 2717 * be deprecated in upcoming platforms, avoid writing these bits for the 2718 * platforms that do not use legacy Timing Generator. 2719 */ 2720 if (intel_vrr_always_use_vrr_tg(display)) 2721 crtc_vtotal = 1; 2722 2723 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), 2724 VACTIVE(crtc_vdisplay - 1) | 2725 VTOTAL(crtc_vtotal - 1)); 2726 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), 2727 VBLANK_START(crtc_vblank_start - 1) | 2728 VBLANK_END(crtc_vblank_end - 1)); 2729 intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), 2730 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2731 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2732 2733 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2734 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2735 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2736 * bits. */ 2737 if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP && 2738 (pipe == PIPE_B || pipe == PIPE_C)) 2739 intel_de_write(display, TRANS_VTOTAL(display, pipe), 2740 VACTIVE(crtc_vdisplay - 1) | 2741 VTOTAL(crtc_vtotal - 1)); 2742 2743 if (DISPLAY_VER(display) >= 30) { 2744 /* 2745 * Address issues for resolutions with high refresh rate that 2746 * have small Hblank, specifically where Hblank is smaller than 2747 * one MTP. Simulations indicate this will address the 2748 * jitter issues that currently causes BS to be immediately 2749 * followed by BE which DPRX devices are unable to handle. 2750 * https://groups.vesa.org/wg/DP/document/20494 2751 */ 2752 intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder), 2753 crtc_state->min_hblank); 2754 } 2755 } 2756 2757 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state) 2758 { 2759 struct intel_display *display = to_intel_display(crtc_state); 2760 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2761 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2762 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2763 2764 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 2765 2766 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2767 crtc_vtotal = adjusted_mode->crtc_vtotal; 2768 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2769 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2770 2771 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2772 /* the chip adds 2 halflines automatically */ 2773 crtc_vtotal -= 1; 2774 crtc_vblank_end -= 1; 2775 } 2776 2777 if (DISPLAY_VER(display) >= 13) { 2778 intel_de_write(display, 2779 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder), 2780 crtc_state->set_context_latency); 2781 2782 /* 2783 * VBLANK_START not used by hw, just clear it 2784 * to make it stand out in register dumps. 2785 */ 2786 crtc_vblank_start = 1; 2787 } else if (DISPLAY_VER(display) == 12) { 2788 /* VBLANK_START - VACTIVE defines SCL on TGL */ 2789 crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency; 2790 } 2791 2792 /* 2793 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode. 2794 * But let's write it anyway to keep the state checker happy. 2795 */ 2796 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), 2797 VBLANK_START(crtc_vblank_start - 1) | 2798 VBLANK_END(crtc_vblank_end - 1)); 2799 /* 2800 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal 2801 * bits are not required. Since the support for these bits is going to 2802 * be deprecated in upcoming platforms, avoid writing these bits for the 2803 * platforms that do not use legacy Timing Generator. 2804 */ 2805 if (intel_vrr_always_use_vrr_tg(display)) 2806 crtc_vtotal = 1; 2807 2808 /* 2809 * The double buffer latch point for TRANS_VTOTAL 2810 * is the transcoder's undelayed vblank. 2811 */ 2812 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), 2813 VACTIVE(crtc_vdisplay - 1) | 2814 VTOTAL(crtc_vtotal - 1)); 2815 2816 intel_vrr_set_fixed_rr_timings(crtc_state); 2817 intel_vrr_transcoder_enable(crtc_state); 2818 } 2819 2820 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2821 { 2822 struct intel_display *display = to_intel_display(crtc_state); 2823 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2824 int width = drm_rect_width(&crtc_state->pipe_src); 2825 int height = drm_rect_height(&crtc_state->pipe_src); 2826 enum pipe pipe = crtc->pipe; 2827 2828 /* pipesrc controls the size that is scaled from, which should 2829 * always be the user's requested size. 2830 */ 2831 intel_de_write(display, PIPESRC(display, pipe), 2832 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2833 } 2834 2835 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2836 { 2837 struct intel_display *display = to_intel_display(crtc_state); 2838 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2839 2840 if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35) 2841 return false; 2842 2843 if (DISPLAY_VER(display) >= 9 || 2844 display->platform.broadwell || display->platform.haswell) 2845 return intel_de_read(display, 2846 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2847 else 2848 return intel_de_read(display, 2849 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2850 } 2851 2852 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2853 struct intel_crtc_state *pipe_config) 2854 { 2855 struct intel_display *display = to_intel_display(crtc); 2856 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2857 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2858 u32 tmp; 2859 2860 tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)); 2861 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2862 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2863 2864 if (!transcoder_is_dsi(cpu_transcoder)) { 2865 tmp = intel_de_read(display, 2866 TRANS_HBLANK(display, cpu_transcoder)); 2867 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2868 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2869 } 2870 2871 tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)); 2872 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2873 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2874 2875 tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)); 2876 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2877 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2878 2879 /* FIXME TGL+ DSI transcoders have this! */ 2880 if (!transcoder_is_dsi(cpu_transcoder)) { 2881 tmp = intel_de_read(display, 2882 TRANS_VBLANK(display, cpu_transcoder)); 2883 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2884 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2885 } 2886 tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)); 2887 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2888 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2889 2890 if (intel_pipe_is_interlaced(pipe_config)) { 2891 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2892 adjusted_mode->crtc_vtotal += 1; 2893 adjusted_mode->crtc_vblank_end += 1; 2894 } 2895 2896 if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) { 2897 pipe_config->set_context_latency = 2898 intel_de_read(display, 2899 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)); 2900 adjusted_mode->crtc_vblank_start = 2901 adjusted_mode->crtc_vdisplay + 2902 pipe_config->set_context_latency; 2903 } else if (DISPLAY_VER(display) == 12) { 2904 /* 2905 * TGL doesn't have a dedicated register for SCL. 2906 * Instead, the hardware derives SCL from the difference between 2907 * TRANS_VBLANK.vblank_start and TRANS_VTOTAL.vactive. 2908 * To reflect the HW behaviour, readout the value for SCL as 2909 * Vblank start - Vactive. 2910 */ 2911 pipe_config->set_context_latency = 2912 adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; 2913 } 2914 2915 if (DISPLAY_VER(display) >= 30) 2916 pipe_config->min_hblank = intel_de_read(display, 2917 DP_MIN_HBLANK_CTL(cpu_transcoder)); 2918 } 2919 2920 static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2921 { 2922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2923 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2924 enum pipe primary_pipe, pipe = crtc->pipe; 2925 int width; 2926 2927 if (num_pipes == 1) 2928 return; 2929 2930 primary_pipe = joiner_primary_pipe(crtc_state); 2931 width = drm_rect_width(&crtc_state->pipe_src); 2932 2933 drm_rect_translate_to(&crtc_state->pipe_src, 2934 (pipe - primary_pipe) * width, 0); 2935 } 2936 2937 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2938 struct intel_crtc_state *pipe_config) 2939 { 2940 struct intel_display *display = to_intel_display(crtc); 2941 u32 tmp; 2942 2943 tmp = intel_de_read(display, PIPESRC(display, crtc->pipe)); 2944 2945 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2946 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2947 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2948 2949 intel_joiner_adjust_pipe_src(pipe_config); 2950 } 2951 2952 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2953 { 2954 struct intel_display *display = to_intel_display(crtc_state); 2955 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2956 u32 val = 0; 2957 2958 /* 2959 * - We keep both pipes enabled on 830 2960 * - During modeset the pipe is still disabled and must remain so 2961 * - During fastset the pipe is already enabled and must remain so 2962 */ 2963 if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state)) 2964 val |= TRANSCONF_ENABLE; 2965 2966 if (crtc_state->double_wide) 2967 val |= TRANSCONF_DOUBLE_WIDE; 2968 2969 /* only g4x and later have fancy bpc/dither controls */ 2970 if (display->platform.g4x || display->platform.valleyview || 2971 display->platform.cherryview) { 2972 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2973 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2974 val |= TRANSCONF_DITHER_EN | 2975 TRANSCONF_DITHER_TYPE_SP; 2976 2977 switch (crtc_state->pipe_bpp) { 2978 default: 2979 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2980 MISSING_CASE(crtc_state->pipe_bpp); 2981 fallthrough; 2982 case 18: 2983 val |= TRANSCONF_BPC_6; 2984 break; 2985 case 24: 2986 val |= TRANSCONF_BPC_8; 2987 break; 2988 case 30: 2989 val |= TRANSCONF_BPC_10; 2990 break; 2991 } 2992 } 2993 2994 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2995 if (DISPLAY_VER(display) < 4 || 2996 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2997 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2998 else 2999 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 3000 } else { 3001 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 3002 } 3003 3004 if ((display->platform.valleyview || display->platform.cherryview) && 3005 crtc_state->limited_color_range) 3006 val |= TRANSCONF_COLOR_RANGE_SELECT; 3007 3008 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3009 3010 if (crtc_state->wgc_enable) 3011 val |= TRANSCONF_WGC_ENABLE; 3012 3013 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3014 3015 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3016 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3017 } 3018 3019 static enum intel_output_format 3020 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 3021 { 3022 struct intel_display *display = to_intel_display(crtc); 3023 u32 tmp; 3024 3025 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); 3026 3027 if (tmp & PIPE_MISC_YUV420_ENABLE) { 3028 /* 3029 * We support 4:2:0 in full blend mode only. 3030 * For xe3_lpd+ this is implied in YUV420 Enable bit. 3031 * Ensure the same for prior platforms in YUV420 Mode bit. 3032 */ 3033 if (DISPLAY_VER(display) < 30) 3034 drm_WARN_ON(display->drm, 3035 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 3036 3037 return INTEL_OUTPUT_FORMAT_YCBCR420; 3038 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 3039 return INTEL_OUTPUT_FORMAT_YCBCR444; 3040 } else { 3041 return INTEL_OUTPUT_FORMAT_RGB; 3042 } 3043 } 3044 3045 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3046 struct intel_crtc_state *pipe_config) 3047 { 3048 struct intel_display *display = to_intel_display(crtc); 3049 enum intel_display_power_domain power_domain; 3050 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; 3051 struct ref_tracker *wakeref; 3052 bool ret = false; 3053 u32 tmp; 3054 3055 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3056 wakeref = intel_display_power_get_if_enabled(display, power_domain); 3057 if (!wakeref) 3058 return false; 3059 3060 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 3061 if (!(tmp & TRANSCONF_ENABLE)) 3062 goto out; 3063 3064 pipe_config->cpu_transcoder = cpu_transcoder; 3065 3066 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3067 pipe_config->sink_format = pipe_config->output_format; 3068 3069 if (display->platform.g4x || display->platform.valleyview || 3070 display->platform.cherryview) { 3071 switch (tmp & TRANSCONF_BPC_MASK) { 3072 case TRANSCONF_BPC_6: 3073 pipe_config->pipe_bpp = 18; 3074 break; 3075 case TRANSCONF_BPC_8: 3076 pipe_config->pipe_bpp = 24; 3077 break; 3078 case TRANSCONF_BPC_10: 3079 pipe_config->pipe_bpp = 30; 3080 break; 3081 default: 3082 MISSING_CASE(tmp); 3083 break; 3084 } 3085 } 3086 3087 if ((display->platform.valleyview || display->platform.cherryview) && 3088 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 3089 pipe_config->limited_color_range = true; 3090 3091 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 3092 3093 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3094 3095 if ((display->platform.valleyview || display->platform.cherryview) && 3096 (tmp & TRANSCONF_WGC_ENABLE)) 3097 pipe_config->wgc_enable = true; 3098 3099 intel_color_get_config(pipe_config); 3100 3101 if (HAS_DOUBLE_WIDE(display)) 3102 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 3103 3104 intel_get_transcoder_timings(crtc, pipe_config); 3105 intel_get_pipe_src_size(crtc, pipe_config); 3106 3107 i9xx_pfit_get_config(pipe_config); 3108 3109 i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state); 3110 3111 if (DISPLAY_VER(display) >= 4) { 3112 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md; 3113 pipe_config->pixel_multiplier = 3114 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3115 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3116 } else if (display->platform.i945g || display->platform.i945gm || 3117 display->platform.g33 || display->platform.pineview) { 3118 tmp = pipe_config->dpll_hw_state.i9xx.dpll; 3119 pipe_config->pixel_multiplier = 3120 ((tmp & SDVO_MULTIPLIER_MASK) 3121 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3122 } else { 3123 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3124 * port and will be fixed up in the encoder->get_config 3125 * function. */ 3126 pipe_config->pixel_multiplier = 1; 3127 } 3128 3129 if (display->platform.cherryview) 3130 chv_crtc_clock_get(pipe_config); 3131 else if (display->platform.valleyview) 3132 vlv_crtc_clock_get(pipe_config); 3133 else 3134 i9xx_crtc_clock_get(pipe_config); 3135 3136 /* 3137 * Normally the dotclock is filled in by the encoder .get_config() 3138 * but in case the pipe is enabled w/o any ports we need a sane 3139 * default. 3140 */ 3141 pipe_config->hw.adjusted_mode.crtc_clock = 3142 pipe_config->port_clock / pipe_config->pixel_multiplier; 3143 3144 ret = true; 3145 3146 out: 3147 intel_display_power_put(display, power_domain, wakeref); 3148 3149 return ret; 3150 } 3151 3152 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3153 { 3154 struct intel_display *display = to_intel_display(crtc_state); 3155 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3156 u32 val = 0; 3157 3158 /* 3159 * - During modeset the pipe is still disabled and must remain so 3160 * - During fastset the pipe is already enabled and must remain so 3161 */ 3162 if (!intel_crtc_needs_modeset(crtc_state)) 3163 val |= TRANSCONF_ENABLE; 3164 3165 switch (crtc_state->pipe_bpp) { 3166 default: 3167 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3168 MISSING_CASE(crtc_state->pipe_bpp); 3169 fallthrough; 3170 case 18: 3171 val |= TRANSCONF_BPC_6; 3172 break; 3173 case 24: 3174 val |= TRANSCONF_BPC_8; 3175 break; 3176 case 30: 3177 val |= TRANSCONF_BPC_10; 3178 break; 3179 case 36: 3180 val |= TRANSCONF_BPC_12; 3181 break; 3182 } 3183 3184 if (crtc_state->dither) 3185 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3186 3187 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3188 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3189 else 3190 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3191 3192 /* 3193 * This would end up with an odd purple hue over 3194 * the entire display. Make sure we don't do it. 3195 */ 3196 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 3197 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3198 3199 if (crtc_state->limited_color_range && 3200 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3201 val |= TRANSCONF_COLOR_RANGE_SELECT; 3202 3203 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3204 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3205 3206 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3207 3208 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3209 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3210 3211 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3212 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3213 } 3214 3215 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3216 { 3217 struct intel_display *display = to_intel_display(crtc_state); 3218 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3219 u32 val = 0; 3220 3221 /* 3222 * - During modeset the pipe is still disabled and must remain so 3223 * - During fastset the pipe is already enabled and must remain so 3224 */ 3225 if (!intel_crtc_needs_modeset(crtc_state)) 3226 val |= TRANSCONF_ENABLE; 3227 3228 if (display->platform.haswell && crtc_state->dither) 3229 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3230 3231 if (DISPLAY_VER(display) < 35) { 3232 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3233 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3234 else 3235 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3236 } 3237 3238 if (display->platform.haswell && 3239 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3240 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3241 3242 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3243 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3244 } 3245 3246 static void bdw_set_pipe_misc(struct intel_dsb *dsb, 3247 const struct intel_crtc_state *crtc_state) 3248 { 3249 struct intel_display *display = to_intel_display(crtc_state); 3250 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3251 u32 val = 0; 3252 3253 switch (crtc_state->pipe_bpp) { 3254 case 18: 3255 val |= PIPE_MISC_BPC_6; 3256 break; 3257 case 24: 3258 val |= PIPE_MISC_BPC_8; 3259 break; 3260 case 30: 3261 val |= PIPE_MISC_BPC_10; 3262 break; 3263 case 36: 3264 /* Port output 12BPC defined for ADLP+ */ 3265 if (DISPLAY_VER(display) >= 13) 3266 val |= PIPE_MISC_BPC_12_ADLP; 3267 break; 3268 default: 3269 MISSING_CASE(crtc_state->pipe_bpp); 3270 break; 3271 } 3272 3273 if (crtc_state->dither) 3274 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3275 3276 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3277 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3278 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3279 3280 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3281 val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE : 3282 PIPE_MISC_YUV420_ENABLE | PIPE_MISC_YUV420_MODE_FULL_BLEND; 3283 3284 if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state)) 3285 val |= PIPE_MISC_HDR_MODE_PRECISION; 3286 3287 if (DISPLAY_VER(display) >= 12) 3288 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3289 3290 /* allow PSR with sprite enabled */ 3291 if (display->platform.broadwell) 3292 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE; 3293 3294 intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val); 3295 } 3296 3297 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3298 { 3299 struct intel_display *display = to_intel_display(crtc); 3300 u32 tmp; 3301 3302 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); 3303 3304 switch (tmp & PIPE_MISC_BPC_MASK) { 3305 case PIPE_MISC_BPC_6: 3306 return 18; 3307 case PIPE_MISC_BPC_8: 3308 return 24; 3309 case PIPE_MISC_BPC_10: 3310 return 30; 3311 /* 3312 * PORT OUTPUT 12 BPC defined for ADLP+. 3313 * 3314 * TODO: 3315 * For previous platforms with DSI interface, bits 5:7 3316 * are used for storing pipe_bpp irrespective of dithering. 3317 * Since the value of 12 BPC is not defined for these bits 3318 * on older platforms, need to find a workaround for 12 BPC 3319 * MIPI DSI HW readout. 3320 */ 3321 case PIPE_MISC_BPC_12_ADLP: 3322 if (DISPLAY_VER(display) >= 13) 3323 return 36; 3324 fallthrough; 3325 default: 3326 MISSING_CASE(tmp); 3327 return 0; 3328 } 3329 } 3330 3331 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3332 { 3333 /* 3334 * Account for spread spectrum to avoid 3335 * oversubscribing the link. Max center spread 3336 * is 2.5%; use 5% for safety's sake. 3337 */ 3338 u32 bps = target_clock * bpp * 21 / 20; 3339 return DIV_ROUND_UP(bps, link_bw * 8); 3340 } 3341 3342 void intel_get_m_n(struct intel_display *display, 3343 struct intel_link_m_n *m_n, 3344 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3345 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3346 { 3347 m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK; 3348 m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK; 3349 m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK; 3350 m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK; 3351 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1; 3352 } 3353 3354 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3355 enum transcoder transcoder, 3356 struct intel_link_m_n *m_n) 3357 { 3358 struct intel_display *display = to_intel_display(crtc); 3359 enum pipe pipe = crtc->pipe; 3360 3361 if (DISPLAY_VER(display) >= 5) 3362 intel_get_m_n(display, m_n, 3363 PIPE_DATA_M1(display, transcoder), 3364 PIPE_DATA_N1(display, transcoder), 3365 PIPE_LINK_M1(display, transcoder), 3366 PIPE_LINK_N1(display, transcoder)); 3367 else 3368 intel_get_m_n(display, m_n, 3369 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3370 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3371 } 3372 3373 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3374 enum transcoder transcoder, 3375 struct intel_link_m_n *m_n) 3376 { 3377 struct intel_display *display = to_intel_display(crtc); 3378 3379 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) 3380 return; 3381 3382 intel_get_m_n(display, m_n, 3383 PIPE_DATA_M2(display, transcoder), 3384 PIPE_DATA_N2(display, transcoder), 3385 PIPE_LINK_M2(display, transcoder), 3386 PIPE_LINK_N2(display, transcoder)); 3387 } 3388 3389 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3390 struct intel_crtc_state *pipe_config) 3391 { 3392 struct intel_display *display = to_intel_display(crtc); 3393 enum intel_display_power_domain power_domain; 3394 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; 3395 struct ref_tracker *wakeref; 3396 bool ret = false; 3397 u32 tmp; 3398 3399 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3400 wakeref = intel_display_power_get_if_enabled(display, power_domain); 3401 if (!wakeref) 3402 return false; 3403 3404 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 3405 if (!(tmp & TRANSCONF_ENABLE)) 3406 goto out; 3407 3408 pipe_config->cpu_transcoder = cpu_transcoder; 3409 3410 switch (tmp & TRANSCONF_BPC_MASK) { 3411 case TRANSCONF_BPC_6: 3412 pipe_config->pipe_bpp = 18; 3413 break; 3414 case TRANSCONF_BPC_8: 3415 pipe_config->pipe_bpp = 24; 3416 break; 3417 case TRANSCONF_BPC_10: 3418 pipe_config->pipe_bpp = 30; 3419 break; 3420 case TRANSCONF_BPC_12: 3421 pipe_config->pipe_bpp = 36; 3422 break; 3423 default: 3424 break; 3425 } 3426 3427 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3428 pipe_config->limited_color_range = true; 3429 3430 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3431 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3432 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3433 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3434 break; 3435 default: 3436 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3437 break; 3438 } 3439 3440 pipe_config->sink_format = pipe_config->output_format; 3441 3442 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3443 3444 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3445 3446 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3447 3448 intel_color_get_config(pipe_config); 3449 3450 pipe_config->pixel_multiplier = 1; 3451 3452 ilk_pch_get_config(pipe_config); 3453 3454 intel_get_transcoder_timings(crtc, pipe_config); 3455 intel_get_pipe_src_size(crtc, pipe_config); 3456 3457 ilk_pfit_get_config(pipe_config); 3458 3459 ret = true; 3460 3461 out: 3462 intel_display_power_put(display, power_domain, wakeref); 3463 3464 return ret; 3465 } 3466 3467 static u8 joiner_pipes(struct intel_display *display) 3468 { 3469 u8 pipes; 3470 3471 if (DISPLAY_VER(display) >= 12) 3472 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3473 else if (DISPLAY_VER(display) >= 11) 3474 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3475 else 3476 pipes = 0; 3477 3478 return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask; 3479 } 3480 3481 static bool transcoder_ddi_func_is_enabled(struct intel_display *display, 3482 enum transcoder cpu_transcoder) 3483 { 3484 enum intel_display_power_domain power_domain; 3485 u32 tmp = 0; 3486 3487 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3488 3489 with_intel_display_power_if_enabled(display, power_domain) 3490 tmp = intel_de_read(display, 3491 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3492 3493 return tmp & TRANS_DDI_FUNC_ENABLE; 3494 } 3495 3496 static void enabled_uncompressed_joiner_pipes(struct intel_display *display, 3497 u8 *primary_pipes, u8 *secondary_pipes) 3498 { 3499 struct intel_crtc *crtc; 3500 3501 *primary_pipes = 0; 3502 *secondary_pipes = 0; 3503 3504 if (!HAS_UNCOMPRESSED_JOINER(display)) 3505 return; 3506 3507 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, 3508 joiner_pipes(display)) { 3509 enum intel_display_power_domain power_domain; 3510 enum pipe pipe = crtc->pipe; 3511 3512 power_domain = POWER_DOMAIN_PIPE(pipe); 3513 with_intel_display_power_if_enabled(display, power_domain) { 3514 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3515 3516 if (tmp & UNCOMPRESSED_JOINER_PRIMARY) 3517 *primary_pipes |= BIT(pipe); 3518 if (tmp & UNCOMPRESSED_JOINER_SECONDARY) 3519 *secondary_pipes |= BIT(pipe); 3520 } 3521 } 3522 } 3523 3524 static void enabled_bigjoiner_pipes(struct intel_display *display, 3525 u8 *primary_pipes, u8 *secondary_pipes) 3526 { 3527 struct intel_crtc *crtc; 3528 3529 *primary_pipes = 0; 3530 *secondary_pipes = 0; 3531 3532 if (!HAS_BIGJOINER(display)) 3533 return; 3534 3535 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, 3536 joiner_pipes(display)) { 3537 enum intel_display_power_domain power_domain; 3538 enum pipe pipe = crtc->pipe; 3539 3540 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); 3541 with_intel_display_power_if_enabled(display, power_domain) { 3542 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3543 3544 if (!(tmp & BIG_JOINER_ENABLE)) 3545 continue; 3546 3547 if (tmp & PRIMARY_BIG_JOINER_ENABLE) 3548 *primary_pipes |= BIT(pipe); 3549 else 3550 *secondary_pipes |= BIT(pipe); 3551 } 3552 } 3553 } 3554 3555 static u8 expected_secondary_pipes(u8 primary_pipes, int num_pipes) 3556 { 3557 u8 secondary_pipes = 0; 3558 3559 for (int i = 1; i < num_pipes; i++) 3560 secondary_pipes |= primary_pipes << i; 3561 3562 return secondary_pipes; 3563 } 3564 3565 static u8 expected_uncompressed_joiner_secondary_pipes(u8 uncompjoiner_primary_pipes) 3566 { 3567 return expected_secondary_pipes(uncompjoiner_primary_pipes, 2); 3568 } 3569 3570 static u8 expected_bigjoiner_secondary_pipes(u8 bigjoiner_primary_pipes) 3571 { 3572 return expected_secondary_pipes(bigjoiner_primary_pipes, 2); 3573 } 3574 3575 static u8 get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes) 3576 { 3577 primary_pipes &= GENMASK(pipe, 0); 3578 3579 return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0; 3580 } 3581 3582 static u8 expected_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes) 3583 { 3584 return expected_secondary_pipes(ultrajoiner_primary_pipes, 4); 3585 } 3586 3587 static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes, 3588 u8 ultrajoiner_secondary_pipes) 3589 { 3590 return ultrajoiner_secondary_pipes | ultrajoiner_primary_pipes << 3; 3591 } 3592 3593 static void enabled_ultrajoiner_pipes(struct intel_display *display, 3594 u8 *primary_pipes, u8 *secondary_pipes) 3595 { 3596 struct intel_crtc *crtc; 3597 3598 *primary_pipes = 0; 3599 *secondary_pipes = 0; 3600 3601 if (!HAS_ULTRAJOINER(display)) 3602 return; 3603 3604 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, 3605 joiner_pipes(display)) { 3606 enum intel_display_power_domain power_domain; 3607 enum pipe pipe = crtc->pipe; 3608 3609 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); 3610 with_intel_display_power_if_enabled(display, power_domain) { 3611 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3612 3613 if (!(tmp & ULTRA_JOINER_ENABLE)) 3614 continue; 3615 3616 if (tmp & PRIMARY_ULTRA_JOINER_ENABLE) 3617 *primary_pipes |= BIT(pipe); 3618 else 3619 *secondary_pipes |= BIT(pipe); 3620 } 3621 } 3622 } 3623 3624 static void enabled_joiner_pipes(struct intel_display *display, 3625 enum pipe pipe, 3626 u8 *primary_pipe, u8 *secondary_pipes) 3627 { 3628 u8 primary_ultrajoiner_pipes; 3629 u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes; 3630 u8 secondary_ultrajoiner_pipes; 3631 u8 secondary_uncompressed_joiner_pipes, secondary_bigjoiner_pipes; 3632 u8 ultrajoiner_pipes; 3633 u8 uncompressed_joiner_pipes, bigjoiner_pipes; 3634 3635 enabled_ultrajoiner_pipes(display, &primary_ultrajoiner_pipes, 3636 &secondary_ultrajoiner_pipes); 3637 /* 3638 * For some strange reason the last pipe in the set of four 3639 * shouldn't have ultrajoiner enable bit set in hardware. 3640 * Set the bit anyway to make life easier. 3641 */ 3642 drm_WARN_ON(display->drm, 3643 expected_secondary_pipes(primary_ultrajoiner_pipes, 3) != 3644 secondary_ultrajoiner_pipes); 3645 secondary_ultrajoiner_pipes = 3646 fixup_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes, 3647 secondary_ultrajoiner_pipes); 3648 3649 drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0); 3650 3651 enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes, 3652 &secondary_uncompressed_joiner_pipes); 3653 3654 drm_WARN_ON(display->drm, 3655 (primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0); 3656 3657 enabled_bigjoiner_pipes(display, &primary_bigjoiner_pipes, 3658 &secondary_bigjoiner_pipes); 3659 3660 drm_WARN_ON(display->drm, 3661 (primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0); 3662 3663 ultrajoiner_pipes = primary_ultrajoiner_pipes | secondary_ultrajoiner_pipes; 3664 uncompressed_joiner_pipes = primary_uncompressed_joiner_pipes | 3665 secondary_uncompressed_joiner_pipes; 3666 bigjoiner_pipes = primary_bigjoiner_pipes | secondary_bigjoiner_pipes; 3667 3668 drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes, 3669 "Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x)\n", 3670 ultrajoiner_pipes, bigjoiner_pipes); 3671 3672 drm_WARN(display->drm, secondary_ultrajoiner_pipes != 3673 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes), 3674 "Wrong secondary ultrajoiner pipes(expected %#x, current %#x)\n", 3675 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes), 3676 secondary_ultrajoiner_pipes); 3677 3678 drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0, 3679 "Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect\n", 3680 uncompressed_joiner_pipes, bigjoiner_pipes); 3681 3682 drm_WARN(display->drm, secondary_bigjoiner_pipes != 3683 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes), 3684 "Wrong secondary bigjoiner pipes(expected %#x, current %#x)\n", 3685 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes), 3686 secondary_bigjoiner_pipes); 3687 3688 drm_WARN(display->drm, secondary_uncompressed_joiner_pipes != 3689 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes), 3690 "Wrong secondary uncompressed joiner pipes(expected %#x, current %#x)\n", 3691 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes), 3692 secondary_uncompressed_joiner_pipes); 3693 3694 *primary_pipe = 0; 3695 *secondary_pipes = 0; 3696 3697 if (ultrajoiner_pipes & BIT(pipe)) { 3698 *primary_pipe = get_joiner_primary_pipe(pipe, primary_ultrajoiner_pipes); 3699 *secondary_pipes = secondary_ultrajoiner_pipes & 3700 expected_ultrajoiner_secondary_pipes(*primary_pipe); 3701 3702 drm_WARN(display->drm, 3703 expected_ultrajoiner_secondary_pipes(*primary_pipe) != 3704 *secondary_pipes, 3705 "Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3706 *primary_pipe, 3707 expected_ultrajoiner_secondary_pipes(*primary_pipe), 3708 *secondary_pipes); 3709 return; 3710 } 3711 3712 if (uncompressed_joiner_pipes & BIT(pipe)) { 3713 *primary_pipe = get_joiner_primary_pipe(pipe, primary_uncompressed_joiner_pipes); 3714 *secondary_pipes = secondary_uncompressed_joiner_pipes & 3715 expected_uncompressed_joiner_secondary_pipes(*primary_pipe); 3716 3717 drm_WARN(display->drm, 3718 expected_uncompressed_joiner_secondary_pipes(*primary_pipe) != 3719 *secondary_pipes, 3720 "Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3721 *primary_pipe, 3722 expected_uncompressed_joiner_secondary_pipes(*primary_pipe), 3723 *secondary_pipes); 3724 return; 3725 } 3726 3727 if (bigjoiner_pipes & BIT(pipe)) { 3728 *primary_pipe = get_joiner_primary_pipe(pipe, primary_bigjoiner_pipes); 3729 *secondary_pipes = secondary_bigjoiner_pipes & 3730 expected_bigjoiner_secondary_pipes(*primary_pipe); 3731 3732 drm_WARN(display->drm, 3733 expected_bigjoiner_secondary_pipes(*primary_pipe) != 3734 *secondary_pipes, 3735 "Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3736 *primary_pipe, 3737 expected_bigjoiner_secondary_pipes(*primary_pipe), 3738 *secondary_pipes); 3739 return; 3740 } 3741 } 3742 3743 static u8 hsw_panel_transcoders(struct intel_display *display) 3744 { 3745 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3746 3747 if (DISPLAY_VER(display) >= 11) 3748 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3749 3750 return panel_transcoder_mask; 3751 } 3752 3753 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3754 { 3755 struct intel_display *display = to_intel_display(crtc); 3756 u8 panel_transcoder_mask = hsw_panel_transcoders(display); 3757 enum transcoder cpu_transcoder; 3758 u8 primary_pipe, secondary_pipes; 3759 u8 enabled_transcoders = 0; 3760 3761 /* 3762 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3763 * consistency and less surprising code; it's in always on power). 3764 */ 3765 for_each_cpu_transcoder_masked(display, cpu_transcoder, 3766 panel_transcoder_mask) { 3767 enum intel_display_power_domain power_domain; 3768 enum pipe trans_pipe; 3769 u32 tmp = 0; 3770 3771 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3772 with_intel_display_power_if_enabled(display, power_domain) 3773 tmp = intel_de_read(display, 3774 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3775 3776 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3777 continue; 3778 3779 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3780 default: 3781 drm_WARN(display->drm, 1, 3782 "unknown pipe linked to transcoder %s\n", 3783 transcoder_name(cpu_transcoder)); 3784 fallthrough; 3785 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3786 case TRANS_DDI_EDP_INPUT_A_ON: 3787 trans_pipe = PIPE_A; 3788 break; 3789 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3790 trans_pipe = PIPE_B; 3791 break; 3792 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3793 trans_pipe = PIPE_C; 3794 break; 3795 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3796 trans_pipe = PIPE_D; 3797 break; 3798 } 3799 3800 if (trans_pipe == crtc->pipe) 3801 enabled_transcoders |= BIT(cpu_transcoder); 3802 } 3803 3804 /* single pipe or joiner primary */ 3805 cpu_transcoder = (enum transcoder) crtc->pipe; 3806 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) 3807 enabled_transcoders |= BIT(cpu_transcoder); 3808 3809 /* joiner secondary -> consider the primary pipe's transcoder as well */ 3810 enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes); 3811 if (secondary_pipes & BIT(crtc->pipe)) { 3812 cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1; 3813 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) 3814 enabled_transcoders |= BIT(cpu_transcoder); 3815 } 3816 3817 return enabled_transcoders; 3818 } 3819 3820 static bool has_edp_transcoders(u8 enabled_transcoders) 3821 { 3822 return enabled_transcoders & BIT(TRANSCODER_EDP); 3823 } 3824 3825 static bool has_dsi_transcoders(u8 enabled_transcoders) 3826 { 3827 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3828 BIT(TRANSCODER_DSI_1)); 3829 } 3830 3831 static bool has_pipe_transcoders(u8 enabled_transcoders) 3832 { 3833 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3834 BIT(TRANSCODER_DSI_0) | 3835 BIT(TRANSCODER_DSI_1)); 3836 } 3837 3838 static void assert_enabled_transcoders(struct intel_display *display, 3839 u8 enabled_transcoders) 3840 { 3841 /* Only one type of transcoder please */ 3842 drm_WARN_ON(display->drm, 3843 has_edp_transcoders(enabled_transcoders) + 3844 has_dsi_transcoders(enabled_transcoders) + 3845 has_pipe_transcoders(enabled_transcoders) > 1); 3846 3847 /* Only DSI transcoders can be ganged */ 3848 drm_WARN_ON(display->drm, 3849 !has_dsi_transcoders(enabled_transcoders) && 3850 !is_power_of_2(enabled_transcoders)); 3851 } 3852 3853 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3854 struct intel_crtc_state *pipe_config, 3855 struct intel_display_power_domain_set *power_domain_set) 3856 { 3857 struct intel_display *display = to_intel_display(crtc); 3858 unsigned long enabled_transcoders; 3859 u32 tmp; 3860 3861 enabled_transcoders = hsw_enabled_transcoders(crtc); 3862 if (!enabled_transcoders) 3863 return false; 3864 3865 assert_enabled_transcoders(display, enabled_transcoders); 3866 3867 /* 3868 * With the exception of DSI we should only ever have 3869 * a single enabled transcoder. With DSI let's just 3870 * pick the first one. 3871 */ 3872 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3873 3874 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, 3875 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3876 return false; 3877 3878 if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) { 3879 tmp = intel_de_read(display, 3880 TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder)); 3881 3882 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3883 pipe_config->pch_pfit.force_thru = true; 3884 } 3885 3886 tmp = intel_de_read(display, 3887 TRANSCONF(display, pipe_config->cpu_transcoder)); 3888 3889 return tmp & TRANSCONF_ENABLE; 3890 } 3891 3892 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3893 struct intel_crtc_state *pipe_config, 3894 struct intel_display_power_domain_set *power_domain_set) 3895 { 3896 struct intel_display *display = to_intel_display(crtc); 3897 enum transcoder cpu_transcoder; 3898 enum port port; 3899 u32 tmp; 3900 3901 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3902 if (port == PORT_A) 3903 cpu_transcoder = TRANSCODER_DSI_A; 3904 else 3905 cpu_transcoder = TRANSCODER_DSI_C; 3906 3907 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, 3908 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3909 continue; 3910 3911 /* 3912 * The PLL needs to be enabled with a valid divider 3913 * configuration, otherwise accessing DSI registers will hang 3914 * the machine. See BSpec North Display Engine 3915 * registers/MIPI[BXT]. We can break out here early, since we 3916 * need the same DSI PLL to be enabled for both DSI ports. 3917 */ 3918 if (!bxt_dsi_pll_is_enabled(display)) 3919 break; 3920 3921 /* XXX: this works for video mode only */ 3922 tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port)); 3923 if (!(tmp & DPI_ENABLE)) 3924 continue; 3925 3926 tmp = intel_de_read(display, MIPI_CTRL(display, port)); 3927 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3928 continue; 3929 3930 pipe_config->cpu_transcoder = cpu_transcoder; 3931 break; 3932 } 3933 3934 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3935 } 3936 3937 static void intel_joiner_get_config(struct intel_crtc_state *crtc_state) 3938 { 3939 struct intel_display *display = to_intel_display(crtc_state); 3940 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3941 u8 primary_pipe, secondary_pipes; 3942 enum pipe pipe = crtc->pipe; 3943 3944 enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes); 3945 3946 if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0) 3947 return; 3948 3949 crtc_state->joiner_pipes = primary_pipe | secondary_pipes; 3950 } 3951 3952 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3953 struct intel_crtc_state *pipe_config) 3954 { 3955 struct intel_display *display = to_intel_display(crtc); 3956 bool active; 3957 u32 tmp; 3958 3959 if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, 3960 POWER_DOMAIN_PIPE(crtc->pipe))) 3961 return false; 3962 3963 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3964 3965 if ((display->platform.geminilake || display->platform.broxton) && 3966 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3967 drm_WARN_ON(display->drm, active); 3968 active = true; 3969 } 3970 3971 if (!active) 3972 goto out; 3973 3974 intel_joiner_get_config(pipe_config); 3975 intel_dsc_get_config(pipe_config); 3976 3977 /* intel_vrr_get_config() depends on .framestart_delay */ 3978 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3979 tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder)); 3980 3981 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 3982 } else { 3983 /* no idea if this is correct */ 3984 pipe_config->framestart_delay = 1; 3985 } 3986 3987 /* 3988 * intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY 3989 * readout done by intel_get_transcoder_timings(). 3990 */ 3991 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3992 DISPLAY_VER(display) >= 11) 3993 intel_get_transcoder_timings(crtc, pipe_config); 3994 3995 if (transcoder_has_vrr(pipe_config)) 3996 intel_vrr_get_config(pipe_config); 3997 3998 intel_get_pipe_src_size(crtc, pipe_config); 3999 4000 if (display->platform.haswell) { 4001 u32 tmp = intel_de_read(display, 4002 TRANSCONF(display, pipe_config->cpu_transcoder)); 4003 4004 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 4005 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4006 else 4007 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4008 } else { 4009 pipe_config->output_format = 4010 bdw_get_pipe_misc_output_format(crtc); 4011 } 4012 4013 pipe_config->sink_format = pipe_config->output_format; 4014 4015 intel_color_get_config(pipe_config); 4016 4017 tmp = intel_de_read(display, WM_LINETIME(crtc->pipe)); 4018 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4019 if (display->platform.broadwell || display->platform.haswell) 4020 pipe_config->ips_linetime = 4021 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4022 4023 if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, 4024 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4025 if (DISPLAY_VER(display) >= 9) 4026 skl_scaler_get_config(pipe_config); 4027 else 4028 ilk_pfit_get_config(pipe_config); 4029 } 4030 4031 hsw_ips_get_config(pipe_config); 4032 4033 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4034 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4035 pipe_config->pixel_multiplier = 4036 intel_de_read(display, 4037 TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1; 4038 } else { 4039 pipe_config->pixel_multiplier = 1; 4040 } 4041 4042 out: 4043 intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains); 4044 4045 return active; 4046 } 4047 4048 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4049 { 4050 struct intel_display *display = to_intel_display(crtc_state); 4051 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4052 4053 if (!display->funcs.display->get_pipe_config(crtc, crtc_state)) 4054 return false; 4055 4056 crtc_state->hw.active = true; 4057 4058 intel_crtc_readout_derived_state(crtc_state); 4059 4060 return true; 4061 } 4062 4063 int intel_dotclock_calculate(int link_freq, 4064 const struct intel_link_m_n *m_n) 4065 { 4066 /* 4067 * The calculation for the data clock -> pixel clock is: 4068 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4069 * But we want to avoid losing precision if possible, so: 4070 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4071 * 4072 * and for link freq (10kbs units) -> pixel clock it is: 4073 * link_symbol_clock = link_freq * 10 / link_symbol_size 4074 * pixel_clock = (m * link_symbol_clock) / n 4075 * or for more precision: 4076 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size) 4077 */ 4078 4079 if (!m_n->link_n) 4080 return 0; 4081 4082 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10), 4083 m_n->link_n * intel_dp_link_symbol_size(link_freq)); 4084 } 4085 4086 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 4087 { 4088 int dotclock; 4089 4090 if (intel_crtc_has_dp_encoder(pipe_config)) 4091 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 4092 &pipe_config->dp_m_n); 4093 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 4094 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 4095 pipe_config->pipe_bpp); 4096 else 4097 dotclock = pipe_config->port_clock; 4098 4099 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 4100 !intel_crtc_has_dp_encoder(pipe_config)) 4101 dotclock *= 2; 4102 4103 if (pipe_config->pixel_multiplier) 4104 dotclock /= pipe_config->pixel_multiplier; 4105 4106 return dotclock; 4107 } 4108 4109 /* Returns the currently programmed mode of the given encoder. */ 4110 struct drm_display_mode * 4111 intel_encoder_current_mode(struct intel_encoder *encoder) 4112 { 4113 struct intel_display *display = to_intel_display(encoder); 4114 struct intel_crtc_state *crtc_state; 4115 struct drm_display_mode *mode; 4116 struct intel_crtc *crtc; 4117 enum pipe pipe; 4118 4119 if (!encoder->get_hw_state(encoder, &pipe)) 4120 return NULL; 4121 4122 crtc = intel_crtc_for_pipe(display, pipe); 4123 4124 mode = kzalloc_obj(*mode); 4125 if (!mode) 4126 return NULL; 4127 4128 crtc_state = intel_crtc_state_alloc(crtc); 4129 if (!crtc_state) { 4130 kfree(mode); 4131 return NULL; 4132 } 4133 4134 if (!intel_crtc_get_pipe_config(crtc_state)) { 4135 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); 4136 kfree(mode); 4137 return NULL; 4138 } 4139 4140 intel_encoder_get_config(encoder, crtc_state); 4141 4142 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4143 4144 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); 4145 4146 return mode; 4147 } 4148 4149 static bool encoders_cloneable(const struct intel_encoder *a, 4150 const struct intel_encoder *b) 4151 { 4152 /* masks could be asymmetric, so check both ways */ 4153 return a == b || (a->cloneable & BIT(b->type) && 4154 b->cloneable & BIT(a->type)); 4155 } 4156 4157 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4158 struct intel_crtc *crtc, 4159 struct intel_encoder *encoder) 4160 { 4161 struct intel_encoder *source_encoder; 4162 struct drm_connector *connector; 4163 struct drm_connector_state *connector_state; 4164 int i; 4165 4166 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4167 if (connector_state->crtc != &crtc->base) 4168 continue; 4169 4170 source_encoder = 4171 to_intel_encoder(connector_state->best_encoder); 4172 if (!encoders_cloneable(encoder, source_encoder)) 4173 return false; 4174 } 4175 4176 return true; 4177 } 4178 4179 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4180 { 4181 const struct drm_display_mode *pipe_mode = 4182 &crtc_state->hw.pipe_mode; 4183 int linetime_wm; 4184 4185 if (!crtc_state->hw.enable) 4186 return 0; 4187 4188 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4189 pipe_mode->crtc_clock); 4190 4191 return min(linetime_wm, 0x1ff); 4192 } 4193 4194 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4195 const struct intel_cdclk_state *cdclk_state) 4196 { 4197 const struct drm_display_mode *pipe_mode = 4198 &crtc_state->hw.pipe_mode; 4199 int linetime_wm; 4200 4201 if (!crtc_state->hw.enable) 4202 return 0; 4203 4204 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4205 intel_cdclk_logical(cdclk_state)); 4206 4207 return min(linetime_wm, 0x1ff); 4208 } 4209 4210 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4211 { 4212 struct intel_display *display = to_intel_display(crtc_state); 4213 const struct drm_display_mode *pipe_mode = 4214 &crtc_state->hw.pipe_mode; 4215 int linetime_wm; 4216 4217 if (!crtc_state->hw.enable) 4218 return 0; 4219 4220 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4221 crtc_state->pixel_rate); 4222 4223 /* Display WA #1135: BXT:ALL GLK:ALL */ 4224 if ((display->platform.geminilake || display->platform.broxton) && 4225 skl_watermark_ipc_enabled(display)) 4226 linetime_wm /= 2; 4227 4228 return min(linetime_wm, 0x1ff); 4229 } 4230 4231 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4232 struct intel_crtc *crtc) 4233 { 4234 struct intel_display *display = to_intel_display(state); 4235 struct intel_crtc_state *crtc_state = 4236 intel_atomic_get_new_crtc_state(state, crtc); 4237 const struct intel_cdclk_state *cdclk_state; 4238 4239 if (DISPLAY_VER(display) >= 9) 4240 crtc_state->linetime = skl_linetime_wm(crtc_state); 4241 else 4242 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4243 4244 if (!hsw_crtc_supports_ips(crtc)) 4245 return 0; 4246 4247 cdclk_state = intel_atomic_get_cdclk_state(state); 4248 if (IS_ERR(cdclk_state)) 4249 return PTR_ERR(cdclk_state); 4250 4251 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4252 cdclk_state); 4253 4254 return 0; 4255 } 4256 4257 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4258 struct intel_crtc *crtc) 4259 { 4260 struct intel_display *display = to_intel_display(crtc); 4261 struct intel_crtc_state *crtc_state = 4262 intel_atomic_get_new_crtc_state(state, crtc); 4263 int ret; 4264 4265 if (DISPLAY_VER(display) < 5 && !display->platform.g4x && 4266 intel_crtc_needs_modeset(crtc_state) && 4267 !crtc_state->hw.active) 4268 crtc_state->update_wm_post = true; 4269 4270 if (intel_crtc_needs_modeset(crtc_state)) { 4271 ret = intel_dpll_crtc_get_dpll(state, crtc); 4272 if (ret) 4273 return ret; 4274 } 4275 4276 ret = intel_color_check(state, crtc); 4277 if (ret) 4278 return ret; 4279 4280 ret = intel_wm_compute(state, crtc); 4281 if (ret) { 4282 drm_dbg_kms(display->drm, 4283 "[CRTC:%d:%s] watermarks are invalid\n", 4284 crtc->base.base.id, crtc->base.name); 4285 return ret; 4286 } 4287 4288 ret = intel_casf_compute_config(crtc_state); 4289 if (ret) 4290 return ret; 4291 4292 if (DISPLAY_VER(display) >= 9) { 4293 if (intel_crtc_needs_modeset(crtc_state) || 4294 intel_crtc_needs_fastset(crtc_state) || 4295 intel_casf_needs_scaler(crtc_state)) { 4296 ret = skl_update_scaler_crtc(crtc_state); 4297 if (ret) 4298 return ret; 4299 } 4300 4301 ret = intel_atomic_setup_scalers(state, crtc); 4302 if (ret) 4303 return ret; 4304 } 4305 4306 if (HAS_IPS(display)) { 4307 ret = hsw_ips_compute_config(state, crtc); 4308 if (ret) 4309 return ret; 4310 } 4311 4312 if (DISPLAY_VER(display) >= 9 || 4313 display->platform.broadwell || display->platform.haswell) { 4314 ret = hsw_compute_linetime_wm(state, crtc); 4315 if (ret) 4316 return ret; 4317 4318 } 4319 4320 ret = intel_psr2_sel_fetch_update(state, crtc); 4321 if (ret) 4322 return ret; 4323 4324 return 0; 4325 } 4326 4327 static int 4328 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4329 struct intel_crtc_state *crtc_state) 4330 { 4331 struct intel_display *display = to_intel_display(crtc_state); 4332 struct drm_connector *connector = conn_state->connector; 4333 const struct drm_display_info *info = &connector->display_info; 4334 int bpp; 4335 4336 switch (conn_state->max_bpc) { 4337 case 6 ... 7: 4338 bpp = 6 * 3; 4339 break; 4340 case 8 ... 9: 4341 bpp = 8 * 3; 4342 break; 4343 case 10 ... 11: 4344 bpp = 10 * 3; 4345 break; 4346 case 12 ... 16: 4347 bpp = 12 * 3; 4348 break; 4349 default: 4350 MISSING_CASE(conn_state->max_bpc); 4351 return -EINVAL; 4352 } 4353 4354 if (bpp < crtc_state->pipe_bpp) { 4355 drm_dbg_kms(display->drm, 4356 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4357 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4358 connector->base.id, connector->name, 4359 bpp, 3 * info->bpc, 4360 3 * conn_state->max_requested_bpc, 4361 crtc_state->pipe_bpp); 4362 4363 crtc_state->pipe_bpp = bpp; 4364 } 4365 4366 return 0; 4367 } 4368 4369 int intel_display_min_pipe_bpp(void) 4370 { 4371 return 6 * 3; 4372 } 4373 4374 int intel_display_max_pipe_bpp(struct intel_display *display) 4375 { 4376 if (display->platform.g4x || display->platform.valleyview || 4377 display->platform.cherryview) 4378 return 10*3; 4379 else if (DISPLAY_VER(display) >= 5) 4380 return 12*3; 4381 else 4382 return 8*3; 4383 } 4384 4385 static int 4386 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4387 struct intel_crtc *crtc) 4388 { 4389 struct intel_display *display = to_intel_display(crtc); 4390 struct intel_crtc_state *crtc_state = 4391 intel_atomic_get_new_crtc_state(state, crtc); 4392 struct drm_connector *connector; 4393 struct drm_connector_state *connector_state; 4394 int i; 4395 4396 crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display); 4397 4398 /* Clamp display bpp to connector max bpp */ 4399 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4400 int ret; 4401 4402 if (connector_state->crtc != &crtc->base) 4403 continue; 4404 4405 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4406 if (ret) 4407 return ret; 4408 } 4409 4410 return 0; 4411 } 4412 4413 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4414 { 4415 struct intel_display *display = to_intel_display(state); 4416 struct drm_connector *connector; 4417 struct drm_connector_list_iter conn_iter; 4418 unsigned int used_ports = 0; 4419 unsigned int used_mst_ports = 0; 4420 bool ret = true; 4421 4422 /* 4423 * We're going to peek into connector->state, 4424 * hence connection_mutex must be held. 4425 */ 4426 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); 4427 4428 /* 4429 * Walk the connector list instead of the encoder 4430 * list to detect the problem on ddi platforms 4431 * where there's just one encoder per digital port. 4432 */ 4433 drm_connector_list_iter_begin(display->drm, &conn_iter); 4434 drm_for_each_connector_iter(connector, &conn_iter) { 4435 struct drm_connector_state *connector_state; 4436 struct intel_encoder *encoder; 4437 4438 connector_state = 4439 drm_atomic_get_new_connector_state(&state->base, 4440 connector); 4441 if (!connector_state) 4442 connector_state = connector->state; 4443 4444 if (!connector_state->best_encoder) 4445 continue; 4446 4447 encoder = to_intel_encoder(connector_state->best_encoder); 4448 4449 drm_WARN_ON(display->drm, !connector_state->crtc); 4450 4451 switch (encoder->type) { 4452 case INTEL_OUTPUT_DDI: 4453 if (drm_WARN_ON(display->drm, !HAS_DDI(display))) 4454 break; 4455 fallthrough; 4456 case INTEL_OUTPUT_DP: 4457 case INTEL_OUTPUT_HDMI: 4458 case INTEL_OUTPUT_EDP: 4459 /* the same port mustn't appear more than once */ 4460 if (used_ports & BIT(encoder->port)) 4461 ret = false; 4462 4463 used_ports |= BIT(encoder->port); 4464 break; 4465 case INTEL_OUTPUT_DP_MST: 4466 used_mst_ports |= 4467 1 << encoder->port; 4468 break; 4469 default: 4470 break; 4471 } 4472 } 4473 drm_connector_list_iter_end(&conn_iter); 4474 4475 /* can't mix MST and SST/HDMI on the same port */ 4476 if (used_ports & used_mst_ports) 4477 return false; 4478 4479 return ret; 4480 } 4481 4482 static void 4483 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4484 struct intel_crtc *crtc) 4485 { 4486 struct intel_crtc_state *crtc_state = 4487 intel_atomic_get_new_crtc_state(state, crtc); 4488 4489 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); 4490 4491 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4492 crtc_state->uapi.degamma_lut); 4493 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4494 crtc_state->uapi.gamma_lut); 4495 drm_property_replace_blob(&crtc_state->hw.ctm, 4496 crtc_state->uapi.ctm); 4497 } 4498 4499 static void 4500 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4501 struct intel_crtc *crtc) 4502 { 4503 struct intel_crtc_state *crtc_state = 4504 intel_atomic_get_new_crtc_state(state, crtc); 4505 4506 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); 4507 4508 crtc_state->hw.enable = crtc_state->uapi.enable; 4509 crtc_state->hw.active = crtc_state->uapi.active; 4510 drm_mode_copy(&crtc_state->hw.mode, 4511 &crtc_state->uapi.mode); 4512 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4513 &crtc_state->uapi.adjusted_mode); 4514 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4515 4516 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4517 } 4518 4519 static void 4520 copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4521 struct intel_crtc *secondary_crtc) 4522 { 4523 struct intel_crtc_state *secondary_crtc_state = 4524 intel_atomic_get_new_crtc_state(state, secondary_crtc); 4525 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); 4526 const struct intel_crtc_state *primary_crtc_state = 4527 intel_atomic_get_new_crtc_state(state, primary_crtc); 4528 4529 drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut, 4530 primary_crtc_state->hw.degamma_lut); 4531 drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut, 4532 primary_crtc_state->hw.gamma_lut); 4533 drm_property_replace_blob(&secondary_crtc_state->hw.ctm, 4534 primary_crtc_state->hw.ctm); 4535 4536 secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed; 4537 } 4538 4539 static int 4540 copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, 4541 struct intel_crtc *secondary_crtc) 4542 { 4543 struct intel_crtc_state *secondary_crtc_state = 4544 intel_atomic_get_new_crtc_state(state, secondary_crtc); 4545 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); 4546 const struct intel_crtc_state *primary_crtc_state = 4547 intel_atomic_get_new_crtc_state(state, primary_crtc); 4548 struct intel_crtc_state *saved_state; 4549 4550 WARN_ON(primary_crtc_state->joiner_pipes != 4551 secondary_crtc_state->joiner_pipes); 4552 4553 saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4554 if (!saved_state) 4555 return -ENOMEM; 4556 4557 /* preserve some things from the slave's original crtc state */ 4558 saved_state->uapi = secondary_crtc_state->uapi; 4559 saved_state->scaler_state = secondary_crtc_state->scaler_state; 4560 saved_state->intel_dpll = secondary_crtc_state->intel_dpll; 4561 saved_state->crc_enabled = secondary_crtc_state->crc_enabled; 4562 4563 intel_crtc_free_hw_state(secondary_crtc_state); 4564 if (secondary_crtc_state->dp_tunnel_ref.tunnel) 4565 drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref); 4566 memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state)); 4567 kfree(saved_state); 4568 4569 /* Re-init hw state */ 4570 memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw)); 4571 secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable; 4572 secondary_crtc_state->hw.active = primary_crtc_state->hw.active; 4573 drm_mode_copy(&secondary_crtc_state->hw.mode, 4574 &primary_crtc_state->hw.mode); 4575 drm_mode_copy(&secondary_crtc_state->hw.pipe_mode, 4576 &primary_crtc_state->hw.pipe_mode); 4577 drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode, 4578 &primary_crtc_state->hw.adjusted_mode); 4579 secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter; 4580 4581 if (primary_crtc_state->dp_tunnel_ref.tunnel) 4582 drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel, 4583 &secondary_crtc_state->dp_tunnel_ref); 4584 4585 copy_joiner_crtc_state_nomodeset(state, secondary_crtc); 4586 4587 secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed; 4588 secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed; 4589 secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed; 4590 4591 WARN_ON(primary_crtc_state->joiner_pipes != 4592 secondary_crtc_state->joiner_pipes); 4593 4594 return 0; 4595 } 4596 4597 static int 4598 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 4599 struct intel_crtc *crtc) 4600 { 4601 struct intel_display *display = to_intel_display(state); 4602 struct intel_crtc_state *crtc_state = 4603 intel_atomic_get_new_crtc_state(state, crtc); 4604 struct intel_crtc_state *saved_state; 4605 4606 saved_state = intel_crtc_state_alloc(crtc); 4607 if (!saved_state) 4608 return -ENOMEM; 4609 4610 /* free the old crtc_state->hw members */ 4611 intel_crtc_free_hw_state(crtc_state); 4612 4613 intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state); 4614 4615 /* FIXME: before the switch to atomic started, a new pipe_config was 4616 * kzalloc'd. Code that depends on any field being zero should be 4617 * fixed, so that the crtc_state can be safely duplicated. For now, 4618 * only fields that are know to not cause problems are preserved. */ 4619 4620 saved_state->uapi = crtc_state->uapi; 4621 saved_state->inherited = crtc_state->inherited; 4622 saved_state->scaler_state = crtc_state->scaler_state; 4623 saved_state->intel_dpll = crtc_state->intel_dpll; 4624 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 4625 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 4626 sizeof(saved_state->icl_port_dplls)); 4627 saved_state->crc_enabled = crtc_state->crc_enabled; 4628 if (display->platform.g4x || 4629 display->platform.valleyview || display->platform.cherryview) 4630 saved_state->wm = crtc_state->wm; 4631 4632 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 4633 kfree(saved_state); 4634 4635 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 4636 4637 return 0; 4638 } 4639 4640 static int 4641 intel_modeset_pipe_config(struct intel_atomic_state *state, 4642 struct intel_crtc *crtc, 4643 const struct intel_link_bw_limits *limits) 4644 { 4645 struct intel_display *display = to_intel_display(crtc); 4646 struct intel_crtc_state *crtc_state = 4647 intel_atomic_get_new_crtc_state(state, crtc); 4648 struct drm_connector *connector; 4649 struct drm_connector_state *connector_state; 4650 int pipe_src_w, pipe_src_h; 4651 int base_bpp, ret, i; 4652 4653 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 4654 4655 crtc_state->framestart_delay = 1; 4656 4657 /* 4658 * Sanitize sync polarity flags based on requested ones. If neither 4659 * positive or negative polarity is requested, treat this as meaning 4660 * negative polarity. 4661 */ 4662 if (!(crtc_state->hw.adjusted_mode.flags & 4663 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 4664 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 4665 4666 if (!(crtc_state->hw.adjusted_mode.flags & 4667 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 4668 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 4669 4670 ret = compute_baseline_pipe_bpp(state, crtc); 4671 if (ret) 4672 return ret; 4673 4674 crtc_state->dsc.compression_enabled_on_link = limits->link_dsc_pipes & BIT(crtc->pipe); 4675 crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe]; 4676 4677 if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) { 4678 drm_dbg_kms(display->drm, 4679 "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n", 4680 crtc->base.base.id, crtc->base.name, 4681 FXP_Q4_ARGS(crtc_state->max_link_bpp_x16)); 4682 crtc_state->bw_constrained = true; 4683 } 4684 4685 base_bpp = crtc_state->pipe_bpp; 4686 4687 /* 4688 * Determine the real pipe dimensions. Note that stereo modes can 4689 * increase the actual pipe size due to the frame doubling and 4690 * insertion of additional space for blanks between the frame. This 4691 * is stored in the crtc timings. We use the requested mode to do this 4692 * computation to clearly distinguish it from the adjusted mode, which 4693 * can be changed by the connectors in the below retry loop. 4694 */ 4695 drm_mode_get_hv_timing(&crtc_state->hw.mode, 4696 &pipe_src_w, &pipe_src_h); 4697 drm_rect_init(&crtc_state->pipe_src, 0, 0, 4698 pipe_src_w, pipe_src_h); 4699 4700 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4701 struct intel_encoder *encoder = 4702 to_intel_encoder(connector_state->best_encoder); 4703 4704 if (connector_state->crtc != &crtc->base) 4705 continue; 4706 4707 if (!check_single_encoder_cloning(state, crtc, encoder)) { 4708 drm_dbg_kms(display->drm, 4709 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 4710 encoder->base.base.id, encoder->base.name); 4711 return -EINVAL; 4712 } 4713 4714 /* 4715 * Determine output_types before calling the .compute_config() 4716 * hooks so that the hooks can use this information safely. 4717 */ 4718 if (encoder->compute_output_type) 4719 crtc_state->output_types |= 4720 BIT(encoder->compute_output_type(encoder, crtc_state, 4721 connector_state)); 4722 else 4723 crtc_state->output_types |= BIT(encoder->type); 4724 } 4725 4726 /* Ensure the port clock defaults are reset when retrying. */ 4727 crtc_state->port_clock = 0; 4728 crtc_state->pixel_multiplier = 1; 4729 4730 /* Fill in default crtc timings, allow encoders to overwrite them. */ 4731 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 4732 CRTC_STEREO_DOUBLE); 4733 4734 /* Pass our mode to the connectors and the CRTC to give them a chance to 4735 * adjust it according to limitations or connector properties, and also 4736 * a chance to reject the mode entirely. 4737 */ 4738 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4739 struct intel_encoder *encoder = 4740 to_intel_encoder(connector_state->best_encoder); 4741 4742 if (connector_state->crtc != &crtc->base) 4743 continue; 4744 4745 ret = encoder->compute_config(encoder, crtc_state, 4746 connector_state); 4747 if (ret == -EDEADLK) 4748 return ret; 4749 if (ret < 0) { 4750 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n", 4751 encoder->base.base.id, encoder->base.name, ret); 4752 return ret; 4753 } 4754 } 4755 4756 /* Set default port clock if not overwritten by the encoder. Needs to be 4757 * done afterwards in case the encoder adjusts the mode. */ 4758 if (!crtc_state->port_clock) 4759 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 4760 * crtc_state->pixel_multiplier; 4761 4762 ret = intel_crtc_compute_config(state, crtc); 4763 if (ret == -EDEADLK) 4764 return ret; 4765 if (ret < 0) { 4766 drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n", 4767 crtc->base.base.id, crtc->base.name, ret); 4768 return ret; 4769 } 4770 4771 /* Dithering seems to not pass-through bits correctly when it should, so 4772 * only enable it on 6bpc panels and when its not a compliance 4773 * test requesting 6bpc video pattern. 4774 */ 4775 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 4776 !crtc_state->dither_force_disable; 4777 drm_dbg_kms(display->drm, 4778 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 4779 crtc->base.base.id, crtc->base.name, 4780 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 4781 4782 return 0; 4783 } 4784 4785 static int 4786 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 4787 struct intel_crtc *crtc) 4788 { 4789 struct intel_crtc_state *crtc_state = 4790 intel_atomic_get_new_crtc_state(state, crtc); 4791 struct drm_connector_state *conn_state; 4792 struct drm_connector *connector; 4793 int i; 4794 4795 for_each_new_connector_in_state(&state->base, connector, 4796 conn_state, i) { 4797 struct intel_encoder *encoder = 4798 to_intel_encoder(conn_state->best_encoder); 4799 int ret; 4800 4801 if (conn_state->crtc != &crtc->base || 4802 !encoder->compute_config_late) 4803 continue; 4804 4805 ret = encoder->compute_config_late(encoder, crtc_state, 4806 conn_state); 4807 if (ret) 4808 return ret; 4809 } 4810 4811 return 0; 4812 } 4813 4814 bool intel_fuzzy_clock_check(int clock1, int clock2) 4815 { 4816 int diff; 4817 4818 if (clock1 == clock2) 4819 return true; 4820 4821 if (!clock1 || !clock2) 4822 return false; 4823 4824 diff = abs(clock1 - clock2); 4825 4826 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 4827 return true; 4828 4829 return false; 4830 } 4831 4832 static bool 4833 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 4834 const struct intel_link_m_n *m2_n2) 4835 { 4836 return m_n->tu == m2_n2->tu && 4837 m_n->data_m == m2_n2->data_m && 4838 m_n->data_n == m2_n2->data_n && 4839 m_n->link_m == m2_n2->link_m && 4840 m_n->link_n == m2_n2->link_n; 4841 } 4842 4843 static bool 4844 intel_compare_infoframe(const union hdmi_infoframe *a, 4845 const union hdmi_infoframe *b) 4846 { 4847 return memcmp(a, b, sizeof(*a)) == 0; 4848 } 4849 4850 static bool 4851 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 4852 const struct drm_dp_vsc_sdp *b) 4853 { 4854 return a->pixelformat == b->pixelformat && 4855 a->colorimetry == b->colorimetry && 4856 a->bpc == b->bpc && 4857 a->dynamic_range == b->dynamic_range && 4858 a->content_type == b->content_type; 4859 } 4860 4861 static bool 4862 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a, 4863 const struct drm_dp_as_sdp *b) 4864 { 4865 return a->vtotal == b->vtotal && 4866 a->target_rr == b->target_rr && 4867 a->duration_incr_ms == b->duration_incr_ms && 4868 a->duration_decr_ms == b->duration_decr_ms && 4869 a->mode == b->mode; 4870 } 4871 4872 static bool 4873 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 4874 { 4875 return memcmp(a, b, len) == 0; 4876 } 4877 4878 static void __printf(5, 6) 4879 pipe_config_mismatch(struct drm_printer *p, bool fastset, 4880 const struct intel_crtc *crtc, 4881 const char *name, const char *format, ...) 4882 { 4883 struct va_format vaf; 4884 va_list args; 4885 4886 va_start(args, format); 4887 vaf.fmt = format; 4888 vaf.va = &args; 4889 4890 if (fastset) 4891 drm_printf(p, "[CRTC:%d:%s] fastset requirement not met in %s %pV\n", 4892 crtc->base.base.id, crtc->base.name, name, &vaf); 4893 else 4894 drm_printf(p, "[CRTC:%d:%s] mismatch in %s %pV\n", 4895 crtc->base.base.id, crtc->base.name, name, &vaf); 4896 4897 va_end(args); 4898 } 4899 4900 static void 4901 pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset, 4902 const struct intel_crtc *crtc, 4903 const char *name, 4904 const union hdmi_infoframe *a, 4905 const union hdmi_infoframe *b) 4906 { 4907 struct intel_display *display = to_intel_display(crtc); 4908 const char *loglevel; 4909 4910 if (fastset) { 4911 if (!drm_debug_enabled(DRM_UT_KMS)) 4912 return; 4913 4914 loglevel = KERN_DEBUG; 4915 } else { 4916 loglevel = KERN_ERR; 4917 } 4918 4919 pipe_config_mismatch(p, fastset, crtc, name, "infoframe"); 4920 4921 drm_printf(p, "expected:\n"); 4922 hdmi_infoframe_log(loglevel, display->drm->dev, a); 4923 drm_printf(p, "found:\n"); 4924 hdmi_infoframe_log(loglevel, display->drm->dev, b); 4925 } 4926 4927 static void 4928 pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset, 4929 const struct intel_crtc *crtc, 4930 const char *name, 4931 const struct drm_dp_vsc_sdp *a, 4932 const struct drm_dp_vsc_sdp *b) 4933 { 4934 pipe_config_mismatch(p, fastset, crtc, name, "dp vsc sdp"); 4935 4936 drm_printf(p, "expected:\n"); 4937 drm_dp_vsc_sdp_log(p, a); 4938 drm_printf(p, "found:\n"); 4939 drm_dp_vsc_sdp_log(p, b); 4940 } 4941 4942 static void 4943 pipe_config_dp_as_sdp_mismatch(struct drm_printer *p, bool fastset, 4944 const struct intel_crtc *crtc, 4945 const char *name, 4946 const struct drm_dp_as_sdp *a, 4947 const struct drm_dp_as_sdp *b) 4948 { 4949 pipe_config_mismatch(p, fastset, crtc, name, "dp as sdp"); 4950 4951 drm_printf(p, "expected:\n"); 4952 drm_dp_as_sdp_log(p, a); 4953 drm_printf(p, "found:\n"); 4954 drm_dp_as_sdp_log(p, b); 4955 } 4956 4957 /* Returns the length up to and including the last differing byte */ 4958 static size_t 4959 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 4960 { 4961 int i; 4962 4963 for (i = len - 1; i >= 0; i--) { 4964 if (a[i] != b[i]) 4965 return i + 1; 4966 } 4967 4968 return 0; 4969 } 4970 4971 static void 4972 pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset, 4973 const struct intel_crtc *crtc, 4974 const char *name, 4975 const u8 *a, const u8 *b, size_t len) 4976 { 4977 pipe_config_mismatch(p, fastset, crtc, name, "buffer"); 4978 4979 /* only dump up to the last difference */ 4980 len = memcmp_diff_len(a, b, len); 4981 4982 drm_print_hex_dump(p, "expected: ", a, len); 4983 drm_print_hex_dump(p, "found: ", b, len); 4984 } 4985 4986 static void 4987 pipe_config_pll_mismatch(struct drm_printer *p, bool fastset, 4988 const struct intel_crtc *crtc, 4989 const char *name, 4990 const struct intel_dpll_hw_state *a, 4991 const struct intel_dpll_hw_state *b) 4992 { 4993 struct intel_display *display = to_intel_display(crtc); 4994 4995 pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */ 4996 4997 drm_printf(p, "expected:\n"); 4998 intel_dpll_dump_hw_state(display, p, a); 4999 drm_printf(p, "found:\n"); 5000 intel_dpll_dump_hw_state(display, p, b); 5001 } 5002 5003 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state) 5004 { 5005 struct intel_display *display = to_intel_display(old_crtc_state); 5006 5007 /* 5008 * Allow fastboot to fix up vblank delay (handled via LRR 5009 * codepaths), a bit dodgy as the registers aren't 5010 * double buffered but seems to be working more or less... 5011 * 5012 * Also allow this when the VRR timing generator is always on, 5013 * and optimized guardband is used. In such cases, 5014 * vblank delay may vary even without inherited state, but it's 5015 * still safe as VRR guardband is still same. 5016 */ 5017 return HAS_LRR(display) && 5018 (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) && 5019 !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI); 5020 } 5021 5022 static void 5023 pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset, 5024 const struct intel_crtc *crtc, 5025 const char *name, 5026 const struct intel_lt_phy_pll_state *a, 5027 const struct intel_lt_phy_pll_state *b) 5028 { 5029 struct intel_display *display = to_intel_display(crtc); 5030 char *chipname = "LTPHY"; 5031 5032 pipe_config_mismatch(p, fastset, crtc, name, chipname); 5033 5034 drm_printf(p, "expected:\n"); 5035 intel_lt_phy_dump_hw_state(display, a); 5036 drm_printf(p, "found:\n"); 5037 intel_lt_phy_dump_hw_state(display, b); 5038 } 5039 5040 bool 5041 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5042 const struct intel_crtc_state *pipe_config, 5043 bool fastset) 5044 { 5045 struct intel_display *display = to_intel_display(current_config); 5046 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5047 struct drm_printer p; 5048 u32 exclude_infoframes = 0; 5049 bool ret = true; 5050 5051 if (fastset) 5052 p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL); 5053 else 5054 p = drm_err_printer(display->drm, NULL); 5055 5056 #define PIPE_CONF_CHECK_X(name) do { \ 5057 if (current_config->name != pipe_config->name) { \ 5058 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5059 __stringify(name) " is bool"); \ 5060 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5061 "(expected 0x%08x, found 0x%08x)", \ 5062 current_config->name, \ 5063 pipe_config->name); \ 5064 ret = false; \ 5065 } \ 5066 } while (0) 5067 5068 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5069 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5070 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5071 __stringify(name) " is bool"); \ 5072 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5073 "(expected 0x%08x, found 0x%08x)", \ 5074 current_config->name & (mask), \ 5075 pipe_config->name & (mask)); \ 5076 ret = false; \ 5077 } \ 5078 } while (0) 5079 5080 #define PIPE_CONF_CHECK_I(name) do { \ 5081 if (current_config->name != pipe_config->name) { \ 5082 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5083 __stringify(name) " is bool"); \ 5084 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5085 "(expected %i, found %i)", \ 5086 current_config->name, \ 5087 pipe_config->name); \ 5088 ret = false; \ 5089 } \ 5090 } while (0) 5091 5092 #define PIPE_CONF_CHECK_LLI(name) do { \ 5093 if (current_config->name != pipe_config->name) { \ 5094 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5095 "(expected %lli, found %lli)", \ 5096 current_config->name, \ 5097 pipe_config->name); \ 5098 ret = false; \ 5099 } \ 5100 } while (0) 5101 5102 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5103 if (current_config->name != pipe_config->name) { \ 5104 BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \ 5105 __stringify(name) " is not bool"); \ 5106 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5107 "(expected %s, found %s)", \ 5108 str_yes_no(current_config->name), \ 5109 str_yes_no(pipe_config->name)); \ 5110 ret = false; \ 5111 } \ 5112 } while (0) 5113 5114 #define PIPE_CONF_CHECK_P(name) do { \ 5115 if (current_config->name != pipe_config->name) { \ 5116 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5117 "(expected %p, found %p)", \ 5118 current_config->name, \ 5119 pipe_config->name); \ 5120 ret = false; \ 5121 } \ 5122 } while (0) 5123 5124 #define PIPE_CONF_CHECK_M_N(name) do { \ 5125 if (!intel_compare_link_m_n(¤t_config->name, \ 5126 &pipe_config->name)) { \ 5127 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5128 "(expected tu %i data %i/%i link %i/%i, " \ 5129 "found tu %i, data %i/%i link %i/%i)", \ 5130 current_config->name.tu, \ 5131 current_config->name.data_m, \ 5132 current_config->name.data_n, \ 5133 current_config->name.link_m, \ 5134 current_config->name.link_n, \ 5135 pipe_config->name.tu, \ 5136 pipe_config->name.data_m, \ 5137 pipe_config->name.data_n, \ 5138 pipe_config->name.link_m, \ 5139 pipe_config->name.link_n); \ 5140 ret = false; \ 5141 } \ 5142 } while (0) 5143 5144 #define PIPE_CONF_CHECK_PLL(name) do { \ 5145 if (!intel_dpll_compare_hw_state(display, ¤t_config->name, \ 5146 &pipe_config->name)) { \ 5147 pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5148 ¤t_config->name, \ 5149 &pipe_config->name); \ 5150 ret = false; \ 5151 } \ 5152 } while (0) 5153 5154 #define PIPE_CONF_CHECK_PLL_LT(name) do { \ 5155 if (!intel_lt_phy_pll_compare_hw_state(¤t_config->name, \ 5156 &pipe_config->name)) { \ 5157 pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5158 ¤t_config->name, \ 5159 &pipe_config->name); \ 5160 ret = false; \ 5161 } \ 5162 } while (0) 5163 5164 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5165 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5166 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5167 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5168 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5169 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5170 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5171 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5172 if (!fastset || !allow_vblank_delay_fastset(current_config)) \ 5173 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5174 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5175 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5176 if (!fastset || !pipe_config->update_lrr) { \ 5177 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5178 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5179 } \ 5180 } while (0) 5181 5182 #define PIPE_CONF_CHECK_RECT(name) do { \ 5183 PIPE_CONF_CHECK_I(name.x1); \ 5184 PIPE_CONF_CHECK_I(name.x2); \ 5185 PIPE_CONF_CHECK_I(name.y1); \ 5186 PIPE_CONF_CHECK_I(name.y2); \ 5187 } while (0) 5188 5189 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5190 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5191 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5192 "(%x) (expected %i, found %i)", \ 5193 (mask), \ 5194 current_config->name & (mask), \ 5195 pipe_config->name & (mask)); \ 5196 ret = false; \ 5197 } \ 5198 } while (0) 5199 5200 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5201 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5202 &pipe_config->infoframes.name)) { \ 5203 pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \ 5204 ¤t_config->infoframes.name, \ 5205 &pipe_config->infoframes.name); \ 5206 ret = false; \ 5207 } \ 5208 } while (0) 5209 5210 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5211 if (!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5212 &pipe_config->infoframes.name)) { \ 5213 pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \ 5214 ¤t_config->infoframes.name, \ 5215 &pipe_config->infoframes.name); \ 5216 ret = false; \ 5217 } \ 5218 } while (0) 5219 5220 #define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \ 5221 if (!intel_compare_dp_as_sdp(¤t_config->infoframes.name, \ 5222 &pipe_config->infoframes.name)) { \ 5223 pipe_config_dp_as_sdp_mismatch(&p, fastset, crtc, __stringify(name), \ 5224 ¤t_config->infoframes.name, \ 5225 &pipe_config->infoframes.name); \ 5226 ret = false; \ 5227 } \ 5228 } while (0) 5229 5230 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5231 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5232 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5233 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5234 pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \ 5235 current_config->name, \ 5236 pipe_config->name, \ 5237 (len)); \ 5238 ret = false; \ 5239 } \ 5240 } while (0) 5241 5242 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5243 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5244 !intel_color_lut_equal(current_config, \ 5245 current_config->lut, pipe_config->lut, \ 5246 is_pre_csc_lut)) { \ 5247 pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \ 5248 "hw_state doesn't match sw_state"); \ 5249 ret = false; \ 5250 } \ 5251 } while (0) 5252 5253 #define PIPE_CONF_CHECK_CSC(name) do { \ 5254 PIPE_CONF_CHECK_X(name.preoff[0]); \ 5255 PIPE_CONF_CHECK_X(name.preoff[1]); \ 5256 PIPE_CONF_CHECK_X(name.preoff[2]); \ 5257 PIPE_CONF_CHECK_X(name.coeff[0]); \ 5258 PIPE_CONF_CHECK_X(name.coeff[1]); \ 5259 PIPE_CONF_CHECK_X(name.coeff[2]); \ 5260 PIPE_CONF_CHECK_X(name.coeff[3]); \ 5261 PIPE_CONF_CHECK_X(name.coeff[4]); \ 5262 PIPE_CONF_CHECK_X(name.coeff[5]); \ 5263 PIPE_CONF_CHECK_X(name.coeff[6]); \ 5264 PIPE_CONF_CHECK_X(name.coeff[7]); \ 5265 PIPE_CONF_CHECK_X(name.coeff[8]); \ 5266 PIPE_CONF_CHECK_X(name.postoff[0]); \ 5267 PIPE_CONF_CHECK_X(name.postoff[1]); \ 5268 PIPE_CONF_CHECK_X(name.postoff[2]); \ 5269 } while (0) 5270 5271 #define PIPE_CONF_QUIRK(quirk) \ 5272 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5273 5274 PIPE_CONF_CHECK_BOOL(hw.enable); 5275 PIPE_CONF_CHECK_BOOL(hw.active); 5276 5277 PIPE_CONF_CHECK_I(cpu_transcoder); 5278 PIPE_CONF_CHECK_I(mst_master_transcoder); 5279 5280 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5281 PIPE_CONF_CHECK_I(fdi_lanes); 5282 PIPE_CONF_CHECK_M_N(fdi_m_n); 5283 5284 PIPE_CONF_CHECK_I(lane_count); 5285 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5286 5287 PIPE_CONF_CHECK_I(min_hblank); 5288 5289 if (HAS_DOUBLE_BUFFERED_M_N(display)) { 5290 if (!fastset || !pipe_config->update_m_n) 5291 PIPE_CONF_CHECK_M_N(dp_m_n); 5292 } else { 5293 PIPE_CONF_CHECK_M_N(dp_m_n); 5294 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5295 } 5296 5297 PIPE_CONF_CHECK_X(output_types); 5298 5299 PIPE_CONF_CHECK_I(framestart_delay); 5300 PIPE_CONF_CHECK_I(msa_timing_delay); 5301 5302 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5303 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5304 5305 PIPE_CONF_CHECK_I(pixel_multiplier); 5306 5307 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5308 DRM_MODE_FLAG_INTERLACE); 5309 5310 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5311 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5312 DRM_MODE_FLAG_PHSYNC); 5313 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5314 DRM_MODE_FLAG_NHSYNC); 5315 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5316 DRM_MODE_FLAG_PVSYNC); 5317 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5318 DRM_MODE_FLAG_NVSYNC); 5319 } 5320 5321 PIPE_CONF_CHECK_I(output_format); 5322 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5323 if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) || 5324 display->platform.valleyview || display->platform.cherryview) 5325 PIPE_CONF_CHECK_BOOL(limited_color_range); 5326 5327 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5328 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5329 PIPE_CONF_CHECK_BOOL(has_infoframe); 5330 PIPE_CONF_CHECK_BOOL(enhanced_framing); 5331 PIPE_CONF_CHECK_BOOL(fec_enable); 5332 5333 if (!fastset) { 5334 PIPE_CONF_CHECK_BOOL(has_audio); 5335 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5336 } 5337 5338 PIPE_CONF_CHECK_X(gmch_pfit.control); 5339 /* pfit ratios are autocomputed by the hw on gen4+ */ 5340 if (DISPLAY_VER(display) < 4) 5341 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5342 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5343 5344 /* 5345 * Changing the EDP transcoder input mux 5346 * (A_ONOFF vs. A_ON) requires a full modeset. 5347 */ 5348 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5349 5350 if (!fastset) { 5351 PIPE_CONF_CHECK_RECT(pipe_src); 5352 5353 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5354 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5355 5356 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5357 PIPE_CONF_CHECK_I(pixel_rate); 5358 PIPE_CONF_CHECK_BOOL(hw.casf_params.casf_enable); 5359 PIPE_CONF_CHECK_I(hw.casf_params.win_size); 5360 PIPE_CONF_CHECK_I(hw.casf_params.strength); 5361 5362 PIPE_CONF_CHECK_X(gamma_mode); 5363 if (display->platform.cherryview) 5364 PIPE_CONF_CHECK_X(cgm_mode); 5365 else 5366 PIPE_CONF_CHECK_X(csc_mode); 5367 PIPE_CONF_CHECK_BOOL(gamma_enable); 5368 PIPE_CONF_CHECK_BOOL(csc_enable); 5369 PIPE_CONF_CHECK_BOOL(wgc_enable); 5370 5371 PIPE_CONF_CHECK_I(linetime); 5372 PIPE_CONF_CHECK_I(ips_linetime); 5373 5374 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5375 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5376 5377 PIPE_CONF_CHECK_CSC(csc); 5378 PIPE_CONF_CHECK_CSC(output_csc); 5379 } 5380 5381 PIPE_CONF_CHECK_BOOL(double_wide); 5382 5383 if (display->dpll.mgr) 5384 PIPE_CONF_CHECK_P(intel_dpll); 5385 5386 /* FIXME convert everything over the dpll_mgr */ 5387 if (display->dpll.mgr || HAS_GMCH(display)) 5388 PIPE_CONF_CHECK_PLL(dpll_hw_state); 5389 5390 /* FIXME convert MTL+ platforms over to dpll_mgr */ 5391 if (HAS_LT_PHY(display)) 5392 PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll); 5393 5394 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5395 PIPE_CONF_CHECK_X(dsi_pll.div); 5396 5397 if (display->platform.g4x || DISPLAY_VER(display) >= 5) 5398 PIPE_CONF_CHECK_I(pipe_bpp); 5399 5400 if (!fastset || !pipe_config->update_m_n) { 5401 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5402 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5403 } 5404 PIPE_CONF_CHECK_I(port_clock); 5405 5406 PIPE_CONF_CHECK_I(min_voltage_level); 5407 5408 if (current_config->has_psr || pipe_config->has_psr) 5409 exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 5410 5411 if (current_config->vrr.enable || pipe_config->vrr.enable) 5412 exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); 5413 5414 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, ~exclude_infoframes); 5415 PIPE_CONF_CHECK_X(infoframes.gcp); 5416 PIPE_CONF_CHECK_INFOFRAME(avi); 5417 PIPE_CONF_CHECK_INFOFRAME(spd); 5418 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5419 if (!fastset) { 5420 PIPE_CONF_CHECK_INFOFRAME(drm); 5421 PIPE_CONF_CHECK_DP_AS_SDP(as_sdp); 5422 } 5423 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5424 5425 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5426 PIPE_CONF_CHECK_I(master_transcoder); 5427 PIPE_CONF_CHECK_X(joiner_pipes); 5428 5429 PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable); 5430 PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb); 5431 PIPE_CONF_CHECK_BOOL(dsc.config.simple_422); 5432 PIPE_CONF_CHECK_BOOL(dsc.config.native_422); 5433 PIPE_CONF_CHECK_BOOL(dsc.config.native_420); 5434 PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable); 5435 PIPE_CONF_CHECK_I(dsc.config.line_buf_depth); 5436 PIPE_CONF_CHECK_I(dsc.config.bits_per_component); 5437 PIPE_CONF_CHECK_I(dsc.config.pic_width); 5438 PIPE_CONF_CHECK_I(dsc.config.pic_height); 5439 PIPE_CONF_CHECK_I(dsc.config.slice_width); 5440 PIPE_CONF_CHECK_I(dsc.config.slice_height); 5441 PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay); 5442 PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay); 5443 PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval); 5444 PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval); 5445 PIPE_CONF_CHECK_I(dsc.config.initial_scale_value); 5446 PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset); 5447 PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp); 5448 PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp); 5449 PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset); 5450 PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset); 5451 PIPE_CONF_CHECK_I(dsc.config.initial_offset); 5452 PIPE_CONF_CHECK_I(dsc.config.final_offset); 5453 PIPE_CONF_CHECK_I(dsc.config.rc_model_size); 5454 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0); 5455 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1); 5456 PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size); 5457 PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset); 5458 PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset); 5459 5460 PIPE_CONF_CHECK_BOOL(dsc.compression_enable); 5461 PIPE_CONF_CHECK_I(dsc.num_streams); 5462 PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); 5463 5464 PIPE_CONF_CHECK_BOOL(splitter.enable); 5465 PIPE_CONF_CHECK_I(splitter.link_count); 5466 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5467 5468 if (!fastset) { 5469 PIPE_CONF_CHECK_BOOL(vrr.enable); 5470 PIPE_CONF_CHECK_I(vrr.vmin); 5471 PIPE_CONF_CHECK_I(vrr.vmax); 5472 PIPE_CONF_CHECK_I(vrr.flipline); 5473 PIPE_CONF_CHECK_I(vrr.vsync_start); 5474 PIPE_CONF_CHECK_I(vrr.vsync_end); 5475 PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); 5476 PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); 5477 PIPE_CONF_CHECK_BOOL(cmrr.enable); 5478 PIPE_CONF_CHECK_I(vrr.dc_balance.vmin); 5479 PIPE_CONF_CHECK_I(vrr.dc_balance.vmax); 5480 PIPE_CONF_CHECK_I(vrr.dc_balance.guardband); 5481 PIPE_CONF_CHECK_I(vrr.dc_balance.slope); 5482 PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase); 5483 PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease); 5484 PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target); 5485 } 5486 5487 if (!fastset || intel_vrr_always_use_vrr_tg(display)) { 5488 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5489 PIPE_CONF_CHECK_I(vrr.guardband); 5490 } 5491 5492 PIPE_CONF_CHECK_I(set_context_latency); 5493 5494 #undef PIPE_CONF_CHECK_X 5495 #undef PIPE_CONF_CHECK_I 5496 #undef PIPE_CONF_CHECK_LLI 5497 #undef PIPE_CONF_CHECK_BOOL 5498 #undef PIPE_CONF_CHECK_P 5499 #undef PIPE_CONF_CHECK_FLAGS 5500 #undef PIPE_CONF_CHECK_COLOR_LUT 5501 #undef PIPE_CONF_CHECK_TIMINGS 5502 #undef PIPE_CONF_CHECK_RECT 5503 #undef PIPE_CONF_QUIRK 5504 5505 return ret; 5506 } 5507 5508 static void 5509 intel_verify_planes(struct intel_atomic_state *state) 5510 { 5511 struct intel_plane *plane; 5512 const struct intel_plane_state *plane_state; 5513 int i; 5514 5515 for_each_new_intel_plane_in_state(state, plane, 5516 plane_state, i) 5517 assert_plane(plane, plane_state->is_y_plane || 5518 plane_state->uapi.visible); 5519 } 5520 5521 static int intel_modeset_pipe(struct intel_atomic_state *state, 5522 struct intel_crtc_state *crtc_state, 5523 const char *reason) 5524 { 5525 struct intel_display *display = to_intel_display(state); 5526 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5527 int ret; 5528 5529 drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5530 crtc->base.base.id, crtc->base.name, reason); 5531 5532 ret = drm_atomic_add_affected_connectors(&state->base, 5533 &crtc->base); 5534 if (ret) 5535 return ret; 5536 5537 ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc); 5538 if (ret) 5539 return ret; 5540 5541 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc); 5542 if (ret) 5543 return ret; 5544 5545 ret = intel_plane_add_affected(state, crtc); 5546 if (ret) 5547 return ret; 5548 5549 crtc_state->uapi.mode_changed = true; 5550 5551 return 0; 5552 } 5553 5554 /** 5555 * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes 5556 * @state: intel atomic state 5557 * @reason: the reason for the full modeset 5558 * @mask: mask of pipes to modeset 5559 * 5560 * Add pipes in @mask to @state and force a full modeset on the enabled ones 5561 * due to the description in @reason. 5562 * This function can be called only before new plane states are computed. 5563 * 5564 * Returns 0 in case of success, negative error code otherwise. 5565 */ 5566 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, 5567 const char *reason, u8 mask) 5568 { 5569 struct intel_display *display = to_intel_display(state); 5570 struct intel_crtc *crtc; 5571 5572 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) { 5573 struct intel_crtc_state *crtc_state; 5574 int ret; 5575 5576 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5577 if (IS_ERR(crtc_state)) 5578 return PTR_ERR(crtc_state); 5579 5580 if (!crtc_state->hw.enable || 5581 intel_crtc_needs_modeset(crtc_state)) 5582 continue; 5583 5584 ret = intel_modeset_pipe(state, crtc_state, reason); 5585 if (ret) 5586 return ret; 5587 } 5588 5589 return 0; 5590 } 5591 5592 static void 5593 intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state) 5594 { 5595 crtc_state->uapi.mode_changed = true; 5596 5597 crtc_state->update_pipe = false; 5598 crtc_state->update_m_n = false; 5599 crtc_state->update_lrr = false; 5600 } 5601 5602 /** 5603 * intel_modeset_all_pipes_late - force a full modeset on all pipes 5604 * @state: intel atomic state 5605 * @reason: the reason for the full modeset 5606 * 5607 * Add all pipes to @state and force a full modeset on the active ones due to 5608 * the description in @reason. 5609 * This function can be called only after new plane states are computed already. 5610 * 5611 * Returns 0 in case of success, negative error code otherwise. 5612 */ 5613 int intel_modeset_all_pipes_late(struct intel_atomic_state *state, 5614 const char *reason) 5615 { 5616 struct intel_display *display = to_intel_display(state); 5617 struct intel_crtc *crtc; 5618 5619 for_each_intel_crtc(display->drm, crtc) { 5620 struct intel_crtc_state *crtc_state; 5621 int ret; 5622 5623 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5624 if (IS_ERR(crtc_state)) 5625 return PTR_ERR(crtc_state); 5626 5627 if (!crtc_state->hw.active || 5628 intel_crtc_needs_modeset(crtc_state)) 5629 continue; 5630 5631 ret = intel_modeset_pipe(state, crtc_state, reason); 5632 if (ret) 5633 return ret; 5634 5635 intel_crtc_flag_modeset(crtc_state); 5636 5637 crtc_state->update_planes |= crtc_state->active_planes; 5638 crtc_state->async_flip_planes = 0; 5639 crtc_state->do_async_flip = false; 5640 } 5641 5642 return 0; 5643 } 5644 5645 int intel_modeset_commit_pipes(struct intel_display *display, 5646 u8 pipe_mask, 5647 struct drm_modeset_acquire_ctx *ctx) 5648 { 5649 struct drm_atomic_state *state; 5650 struct intel_crtc *crtc; 5651 int ret; 5652 5653 state = drm_atomic_state_alloc(display->drm); 5654 if (!state) 5655 return -ENOMEM; 5656 5657 state->acquire_ctx = ctx; 5658 to_intel_atomic_state(state)->internal = true; 5659 5660 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) { 5661 struct intel_crtc_state *crtc_state = 5662 intel_atomic_get_crtc_state(state, crtc); 5663 5664 if (IS_ERR(crtc_state)) { 5665 ret = PTR_ERR(crtc_state); 5666 goto out; 5667 } 5668 5669 crtc_state->uapi.connectors_changed = true; 5670 } 5671 5672 ret = drm_atomic_commit(state); 5673 out: 5674 drm_atomic_state_put(state); 5675 5676 return ret; 5677 } 5678 5679 /* 5680 * This implements the workaround described in the "notes" section of the mode 5681 * set sequence documentation. When going from no pipes or single pipe to 5682 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5683 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5684 */ 5685 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5686 { 5687 struct intel_crtc_state *crtc_state; 5688 struct intel_crtc *crtc; 5689 struct intel_crtc_state *first_crtc_state = NULL; 5690 struct intel_crtc_state *other_crtc_state = NULL; 5691 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5692 int i; 5693 5694 /* look at all crtc's that are going to be enabled in during modeset */ 5695 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5696 if (!crtc_state->hw.active || 5697 !intel_crtc_needs_modeset(crtc_state)) 5698 continue; 5699 5700 if (first_crtc_state) { 5701 other_crtc_state = crtc_state; 5702 break; 5703 } else { 5704 first_crtc_state = crtc_state; 5705 first_pipe = crtc->pipe; 5706 } 5707 } 5708 5709 /* No workaround needed? */ 5710 if (!first_crtc_state) 5711 return 0; 5712 5713 /* w/a possibly needed, check how many crtc's are already enabled. */ 5714 for_each_intel_crtc(state->base.dev, crtc) { 5715 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5716 if (IS_ERR(crtc_state)) 5717 return PTR_ERR(crtc_state); 5718 5719 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5720 5721 if (!crtc_state->hw.active || 5722 intel_crtc_needs_modeset(crtc_state)) 5723 continue; 5724 5725 /* 2 or more enabled crtcs means no need for w/a */ 5726 if (enabled_pipe != INVALID_PIPE) 5727 return 0; 5728 5729 enabled_pipe = crtc->pipe; 5730 } 5731 5732 if (enabled_pipe != INVALID_PIPE) 5733 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5734 else if (other_crtc_state) 5735 other_crtc_state->hsw_workaround_pipe = first_pipe; 5736 5737 return 0; 5738 } 5739 5740 u8 intel_calc_enabled_pipes(struct intel_atomic_state *state, 5741 u8 enabled_pipes) 5742 { 5743 const struct intel_crtc_state *crtc_state; 5744 struct intel_crtc *crtc; 5745 int i; 5746 5747 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5748 if (crtc_state->hw.enable) 5749 enabled_pipes |= BIT(crtc->pipe); 5750 else 5751 enabled_pipes &= ~BIT(crtc->pipe); 5752 } 5753 5754 return enabled_pipes; 5755 } 5756 5757 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5758 u8 active_pipes) 5759 { 5760 const struct intel_crtc_state *crtc_state; 5761 struct intel_crtc *crtc; 5762 int i; 5763 5764 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5765 if (crtc_state->hw.active) 5766 active_pipes |= BIT(crtc->pipe); 5767 else 5768 active_pipes &= ~BIT(crtc->pipe); 5769 } 5770 5771 return active_pipes; 5772 } 5773 5774 static int intel_modeset_checks(struct intel_atomic_state *state) 5775 { 5776 struct intel_display *display = to_intel_display(state); 5777 5778 state->modeset = true; 5779 5780 if (display->platform.haswell) 5781 return hsw_mode_set_planes_workaround(state); 5782 5783 return 0; 5784 } 5785 5786 static bool lrr_params_changed(const struct intel_crtc_state *old_crtc_state, 5787 const struct intel_crtc_state *new_crtc_state) 5788 { 5789 const struct drm_display_mode *old_adjusted_mode = &old_crtc_state->hw.adjusted_mode; 5790 const struct drm_display_mode *new_adjusted_mode = &new_crtc_state->hw.adjusted_mode; 5791 5792 return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start || 5793 old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end || 5794 old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal || 5795 old_crtc_state->set_context_latency != new_crtc_state->set_context_latency; 5796 } 5797 5798 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 5799 struct intel_crtc_state *new_crtc_state) 5800 { 5801 struct intel_display *display = to_intel_display(new_crtc_state); 5802 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 5803 5804 /* only allow LRR when the timings stay within the VRR range */ 5805 if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range) 5806 new_crtc_state->update_lrr = false; 5807 5808 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) { 5809 drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n", 5810 crtc->base.base.id, crtc->base.name); 5811 } else { 5812 if (allow_vblank_delay_fastset(old_crtc_state)) 5813 new_crtc_state->update_lrr = true; 5814 new_crtc_state->uapi.mode_changed = false; 5815 } 5816 5817 if (intel_compare_link_m_n(&old_crtc_state->dp_m_n, 5818 &new_crtc_state->dp_m_n)) 5819 new_crtc_state->update_m_n = false; 5820 5821 if (!lrr_params_changed(old_crtc_state, new_crtc_state)) 5822 new_crtc_state->update_lrr = false; 5823 5824 if (intel_crtc_needs_modeset(new_crtc_state)) 5825 intel_crtc_flag_modeset(new_crtc_state); 5826 else 5827 new_crtc_state->update_pipe = true; 5828 } 5829 5830 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 5831 { 5832 struct intel_display *display = to_intel_display(state); 5833 struct intel_crtc_state __maybe_unused *crtc_state; 5834 struct intel_crtc *crtc; 5835 int i; 5836 5837 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5838 int ret; 5839 5840 ret = intel_crtc_atomic_check(state, crtc); 5841 if (ret) { 5842 drm_dbg_atomic(display->drm, 5843 "[CRTC:%d:%s] atomic driver check failed\n", 5844 crtc->base.base.id, crtc->base.name); 5845 return ret; 5846 } 5847 } 5848 5849 return 0; 5850 } 5851 5852 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 5853 u8 transcoders) 5854 { 5855 const struct intel_crtc_state *new_crtc_state; 5856 struct intel_crtc *crtc; 5857 int i; 5858 5859 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5860 if (new_crtc_state->hw.enable && 5861 transcoders & BIT(new_crtc_state->cpu_transcoder) && 5862 intel_crtc_needs_modeset(new_crtc_state)) 5863 return true; 5864 } 5865 5866 return false; 5867 } 5868 5869 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 5870 u8 pipes) 5871 { 5872 const struct intel_crtc_state *new_crtc_state; 5873 struct intel_crtc *crtc; 5874 int i; 5875 5876 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5877 if (new_crtc_state->hw.enable && 5878 pipes & BIT(crtc->pipe) && 5879 intel_crtc_needs_modeset(new_crtc_state)) 5880 return true; 5881 } 5882 5883 return false; 5884 } 5885 5886 static int intel_atomic_check_joiner(struct intel_atomic_state *state, 5887 struct intel_crtc *primary_crtc) 5888 { 5889 struct intel_display *display = to_intel_display(state); 5890 struct intel_crtc_state *primary_crtc_state = 5891 intel_atomic_get_new_crtc_state(state, primary_crtc); 5892 struct intel_crtc *secondary_crtc; 5893 5894 if (!primary_crtc_state->joiner_pipes) 5895 return 0; 5896 5897 /* sanity check */ 5898 if (drm_WARN_ON(display->drm, 5899 primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state))) 5900 return -EINVAL; 5901 5902 if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) { 5903 drm_dbg_kms(display->drm, 5904 "[CRTC:%d:%s] Cannot act as joiner primary " 5905 "(need 0x%x as pipes, only 0x%x possible)\n", 5906 primary_crtc->base.base.id, primary_crtc->base.name, 5907 primary_crtc_state->joiner_pipes, joiner_pipes(display)); 5908 return -EINVAL; 5909 } 5910 5911 for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc, 5912 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { 5913 struct intel_crtc_state *secondary_crtc_state; 5914 int ret; 5915 5916 secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc); 5917 if (IS_ERR(secondary_crtc_state)) 5918 return PTR_ERR(secondary_crtc_state); 5919 5920 /* primary being enabled, secondary was already configured? */ 5921 if (secondary_crtc_state->uapi.enable) { 5922 drm_dbg_kms(display->drm, 5923 "[CRTC:%d:%s] secondary is enabled as normal CRTC, but " 5924 "[CRTC:%d:%s] claiming this CRTC for joiner.\n", 5925 secondary_crtc->base.base.id, secondary_crtc->base.name, 5926 primary_crtc->base.base.id, primary_crtc->base.name); 5927 return -EINVAL; 5928 } 5929 5930 /* 5931 * The state copy logic assumes the primary crtc gets processed 5932 * before the secondary crtc during the main compute_config loop. 5933 * This works because the crtcs are created in pipe order, 5934 * and the hardware requires primary pipe < secondary pipe as well. 5935 * Should that change we need to rethink the logic. 5936 */ 5937 if (WARN_ON(drm_crtc_index(&primary_crtc->base) > 5938 drm_crtc_index(&secondary_crtc->base))) 5939 return -EINVAL; 5940 5941 drm_dbg_kms(display->drm, 5942 "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n", 5943 secondary_crtc->base.base.id, secondary_crtc->base.name, 5944 primary_crtc->base.base.id, primary_crtc->base.name); 5945 5946 secondary_crtc_state->joiner_pipes = 5947 primary_crtc_state->joiner_pipes; 5948 5949 ret = copy_joiner_crtc_state_modeset(state, secondary_crtc); 5950 if (ret) 5951 return ret; 5952 } 5953 5954 return 0; 5955 } 5956 5957 static void kill_joiner_secondaries(struct intel_atomic_state *state, 5958 struct intel_crtc *primary_crtc) 5959 { 5960 struct intel_display *display = to_intel_display(state); 5961 struct intel_crtc_state *primary_crtc_state = 5962 intel_atomic_get_new_crtc_state(state, primary_crtc); 5963 struct intel_crtc *secondary_crtc; 5964 5965 for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc, 5966 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { 5967 struct intel_crtc_state *secondary_crtc_state = 5968 intel_atomic_get_new_crtc_state(state, secondary_crtc); 5969 5970 secondary_crtc_state->joiner_pipes = 0; 5971 5972 intel_crtc_copy_uapi_to_hw_state_modeset(state, secondary_crtc); 5973 } 5974 5975 primary_crtc_state->joiner_pipes = 0; 5976 } 5977 5978 /** 5979 * DOC: asynchronous flip implementation 5980 * 5981 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 5982 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 5983 * Correspondingly, support is currently added for primary plane only. 5984 * 5985 * Async flip can only change the plane surface address, so anything else 5986 * changing is rejected from the intel_async_flip_check_hw() function. 5987 * Once this check is cleared, flip done interrupt is enabled using 5988 * the intel_crtc_enable_flip_done() function. 5989 * 5990 * As soon as the surface address register is written, flip done interrupt is 5991 * generated and the requested events are sent to the userspace in the interrupt 5992 * handler itself. The timestamp and sequence sent during the flip done event 5993 * correspond to the last vblank and have no relation to the actual time when 5994 * the flip done event was sent. 5995 */ 5996 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 5997 struct intel_crtc *crtc) 5998 { 5999 struct intel_display *display = to_intel_display(state); 6000 const struct intel_crtc_state *new_crtc_state = 6001 intel_atomic_get_new_crtc_state(state, crtc); 6002 const struct intel_plane_state *old_plane_state; 6003 struct intel_plane_state *new_plane_state; 6004 struct intel_plane *plane; 6005 int i; 6006 6007 if (!new_crtc_state->uapi.async_flip) 6008 return 0; 6009 6010 if (!new_crtc_state->uapi.active) { 6011 drm_dbg_kms(display->drm, 6012 "[CRTC:%d:%s] not active\n", 6013 crtc->base.base.id, crtc->base.name); 6014 return -EINVAL; 6015 } 6016 6017 if (intel_crtc_needs_modeset(new_crtc_state)) { 6018 drm_dbg_kms(display->drm, 6019 "[CRTC:%d:%s] modeset required\n", 6020 crtc->base.base.id, crtc->base.name); 6021 return -EINVAL; 6022 } 6023 6024 /* 6025 * FIXME: joiner+async flip is busted currently. 6026 * Remove this check once the issues are fixed. 6027 */ 6028 if (new_crtc_state->joiner_pipes) { 6029 drm_dbg_kms(display->drm, 6030 "[CRTC:%d:%s] async flip disallowed with joiner\n", 6031 crtc->base.base.id, crtc->base.name); 6032 return -EINVAL; 6033 } 6034 6035 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6036 new_plane_state, i) { 6037 if (plane->pipe != crtc->pipe) 6038 continue; 6039 6040 /* 6041 * TODO: Async flip is only supported through the page flip IOCTL 6042 * as of now. So support currently added for primary plane only. 6043 * Support for other planes on platforms on which supports 6044 * this(vlv/chv and icl+) should be added when async flip is 6045 * enabled in the atomic IOCTL path. 6046 */ 6047 if (!plane->async_flip) { 6048 drm_dbg_kms(display->drm, 6049 "[PLANE:%d:%s] async flip not supported\n", 6050 plane->base.base.id, plane->base.name); 6051 return -EINVAL; 6052 } 6053 6054 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6055 drm_dbg_kms(display->drm, 6056 "[PLANE:%d:%s] no old or new framebuffer\n", 6057 plane->base.base.id, plane->base.name); 6058 return -EINVAL; 6059 } 6060 } 6061 6062 return 0; 6063 } 6064 6065 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6066 { 6067 struct intel_display *display = to_intel_display(state); 6068 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6069 const struct intel_plane_state *new_plane_state, *old_plane_state; 6070 struct intel_plane *plane; 6071 int i; 6072 6073 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6074 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6075 6076 if (!new_crtc_state->uapi.async_flip) 6077 return 0; 6078 6079 if (!new_crtc_state->hw.active) { 6080 drm_dbg_kms(display->drm, 6081 "[CRTC:%d:%s] not active\n", 6082 crtc->base.base.id, crtc->base.name); 6083 return -EINVAL; 6084 } 6085 6086 if (intel_crtc_needs_modeset(new_crtc_state)) { 6087 drm_dbg_kms(display->drm, 6088 "[CRTC:%d:%s] modeset required\n", 6089 crtc->base.base.id, crtc->base.name); 6090 return -EINVAL; 6091 } 6092 6093 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 6094 drm_dbg_kms(display->drm, 6095 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 6096 crtc->base.base.id, crtc->base.name); 6097 return -EINVAL; 6098 } 6099 6100 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6101 new_plane_state, i) { 6102 if (plane->pipe != crtc->pipe) 6103 continue; 6104 6105 /* 6106 * Only async flip capable planes should be in the state 6107 * if we're really about to ask the hardware to perform 6108 * an async flip. We should never get this far otherwise. 6109 */ 6110 if (drm_WARN_ON(display->drm, 6111 new_crtc_state->do_async_flip && !plane->async_flip)) 6112 return -EINVAL; 6113 6114 /* 6115 * Only check async flip capable planes other planes 6116 * may be involved in the initial commit due to 6117 * the wm0/ddb optimization. 6118 * 6119 * TODO maybe should track which planes actually 6120 * were requested to do the async flip... 6121 */ 6122 if (!plane->async_flip) 6123 continue; 6124 6125 if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format, 6126 new_plane_state->hw.fb->modifier)) { 6127 drm_dbg_kms(display->drm, 6128 "[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n", 6129 plane->base.base.id, plane->base.name, 6130 &new_plane_state->hw.fb->format->format, 6131 new_plane_state->hw.fb->modifier); 6132 return -EINVAL; 6133 } 6134 6135 /* 6136 * We turn the first async flip request into a sync flip 6137 * so that we can reconfigure the plane (eg. change modifier). 6138 */ 6139 if (!new_crtc_state->do_async_flip) 6140 continue; 6141 6142 if (old_plane_state->view.color_plane[0].mapping_stride != 6143 new_plane_state->view.color_plane[0].mapping_stride) { 6144 drm_dbg_kms(display->drm, 6145 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6146 plane->base.base.id, plane->base.name); 6147 return -EINVAL; 6148 } 6149 6150 if (old_plane_state->hw.fb->modifier != 6151 new_plane_state->hw.fb->modifier) { 6152 drm_dbg_kms(display->drm, 6153 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6154 plane->base.base.id, plane->base.name); 6155 return -EINVAL; 6156 } 6157 6158 if (old_plane_state->hw.fb->format != 6159 new_plane_state->hw.fb->format) { 6160 drm_dbg_kms(display->drm, 6161 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6162 plane->base.base.id, plane->base.name); 6163 return -EINVAL; 6164 } 6165 6166 if (old_plane_state->hw.rotation != 6167 new_plane_state->hw.rotation) { 6168 drm_dbg_kms(display->drm, 6169 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6170 plane->base.base.id, plane->base.name); 6171 return -EINVAL; 6172 } 6173 6174 if (skl_plane_aux_dist(old_plane_state, 0) != 6175 skl_plane_aux_dist(new_plane_state, 0)) { 6176 drm_dbg_kms(display->drm, 6177 "[PLANE:%d:%s] AUX_DIST cannot be changed in async flip\n", 6178 plane->base.base.id, plane->base.name); 6179 return -EINVAL; 6180 } 6181 6182 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6183 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6184 drm_dbg_kms(display->drm, 6185 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6186 plane->base.base.id, plane->base.name); 6187 return -EINVAL; 6188 } 6189 6190 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6191 drm_dbg_kms(display->drm, 6192 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6193 plane->base.base.id, plane->base.name); 6194 return -EINVAL; 6195 } 6196 6197 if (old_plane_state->hw.pixel_blend_mode != 6198 new_plane_state->hw.pixel_blend_mode) { 6199 drm_dbg_kms(display->drm, 6200 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6201 plane->base.base.id, plane->base.name); 6202 return -EINVAL; 6203 } 6204 6205 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6206 drm_dbg_kms(display->drm, 6207 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6208 plane->base.base.id, plane->base.name); 6209 return -EINVAL; 6210 } 6211 6212 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6213 drm_dbg_kms(display->drm, 6214 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6215 plane->base.base.id, plane->base.name); 6216 return -EINVAL; 6217 } 6218 6219 /* plane decryption is allow to change only in synchronous flips */ 6220 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6221 drm_dbg_kms(display->drm, 6222 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6223 plane->base.base.id, plane->base.name); 6224 return -EINVAL; 6225 } 6226 } 6227 6228 return 0; 6229 } 6230 6231 static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state) 6232 { 6233 struct intel_display *display = to_intel_display(state); 6234 const struct intel_plane_state *plane_state; 6235 struct intel_crtc_state *crtc_state; 6236 struct intel_plane *plane; 6237 struct intel_crtc *crtc; 6238 u8 affected_pipes = 0; 6239 u8 modeset_pipes = 0; 6240 int i; 6241 6242 /* 6243 * Any plane which is in use by the joiner needs its crtc. 6244 * Pull those in first as this will not have happened yet 6245 * if the plane remains disabled according to uapi. 6246 */ 6247 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6248 crtc = to_intel_crtc(plane_state->hw.crtc); 6249 if (!crtc) 6250 continue; 6251 6252 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6253 if (IS_ERR(crtc_state)) 6254 return PTR_ERR(crtc_state); 6255 } 6256 6257 /* Now pull in all joined crtcs */ 6258 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6259 affected_pipes |= crtc_state->joiner_pipes; 6260 if (intel_crtc_needs_modeset(crtc_state)) 6261 modeset_pipes |= crtc_state->joiner_pipes; 6262 } 6263 6264 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) { 6265 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6266 if (IS_ERR(crtc_state)) 6267 return PTR_ERR(crtc_state); 6268 } 6269 6270 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) { 6271 int ret; 6272 6273 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6274 6275 crtc_state->uapi.mode_changed = true; 6276 6277 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6278 if (ret) 6279 return ret; 6280 6281 ret = intel_plane_add_affected(state, crtc); 6282 if (ret) 6283 return ret; 6284 } 6285 6286 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6287 /* Kill old joiner link, we may re-establish afterwards */ 6288 if (intel_crtc_needs_modeset(crtc_state) && 6289 intel_crtc_is_joiner_primary(crtc_state)) 6290 kill_joiner_secondaries(state, crtc); 6291 } 6292 6293 return 0; 6294 } 6295 6296 static int intel_atomic_check_config(struct intel_atomic_state *state, 6297 struct intel_link_bw_limits *limits, 6298 enum pipe *failed_pipe) 6299 { 6300 struct intel_display *display = to_intel_display(state); 6301 struct intel_crtc_state *new_crtc_state; 6302 struct intel_crtc *crtc; 6303 int ret; 6304 int i; 6305 6306 *failed_pipe = INVALID_PIPE; 6307 6308 ret = intel_joiner_add_affected_crtcs(state); 6309 if (ret) 6310 return ret; 6311 6312 ret = intel_fdi_add_affected_crtcs(state); 6313 if (ret) 6314 return ret; 6315 6316 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6317 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6318 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 6319 copy_joiner_crtc_state_nomodeset(state, crtc); 6320 else 6321 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6322 continue; 6323 } 6324 6325 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) 6326 continue; 6327 6328 ret = intel_crtc_prepare_cleared_state(state, crtc); 6329 if (ret) 6330 goto fail; 6331 6332 if (!new_crtc_state->hw.enable) 6333 continue; 6334 6335 ret = intel_modeset_pipe_config(state, crtc, limits); 6336 if (ret) 6337 goto fail; 6338 } 6339 6340 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6341 if (!intel_crtc_needs_modeset(new_crtc_state)) 6342 continue; 6343 6344 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) 6345 continue; 6346 6347 if (!new_crtc_state->hw.enable) 6348 continue; 6349 6350 ret = intel_modeset_pipe_config_late(state, crtc); 6351 if (ret) 6352 goto fail; 6353 } 6354 6355 fail: 6356 if (ret) 6357 *failed_pipe = crtc->pipe; 6358 6359 return ret; 6360 } 6361 6362 static int intel_atomic_check_config_and_link(struct intel_atomic_state *state) 6363 { 6364 struct intel_link_bw_limits new_limits; 6365 struct intel_link_bw_limits old_limits; 6366 int ret; 6367 6368 intel_link_bw_init_limits(state, &new_limits); 6369 old_limits = new_limits; 6370 6371 while (true) { 6372 enum pipe failed_pipe; 6373 6374 ret = intel_atomic_check_config(state, &new_limits, 6375 &failed_pipe); 6376 if (ret) { 6377 /* 6378 * The bpp limit for a pipe is below the minimum it supports, set the 6379 * limit to the minimum and recalculate the config. 6380 */ 6381 if (ret == -EINVAL && 6382 intel_link_bw_set_bpp_limit_for_pipe(state, 6383 &old_limits, 6384 &new_limits, 6385 failed_pipe)) 6386 continue; 6387 6388 break; 6389 } 6390 6391 old_limits = new_limits; 6392 6393 ret = intel_link_bw_atomic_check(state, &new_limits); 6394 if (ret != -EAGAIN) 6395 break; 6396 } 6397 6398 return ret; 6399 } 6400 /** 6401 * intel_atomic_check - validate state object 6402 * @dev: drm device 6403 * @_state: state to validate 6404 */ 6405 int intel_atomic_check(struct drm_device *dev, 6406 struct drm_atomic_state *_state) 6407 { 6408 struct intel_display *display = to_intel_display(dev); 6409 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6410 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6411 struct intel_crtc *crtc; 6412 int ret, i; 6413 6414 if (!intel_display_driver_check_access(display)) 6415 return -ENODEV; 6416 6417 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6418 new_crtc_state, i) { 6419 /* 6420 * crtc's state no longer considered to be inherited 6421 * after the first userspace/client initiated commit. 6422 */ 6423 if (!state->internal) 6424 new_crtc_state->inherited = false; 6425 6426 if (new_crtc_state->inherited != old_crtc_state->inherited) 6427 new_crtc_state->uapi.mode_changed = true; 6428 6429 if (new_crtc_state->uapi.scaling_filter != 6430 old_crtc_state->uapi.scaling_filter) 6431 new_crtc_state->uapi.mode_changed = true; 6432 } 6433 6434 intel_vrr_check_modeset(state); 6435 6436 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6437 if (ret) 6438 goto fail; 6439 6440 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6441 ret = intel_async_flip_check_uapi(state, crtc); 6442 if (ret) 6443 return ret; 6444 } 6445 6446 ret = intel_atomic_check_config_and_link(state); 6447 if (ret) 6448 goto fail; 6449 6450 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6451 if (!intel_crtc_needs_modeset(new_crtc_state)) 6452 continue; 6453 6454 if (intel_crtc_is_joiner_secondary(new_crtc_state)) { 6455 drm_WARN_ON(display->drm, new_crtc_state->uapi.enable); 6456 continue; 6457 } 6458 6459 ret = intel_atomic_check_joiner(state, crtc); 6460 if (ret) 6461 goto fail; 6462 } 6463 6464 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6465 new_crtc_state, i) { 6466 if (!intel_crtc_needs_modeset(new_crtc_state)) 6467 continue; 6468 6469 intel_joiner_adjust_pipe_src(new_crtc_state); 6470 6471 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6472 } 6473 6474 /** 6475 * Check if fastset is allowed by external dependencies like other 6476 * pipes and transcoders. 6477 * 6478 * Right now it only forces a fullmodeset when the MST master 6479 * transcoder did not changed but the pipe of the master transcoder 6480 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6481 * in case of port synced crtcs, if one of the synced crtcs 6482 * needs a full modeset, all other synced crtcs should be 6483 * forced a full modeset. 6484 */ 6485 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6486 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6487 continue; 6488 6489 if (intel_dp_mst_crtc_needs_modeset(state, crtc)) 6490 intel_crtc_flag_modeset(new_crtc_state); 6491 6492 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6493 enum transcoder master = new_crtc_state->mst_master_transcoder; 6494 6495 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) 6496 intel_crtc_flag_modeset(new_crtc_state); 6497 } 6498 6499 if (is_trans_port_sync_mode(new_crtc_state)) { 6500 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6501 6502 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6503 trans |= BIT(new_crtc_state->master_transcoder); 6504 6505 if (intel_cpu_transcoders_need_modeset(state, trans)) 6506 intel_crtc_flag_modeset(new_crtc_state); 6507 } 6508 6509 if (new_crtc_state->joiner_pipes) { 6510 if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes)) 6511 intel_crtc_flag_modeset(new_crtc_state); 6512 } 6513 } 6514 6515 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6516 new_crtc_state, i) { 6517 if (!intel_crtc_needs_modeset(new_crtc_state)) 6518 continue; 6519 6520 intel_dpll_release(state, crtc); 6521 } 6522 6523 if (intel_any_crtc_needs_modeset(state) && !check_digital_port_conflicts(state)) { 6524 drm_dbg_kms(display->drm, "rejecting conflicting digital port configuration\n"); 6525 ret = -EINVAL; 6526 goto fail; 6527 } 6528 6529 ret = intel_plane_atomic_check(state); 6530 if (ret) 6531 goto fail; 6532 6533 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 6534 new_crtc_state->min_cdclk = intel_crtc_min_cdclk(new_crtc_state); 6535 6536 ret = intel_compute_global_watermarks(state); 6537 if (ret) 6538 goto fail; 6539 6540 ret = intel_bw_atomic_check(state); 6541 if (ret) 6542 goto fail; 6543 6544 ret = intel_cdclk_atomic_check(state); 6545 if (ret) 6546 goto fail; 6547 6548 if (intel_any_crtc_needs_modeset(state)) { 6549 ret = intel_modeset_checks(state); 6550 if (ret) 6551 goto fail; 6552 } 6553 6554 ret = intel_pmdemand_atomic_check(state); 6555 if (ret) 6556 goto fail; 6557 6558 ret = intel_atomic_check_crtcs(state); 6559 if (ret) 6560 goto fail; 6561 6562 ret = intel_fbc_atomic_check(state); 6563 if (ret) 6564 goto fail; 6565 6566 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6567 new_crtc_state, i) { 6568 intel_color_assert_luts(new_crtc_state); 6569 6570 ret = intel_async_flip_check_hw(state, crtc); 6571 if (ret) 6572 goto fail; 6573 6574 /* Either full modeset or fastset (or neither), never both */ 6575 drm_WARN_ON(display->drm, 6576 intel_crtc_needs_modeset(new_crtc_state) && 6577 intel_crtc_needs_fastset(new_crtc_state)); 6578 6579 if (!intel_crtc_needs_modeset(new_crtc_state) && 6580 !intel_crtc_needs_fastset(new_crtc_state)) 6581 continue; 6582 6583 intel_crtc_state_dump(new_crtc_state, state, 6584 intel_crtc_needs_modeset(new_crtc_state) ? 6585 "modeset" : "fastset"); 6586 } 6587 6588 return 0; 6589 6590 fail: 6591 if (ret == -EDEADLK) 6592 return ret; 6593 6594 /* 6595 * FIXME would probably be nice to know which crtc specifically 6596 * caused the failure, in cases where we can pinpoint it. 6597 */ 6598 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6599 new_crtc_state, i) 6600 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6601 6602 return ret; 6603 } 6604 6605 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6606 { 6607 int ret; 6608 6609 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6610 if (ret < 0) 6611 return ret; 6612 6613 return 0; 6614 } 6615 6616 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6617 struct intel_crtc_state *crtc_state) 6618 { 6619 struct intel_display *display = to_intel_display(crtc); 6620 6621 if (DISPLAY_VER(display) != 2 || crtc_state->active_planes) 6622 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); 6623 6624 if (crtc_state->has_pch_encoder) { 6625 enum pipe pch_transcoder = 6626 intel_crtc_pch_transcoder(crtc); 6627 6628 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true); 6629 } 6630 } 6631 6632 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6633 const struct intel_crtc_state *new_crtc_state) 6634 { 6635 struct intel_display *display = to_intel_display(new_crtc_state); 6636 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6637 6638 /* 6639 * Update pipe size and adjust fitter if needed: the reason for this is 6640 * that in compute_mode_changes we check the native mode (not the pfit 6641 * mode) to see if we can flip rather than do a full mode set. In the 6642 * fastboot case, we'll flip, but if we don't update the pipesrc and 6643 * pfit state, we'll end up with a big fb scanned out into the wrong 6644 * sized surface. 6645 */ 6646 intel_set_pipe_src_size(new_crtc_state); 6647 6648 /* on skylake this is done by detaching scalers */ 6649 if (DISPLAY_VER(display) >= 9) { 6650 if (new_crtc_state->pch_pfit.enabled) 6651 skl_pfit_enable(new_crtc_state); 6652 } else if (HAS_PCH_SPLIT(display)) { 6653 if (new_crtc_state->pch_pfit.enabled) 6654 ilk_pfit_enable(new_crtc_state); 6655 else if (old_crtc_state->pch_pfit.enabled) 6656 ilk_pfit_disable(old_crtc_state); 6657 } 6658 6659 /* 6660 * The register is supposedly single buffered so perhaps 6661 * not 100% correct to do this here. But SKL+ calculate 6662 * this based on the adjust pixel rate so pfit changes do 6663 * affect it and so it must be updated for fastsets. 6664 * HSW/BDW only really need this here for fastboot, after 6665 * that the value should not change without a full modeset. 6666 */ 6667 if (DISPLAY_VER(display) >= 9 || 6668 display->platform.broadwell || display->platform.haswell) 6669 hsw_set_linetime_wm(new_crtc_state); 6670 6671 if (new_crtc_state->update_m_n) 6672 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6673 &new_crtc_state->dp_m_n); 6674 6675 if (new_crtc_state->update_lrr) 6676 intel_set_transcoder_timings_lrr(new_crtc_state); 6677 } 6678 6679 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6680 struct intel_crtc *crtc) 6681 { 6682 struct intel_display *display = to_intel_display(state); 6683 const struct intel_crtc_state *old_crtc_state = 6684 intel_atomic_get_old_crtc_state(state, crtc); 6685 const struct intel_crtc_state *new_crtc_state = 6686 intel_atomic_get_new_crtc_state(state, crtc); 6687 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6688 6689 drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq); 6690 6691 /* 6692 * During modesets pipe configuration was programmed as the 6693 * CRTC was enabled. 6694 */ 6695 if (!modeset) { 6696 if (intel_crtc_needs_color_update(new_crtc_state)) 6697 intel_color_commit_arm(NULL, new_crtc_state); 6698 6699 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) 6700 bdw_set_pipe_misc(NULL, new_crtc_state); 6701 6702 if (intel_crtc_needs_fastset(new_crtc_state)) 6703 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6704 } 6705 6706 intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state); 6707 6708 intel_atomic_update_watermarks(state, crtc); 6709 } 6710 6711 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6712 struct intel_crtc *crtc) 6713 { 6714 struct intel_display *display = to_intel_display(state); 6715 const struct intel_crtc_state *new_crtc_state = 6716 intel_atomic_get_new_crtc_state(state, crtc); 6717 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6718 6719 drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq); 6720 6721 /* 6722 * Disable the scaler(s) after the plane(s) so that we don't 6723 * get a catastrophic underrun even if the two operations 6724 * end up happening in two different frames. 6725 */ 6726 if (DISPLAY_VER(display) >= 9 && !modeset) 6727 skl_detach_scalers(NULL, new_crtc_state); 6728 6729 if (!modeset && 6730 intel_crtc_needs_color_update(new_crtc_state) && 6731 !intel_color_uses_dsb(new_crtc_state) && 6732 HAS_DOUBLE_BUFFERED_LUT(display)) 6733 intel_color_load_luts(new_crtc_state); 6734 6735 if (intel_crtc_vrr_enabling(state, crtc)) 6736 intel_vrr_enable(new_crtc_state); 6737 } 6738 6739 static void intel_enable_crtc(struct intel_atomic_state *state, 6740 struct intel_crtc *crtc) 6741 { 6742 struct intel_display *display = to_intel_display(state); 6743 const struct intel_crtc_state *new_crtc_state = 6744 intel_atomic_get_new_crtc_state(state, crtc); 6745 struct intel_crtc *pipe_crtc; 6746 6747 if (!intel_crtc_needs_modeset(new_crtc_state)) 6748 return; 6749 6750 for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc, 6751 intel_crtc_joined_pipe_mask(new_crtc_state)) { 6752 const struct intel_crtc_state *pipe_crtc_state = 6753 intel_atomic_get_new_crtc_state(state, pipe_crtc); 6754 6755 /* VRR will be enable later, if required */ 6756 intel_crtc_update_active_timings(pipe_crtc_state, false); 6757 } 6758 6759 intel_psr_notify_pipe_change(state, crtc, true); 6760 6761 display->funcs.display->crtc_enable(state, crtc); 6762 6763 /* vblanks work again, re-enable pipe CRC. */ 6764 intel_crtc_enable_pipe_crc(crtc); 6765 } 6766 6767 static void intel_pre_update_crtc(struct intel_atomic_state *state, 6768 struct intel_crtc *crtc) 6769 { 6770 struct intel_display *display = to_intel_display(state); 6771 const struct intel_crtc_state *old_crtc_state = 6772 intel_atomic_get_old_crtc_state(state, crtc); 6773 struct intel_crtc_state *new_crtc_state = 6774 intel_atomic_get_new_crtc_state(state, crtc); 6775 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6776 6777 if (old_crtc_state->inherited || 6778 intel_crtc_needs_modeset(new_crtc_state)) { 6779 if (HAS_DPT(display)) 6780 intel_dpt_configure(crtc); 6781 } 6782 6783 if (!modeset) { 6784 if (new_crtc_state->preload_luts && 6785 intel_crtc_needs_color_update(new_crtc_state)) 6786 intel_color_load_luts(new_crtc_state); 6787 6788 intel_pre_plane_update(state, crtc); 6789 6790 if (intel_crtc_needs_fastset(new_crtc_state)) 6791 intel_encoders_update_pipe(state, crtc); 6792 6793 if (DISPLAY_VER(display) >= 11 && 6794 intel_crtc_needs_fastset(new_crtc_state)) 6795 icl_set_pipe_chicken(new_crtc_state); 6796 6797 if (vrr_params_changed(old_crtc_state, new_crtc_state) || 6798 cmrr_params_changed(old_crtc_state, new_crtc_state)) 6799 intel_vrr_set_transcoder_timings(new_crtc_state); 6800 } 6801 6802 if (intel_casf_enabling(new_crtc_state, old_crtc_state)) 6803 intel_casf_enable(new_crtc_state); 6804 else if (new_crtc_state->hw.casf_params.strength != old_crtc_state->hw.casf_params.strength) 6805 intel_casf_update_strength(new_crtc_state); 6806 6807 intel_fbc_update(state, crtc); 6808 6809 drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF)); 6810 6811 if (!modeset && 6812 intel_crtc_needs_color_update(new_crtc_state) && 6813 !new_crtc_state->use_dsb && !new_crtc_state->use_flipq) 6814 intel_color_commit_noarm(NULL, new_crtc_state); 6815 6816 if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq) 6817 intel_crtc_planes_update_noarm(NULL, state, crtc); 6818 } 6819 6820 static void intel_update_crtc(struct intel_atomic_state *state, 6821 struct intel_crtc *crtc) 6822 { 6823 const struct intel_crtc_state *old_crtc_state = 6824 intel_atomic_get_old_crtc_state(state, crtc); 6825 struct intel_crtc_state *new_crtc_state = 6826 intel_atomic_get_new_crtc_state(state, crtc); 6827 6828 if (new_crtc_state->use_flipq) { 6829 intel_flipq_enable(new_crtc_state); 6830 6831 intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->flipq_event); 6832 6833 intel_flipq_add(crtc, INTEL_FLIPQ_PLANE_1, 0, INTEL_DSB_0, 6834 new_crtc_state->dsb_commit); 6835 } else if (new_crtc_state->use_dsb) { 6836 intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event); 6837 6838 intel_dsb_commit(new_crtc_state->dsb_commit); 6839 } else { 6840 /* Perform vblank evasion around commit operation */ 6841 intel_pipe_update_start(state, crtc); 6842 6843 if (new_crtc_state->dsb_commit) 6844 intel_dsb_commit(new_crtc_state->dsb_commit); 6845 6846 commit_pipe_pre_planes(state, crtc); 6847 6848 intel_crtc_planes_update_arm(NULL, state, crtc); 6849 6850 commit_pipe_post_planes(state, crtc); 6851 6852 intel_pipe_update_end(state, crtc); 6853 } 6854 6855 /* 6856 * VRR/Seamless M/N update may need to update frame timings. 6857 * 6858 * FIXME Should be synchronized with the start of vblank somehow... 6859 */ 6860 if (intel_crtc_vrr_enabling(state, crtc) || 6861 new_crtc_state->update_m_n || new_crtc_state->update_lrr) 6862 intel_crtc_update_active_timings(new_crtc_state, 6863 new_crtc_state->vrr.enable); 6864 6865 if (new_crtc_state->vrr.dc_balance.enable) 6866 intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc); 6867 6868 /* 6869 * We usually enable FIFO underrun interrupts as part of the 6870 * CRTC enable sequence during modesets. But when we inherit a 6871 * valid pipe configuration from the BIOS we need to take care 6872 * of enabling them on the CRTC's first fastset. 6873 */ 6874 if (intel_crtc_needs_fastset(new_crtc_state) && 6875 old_crtc_state->inherited) 6876 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 6877 } 6878 6879 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 6880 struct intel_crtc *crtc) 6881 { 6882 struct intel_display *display = to_intel_display(state); 6883 const struct intel_crtc_state *old_crtc_state = 6884 intel_atomic_get_old_crtc_state(state, crtc); 6885 struct intel_crtc *pipe_crtc; 6886 6887 /* 6888 * We need to disable pipe CRC before disabling the pipe, 6889 * or we race against vblank off. 6890 */ 6891 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 6892 intel_crtc_joined_pipe_mask(old_crtc_state)) 6893 intel_crtc_disable_pipe_crc(pipe_crtc); 6894 6895 intel_psr_notify_pipe_change(state, crtc, false); 6896 6897 display->funcs.display->crtc_disable(state, crtc); 6898 6899 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 6900 intel_crtc_joined_pipe_mask(old_crtc_state)) { 6901 const struct intel_crtc_state *new_pipe_crtc_state = 6902 intel_atomic_get_new_crtc_state(state, pipe_crtc); 6903 6904 pipe_crtc->active = false; 6905 intel_fbc_disable(pipe_crtc); 6906 6907 if (!new_pipe_crtc_state->hw.active) 6908 intel_initial_watermarks(state, pipe_crtc); 6909 } 6910 } 6911 6912 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 6913 { 6914 struct intel_display *display = to_intel_display(state); 6915 const struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6916 struct intel_crtc *crtc; 6917 u8 disable_pipes = 0; 6918 int i; 6919 6920 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6921 new_crtc_state, i) { 6922 if (!intel_crtc_needs_modeset(new_crtc_state)) 6923 continue; 6924 6925 /* 6926 * Needs to be done even for pipes 6927 * that weren't enabled previously. 6928 */ 6929 intel_pre_plane_update(state, crtc); 6930 6931 if (!old_crtc_state->hw.active) 6932 continue; 6933 6934 disable_pipes |= BIT(crtc->pipe); 6935 } 6936 6937 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) { 6938 if ((disable_pipes & BIT(crtc->pipe)) == 0) 6939 continue; 6940 6941 intel_crtc_disable_planes(state, crtc); 6942 6943 drm_vblank_work_flush_all(&crtc->base); 6944 } 6945 6946 /* Only disable port sync and MST slaves */ 6947 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) { 6948 if ((disable_pipes & BIT(crtc->pipe)) == 0) 6949 continue; 6950 6951 if (intel_crtc_is_joiner_secondary(old_crtc_state)) 6952 continue; 6953 6954 /* In case of Transcoder port Sync master slave CRTCs can be 6955 * assigned in any order and we need to make sure that 6956 * slave CRTCs are disabled first and then master CRTC since 6957 * Slave vblanks are masked till Master Vblanks. 6958 */ 6959 if (!is_trans_port_sync_slave(old_crtc_state) && 6960 !intel_dp_mst_is_slave_trans(old_crtc_state)) 6961 continue; 6962 6963 intel_old_crtc_state_disables(state, crtc); 6964 6965 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); 6966 } 6967 6968 /* Disable everything else left on */ 6969 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) { 6970 if ((disable_pipes & BIT(crtc->pipe)) == 0) 6971 continue; 6972 6973 if (intel_crtc_is_joiner_secondary(old_crtc_state)) 6974 continue; 6975 6976 intel_old_crtc_state_disables(state, crtc); 6977 6978 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); 6979 } 6980 6981 drm_WARN_ON(display->drm, disable_pipes); 6982 } 6983 6984 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 6985 { 6986 struct intel_crtc_state *new_crtc_state; 6987 struct intel_crtc *crtc; 6988 int i; 6989 6990 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6991 if (!new_crtc_state->hw.active) 6992 continue; 6993 6994 intel_enable_crtc(state, crtc); 6995 intel_pre_update_crtc(state, crtc); 6996 } 6997 6998 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6999 if (!new_crtc_state->hw.active) 7000 continue; 7001 7002 intel_update_crtc(state, crtc); 7003 } 7004 } 7005 7006 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7007 { 7008 struct intel_display *display = to_intel_display(state); 7009 struct intel_crtc *crtc; 7010 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7011 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7012 u8 update_pipes = 0, modeset_pipes = 0; 7013 int i; 7014 7015 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7016 enum pipe pipe = crtc->pipe; 7017 7018 if (!new_crtc_state->hw.active) 7019 continue; 7020 7021 /* ignore allocations for crtc's that have been turned off. */ 7022 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7023 entries[pipe] = old_crtc_state->wm.skl.ddb; 7024 update_pipes |= BIT(pipe); 7025 } else { 7026 modeset_pipes |= BIT(pipe); 7027 } 7028 } 7029 7030 /* 7031 * Whenever the number of active pipes changes, we need to make sure we 7032 * update the pipes in the right order so that their ddb allocations 7033 * never overlap with each other between CRTC updates. Otherwise we'll 7034 * cause pipe underruns and other bad stuff. 7035 * 7036 * So first lets enable all pipes that do not need a fullmodeset as 7037 * those don't have any external dependency. 7038 */ 7039 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7040 enum pipe pipe = crtc->pipe; 7041 7042 if ((update_pipes & BIT(pipe)) == 0) 7043 continue; 7044 7045 intel_pre_update_crtc(state, crtc); 7046 } 7047 7048 intel_dbuf_mbus_pre_ddb_update(state); 7049 7050 while (update_pipes) { 7051 /* 7052 * Commit in reverse order to make joiner primary 7053 * send the uapi events after secondaries are done. 7054 */ 7055 for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state, 7056 new_crtc_state, i) { 7057 enum pipe pipe = crtc->pipe; 7058 7059 if ((update_pipes & BIT(pipe)) == 0) 7060 continue; 7061 7062 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7063 entries, I915_MAX_PIPES, pipe)) 7064 continue; 7065 7066 entries[pipe] = new_crtc_state->wm.skl.ddb; 7067 update_pipes &= ~BIT(pipe); 7068 7069 intel_update_crtc(state, crtc); 7070 7071 /* 7072 * If this is an already active pipe, it's DDB changed, 7073 * and this isn't the last pipe that needs updating 7074 * then we need to wait for a vblank to pass for the 7075 * new ddb allocation to take effect. 7076 */ 7077 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7078 &old_crtc_state->wm.skl.ddb) && 7079 (update_pipes | modeset_pipes)) 7080 intel_crtc_wait_for_next_vblank(crtc); 7081 } 7082 } 7083 7084 intel_dbuf_mbus_post_ddb_update(state); 7085 7086 update_pipes = modeset_pipes; 7087 7088 /* 7089 * Enable all pipes that needs a modeset and do not depends on other 7090 * pipes 7091 */ 7092 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7093 enum pipe pipe = crtc->pipe; 7094 7095 if ((modeset_pipes & BIT(pipe)) == 0) 7096 continue; 7097 7098 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 7099 continue; 7100 7101 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7102 is_trans_port_sync_master(new_crtc_state)) 7103 continue; 7104 7105 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); 7106 7107 intel_enable_crtc(state, crtc); 7108 } 7109 7110 /* 7111 * Then we enable all remaining pipes that depend on other 7112 * pipes: MST slaves and port sync masters 7113 */ 7114 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7115 enum pipe pipe = crtc->pipe; 7116 7117 if ((modeset_pipes & BIT(pipe)) == 0) 7118 continue; 7119 7120 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 7121 continue; 7122 7123 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); 7124 7125 intel_enable_crtc(state, crtc); 7126 } 7127 7128 /* 7129 * Finally we do the plane updates/etc. for all pipes that got enabled. 7130 */ 7131 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7132 enum pipe pipe = crtc->pipe; 7133 7134 if ((update_pipes & BIT(pipe)) == 0) 7135 continue; 7136 7137 intel_pre_update_crtc(state, crtc); 7138 } 7139 7140 /* 7141 * Commit in reverse order to make joiner primary 7142 * send the uapi events after secondaries are done. 7143 */ 7144 for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) { 7145 enum pipe pipe = crtc->pipe; 7146 7147 if ((update_pipes & BIT(pipe)) == 0) 7148 continue; 7149 7150 drm_WARN_ON(display->drm, 7151 skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7152 entries, I915_MAX_PIPES, pipe)); 7153 7154 entries[pipe] = new_crtc_state->wm.skl.ddb; 7155 update_pipes &= ~BIT(pipe); 7156 7157 intel_update_crtc(state, crtc); 7158 } 7159 7160 drm_WARN_ON(display->drm, modeset_pipes); 7161 drm_WARN_ON(display->drm, update_pipes); 7162 } 7163 7164 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7165 { 7166 struct drm_plane *plane; 7167 struct drm_plane_state *new_plane_state; 7168 long ret; 7169 int i; 7170 7171 for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) { 7172 if (new_plane_state->fence) { 7173 ret = dma_fence_wait_timeout(new_plane_state->fence, false, 7174 i915_fence_timeout()); 7175 if (ret <= 0) 7176 break; 7177 7178 dma_fence_put(new_plane_state->fence); 7179 new_plane_state->fence = NULL; 7180 } 7181 } 7182 } 7183 7184 static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state) 7185 { 7186 if (crtc_state->dsb_commit) 7187 intel_dsb_wait(crtc_state->dsb_commit); 7188 7189 intel_color_wait_commit(crtc_state); 7190 } 7191 7192 static void intel_atomic_dsb_cleanup(struct intel_crtc_state *crtc_state) 7193 { 7194 if (crtc_state->dsb_commit) { 7195 intel_dsb_cleanup(crtc_state->dsb_commit); 7196 crtc_state->dsb_commit = NULL; 7197 } 7198 7199 intel_color_cleanup_commit(crtc_state); 7200 } 7201 7202 static void intel_atomic_cleanup_work(struct work_struct *work) 7203 { 7204 struct intel_atomic_state *state = 7205 container_of(work, struct intel_atomic_state, cleanup_work); 7206 struct intel_display *display = to_intel_display(state); 7207 struct intel_crtc_state *old_crtc_state; 7208 struct intel_crtc *crtc; 7209 int i; 7210 7211 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 7212 intel_atomic_dsb_cleanup(old_crtc_state); 7213 7214 drm_atomic_helper_cleanup_planes(display->drm, &state->base); 7215 drm_atomic_helper_commit_cleanup_done(&state->base); 7216 drm_atomic_state_put(&state->base); 7217 } 7218 7219 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7220 { 7221 struct intel_display *display = to_intel_display(state); 7222 struct intel_plane *plane; 7223 struct intel_plane_state *plane_state; 7224 int i; 7225 7226 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7227 struct drm_framebuffer *fb = plane_state->hw.fb; 7228 int cc_plane; 7229 int ret; 7230 7231 if (!fb) 7232 continue; 7233 7234 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7235 if (cc_plane < 0) 7236 continue; 7237 7238 /* 7239 * The layout of the fast clear color value expected by HW 7240 * (the DRM ABI requiring this value to be located in fb at 7241 * offset 0 of cc plane, plane #2 previous generations or 7242 * plane #1 for flat ccs): 7243 * - 4 x 4 bytes per-channel value 7244 * (in surface type specific float/int format provided by the fb user) 7245 * - 8 bytes native color value used by the display 7246 * (converted/written by GPU during a fast clear operation using the 7247 * above per-channel values) 7248 * 7249 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7250 * caller made sure that the object is synced wrt. the related color clear value 7251 * GPU write on it. 7252 */ 7253 ret = intel_bo_read_from_page(intel_fb_bo(fb), 7254 fb->offsets[cc_plane] + 16, 7255 &plane_state->ccval, 7256 sizeof(plane_state->ccval)); 7257 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7258 drm_WARN_ON(display->drm, ret); 7259 } 7260 } 7261 7262 static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, 7263 struct intel_crtc *crtc) 7264 { 7265 struct intel_display *display = to_intel_display(state); 7266 struct intel_crtc_state *new_crtc_state = 7267 intel_atomic_get_new_crtc_state(state, crtc); 7268 7269 if (!new_crtc_state->hw.active) 7270 return; 7271 7272 if (state->base.legacy_cursor_update) 7273 return; 7274 7275 /* FIXME deal with everything */ 7276 new_crtc_state->use_flipq = 7277 intel_flipq_supported(display) && 7278 !new_crtc_state->do_async_flip && 7279 !new_crtc_state->vrr.enable && 7280 !new_crtc_state->has_psr && 7281 !intel_crtc_needs_modeset(new_crtc_state) && 7282 !intel_crtc_needs_fastset(new_crtc_state) && 7283 !intel_crtc_needs_color_update(new_crtc_state); 7284 7285 new_crtc_state->use_dsb = 7286 !new_crtc_state->use_flipq && 7287 !new_crtc_state->do_async_flip && 7288 (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && 7289 !intel_crtc_needs_modeset(new_crtc_state) && 7290 !intel_crtc_needs_fastset(new_crtc_state); 7291 7292 intel_color_prepare_commit(state, crtc); 7293 } 7294 7295 static void intel_atomic_dsb_finish(struct intel_atomic_state *state, 7296 struct intel_crtc *crtc) 7297 { 7298 struct intel_display *display = to_intel_display(state); 7299 struct intel_crtc_state *new_crtc_state = 7300 intel_atomic_get_new_crtc_state(state, crtc); 7301 unsigned int size = new_crtc_state->plane_color_changed ? 8192 : 1024; 7302 7303 if (!new_crtc_state->use_flipq && 7304 !new_crtc_state->use_dsb && 7305 !new_crtc_state->dsb_color) 7306 return; 7307 7308 /* 7309 * Rough estimate: 7310 * ~64 registers per each plane * 8 planes = 512 7311 * Double that for pipe stuff and other overhead. 7312 * ~4913 registers for 3DLUT 7313 * ~200 color registers * 3 HDR planes 7314 */ 7315 new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 7316 new_crtc_state->use_dsb || 7317 new_crtc_state->use_flipq ? size : 16); 7318 if (!new_crtc_state->dsb_commit) { 7319 new_crtc_state->use_flipq = false; 7320 new_crtc_state->use_dsb = false; 7321 intel_color_cleanup_commit(new_crtc_state); 7322 return; 7323 } 7324 7325 if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) { 7326 /* Wa_18034343758 */ 7327 if (new_crtc_state->use_flipq) 7328 intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc); 7329 7330 if (new_crtc_state->vrr.dc_balance.enable) { 7331 /* 7332 * Pause the DMC DC balancing for the remainder of 7333 * the commit so that vmin/vmax won't change after 7334 * we've baked them into the DSB vblank evasion 7335 * commands. 7336 * 7337 * FIXME maybe need a small delay here to make sure 7338 * DMC has finished updating the values? Or we need 7339 * a better DMC<->driver protocol that gives is real 7340 * guarantees about that... 7341 */ 7342 intel_pipedmc_dcb_disable(NULL, crtc); 7343 } 7344 7345 if (intel_crtc_needs_color_update(new_crtc_state)) 7346 intel_color_commit_noarm(new_crtc_state->dsb_commit, 7347 new_crtc_state); 7348 intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit, 7349 state, crtc); 7350 7351 /* 7352 * Ensure we have "Frame Change" event when PSR state is 7353 * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank 7354 * evasion hangs as PIPEDSL is reading as 0. 7355 */ 7356 intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit, 7357 state, crtc); 7358 7359 intel_psr_wait_for_idle_dsb(new_crtc_state->dsb_commit, 7360 new_crtc_state); 7361 7362 if (new_crtc_state->use_dsb) 7363 intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit); 7364 7365 if (intel_crtc_needs_color_update(new_crtc_state)) 7366 intel_color_commit_arm(new_crtc_state->dsb_commit, 7367 new_crtc_state); 7368 bdw_set_pipe_misc(new_crtc_state->dsb_commit, 7369 new_crtc_state); 7370 intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit, 7371 new_crtc_state); 7372 intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, 7373 state, crtc); 7374 7375 if (DISPLAY_VER(display) >= 9) 7376 skl_detach_scalers(new_crtc_state->dsb_commit, 7377 new_crtc_state); 7378 7379 /* Wa_18034343758 */ 7380 if (new_crtc_state->use_flipq) 7381 intel_flipq_unhalt_dmc(new_crtc_state->dsb_commit, crtc); 7382 } 7383 7384 if (intel_color_uses_chained_dsb(new_crtc_state)) 7385 intel_dsb_chain(state, new_crtc_state->dsb_commit, 7386 new_crtc_state->dsb_color, true); 7387 else if (intel_color_uses_gosub_dsb(new_crtc_state)) 7388 intel_dsb_gosub(new_crtc_state->dsb_commit, 7389 new_crtc_state->dsb_color); 7390 7391 if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) { 7392 intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); 7393 7394 intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); 7395 intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit); 7396 intel_vrr_check_push_sent(new_crtc_state->dsb_commit, 7397 new_crtc_state); 7398 7399 if (new_crtc_state->vrr.dc_balance.enable) 7400 intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc); 7401 7402 intel_dsb_interrupt(new_crtc_state->dsb_commit); 7403 } 7404 7405 intel_dsb_finish(new_crtc_state->dsb_commit); 7406 } 7407 7408 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7409 { 7410 struct intel_display *display = to_intel_display(state); 7411 struct intel_uncore *uncore = to_intel_uncore(display->drm); 7412 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7413 struct intel_crtc *crtc; 7414 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7415 struct ref_tracker *wakeref = NULL; 7416 int i; 7417 7418 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7419 intel_atomic_dsb_prepare(state, crtc); 7420 7421 intel_atomic_commit_fence_wait(state); 7422 7423 intel_td_flush(display); 7424 7425 intel_atomic_prepare_plane_clear_colors(state); 7426 7427 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7428 intel_fbc_prepare_dirty_rect(state, crtc); 7429 7430 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7431 intel_atomic_dsb_finish(state, crtc); 7432 7433 drm_atomic_helper_wait_for_dependencies(&state->base); 7434 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 7435 intel_atomic_global_state_wait_for_dependencies(state); 7436 7437 /* 7438 * During full modesets we write a lot of registers, wait 7439 * for PLLs, etc. Doing that while DC states are enabled 7440 * is not a good idea. 7441 * 7442 * During fastsets and other updates we also need to 7443 * disable DC states due to the following scenario: 7444 * 1. DC5 exit and PSR exit happen 7445 * 2. Some or all _noarm() registers are written 7446 * 3. Due to some long delay PSR is re-entered 7447 * 4. DC5 entry -> DMC saves the already written new 7448 * _noarm() registers and the old not yet written 7449 * _arm() registers 7450 * 5. DC5 exit -> DMC restores a mixture of old and 7451 * new register values and arms the update 7452 * 6. PSR exit -> hardware latches a mixture of old and 7453 * new register values -> corrupted frame, or worse 7454 * 7. New _arm() registers are finally written 7455 * 8. Hardware finally latches a complete set of new 7456 * register values, and subsequent frames will be OK again 7457 * 7458 * Also note that due to the pipe CSC hardware issues on 7459 * SKL/GLK DC states must remain off until the pipe CSC 7460 * state readout has happened. Otherwise we risk corrupting 7461 * the CSC latched register values with the readout (see 7462 * skl_read_csc() and skl_color_commit_noarm()). 7463 */ 7464 wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); 7465 7466 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7467 new_crtc_state, i) { 7468 if (intel_crtc_needs_modeset(new_crtc_state) || 7469 intel_crtc_needs_fastset(new_crtc_state)) 7470 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7471 } 7472 7473 intel_commit_modeset_disables(state); 7474 7475 intel_dp_tunnel_atomic_alloc_bw(state); 7476 7477 /* FIXME: Eventually get rid of our crtc->config pointer */ 7478 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7479 crtc->config = new_crtc_state; 7480 7481 /* 7482 * In XE_LPD+ Pmdemand combines many parameters such as voltage index, 7483 * plls, cdclk frequency, QGV point selection parameter etc. Voltage 7484 * index, cdclk/ddiclk frequencies are supposed to be configured before 7485 * the cdclk config is set. 7486 */ 7487 intel_pmdemand_pre_plane_update(state); 7488 7489 if (state->modeset) 7490 drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base); 7491 7492 intel_set_cdclk_pre_plane_update(state); 7493 7494 if (state->modeset) 7495 intel_modeset_verify_disabled(state); 7496 7497 intel_sagv_pre_plane_update(state); 7498 7499 /* Complete the events for pipes that have now been disabled */ 7500 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7501 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7502 7503 /* Complete events for now disable pipes here. */ 7504 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7505 spin_lock_irq(&display->drm->event_lock); 7506 drm_crtc_send_vblank_event(&crtc->base, 7507 new_crtc_state->uapi.event); 7508 spin_unlock_irq(&display->drm->event_lock); 7509 7510 new_crtc_state->uapi.event = NULL; 7511 } 7512 } 7513 7514 intel_encoders_update_prepare(state); 7515 7516 intel_dbuf_pre_plane_update(state); 7517 7518 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7519 if (new_crtc_state->do_async_flip) 7520 intel_crtc_enable_flip_done(state, crtc); 7521 } 7522 7523 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7524 display->funcs.display->commit_modeset_enables(state); 7525 7526 /* FIXME probably need to sequence this properly */ 7527 intel_program_dpkgc_latency(state); 7528 7529 intel_wait_for_vblank_workers(state); 7530 7531 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7532 * already, but still need the state for the delayed optimization. To 7533 * fix this: 7534 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7535 * - schedule that vblank worker _before_ calling hw_done 7536 * - at the start of commit_tail, cancel it _synchrously 7537 * - switch over to the vblank wait helper in the core after that since 7538 * we don't need out special handling any more. 7539 */ 7540 drm_atomic_helper_wait_for_flip_done(display->drm, &state->base); 7541 7542 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7543 if (new_crtc_state->do_async_flip) 7544 intel_crtc_disable_flip_done(state, crtc); 7545 7546 intel_atomic_dsb_wait_commit(new_crtc_state); 7547 7548 if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb) 7549 intel_vrr_check_push_sent(NULL, new_crtc_state); 7550 7551 if (new_crtc_state->use_flipq) 7552 intel_flipq_disable(new_crtc_state); 7553 } 7554 7555 /* 7556 * Now that the vblank has passed, we can go ahead and program the 7557 * optimal watermarks on platforms that need two-step watermark 7558 * programming. 7559 * 7560 * TODO: Move this (and other cleanup) to an async worker eventually. 7561 */ 7562 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7563 new_crtc_state, i) { 7564 /* 7565 * Gen2 reports pipe underruns whenever all planes are disabled. 7566 * So re-enable underrun reporting after some planes get enabled. 7567 * 7568 * We do this before .optimize_watermarks() so that we have a 7569 * chance of catching underruns with the intermediate watermarks 7570 * vs. the new plane configuration. 7571 */ 7572 if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7573 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); 7574 7575 intel_optimize_watermarks(state, crtc); 7576 } 7577 7578 intel_dbuf_post_plane_update(state); 7579 7580 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7581 intel_post_plane_update(state, crtc); 7582 7583 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7584 7585 intel_modeset_verify_crtc(state, crtc); 7586 7587 intel_post_plane_update_after_readout(state, crtc); 7588 7589 /* 7590 * DSB cleanup is done in cleanup_work aligning with framebuffer 7591 * cleanup. So copy and reset the dsb structure to sync with 7592 * commit_done and later do dsb cleanup in cleanup_work. 7593 * 7594 * FIXME get rid of this funny new->old swapping 7595 */ 7596 old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color); 7597 old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit); 7598 } 7599 7600 /* Underruns don't always raise interrupts, so check manually */ 7601 intel_check_cpu_fifo_underruns(display); 7602 intel_check_pch_fifo_underruns(display); 7603 7604 if (state->modeset) 7605 intel_verify_planes(state); 7606 7607 intel_sagv_post_plane_update(state); 7608 intel_set_cdclk_post_plane_update(state); 7609 intel_pmdemand_post_plane_update(state); 7610 7611 drm_atomic_helper_commit_hw_done(&state->base); 7612 intel_atomic_global_state_commit_done(state); 7613 7614 if (state->modeset) { 7615 /* As one of the primary mmio accessors, KMS has a high 7616 * likelihood of triggering bugs in unclaimed access. After we 7617 * finish modesetting, see if an error has been flagged, and if 7618 * so enable debugging for the next modeset - and hope we catch 7619 * the culprit. 7620 */ 7621 intel_uncore_arm_unclaimed_mmio_detection(uncore); 7622 } 7623 /* 7624 * Delay re-enabling DC states by 17 ms to avoid the off->on->off 7625 * toggling overhead at and above 60 FPS. 7626 */ 7627 intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17); 7628 intel_display_rpm_put(display, state->wakeref); 7629 7630 /* 7631 * Defer the cleanup of the old state to a separate worker to not 7632 * impede the current task (userspace for blocking modesets) that 7633 * are executed inline. For out-of-line asynchronous modesets/flips, 7634 * deferring to a new worker seems overkill, but we would place a 7635 * schedule point (cond_resched()) here anyway to keep latencies 7636 * down. 7637 */ 7638 INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work); 7639 queue_work(display->wq.cleanup, &state->cleanup_work); 7640 } 7641 7642 static void intel_atomic_commit_work(struct work_struct *work) 7643 { 7644 struct intel_atomic_state *state = 7645 container_of(work, struct intel_atomic_state, base.commit_work); 7646 7647 intel_atomic_commit_tail(state); 7648 } 7649 7650 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7651 { 7652 struct intel_plane_state *old_plane_state, *new_plane_state; 7653 struct intel_plane *plane; 7654 int i; 7655 7656 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7657 new_plane_state, i) 7658 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7659 to_intel_frontbuffer(new_plane_state->hw.fb), 7660 plane->frontbuffer_bit); 7661 } 7662 7663 static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock) 7664 { 7665 int ret; 7666 7667 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7668 if (ret) 7669 return ret; 7670 7671 ret = intel_atomic_global_state_setup_commit(state); 7672 if (ret) 7673 return ret; 7674 7675 return 0; 7676 } 7677 7678 static int intel_atomic_swap_state(struct intel_atomic_state *state) 7679 { 7680 int ret; 7681 7682 ret = drm_atomic_helper_swap_state(&state->base, true); 7683 if (ret) 7684 return ret; 7685 7686 intel_atomic_swap_global_state(state); 7687 7688 intel_dpll_swap_state(state); 7689 7690 intel_atomic_track_fbs(state); 7691 7692 return 0; 7693 } 7694 7695 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 7696 bool nonblock) 7697 { 7698 struct intel_display *display = to_intel_display(dev); 7699 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7700 int ret = 0; 7701 7702 state->wakeref = intel_display_rpm_get(display); 7703 7704 /* 7705 * The intel_legacy_cursor_update() fast path takes care 7706 * of avoiding the vblank waits for simple cursor 7707 * movement and flips. For cursor on/off and size changes, 7708 * we want to perform the vblank waits so that watermark 7709 * updates happen during the correct frames. Gen9+ have 7710 * double buffered watermarks and so shouldn't need this. 7711 * 7712 * Unset state->legacy_cursor_update before the call to 7713 * drm_atomic_helper_setup_commit() because otherwise 7714 * drm_atomic_helper_wait_for_flip_done() is a noop and 7715 * we get FIFO underruns because we didn't wait 7716 * for vblank. 7717 * 7718 * FIXME doing watermarks and fb cleanup from a vblank worker 7719 * (assuming we had any) would solve these problems. 7720 */ 7721 if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) { 7722 struct intel_crtc_state *new_crtc_state; 7723 struct intel_crtc *crtc; 7724 int i; 7725 7726 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7727 if (new_crtc_state->wm.need_postvbl_update || 7728 new_crtc_state->update_wm_post) 7729 state->base.legacy_cursor_update = false; 7730 } 7731 7732 ret = intel_atomic_prepare_commit(state); 7733 if (ret) { 7734 drm_dbg_atomic(display->drm, 7735 "Preparing state failed with %i\n", ret); 7736 intel_display_rpm_put(display, state->wakeref); 7737 return ret; 7738 } 7739 7740 ret = intel_atomic_setup_commit(state, nonblock); 7741 if (!ret) 7742 ret = intel_atomic_swap_state(state); 7743 7744 if (ret) { 7745 drm_atomic_helper_unprepare_planes(dev, &state->base); 7746 intel_display_rpm_put(display, state->wakeref); 7747 return ret; 7748 } 7749 7750 drm_atomic_state_get(&state->base); 7751 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7752 7753 if (nonblock && state->modeset) { 7754 queue_work(display->wq.modeset, &state->base.commit_work); 7755 } else if (nonblock) { 7756 queue_work(display->wq.flip, &state->base.commit_work); 7757 } else { 7758 if (state->modeset) 7759 flush_workqueue(display->wq.modeset); 7760 intel_atomic_commit_tail(state); 7761 } 7762 7763 return 0; 7764 } 7765 7766 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7767 { 7768 struct intel_display *display = to_intel_display(encoder); 7769 struct intel_encoder *source_encoder; 7770 u32 possible_clones = 0; 7771 7772 for_each_intel_encoder(display->drm, source_encoder) { 7773 if (encoders_cloneable(encoder, source_encoder)) 7774 possible_clones |= drm_encoder_mask(&source_encoder->base); 7775 } 7776 7777 return possible_clones; 7778 } 7779 7780 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7781 { 7782 struct intel_display *display = to_intel_display(encoder); 7783 struct intel_crtc *crtc; 7784 u32 possible_crtcs = 0; 7785 7786 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask) 7787 possible_crtcs |= drm_crtc_mask(&crtc->base); 7788 7789 return possible_crtcs; 7790 } 7791 7792 static bool ilk_has_edp_a(struct intel_display *display) 7793 { 7794 if (!display->platform.mobile) 7795 return false; 7796 7797 if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0) 7798 return false; 7799 7800 if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7801 return false; 7802 7803 return true; 7804 } 7805 7806 static bool intel_ddi_crt_present(struct intel_display *display) 7807 { 7808 if (DISPLAY_VER(display) >= 9) 7809 return false; 7810 7811 if (display->platform.haswell_ult || display->platform.broadwell_ult) 7812 return false; 7813 7814 if (HAS_PCH_LPT_H(display) && 7815 intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7816 return false; 7817 7818 /* DDI E can't be used if DDI A requires 4 lanes */ 7819 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7820 return false; 7821 7822 if (!display->vbt.int_crt_support) 7823 return false; 7824 7825 return true; 7826 } 7827 7828 bool assert_port_valid(struct intel_display *display, enum port port) 7829 { 7830 return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)), 7831 "Platform does not support port %c\n", port_name(port)); 7832 } 7833 7834 void intel_setup_outputs(struct intel_display *display) 7835 { 7836 struct intel_encoder *encoder; 7837 bool dpd_is_edp = false; 7838 7839 intel_pps_unlock_regs_wa(display); 7840 7841 if (!HAS_DISPLAY(display)) 7842 return; 7843 7844 if (HAS_DDI(display)) { 7845 if (intel_ddi_crt_present(display)) 7846 intel_crt_init(display); 7847 7848 intel_bios_for_each_encoder(display, intel_ddi_init); 7849 7850 if (display->platform.geminilake || display->platform.broxton) 7851 vlv_dsi_init(display); 7852 } else if (HAS_PCH_SPLIT(display)) { 7853 int found; 7854 7855 /* 7856 * intel_edp_init_connector() depends on this completing first, 7857 * to prevent the registration of both eDP and LVDS and the 7858 * incorrect sharing of the PPS. 7859 */ 7860 intel_lvds_init(display); 7861 intel_crt_init(display); 7862 7863 dpd_is_edp = intel_dp_is_port_edp(display, PORT_D); 7864 7865 if (ilk_has_edp_a(display)) 7866 g4x_dp_init(display, DP_A, PORT_A); 7867 7868 if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) { 7869 /* PCH SDVOB multiplex with HDMIB */ 7870 found = intel_sdvo_init(display, PCH_SDVOB, PORT_B); 7871 if (!found) 7872 g4x_hdmi_init(display, PCH_HDMIB, PORT_B); 7873 if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED)) 7874 g4x_dp_init(display, PCH_DP_B, PORT_B); 7875 } 7876 7877 if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED) 7878 g4x_hdmi_init(display, PCH_HDMIC, PORT_C); 7879 7880 if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED) 7881 g4x_hdmi_init(display, PCH_HDMID, PORT_D); 7882 7883 if (intel_de_read(display, PCH_DP_C) & DP_DETECTED) 7884 g4x_dp_init(display, PCH_DP_C, PORT_C); 7885 7886 if (intel_de_read(display, PCH_DP_D) & DP_DETECTED) 7887 g4x_dp_init(display, PCH_DP_D, PORT_D); 7888 } else if (display->platform.valleyview || display->platform.cherryview) { 7889 bool has_edp, has_port; 7890 7891 if (display->platform.valleyview && display->vbt.int_crt_support) 7892 intel_crt_init(display); 7893 7894 /* 7895 * The DP_DETECTED bit is the latched state of the DDC 7896 * SDA pin at boot. However since eDP doesn't require DDC 7897 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7898 * eDP ports may have been muxed to an alternate function. 7899 * Thus we can't rely on the DP_DETECTED bit alone to detect 7900 * eDP ports. Consult the VBT as well as DP_DETECTED to 7901 * detect eDP ports. 7902 * 7903 * Sadly the straps seem to be missing sometimes even for HDMI 7904 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7905 * and VBT for the presence of the port. Additionally we can't 7906 * trust the port type the VBT declares as we've seen at least 7907 * HDMI ports that the VBT claim are DP or eDP. 7908 */ 7909 has_edp = intel_dp_is_port_edp(display, PORT_B); 7910 has_port = intel_bios_is_port_present(display, PORT_B); 7911 if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port) 7912 has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B); 7913 if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7914 g4x_hdmi_init(display, VLV_HDMIB, PORT_B); 7915 7916 has_edp = intel_dp_is_port_edp(display, PORT_C); 7917 has_port = intel_bios_is_port_present(display, PORT_C); 7918 if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port) 7919 has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C); 7920 if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7921 g4x_hdmi_init(display, VLV_HDMIC, PORT_C); 7922 7923 if (display->platform.cherryview) { 7924 /* 7925 * eDP not supported on port D, 7926 * so no need to worry about it 7927 */ 7928 has_port = intel_bios_is_port_present(display, PORT_D); 7929 if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port) 7930 g4x_dp_init(display, CHV_DP_D, PORT_D); 7931 if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port) 7932 g4x_hdmi_init(display, CHV_HDMID, PORT_D); 7933 } 7934 7935 vlv_dsi_init(display); 7936 } else if (display->platform.pineview) { 7937 intel_lvds_init(display); 7938 intel_crt_init(display); 7939 } else if (IS_DISPLAY_VER(display, 3, 4)) { 7940 bool found = false; 7941 7942 if (display->platform.mobile) 7943 intel_lvds_init(display); 7944 7945 intel_crt_init(display); 7946 7947 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { 7948 drm_dbg_kms(display->drm, "probing SDVOB\n"); 7949 found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B); 7950 if (!found && display->platform.g4x) { 7951 drm_dbg_kms(display->drm, 7952 "probing HDMI on SDVOB\n"); 7953 g4x_hdmi_init(display, GEN4_HDMIB, PORT_B); 7954 } 7955 7956 if (!found && display->platform.g4x) 7957 g4x_dp_init(display, DP_B, PORT_B); 7958 } 7959 7960 /* Before G4X SDVOC doesn't have its own detect register */ 7961 7962 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { 7963 drm_dbg_kms(display->drm, "probing SDVOC\n"); 7964 found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C); 7965 } 7966 7967 if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) { 7968 7969 if (display->platform.g4x) { 7970 drm_dbg_kms(display->drm, 7971 "probing HDMI on SDVOC\n"); 7972 g4x_hdmi_init(display, GEN4_HDMIC, PORT_C); 7973 } 7974 if (display->platform.g4x) 7975 g4x_dp_init(display, DP_C, PORT_C); 7976 } 7977 7978 if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED)) 7979 g4x_dp_init(display, DP_D, PORT_D); 7980 7981 if (SUPPORTS_TV(display)) 7982 intel_tv_init(display); 7983 } else if (DISPLAY_VER(display) == 2) { 7984 if (display->platform.i85x) 7985 intel_lvds_init(display); 7986 7987 intel_crt_init(display); 7988 intel_dvo_init(display); 7989 } 7990 7991 for_each_intel_encoder(display->drm, encoder) { 7992 encoder->base.possible_crtcs = 7993 intel_encoder_possible_crtcs(encoder); 7994 encoder->base.possible_clones = 7995 intel_encoder_possible_clones(encoder); 7996 } 7997 7998 intel_init_pch_refclk(display); 7999 8000 drm_helper_move_panel_connectors_to_head(display->drm); 8001 } 8002 8003 static int max_dotclock(struct intel_display *display) 8004 { 8005 int max_dotclock = display->cdclk.max_dotclk_freq; 8006 8007 if (HAS_ULTRAJOINER(display)) 8008 max_dotclock *= 4; 8009 else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display)) 8010 max_dotclock *= 2; 8011 8012 return max_dotclock; 8013 } 8014 8015 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 8016 const struct drm_display_mode *mode) 8017 { 8018 struct intel_display *display = to_intel_display(dev); 8019 int hdisplay_max, htotal_max; 8020 int vdisplay_max, vtotal_max; 8021 8022 /* 8023 * Can't reject DBLSCAN here because Xorg ddxen can add piles 8024 * of DBLSCAN modes to the output's mode list when they detect 8025 * the scaling mode property on the connector. And they don't 8026 * ask the kernel to validate those modes in any way until 8027 * modeset time at which point the client gets a protocol error. 8028 * So in order to not upset those clients we silently ignore the 8029 * DBLSCAN flag on such connectors. For other connectors we will 8030 * reject modes with the DBLSCAN flag in encoder->compute_config(). 8031 * And we always reject DBLSCAN modes in connector->mode_valid() 8032 * as we never want such modes on the connector's mode list. 8033 */ 8034 8035 if (mode->vscan > 1) 8036 return MODE_NO_VSCAN; 8037 8038 if (mode->flags & DRM_MODE_FLAG_HSKEW) 8039 return MODE_H_ILLEGAL; 8040 8041 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 8042 DRM_MODE_FLAG_NCSYNC | 8043 DRM_MODE_FLAG_PCSYNC)) 8044 return MODE_HSYNC; 8045 8046 if (mode->flags & (DRM_MODE_FLAG_BCAST | 8047 DRM_MODE_FLAG_PIXMUX | 8048 DRM_MODE_FLAG_CLKDIV2)) 8049 return MODE_BAD; 8050 8051 /* 8052 * Reject clearly excessive dotclocks early to 8053 * avoid having to worry about huge integers later. 8054 */ 8055 if (mode->clock > max_dotclock(display)) 8056 return MODE_CLOCK_HIGH; 8057 8058 /* Transcoder timing limits */ 8059 if (DISPLAY_VER(display) >= 11) { 8060 hdisplay_max = 16384; 8061 vdisplay_max = 8192; 8062 htotal_max = 16384; 8063 vtotal_max = 8192; 8064 } else if (DISPLAY_VER(display) >= 9 || 8065 display->platform.broadwell || display->platform.haswell) { 8066 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8067 vdisplay_max = 4096; 8068 htotal_max = 8192; 8069 vtotal_max = 8192; 8070 } else if (DISPLAY_VER(display) >= 3) { 8071 hdisplay_max = 4096; 8072 vdisplay_max = 4096; 8073 htotal_max = 8192; 8074 vtotal_max = 8192; 8075 } else { 8076 hdisplay_max = 2048; 8077 vdisplay_max = 2048; 8078 htotal_max = 4096; 8079 vtotal_max = 4096; 8080 } 8081 8082 if (mode->hdisplay > hdisplay_max || 8083 mode->hsync_start > htotal_max || 8084 mode->hsync_end > htotal_max || 8085 mode->htotal > htotal_max) 8086 return MODE_H_ILLEGAL; 8087 8088 if (mode->vdisplay > vdisplay_max || 8089 mode->vsync_start > vtotal_max || 8090 mode->vsync_end > vtotal_max || 8091 mode->vtotal > vtotal_max) 8092 return MODE_V_ILLEGAL; 8093 8094 /* 8095 * WM_LINETIME only goes up to (almost) 64 usec, and also 8096 * knowing that the linetime is always bounded will ease the 8097 * mind during various calculations. 8098 */ 8099 if (DIV_ROUND_UP(mode->htotal * 1000, mode->clock) > 64) 8100 return MODE_H_ILLEGAL; 8101 8102 return MODE_OK; 8103 } 8104 8105 enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display, 8106 const struct drm_display_mode *mode) 8107 { 8108 /* 8109 * Additional transcoder timing limits, 8110 * excluding BXT/GLK DSI transcoders. 8111 */ 8112 if (DISPLAY_VER(display) >= 5) { 8113 if (mode->hdisplay < 64 || 8114 mode->htotal - mode->hdisplay < 32) 8115 return MODE_H_ILLEGAL; 8116 8117 if (mode->vtotal - mode->vdisplay < 5) 8118 return MODE_V_ILLEGAL; 8119 } else { 8120 if (mode->htotal - mode->hdisplay < 32) 8121 return MODE_H_ILLEGAL; 8122 8123 if (mode->vtotal - mode->vdisplay < 3) 8124 return MODE_V_ILLEGAL; 8125 } 8126 8127 /* 8128 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8129 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8130 */ 8131 if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) && 8132 mode->hsync_start == mode->hdisplay) 8133 return MODE_H_ILLEGAL; 8134 8135 return MODE_OK; 8136 } 8137 8138 enum drm_mode_status 8139 intel_mode_valid_max_plane_size(struct intel_display *display, 8140 const struct drm_display_mode *mode, 8141 int num_joined_pipes) 8142 { 8143 int plane_width_max, plane_height_max; 8144 8145 /* 8146 * intel_mode_valid() should be 8147 * sufficient on older platforms. 8148 */ 8149 if (DISPLAY_VER(display) < 9) 8150 return MODE_OK; 8151 8152 /* 8153 * Most people will probably want a fullscreen 8154 * plane so let's not advertize modes that are 8155 * too big for that. 8156 */ 8157 if (DISPLAY_VER(display) >= 30) { 8158 plane_width_max = 6144 * num_joined_pipes; 8159 plane_height_max = 4800; 8160 } else if (DISPLAY_VER(display) >= 11) { 8161 plane_width_max = 5120 * num_joined_pipes; 8162 plane_height_max = 4320; 8163 } else { 8164 plane_width_max = 5120; 8165 plane_height_max = 4096; 8166 } 8167 8168 if (mode->hdisplay > plane_width_max) 8169 return MODE_H_ILLEGAL; 8170 8171 if (mode->vdisplay > plane_height_max) 8172 return MODE_V_ILLEGAL; 8173 8174 return MODE_OK; 8175 } 8176 8177 static const struct intel_display_funcs skl_display_funcs = { 8178 .get_pipe_config = hsw_get_pipe_config, 8179 .crtc_enable = hsw_crtc_enable, 8180 .crtc_disable = hsw_crtc_disable, 8181 .commit_modeset_enables = skl_commit_modeset_enables, 8182 .get_initial_plane_config = skl_get_initial_plane_config, 8183 .fixup_initial_plane_config = skl_fixup_initial_plane_config, 8184 }; 8185 8186 static const struct intel_display_funcs ddi_display_funcs = { 8187 .get_pipe_config = hsw_get_pipe_config, 8188 .crtc_enable = hsw_crtc_enable, 8189 .crtc_disable = hsw_crtc_disable, 8190 .commit_modeset_enables = intel_commit_modeset_enables, 8191 .get_initial_plane_config = i9xx_get_initial_plane_config, 8192 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8193 }; 8194 8195 static const struct intel_display_funcs pch_split_display_funcs = { 8196 .get_pipe_config = ilk_get_pipe_config, 8197 .crtc_enable = ilk_crtc_enable, 8198 .crtc_disable = ilk_crtc_disable, 8199 .commit_modeset_enables = intel_commit_modeset_enables, 8200 .get_initial_plane_config = i9xx_get_initial_plane_config, 8201 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8202 }; 8203 8204 static const struct intel_display_funcs vlv_display_funcs = { 8205 .get_pipe_config = i9xx_get_pipe_config, 8206 .crtc_enable = valleyview_crtc_enable, 8207 .crtc_disable = i9xx_crtc_disable, 8208 .commit_modeset_enables = intel_commit_modeset_enables, 8209 .get_initial_plane_config = i9xx_get_initial_plane_config, 8210 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8211 }; 8212 8213 static const struct intel_display_funcs i9xx_display_funcs = { 8214 .get_pipe_config = i9xx_get_pipe_config, 8215 .crtc_enable = i9xx_crtc_enable, 8216 .crtc_disable = i9xx_crtc_disable, 8217 .commit_modeset_enables = intel_commit_modeset_enables, 8218 .get_initial_plane_config = i9xx_get_initial_plane_config, 8219 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8220 }; 8221 8222 /** 8223 * intel_init_display_hooks - initialize the display modesetting hooks 8224 * @display: display device private 8225 */ 8226 void intel_init_display_hooks(struct intel_display *display) 8227 { 8228 if (DISPLAY_VER(display) >= 9) { 8229 display->funcs.display = &skl_display_funcs; 8230 } else if (HAS_DDI(display)) { 8231 display->funcs.display = &ddi_display_funcs; 8232 } else if (HAS_PCH_SPLIT(display)) { 8233 display->funcs.display = &pch_split_display_funcs; 8234 } else if (display->platform.cherryview || 8235 display->platform.valleyview) { 8236 display->funcs.display = &vlv_display_funcs; 8237 } else { 8238 display->funcs.display = &i9xx_display_funcs; 8239 } 8240 } 8241 8242 int intel_initial_commit(struct intel_display *display) 8243 { 8244 struct drm_atomic_state *state = NULL; 8245 struct drm_modeset_acquire_ctx ctx; 8246 struct intel_crtc *crtc; 8247 int ret = 0; 8248 8249 state = drm_atomic_state_alloc(display->drm); 8250 if (!state) 8251 return -ENOMEM; 8252 8253 drm_modeset_acquire_init(&ctx, 0); 8254 8255 state->acquire_ctx = &ctx; 8256 to_intel_atomic_state(state)->internal = true; 8257 8258 retry: 8259 for_each_intel_crtc(display->drm, crtc) { 8260 struct intel_crtc_state *crtc_state = 8261 intel_atomic_get_crtc_state(state, crtc); 8262 8263 if (IS_ERR(crtc_state)) { 8264 ret = PTR_ERR(crtc_state); 8265 goto out; 8266 } 8267 8268 if (!crtc_state->hw.active) 8269 crtc_state->inherited = false; 8270 8271 if (crtc_state->hw.active) { 8272 struct intel_encoder *encoder; 8273 8274 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8275 if (ret) 8276 goto out; 8277 8278 /* 8279 * FIXME hack to force a LUT update to avoid the 8280 * plane update forcing the pipe gamma on without 8281 * having a proper LUT loaded. Remove once we 8282 * have readout for pipe gamma enable. 8283 */ 8284 crtc_state->uapi.color_mgmt_changed = true; 8285 8286 for_each_intel_encoder_mask(display->drm, encoder, 8287 crtc_state->uapi.encoder_mask) { 8288 if (encoder->initial_fastset_check && 8289 !encoder->initial_fastset_check(encoder, crtc_state)) { 8290 ret = drm_atomic_add_affected_connectors(state, 8291 &crtc->base); 8292 if (ret) 8293 goto out; 8294 } 8295 } 8296 } 8297 } 8298 8299 ret = drm_atomic_commit(state); 8300 8301 out: 8302 if (ret == -EDEADLK) { 8303 drm_atomic_state_clear(state); 8304 drm_modeset_backoff(&ctx); 8305 goto retry; 8306 } 8307 8308 drm_atomic_state_put(state); 8309 8310 drm_modeset_drop_locks(&ctx); 8311 drm_modeset_acquire_fini(&ctx); 8312 8313 return ret; 8314 } 8315 8316 void i830_enable_pipe(struct intel_display *display, enum pipe pipe) 8317 { 8318 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 8319 enum transcoder cpu_transcoder = (enum transcoder)pipe; 8320 /* 640x480@60Hz, ~25175 kHz */ 8321 struct dpll clock = { 8322 .m1 = 18, 8323 .m2 = 7, 8324 .p1 = 13, 8325 .p2 = 4, 8326 .n = 2, 8327 }; 8328 u32 dpll, fp; 8329 int i; 8330 8331 drm_WARN_ON(display->drm, 8332 i9xx_calc_dpll_params(48000, &clock) != 25154); 8333 8334 drm_dbg_kms(display->drm, 8335 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 8336 pipe_name(pipe), clock.vco, clock.dot); 8337 8338 fp = i9xx_dpll_compute_fp(&clock); 8339 dpll = DPLL_DVO_2X_MODE | 8340 DPLL_VGA_MODE_DIS | 8341 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 8342 PLL_P2_DIVIDE_BY_4 | 8343 PLL_REF_INPUT_DREFCLK | 8344 DPLL_VCO_ENABLE; 8345 8346 intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), 8347 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 8348 intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), 8349 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 8350 intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), 8351 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 8352 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), 8353 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 8354 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), 8355 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 8356 intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), 8357 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 8358 intel_de_write(display, PIPESRC(display, pipe), 8359 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 8360 8361 intel_de_write(display, FP0(pipe), fp); 8362 intel_de_write(display, FP1(pipe), fp); 8363 8364 /* 8365 * Apparently we need to have VGA mode enabled prior to changing 8366 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 8367 * dividers, even though the register value does change. 8368 */ 8369 intel_de_write(display, DPLL(display, pipe), 8370 dpll & ~DPLL_VGA_MODE_DIS); 8371 intel_de_write(display, DPLL(display, pipe), dpll); 8372 8373 /* Wait for the clocks to stabilize. */ 8374 intel_de_posting_read(display, DPLL(display, pipe)); 8375 udelay(150); 8376 8377 /* The pixel multiplier can only be updated once the 8378 * DPLL is enabled and the clocks are stable. 8379 * 8380 * So write it again. 8381 */ 8382 intel_de_write(display, DPLL(display, pipe), dpll); 8383 8384 /* We do this three times for luck */ 8385 for (i = 0; i < 3 ; i++) { 8386 intel_de_write(display, DPLL(display, pipe), dpll); 8387 intel_de_posting_read(display, DPLL(display, pipe)); 8388 udelay(150); /* wait for warmup */ 8389 } 8390 8391 intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE); 8392 intel_de_posting_read(display, TRANSCONF(display, pipe)); 8393 8394 intel_wait_for_pipe_scanline_moving(crtc); 8395 } 8396 8397 void i830_disable_pipe(struct intel_display *display, enum pipe pipe) 8398 { 8399 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 8400 8401 drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n", 8402 pipe_name(pipe)); 8403 8404 drm_WARN_ON(display->drm, 8405 intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE); 8406 drm_WARN_ON(display->drm, 8407 intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE); 8408 drm_WARN_ON(display->drm, 8409 intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE); 8410 drm_WARN_ON(display->drm, 8411 intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK); 8412 drm_WARN_ON(display->drm, 8413 intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK); 8414 8415 intel_de_write(display, TRANSCONF(display, pipe), 0); 8416 intel_de_posting_read(display, TRANSCONF(display, pipe)); 8417 8418 intel_wait_for_pipe_scanline_stopped(crtc); 8419 8420 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); 8421 intel_de_posting_read(display, DPLL(display, pipe)); 8422 } 8423 8424 bool intel_scanout_needs_vtd_wa(struct intel_display *display) 8425 { 8426 return IS_DISPLAY_VER(display, 6, 11) && intel_display_vtd_active(display); 8427 } 8428