1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, 2021 Intel Corporation
5 */
6
7 #ifndef SPI_PXA2XX_H
8 #define SPI_PXA2XX_H
9
10 #include <linux/dmaengine.h>
11 #include <linux/irqreturn.h>
12 #include <linux/types.h>
13 #include <linux/sizes.h>
14
15 #include <linux/pxa2xx_ssp.h>
16
17 struct device;
18 struct gpio_desc;
19
20 /*
21 * The platform data for SSP controller devices
22 * (resides in device.platform_data).
23 */
24 struct pxa2xx_spi_controller {
25 u8 num_chipselect;
26 u8 enable_dma;
27 u8 dma_burst_size;
28 bool is_target;
29
30 /* DMA engine specific config */
31 dma_filter_fn dma_filter;
32 void *tx_param;
33 void *rx_param;
34
35 /* For non-PXA arches */
36 struct ssp_device ssp;
37 };
38
39 struct spi_controller;
40 struct spi_device;
41 struct spi_transfer;
42
43 struct driver_data {
44 /* SSP Info */
45 struct ssp_device *ssp;
46
47 /* SPI framework hookup */
48 enum pxa_ssp_type ssp_type;
49 struct spi_controller *controller;
50
51 /* PXA hookup */
52 struct pxa2xx_spi_controller *controller_info;
53
54 /* SSP masks*/
55 u32 dma_cr1;
56 u32 int_cr1;
57 u32 clear_sr;
58 u32 mask_sr;
59
60 /* DMA engine support */
61 atomic_t dma_running;
62
63 /* Current transfer state info */
64 void *tx;
65 void *tx_end;
66 void *rx;
67 void *rx_end;
68 u8 n_bytes;
69 int (*write)(struct driver_data *drv_data);
70 int (*read)(struct driver_data *drv_data);
71 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
72
73 void __iomem *lpss_base;
74
75 /* Optional slave FIFO ready signal */
76 struct gpio_desc *gpiod_ready;
77 };
78
pxa2xx_spi_read(const struct driver_data * drv_data,u32 reg)79 static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
80 {
81 return pxa_ssp_read_reg(drv_data->ssp, reg);
82 }
83
pxa2xx_spi_write(const struct driver_data * drv_data,u32 reg,u32 val)84 static inline void pxa2xx_spi_write(const struct driver_data *drv_data, u32 reg, u32 val)
85 {
86 pxa_ssp_write_reg(drv_data->ssp, reg, val);
87 }
88
89 #define DMA_ALIGNMENT 8
90
pxa25x_ssp_comp(const struct driver_data * drv_data)91 static inline int pxa25x_ssp_comp(const struct driver_data *drv_data)
92 {
93 switch (drv_data->ssp_type) {
94 case PXA25x_SSP:
95 case CE4100_SSP:
96 case QUARK_X1000_SSP:
97 return 1;
98 default:
99 return 0;
100 }
101 }
102
clear_SSCR1_bits(const struct driver_data * drv_data,u32 bits)103 static inline void clear_SSCR1_bits(const struct driver_data *drv_data, u32 bits)
104 {
105 pxa2xx_spi_write(drv_data, SSCR1, pxa2xx_spi_read(drv_data, SSCR1) & ~bits);
106 }
107
read_SSSR_bits(const struct driver_data * drv_data,u32 bits)108 static inline u32 read_SSSR_bits(const struct driver_data *drv_data, u32 bits)
109 {
110 return pxa2xx_spi_read(drv_data, SSSR) & bits;
111 }
112
write_SSSR_CS(const struct driver_data * drv_data,u32 val)113 static inline void write_SSSR_CS(const struct driver_data *drv_data, u32 val)
114 {
115 if (drv_data->ssp_type == CE4100_SSP ||
116 drv_data->ssp_type == QUARK_X1000_SSP)
117 val |= read_SSSR_bits(drv_data, SSSR_ALT_FRM_MASK);
118
119 pxa2xx_spi_write(drv_data, SSSR, val);
120 }
121
122 extern int pxa2xx_spi_flush(struct driver_data *drv_data);
123
124 #define MAX_DMA_LEN SZ_64K
125 #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
126
127 extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
128 extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
129 struct spi_transfer *xfer);
130 extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
131 extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
132 extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
133 extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
134
135 int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
136 struct pxa2xx_spi_controller *platform_info);
137 void pxa2xx_spi_remove(struct device *dev);
138
139 extern const struct dev_pm_ops pxa2xx_spi_pm_ops;
140
141 #endif /* SPI_PXA2XX_H */
142