1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v13_0_6_pmfw.h"
33 #include "smu13_driver_if_v13_0_6.h"
34 #include "smu_v13_0_6_ppsmc.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "power_state.h"
38 #include "smu_v13_0.h"
39 #include "smu_v13_0_6_ppt.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
47 #include "amdgpu_mca.h"
48 #include "amdgpu_aca.h"
49 #include "smu_cmn.h"
50 #include "mp/mp_13_0_6_offset.h"
51 #include "mp/mp_13_0_6_sh_mask.h"
52 #include "umc_v12_0.h"
53
54 #undef MP1_Public
55 #undef smnMP1_FIRMWARE_FLAGS
56
57 /* TODO: Check final register offsets */
58 #define MP1_Public 0x03b00000
59 #define smnMP1_FIRMWARE_FLAGS 0x3010028
60 /*
61 * DO NOT use these for err/warn/info/debug messages.
62 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
63 * They are more MGPU friendly.
64 */
65 #undef pr_err
66 #undef pr_warn
67 #undef pr_info
68 #undef pr_debug
69
70 MODULE_FIRMWARE("amdgpu/smu_13_0_6.bin");
71 MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
72
73 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
74
75 #define SMU_13_0_6_FEA_MAP(smu_feature, smu_13_0_6_feature) \
76 [smu_feature] = { 1, (smu_13_0_6_feature) }
77
78 #define FEATURE_MASK(feature) (1ULL << feature)
79 #define SMC_DPM_FEATURE \
80 (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \
81 FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_UCLK) | \
82 FEATURE_MASK(FEATURE_DPM_SOCCLK) | FEATURE_MASK(FEATURE_DPM_FCLK) | \
83 FEATURE_MASK(FEATURE_DPM_LCLK) | FEATURE_MASK(FEATURE_DPM_XGMI) | \
84 FEATURE_MASK(FEATURE_DPM_VCN))
85
86 /* possible frequency drift (1Mhz) */
87 #define EPSILON 1
88
89 #define smnPCIE_ESM_CTRL 0x93D0
90 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
91 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
92 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
93 #define MAX_LINK_WIDTH 6
94
95 #define smnPCIE_LC_SPEED_CNTL 0x1a340290
96 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
97 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
98 #define LINK_SPEED_MAX 4
99 #define SMU_13_0_6_DSCLK_THRESHOLD 140
100
101 #define MCA_BANK_IPID(_ip, _hwid, _type) \
102 [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }
103
104 struct mca_bank_ipid {
105 enum amdgpu_mca_ip ip;
106 uint16_t hwid;
107 uint16_t mcatype;
108 };
109
110 struct mca_ras_info {
111 enum amdgpu_ras_block blkid;
112 enum amdgpu_mca_ip ip;
113 int *err_code_array;
114 int err_code_count;
115 int (*get_err_count)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
116 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
117 bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
118 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry);
119 };
120
121 #define P2S_TABLE_ID_A 0x50325341
122 #define P2S_TABLE_ID_X 0x50325358
123 #define P2S_TABLE_ID_3 0x50325303
124
125 // clang-format off
126 static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
127 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
128 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
129 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
130 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
131 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
132 MSG_MAP(RequestI2cTransaction, PPSMC_MSG_RequestI2cTransaction, 0),
133 MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1),
134 MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1),
135 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
136 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
137 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
138 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
139 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
140 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
141 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
142 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
143 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
144 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
145 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
146 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
147 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
148 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI),
149 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
150 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
151 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
152 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
153 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
154 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
155 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
156 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
157 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
158 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
159 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
160 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
161 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
162 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
163 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxDpmFreq, 1),
164 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxDpmFreq, 1),
165 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1),
166 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
167 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0),
168 MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0),
169 MSG_MAP(GetThermalLimit, PPSMC_MSG_ReadThrottlerLimit, 0),
170 MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0),
171 MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI),
172 MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI),
173 MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI),
174 MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI),
175 MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0),
176 MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0),
177 MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0),
178 MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0),
179 MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0),
180 MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 0),
181 };
182
183 // clang-format on
184 static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = {
185 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
186 CLK_MAP(FCLK, PPCLK_FCLK),
187 CLK_MAP(UCLK, PPCLK_UCLK),
188 CLK_MAP(MCLK, PPCLK_UCLK),
189 CLK_MAP(DCLK, PPCLK_DCLK),
190 CLK_MAP(VCLK, PPCLK_VCLK),
191 CLK_MAP(LCLK, PPCLK_LCLK),
192 };
193
194 static const struct cmn2asic_mapping smu_v13_0_6_feature_mask_map[SMU_FEATURE_COUNT] = {
195 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION),
196 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK),
197 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK),
198 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK),
199 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK),
200 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK),
201 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_VCLK_BIT, FEATURE_DPM_VCN),
202 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_DCLK_BIT, FEATURE_DPM_VCN),
203 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI),
204 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK),
205 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK),
206 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK),
207 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK),
208 SMU_13_0_6_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN),
209 SMU_13_0_6_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT),
210 SMU_13_0_6_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC),
211 SMU_13_0_6_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL),
212 SMU_13_0_6_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_SMU_CG),
213 SMU_13_0_6_FEA_MAP(SMU_FEATURE_GFXOFF_BIT, FEATURE_GFXOFF),
214 SMU_13_0_6_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF),
215 SMU_13_0_6_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL),
216 SMU_13_0_6_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN),
217 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
218 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_VCN_BIT, FEATURE_DS_VCN),
219 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MP1CLK_BIT, FEATURE_DS_MP1CLK),
220 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_DS_MPIOCLK),
221 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_DS_MP0CLK),
222 };
223
224 #define TABLE_PMSTATUSLOG 0
225 #define TABLE_SMU_METRICS 1
226 #define TABLE_I2C_COMMANDS 2
227 #define TABLE_COUNT 3
228
229 static const struct cmn2asic_mapping smu_v13_0_6_table_map[SMU_TABLE_COUNT] = {
230 TAB_MAP(PMSTATUSLOG),
231 TAB_MAP(SMU_METRICS),
232 TAB_MAP(I2C_COMMANDS),
233 };
234
235 static const uint8_t smu_v13_0_6_throttler_map[] = {
236 [THROTTLER_PPT_BIT] = (SMU_THROTTLER_PPT0_BIT),
237 [THROTTLER_THERMAL_SOCKET_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
238 [THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
239 [THROTTLER_THERMAL_VR_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
240 [THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
241 };
242
243 #define GET_GPU_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V0) ?\
244 (metrics_v0->field) : (metrics_v2->field))
245 #define GET_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V1) ?\
246 (metrics_v1->field) : GET_GPU_METRIC_FIELD(field, version))
247 #define METRICS_TABLE_SIZE (max3(sizeof(MetricsTableV0_t),\
248 sizeof(MetricsTableV1_t),\
249 sizeof(MetricsTableV2_t)))
250
251 struct smu_v13_0_6_dpm_map {
252 enum smu_clk_type clk_type;
253 uint32_t feature_num;
254 struct smu_13_0_dpm_table *dpm_table;
255 uint32_t *freq_table;
256 };
257
smu_v13_0_6_get_metrics_version(struct smu_context * smu)258 static inline int smu_v13_0_6_get_metrics_version(struct smu_context *smu)
259 {
260 if ((smu->adev->flags & AMD_IS_APU) &&
261 smu->smc_fw_version <= 0x4556900)
262 return METRICS_VERSION_V1;
263 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
264 IP_VERSION(13, 0, 12))
265 return METRICS_VERSION_V2;
266
267 return METRICS_VERSION_V0;
268 }
269
smu_v13_0_6_cap_set(struct smu_context * smu,enum smu_v13_0_6_caps cap)270 static inline void smu_v13_0_6_cap_set(struct smu_context *smu,
271 enum smu_v13_0_6_caps cap)
272 {
273 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
274
275 dpm_context->caps |= BIT_ULL(cap);
276 }
277
smu_v13_0_6_cap_clear(struct smu_context * smu,enum smu_v13_0_6_caps cap)278 static inline void smu_v13_0_6_cap_clear(struct smu_context *smu,
279 enum smu_v13_0_6_caps cap)
280 {
281 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
282
283 dpm_context->caps &= ~BIT_ULL(cap);
284 }
285
smu_v13_0_6_cap_supported(struct smu_context * smu,enum smu_v13_0_6_caps cap)286 bool smu_v13_0_6_cap_supported(struct smu_context *smu,
287 enum smu_v13_0_6_caps cap)
288 {
289 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
290
291 return !!(dpm_context->caps & BIT_ULL(cap));
292 }
293
smu_v13_0_14_init_caps(struct smu_context * smu)294 static void smu_v13_0_14_init_caps(struct smu_context *smu)
295 {
296 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
297 SMU_CAP(SET_UCLK_MAX),
298 SMU_CAP(DPM_POLICY),
299 SMU_CAP(PCIE_METRICS),
300 SMU_CAP(CTF_LIMIT),
301 SMU_CAP(MCA_DEBUG_MODE),
302 SMU_CAP(RMA_MSG),
303 SMU_CAP(ACA_SYND) };
304 uint32_t fw_ver = smu->smc_fw_version;
305
306 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
307 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
308
309 if (fw_ver >= 0x05550E00)
310 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
311 if (fw_ver >= 0x05550B00)
312 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
313 if (fw_ver >= 0x5551200)
314 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
315 if (fw_ver >= 0x5551600) {
316 smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
317 smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE));
318 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
319 }
320 }
321
smu_v13_0_12_init_caps(struct smu_context * smu)322 static void smu_v13_0_12_init_caps(struct smu_context *smu)
323 {
324 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
325 SMU_CAP(PCIE_METRICS),
326 SMU_CAP(CTF_LIMIT),
327 SMU_CAP(MCA_DEBUG_MODE),
328 SMU_CAP(RMA_MSG),
329 SMU_CAP(ACA_SYND),
330 SMU_CAP(OTHER_END_METRICS),
331 SMU_CAP(PER_INST_METRICS) };
332 uint32_t fw_ver = smu->smc_fw_version;
333
334 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
335 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
336
337 if (fw_ver < 0x00561900)
338 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
339
340 if (fw_ver >= 0x00561700)
341 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
342
343 if (fw_ver >= 0x00561E00)
344 smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
345
346 if (fw_ver >= 0x00562500)
347 smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
348
349 if (fw_ver >= 0x04560100) {
350 smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE));
351 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
352 }
353 }
354
smu_v13_0_6_init_caps(struct smu_context * smu)355 static void smu_v13_0_6_init_caps(struct smu_context *smu)
356 {
357 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
358 SMU_CAP(SET_UCLK_MAX),
359 SMU_CAP(DPM_POLICY),
360 SMU_CAP(PCIE_METRICS),
361 SMU_CAP(CTF_LIMIT),
362 SMU_CAP(MCA_DEBUG_MODE),
363 SMU_CAP(RMA_MSG),
364 SMU_CAP(ACA_SYND) };
365 struct amdgpu_device *adev = smu->adev;
366 uint32_t fw_ver = smu->smc_fw_version;
367 uint32_t pgm = (fw_ver >> 24) & 0xFF;
368
369 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
370 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
371
372 if (fw_ver < 0x552F00)
373 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
374 if (fw_ver < 0x554500)
375 smu_v13_0_6_cap_clear(smu, SMU_CAP(CTF_LIMIT));
376
377 if (adev->flags & AMD_IS_APU) {
378 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
379 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
380 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
381 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
382
383 if (fw_ver >= 0x04556A00)
384 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
385 } else {
386 if (fw_ver >= 0x557600)
387 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
388 if (fw_ver < 0x00556000)
389 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
390 if (amdgpu_sriov_vf(adev) && (fw_ver < 0x556600))
391 smu_v13_0_6_cap_clear(smu, SMU_CAP(SET_UCLK_MAX));
392 if (fw_ver < 0x556300)
393 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
394 if (fw_ver < 0x554800)
395 smu_v13_0_6_cap_clear(smu, SMU_CAP(MCA_DEBUG_MODE));
396 if (fw_ver >= 0x556F00)
397 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
398 if (fw_ver < 0x00555a00)
399 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
400 if (fw_ver < 0x00555600)
401 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
402 if ((pgm == 7 && fw_ver >= 0x7550E00) ||
403 (pgm == 0 && fw_ver >= 0x00557E00))
404 smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
405 if ((pgm == 0 && fw_ver >= 0x00557F01) ||
406 (pgm == 7 && fw_ver >= 0x7551000)) {
407 smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
408 smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE));
409 }
410 if ((pgm == 0 && fw_ver >= 0x00558000) ||
411 (pgm == 7 && fw_ver >= 0x7551000))
412 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
413 }
414 if (((pgm == 7) && (fw_ver >= 0x7550700)) ||
415 ((pgm == 0) && (fw_ver >= 0x00557900)) ||
416 ((pgm == 4) && (fw_ver >= 0x4557000)))
417 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
418 }
419
smu_v13_0_x_init_caps(struct smu_context * smu)420 static void smu_v13_0_x_init_caps(struct smu_context *smu)
421 {
422 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
423 case IP_VERSION(13, 0, 12):
424 return smu_v13_0_12_init_caps(smu);
425 case IP_VERSION(13, 0, 14):
426 return smu_v13_0_14_init_caps(smu);
427 default:
428 return smu_v13_0_6_init_caps(smu);
429 }
430 }
431
smu_v13_0_6_check_fw_version(struct smu_context * smu)432 static int smu_v13_0_6_check_fw_version(struct smu_context *smu)
433 {
434 int r;
435
436 r = smu_v13_0_check_fw_version(smu);
437 /* Initialize caps flags once fw version is fetched */
438 if (!r)
439 smu_v13_0_x_init_caps(smu);
440
441 return r;
442 }
443
smu_v13_0_6_init_microcode(struct smu_context * smu)444 static int smu_v13_0_6_init_microcode(struct smu_context *smu)
445 {
446 const struct smc_firmware_header_v2_1 *v2_1;
447 const struct common_firmware_header *hdr;
448 struct amdgpu_firmware_info *ucode = NULL;
449 struct smc_soft_pptable_entry *entries;
450 struct amdgpu_device *adev = smu->adev;
451 uint32_t p2s_table_id = P2S_TABLE_ID_A;
452 int ret = 0, i, p2stable_count;
453 int var = (adev->pdev->device & 0xF);
454 char ucode_prefix[15];
455
456 /* No need to load P2S tables in IOV mode or for smu v13.0.12 */
457 if (amdgpu_sriov_vf(adev) ||
458 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)))
459 return 0;
460
461 if (!(adev->flags & AMD_IS_APU)) {
462 p2s_table_id = P2S_TABLE_ID_X;
463 if (var == 0x5)
464 p2s_table_id = P2S_TABLE_ID_3;
465 }
466
467 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
468 sizeof(ucode_prefix));
469 ret = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
470 "amdgpu/%s.bin", ucode_prefix);
471 if (ret)
472 goto out;
473
474 hdr = (const struct common_firmware_header *)adev->pm.fw->data;
475 amdgpu_ucode_print_smc_hdr(hdr);
476
477 /* SMU v13.0.6 binary file doesn't carry pptables, instead the entries
478 * are used to carry p2s tables.
479 */
480 v2_1 = (const struct smc_firmware_header_v2_1 *)adev->pm.fw->data;
481 entries = (struct smc_soft_pptable_entry
482 *)((uint8_t *)v2_1 +
483 le32_to_cpu(v2_1->pptable_entry_offset));
484 p2stable_count = le32_to_cpu(v2_1->pptable_count);
485 for (i = 0; i < p2stable_count; i++) {
486 if (le32_to_cpu(entries[i].id) == p2s_table_id) {
487 smu->pptable_firmware.data =
488 ((uint8_t *)v2_1 +
489 le32_to_cpu(entries[i].ppt_offset_bytes));
490 smu->pptable_firmware.size =
491 le32_to_cpu(entries[i].ppt_size_bytes);
492 break;
493 }
494 }
495
496 if (smu->pptable_firmware.data && smu->pptable_firmware.size) {
497 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
498 ucode->ucode_id = AMDGPU_UCODE_ID_P2S_TABLE;
499 ucode->fw = &smu->pptable_firmware;
500 adev->firmware.fw_size += ALIGN(ucode->fw->size, PAGE_SIZE);
501 }
502
503 return 0;
504 out:
505 amdgpu_ucode_release(&adev->pm.fw);
506
507 return ret;
508 }
509
smu_v13_0_6_tables_init(struct smu_context * smu)510 static int smu_v13_0_6_tables_init(struct smu_context *smu)
511 {
512 struct smu_table_context *smu_table = &smu->smu_table;
513 struct smu_table *tables = smu_table->tables;
514 struct amdgpu_device *adev = smu->adev;
515 int gpu_metrcs_size = METRICS_TABLE_SIZE;
516
517 if (!(adev->flags & AMD_IS_APU))
518 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
519 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
520
521 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
522 max(gpu_metrcs_size,
523 smu_v13_0_12_get_max_metrics_size()),
524 PAGE_SIZE,
525 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
526
527 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
528 PAGE_SIZE,
529 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
530
531 smu_table->metrics_table = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
532 if (!smu_table->metrics_table)
533 return -ENOMEM;
534 smu_table->metrics_time = 0;
535
536 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_8);
537 smu_table->gpu_metrics_table =
538 kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
539 if (!smu_table->gpu_metrics_table) {
540 kfree(smu_table->metrics_table);
541 return -ENOMEM;
542 }
543
544 smu_table->driver_pptable =
545 kzalloc(sizeof(struct PPTable_t), GFP_KERNEL);
546 if (!smu_table->driver_pptable) {
547 kfree(smu_table->metrics_table);
548 kfree(smu_table->gpu_metrics_table);
549 return -ENOMEM;
550 }
551
552 return 0;
553 }
554
smu_v13_0_6_select_policy_soc_pstate(struct smu_context * smu,int policy)555 static int smu_v13_0_6_select_policy_soc_pstate(struct smu_context *smu,
556 int policy)
557 {
558 struct amdgpu_device *adev = smu->adev;
559 int ret, param;
560
561 switch (policy) {
562 case SOC_PSTATE_DEFAULT:
563 param = 0;
564 break;
565 case SOC_PSTATE_0:
566 param = 1;
567 break;
568 case SOC_PSTATE_1:
569 param = 2;
570 break;
571 case SOC_PSTATE_2:
572 param = 3;
573 break;
574 default:
575 return -EINVAL;
576 }
577
578 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetThrottlingPolicy,
579 param, NULL);
580
581 if (ret)
582 dev_err(adev->dev, "select soc pstate policy %d failed",
583 policy);
584
585 return ret;
586 }
587
smu_v13_0_6_select_plpd_policy(struct smu_context * smu,int level)588 static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level)
589 {
590 struct amdgpu_device *adev = smu->adev;
591 int ret, param;
592
593 switch (level) {
594 case XGMI_PLPD_DEFAULT:
595 param = PPSMC_PLPD_MODE_DEFAULT;
596 break;
597 case XGMI_PLPD_OPTIMIZED:
598 param = PPSMC_PLPD_MODE_OPTIMIZED;
599 break;
600 case XGMI_PLPD_DISALLOW:
601 param = 0;
602 break;
603 default:
604 return -EINVAL;
605 }
606
607 if (level == XGMI_PLPD_DISALLOW)
608 ret = smu_cmn_send_smc_msg_with_param(
609 smu, SMU_MSG_GmiPwrDnControl, param, NULL);
610 else
611 /* change xgmi per-link power down policy */
612 ret = smu_cmn_send_smc_msg_with_param(
613 smu, SMU_MSG_SelectPLPDMode, param, NULL);
614
615 if (ret)
616 dev_err(adev->dev,
617 "select xgmi per-link power down policy %d failed\n",
618 level);
619
620 return ret;
621 }
622
smu_v13_0_6_allocate_dpm_context(struct smu_context * smu)623 static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu)
624 {
625 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
626 struct smu_dpm_policy *policy;
627
628 smu_dpm->dpm_context =
629 kzalloc(sizeof(struct smu_13_0_dpm_context), GFP_KERNEL);
630 if (!smu_dpm->dpm_context)
631 return -ENOMEM;
632 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
633
634 smu_dpm->dpm_policies =
635 kzalloc(sizeof(struct smu_dpm_policy_ctxt), GFP_KERNEL);
636 if (!smu_dpm->dpm_policies) {
637 kfree(smu_dpm->dpm_context);
638 return -ENOMEM;
639 }
640
641 if (!(smu->adev->flags & AMD_IS_APU)) {
642 policy = &(smu_dpm->dpm_policies->policies[0]);
643
644 policy->policy_type = PP_PM_POLICY_SOC_PSTATE;
645 policy->level_mask = BIT(SOC_PSTATE_DEFAULT) |
646 BIT(SOC_PSTATE_0) | BIT(SOC_PSTATE_1) |
647 BIT(SOC_PSTATE_2);
648 policy->current_level = SOC_PSTATE_DEFAULT;
649 policy->set_policy = smu_v13_0_6_select_policy_soc_pstate;
650 smu_cmn_generic_soc_policy_desc(policy);
651 smu_dpm->dpm_policies->policy_mask |=
652 BIT(PP_PM_POLICY_SOC_PSTATE);
653 }
654 policy = &(smu_dpm->dpm_policies->policies[1]);
655
656 policy->policy_type = PP_PM_POLICY_XGMI_PLPD;
657 policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT) |
658 BIT(XGMI_PLPD_OPTIMIZED);
659 policy->current_level = XGMI_PLPD_DEFAULT;
660 policy->set_policy = smu_v13_0_6_select_plpd_policy;
661 smu_cmn_generic_plpd_policy_desc(policy);
662 smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
663
664 return 0;
665 }
666
smu_v13_0_6_init_smc_tables(struct smu_context * smu)667 static int smu_v13_0_6_init_smc_tables(struct smu_context *smu)
668 {
669 int ret = 0;
670
671 ret = smu_v13_0_6_tables_init(smu);
672 if (ret)
673 return ret;
674
675 ret = smu_v13_0_6_allocate_dpm_context(smu);
676
677 return ret;
678 }
679
smu_v13_0_6_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)680 static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu,
681 uint32_t *feature_mask,
682 uint32_t num)
683 {
684 if (num > 2)
685 return -EINVAL;
686
687 /* pptable will handle the features to enable */
688 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
689
690 return 0;
691 }
692
smu_v13_0_6_get_metrics_table(struct smu_context * smu,void * metrics_table,bool bypass_cache)693 int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table,
694 bool bypass_cache)
695 {
696 struct smu_table_context *smu_table = &smu->smu_table;
697 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
698 struct smu_table *table = &smu_table->driver_table;
699 int ret;
700
701 if (bypass_cache || !smu_table->metrics_time ||
702 time_after(jiffies,
703 smu_table->metrics_time + msecs_to_jiffies(1))) {
704 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL);
705 if (ret) {
706 dev_info(smu->adev->dev,
707 "Failed to export SMU metrics table!\n");
708 return ret;
709 }
710
711 amdgpu_asic_invalidate_hdp(smu->adev, NULL);
712 memcpy(smu_table->metrics_table, table->cpu_addr, table_size);
713
714 smu_table->metrics_time = jiffies;
715 }
716
717 if (metrics_table)
718 memcpy(metrics_table, smu_table->metrics_table, table_size);
719
720 return 0;
721 }
722
smu_v13_0_6_get_pm_metrics(struct smu_context * smu,void * metrics,size_t max_size)723 static ssize_t smu_v13_0_6_get_pm_metrics(struct smu_context *smu,
724 void *metrics, size_t max_size)
725 {
726 struct smu_table_context *smu_tbl_ctxt = &smu->smu_table;
727 uint32_t table_version = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].version;
728 uint32_t table_size = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].size;
729 struct amdgpu_pm_metrics *pm_metrics = metrics;
730 uint32_t pmfw_version;
731 int ret;
732
733 if (!pm_metrics || !max_size)
734 return -EINVAL;
735
736 if (max_size < (table_size + sizeof(pm_metrics->common_header)))
737 return -EOVERFLOW;
738
739 /* Don't use cached metrics data */
740 ret = smu_v13_0_6_get_metrics_table(smu, pm_metrics->data, true);
741 if (ret)
742 return ret;
743
744 smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
745
746 memset(&pm_metrics->common_header, 0,
747 sizeof(pm_metrics->common_header));
748 pm_metrics->common_header.mp1_ip_discovery_version =
749 amdgpu_ip_version(smu->adev, MP1_HWIP, 0);
750 pm_metrics->common_header.pmfw_version = pmfw_version;
751 pm_metrics->common_header.pmmetrics_version = table_version;
752 pm_metrics->common_header.structure_size =
753 sizeof(pm_metrics->common_header) + table_size;
754
755 return pm_metrics->common_header.structure_size;
756 }
757
smu_v13_0_6_fill_static_metrics_table(struct smu_context * smu,StaticMetricsTable_t * static_metrics)758 static void smu_v13_0_6_fill_static_metrics_table(struct smu_context *smu,
759 StaticMetricsTable_t *static_metrics)
760 {
761 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
762
763 if (!static_metrics->InputTelemetryVoltageInmV) {
764 dev_warn(smu->adev->dev, "Invalid board voltage %d\n",
765 static_metrics->InputTelemetryVoltageInmV);
766 }
767
768 dpm_context->board_volt = static_metrics->InputTelemetryVoltageInmV;
769
770 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PLDM_VERSION)) &&
771 static_metrics->pldmVersion[0] != 0xFFFFFFFF)
772 smu->adev->firmware.pldm_version =
773 static_metrics->pldmVersion[0];
774 }
775
smu_v13_0_6_get_static_metrics_table(struct smu_context * smu)776 int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu)
777 {
778 struct smu_table_context *smu_table = &smu->smu_table;
779 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
780 struct smu_table *table = &smu_table->driver_table;
781 int ret;
782
783 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetStaticMetricsTable, NULL);
784 if (ret) {
785 dev_info(smu->adev->dev,
786 "Failed to export static metrics table!\n");
787 return ret;
788 }
789
790 amdgpu_asic_invalidate_hdp(smu->adev, NULL);
791 memcpy(smu_table->metrics_table, table->cpu_addr, table_size);
792
793 return 0;
794 }
795
smu_v13_0_6_setup_driver_pptable(struct smu_context * smu)796 static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
797 {
798 struct smu_table_context *smu_table = &smu->smu_table;
799 StaticMetricsTable_t *static_metrics = (StaticMetricsTable_t *)smu_table->metrics_table;
800 MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
801 MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
802 MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
803 struct PPTable_t *pptable =
804 (struct PPTable_t *)smu_table->driver_pptable;
805 int version = smu_v13_0_6_get_metrics_version(smu);
806 int ret, i, retry = 100;
807 uint32_t table_version;
808 uint16_t max_speed;
809 uint8_t max_width;
810
811 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
812 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
813 return smu_v13_0_12_setup_driver_pptable(smu);
814
815 /* Store one-time values in driver PPTable */
816 if (!pptable->Init) {
817 while (--retry) {
818 ret = smu_v13_0_6_get_metrics_table(smu, NULL, true);
819 if (ret)
820 return ret;
821
822 /* Ensure that metrics have been updated */
823 if (GET_METRIC_FIELD(AccumulationCounter, version))
824 break;
825
826 usleep_range(1000, 1100);
827 }
828
829 if (!retry)
830 return -ETIME;
831
832 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion,
833 &table_version);
834 if (ret)
835 return ret;
836 smu_table->tables[SMU_TABLE_SMU_METRICS].version =
837 table_version;
838
839 pptable->MaxSocketPowerLimit =
840 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, version));
841 pptable->MaxGfxclkFrequency =
842 SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, version));
843 pptable->MinGfxclkFrequency =
844 SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, version));
845 max_width = (uint8_t)GET_METRIC_FIELD(XgmiWidth, version);
846 max_speed = (uint16_t)GET_METRIC_FIELD(XgmiBitrate, version);
847 amgpu_xgmi_set_max_speed_width(smu->adev, max_speed, max_width);
848
849 for (i = 0; i < 4; ++i) {
850 pptable->FclkFrequencyTable[i] =
851 SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, version)[i]);
852 pptable->UclkFrequencyTable[i] =
853 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, version)[i]);
854 pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND(
855 GET_METRIC_FIELD(SocclkFrequencyTable, version)[i]);
856 pptable->VclkFrequencyTable[i] =
857 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, version)[i]);
858 pptable->DclkFrequencyTable[i] =
859 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, version)[i]);
860 pptable->LclkFrequencyTable[i] =
861 SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, version)[i]);
862 }
863
864 /* use AID0 serial number by default */
865 pptable->PublicSerialNumber_AID =
866 GET_METRIC_FIELD(PublicSerialNumber_AID, version)[0];
867
868 pptable->Init = true;
869 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
870 ret = smu_v13_0_6_get_static_metrics_table(smu);
871 if (ret)
872 return ret;
873 smu_v13_0_6_fill_static_metrics_table(smu, static_metrics);
874 }
875 }
876
877 return 0;
878 }
879
smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)880 static int smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context *smu,
881 enum smu_clk_type clk_type,
882 uint32_t *min, uint32_t *max)
883 {
884 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
885 struct smu_table_context *smu_table = &smu->smu_table;
886 struct PPTable_t *pptable =
887 (struct PPTable_t *)smu_table->driver_pptable;
888 struct smu_13_0_dpm_table *dpm_table;
889 uint32_t min_clk, max_clk, param;
890 int ret = 0, clk_id = 0;
891
892 /* Use dpm tables, if data is already fetched */
893 if (pptable->Init) {
894 switch (clk_type) {
895 case SMU_MCLK:
896 case SMU_UCLK:
897 dpm_table = &dpm_context->dpm_tables.uclk_table;
898 break;
899 case SMU_GFXCLK:
900 case SMU_SCLK:
901 dpm_table = &dpm_context->dpm_tables.gfx_table;
902 break;
903 case SMU_SOCCLK:
904 dpm_table = &dpm_context->dpm_tables.soc_table;
905 break;
906 case SMU_FCLK:
907 dpm_table = &dpm_context->dpm_tables.fclk_table;
908 break;
909 case SMU_VCLK:
910 dpm_table = &dpm_context->dpm_tables.vclk_table;
911 break;
912 case SMU_DCLK:
913 dpm_table = &dpm_context->dpm_tables.dclk_table;
914 break;
915 default:
916 return -EINVAL;
917 }
918
919 min_clk = dpm_table->min;
920 max_clk = dpm_table->max;
921
922 if (min)
923 *min = min_clk;
924 if (max)
925 *max = max_clk;
926
927 if (min_clk && max_clk)
928 return 0;
929 }
930
931 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) {
932 clk_id = smu_cmn_to_asic_specific_index(
933 smu, CMN2ASIC_MAPPING_CLK, clk_type);
934 if (clk_id < 0) {
935 ret = -EINVAL;
936 goto failed;
937 }
938 param = (clk_id & 0xffff) << 16;
939 }
940
941 if (max) {
942 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
943 ret = smu_cmn_send_smc_msg(
944 smu, SMU_MSG_GetMaxGfxclkFrequency, max);
945 else
946 ret = smu_cmn_send_smc_msg_with_param(
947 smu, SMU_MSG_GetMaxDpmFreq, param, max);
948 if (ret)
949 goto failed;
950 }
951
952 if (min) {
953 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
954 ret = smu_cmn_send_smc_msg(
955 smu, SMU_MSG_GetMinGfxclkFrequency, min);
956 else
957 ret = smu_cmn_send_smc_msg_with_param(
958 smu, SMU_MSG_GetMinDpmFreq, param, min);
959 }
960
961 failed:
962 return ret;
963 }
964
smu_v13_0_6_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * levels)965 static int smu_v13_0_6_get_dpm_level_count(struct smu_context *smu,
966 enum smu_clk_type clk_type,
967 uint32_t *levels)
968 {
969 int ret;
970
971 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels);
972 if (!ret)
973 ++(*levels);
974
975 return ret;
976 }
977
smu_v13_0_6_pm_policy_init(struct smu_context * smu)978 static void smu_v13_0_6_pm_policy_init(struct smu_context *smu)
979 {
980 struct smu_dpm_policy *policy;
981
982 policy = smu_get_pm_policy(smu, PP_PM_POLICY_SOC_PSTATE);
983 if (policy)
984 policy->current_level = SOC_PSTATE_DEFAULT;
985 }
986
smu_v13_0_6_set_default_dpm_table(struct smu_context * smu)987 static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu)
988 {
989 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
990 struct smu_table_context *smu_table = &smu->smu_table;
991 struct smu_13_0_dpm_table *dpm_table = NULL;
992 struct PPTable_t *pptable =
993 (struct PPTable_t *)smu_table->driver_pptable;
994 uint32_t gfxclkmin, gfxclkmax, levels;
995 int ret = 0, i, j;
996 struct smu_v13_0_6_dpm_map dpm_map[] = {
997 { SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT,
998 &dpm_context->dpm_tables.soc_table,
999 pptable->SocclkFrequencyTable },
1000 { SMU_UCLK, SMU_FEATURE_DPM_UCLK_BIT,
1001 &dpm_context->dpm_tables.uclk_table,
1002 pptable->UclkFrequencyTable },
1003 { SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT,
1004 &dpm_context->dpm_tables.fclk_table,
1005 pptable->FclkFrequencyTable },
1006 { SMU_VCLK, SMU_FEATURE_DPM_VCLK_BIT,
1007 &dpm_context->dpm_tables.vclk_table,
1008 pptable->VclkFrequencyTable },
1009 { SMU_DCLK, SMU_FEATURE_DPM_DCLK_BIT,
1010 &dpm_context->dpm_tables.dclk_table,
1011 pptable->DclkFrequencyTable },
1012 };
1013
1014 smu_v13_0_6_setup_driver_pptable(smu);
1015
1016 /* DPM policy not supported in older firmwares */
1017 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM_POLICY))) {
1018 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1019
1020 smu_dpm->dpm_policies->policy_mask &=
1021 ~BIT(PP_PM_POLICY_SOC_PSTATE);
1022 }
1023
1024 smu_v13_0_6_pm_policy_init(smu);
1025 /* gfxclk dpm table setup */
1026 dpm_table = &dpm_context->dpm_tables.gfx_table;
1027 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1028 /* In the case of gfxclk, only fine-grained dpm is honored.
1029 * Get min/max values from FW.
1030 */
1031 ret = smu_v13_0_6_get_dpm_ultimate_freq(smu, SMU_GFXCLK,
1032 &gfxclkmin, &gfxclkmax);
1033 if (ret)
1034 return ret;
1035
1036 dpm_table->count = 2;
1037 dpm_table->dpm_levels[0].value = gfxclkmin;
1038 dpm_table->dpm_levels[0].enabled = true;
1039 dpm_table->dpm_levels[1].value = gfxclkmax;
1040 dpm_table->dpm_levels[1].enabled = true;
1041 dpm_table->min = dpm_table->dpm_levels[0].value;
1042 dpm_table->max = dpm_table->dpm_levels[1].value;
1043 } else {
1044 dpm_table->count = 1;
1045 dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency;
1046 dpm_table->dpm_levels[0].enabled = true;
1047 dpm_table->min = dpm_table->dpm_levels[0].value;
1048 dpm_table->max = dpm_table->dpm_levels[0].value;
1049 }
1050
1051 for (j = 0; j < ARRAY_SIZE(dpm_map); j++) {
1052 dpm_table = dpm_map[j].dpm_table;
1053 levels = 1;
1054 if (smu_cmn_feature_is_enabled(smu, dpm_map[j].feature_num)) {
1055 ret = smu_v13_0_6_get_dpm_level_count(
1056 smu, dpm_map[j].clk_type, &levels);
1057 if (ret)
1058 return ret;
1059 }
1060 dpm_table->count = levels;
1061 for (i = 0; i < dpm_table->count; ++i) {
1062 dpm_table->dpm_levels[i].value =
1063 dpm_map[j].freq_table[i];
1064 dpm_table->dpm_levels[i].enabled = true;
1065
1066 }
1067 dpm_table->min = dpm_table->dpm_levels[0].value;
1068 dpm_table->max = dpm_table->dpm_levels[levels - 1].value;
1069
1070 }
1071
1072 return 0;
1073 }
1074
smu_v13_0_6_setup_pptable(struct smu_context * smu)1075 static int smu_v13_0_6_setup_pptable(struct smu_context *smu)
1076 {
1077 struct smu_table_context *table_context = &smu->smu_table;
1078
1079 /* TODO: PPTable is not available.
1080 * 1) Find an alternate way to get 'PPTable values' here.
1081 * 2) Check if there is SW CTF
1082 */
1083 table_context->thermal_controller_type = 0;
1084
1085 return 0;
1086 }
1087
smu_v13_0_6_check_fw_status(struct smu_context * smu)1088 static int smu_v13_0_6_check_fw_status(struct smu_context *smu)
1089 {
1090 struct amdgpu_device *adev = smu->adev;
1091 uint32_t mp1_fw_flags;
1092
1093 mp1_fw_flags =
1094 RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
1095
1096 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
1097 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
1098 return 0;
1099
1100 return -EIO;
1101 }
1102
smu_v13_0_6_populate_umd_state_clk(struct smu_context * smu)1103 static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu)
1104 {
1105 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1106 struct smu_13_0_dpm_table *gfx_table =
1107 &dpm_context->dpm_tables.gfx_table;
1108 struct smu_13_0_dpm_table *mem_table =
1109 &dpm_context->dpm_tables.uclk_table;
1110 struct smu_13_0_dpm_table *soc_table =
1111 &dpm_context->dpm_tables.soc_table;
1112 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1113
1114 pstate_table->gfxclk_pstate.min = gfx_table->min;
1115 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1116 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
1117 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1118
1119 pstate_table->uclk_pstate.min = mem_table->min;
1120 pstate_table->uclk_pstate.peak = mem_table->max;
1121 pstate_table->uclk_pstate.curr.min = mem_table->min;
1122 pstate_table->uclk_pstate.curr.max = mem_table->max;
1123
1124 pstate_table->socclk_pstate.min = soc_table->min;
1125 pstate_table->socclk_pstate.peak = soc_table->max;
1126 pstate_table->socclk_pstate.curr.min = soc_table->min;
1127 pstate_table->socclk_pstate.curr.max = soc_table->max;
1128
1129 if (gfx_table->count > SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL &&
1130 mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL &&
1131 soc_table->count > SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL) {
1132 pstate_table->gfxclk_pstate.standard =
1133 gfx_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL].value;
1134 pstate_table->uclk_pstate.standard =
1135 mem_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL].value;
1136 pstate_table->socclk_pstate.standard =
1137 soc_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL].value;
1138 } else {
1139 pstate_table->gfxclk_pstate.standard =
1140 pstate_table->gfxclk_pstate.min;
1141 pstate_table->uclk_pstate.standard =
1142 pstate_table->uclk_pstate.min;
1143 pstate_table->socclk_pstate.standard =
1144 pstate_table->socclk_pstate.min;
1145 }
1146
1147 return 0;
1148 }
1149
smu_v13_0_6_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct smu_13_0_dpm_table * dpm_table)1150 static int smu_v13_0_6_get_clk_table(struct smu_context *smu,
1151 struct pp_clock_levels_with_latency *clocks,
1152 struct smu_13_0_dpm_table *dpm_table)
1153 {
1154 int i, count;
1155
1156 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS :
1157 dpm_table->count;
1158 clocks->num_levels = count;
1159
1160 for (i = 0; i < count; i++) {
1161 clocks->data[i].clocks_in_khz =
1162 dpm_table->dpm_levels[i].value * 1000;
1163 clocks->data[i].latency_in_us = 0;
1164 }
1165
1166 return 0;
1167 }
1168
smu_v13_0_6_freqs_in_same_level(int32_t frequency1,int32_t frequency2)1169 static int smu_v13_0_6_freqs_in_same_level(int32_t frequency1,
1170 int32_t frequency2)
1171 {
1172 return (abs(frequency1 - frequency2) <= EPSILON);
1173 }
1174
smu_v13_0_6_get_throttler_status(struct smu_context * smu)1175 static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu)
1176 {
1177 struct smu_power_context *smu_power = &smu->smu_power;
1178 struct smu_13_0_power_context *power_context = smu_power->power_context;
1179 uint32_t throttler_status = 0;
1180
1181 throttler_status = atomic_read(&power_context->throttle_status);
1182 dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status);
1183
1184 return throttler_status;
1185 }
1186
smu_v13_0_6_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)1187 static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
1188 MetricsMember_t member,
1189 uint32_t *value)
1190 {
1191 struct smu_table_context *smu_table = &smu->smu_table;
1192 MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
1193 MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
1194 MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
1195 int version = smu_v13_0_6_get_metrics_version(smu);
1196 struct amdgpu_device *adev = smu->adev;
1197 int ret = 0;
1198 int xcc_id;
1199
1200 ret = smu_v13_0_6_get_metrics_table(smu, NULL, false);
1201 if (ret)
1202 return ret;
1203
1204 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
1205 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
1206 return smu_v13_0_12_get_smu_metrics_data(smu, member, value);
1207
1208 /* For clocks with multiple instances, only report the first one */
1209 switch (member) {
1210 case METRICS_CURR_GFXCLK:
1211 case METRICS_AVERAGE_GFXCLK:
1212 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
1213 xcc_id = GET_INST(GC, 0);
1214 *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
1215 } else {
1216 *value = 0;
1217 }
1218 break;
1219 case METRICS_CURR_SOCCLK:
1220 case METRICS_AVERAGE_SOCCLK:
1221 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[0]);
1222 break;
1223 case METRICS_CURR_UCLK:
1224 case METRICS_AVERAGE_UCLK:
1225 *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
1226 break;
1227 case METRICS_CURR_VCLK:
1228 *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, version)[0]);
1229 break;
1230 case METRICS_CURR_DCLK:
1231 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, version)[0]);
1232 break;
1233 case METRICS_CURR_FCLK:
1234 *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, version));
1235 break;
1236 case METRICS_AVERAGE_GFXACTIVITY:
1237 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
1238 break;
1239 case METRICS_AVERAGE_MEMACTIVITY:
1240 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
1241 break;
1242 case METRICS_CURR_SOCKETPOWER:
1243 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version)) << 8;
1244 break;
1245 case METRICS_TEMPERATURE_HOTSPOT:
1246 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)) *
1247 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1248 break;
1249 case METRICS_TEMPERATURE_MEM:
1250 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version)) *
1251 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1252 break;
1253 /* This is the max of all VRs and not just SOC VR.
1254 * No need to define another data type for the same.
1255 */
1256 case METRICS_TEMPERATURE_VRSOC:
1257 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version)) *
1258 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1259 break;
1260 default:
1261 *value = UINT_MAX;
1262 break;
1263 }
1264
1265 return ret;
1266 }
1267
smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1268 static int smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context *smu,
1269 enum smu_clk_type clk_type,
1270 uint32_t *value)
1271 {
1272 MetricsMember_t member_type;
1273
1274 if (!value)
1275 return -EINVAL;
1276
1277 switch (clk_type) {
1278 case SMU_GFXCLK:
1279 member_type = METRICS_CURR_GFXCLK;
1280 break;
1281 case SMU_UCLK:
1282 member_type = METRICS_CURR_UCLK;
1283 break;
1284 case SMU_SOCCLK:
1285 member_type = METRICS_CURR_SOCCLK;
1286 break;
1287 case SMU_VCLK:
1288 member_type = METRICS_CURR_VCLK;
1289 break;
1290 case SMU_DCLK:
1291 member_type = METRICS_CURR_DCLK;
1292 break;
1293 case SMU_FCLK:
1294 member_type = METRICS_CURR_FCLK;
1295 break;
1296 default:
1297 return -EINVAL;
1298 }
1299
1300 return smu_v13_0_6_get_smu_metrics_data(smu, member_type, value);
1301 }
1302
smu_v13_0_6_print_clks(struct smu_context * smu,char * buf,int size,struct smu_13_0_dpm_table * single_dpm_table,uint32_t curr_clk,const char * clk_name)1303 static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf, int size,
1304 struct smu_13_0_dpm_table *single_dpm_table,
1305 uint32_t curr_clk, const char *clk_name)
1306 {
1307 struct pp_clock_levels_with_latency clocks;
1308 int i, ret, level = -1;
1309 uint32_t clk1, clk2;
1310
1311 ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
1312 if (ret) {
1313 dev_err(smu->adev->dev, "Attempt to get %s clk levels failed!",
1314 clk_name);
1315 return ret;
1316 }
1317
1318 if (!clocks.num_levels)
1319 return -EINVAL;
1320
1321 if (curr_clk < SMU_13_0_6_DSCLK_THRESHOLD) {
1322 size = sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk);
1323 for (i = 0; i < clocks.num_levels; i++)
1324 size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i,
1325 clocks.data[i].clocks_in_khz /
1326 1000);
1327
1328 } else {
1329 if ((clocks.num_levels == 1) ||
1330 (curr_clk < (clocks.data[0].clocks_in_khz / 1000)))
1331 level = 0;
1332 for (i = 0; i < clocks.num_levels; i++) {
1333 clk1 = clocks.data[i].clocks_in_khz / 1000;
1334
1335 if (i < (clocks.num_levels - 1))
1336 clk2 = clocks.data[i + 1].clocks_in_khz / 1000;
1337
1338 if (curr_clk == clk1) {
1339 level = i;
1340 } else if (curr_clk >= clk1 && curr_clk < clk2) {
1341 level = (curr_clk - clk1) <= (clk2 - curr_clk) ?
1342 i :
1343 i + 1;
1344 }
1345
1346 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
1347 clk1, (level == i) ? "*" : "");
1348 }
1349 }
1350
1351 return size;
1352 }
1353
smu_v13_0_6_print_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf)1354 static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
1355 enum smu_clk_type type, char *buf)
1356 {
1357 int now, size = 0;
1358 int ret = 0;
1359 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1360 struct smu_13_0_dpm_table *single_dpm_table;
1361 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1362 struct smu_13_0_dpm_context *dpm_context = NULL;
1363 uint32_t min_clk, max_clk;
1364
1365 smu_cmn_get_sysfs_buf(&buf, &size);
1366
1367 if (amdgpu_ras_intr_triggered()) {
1368 size += sysfs_emit_at(buf, size, "unavailable\n");
1369 return size;
1370 }
1371
1372 dpm_context = smu_dpm->dpm_context;
1373
1374 switch (type) {
1375 case SMU_OD_SCLK:
1376 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1377 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1378 pstate_table->gfxclk_pstate.curr.min,
1379 pstate_table->gfxclk_pstate.curr.max);
1380 break;
1381 case SMU_SCLK:
1382 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_GFXCLK,
1383 &now);
1384 if (ret) {
1385 dev_err(smu->adev->dev,
1386 "Attempt to get current gfx clk Failed!");
1387 return ret;
1388 }
1389
1390 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1391 min_clk = single_dpm_table->min;
1392 max_clk = single_dpm_table->max;
1393
1394 if (now < SMU_13_0_6_DSCLK_THRESHOLD) {
1395 size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
1396 now);
1397 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1398 min_clk);
1399 size += sysfs_emit_at(buf, size, "1: %uMhz\n",
1400 max_clk);
1401
1402 } else if (!smu_v13_0_6_freqs_in_same_level(now, min_clk) &&
1403 !smu_v13_0_6_freqs_in_same_level(now, max_clk)) {
1404 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1405 min_clk);
1406 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1407 now);
1408 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1409 max_clk);
1410 } else {
1411 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1412 min_clk,
1413 smu_v13_0_6_freqs_in_same_level(now, min_clk) ? "*" : "");
1414 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1415 max_clk,
1416 smu_v13_0_6_freqs_in_same_level(now, max_clk) ? "*" : "");
1417 }
1418
1419 break;
1420
1421 case SMU_OD_MCLK:
1422 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SET_UCLK_MAX)))
1423 return 0;
1424
1425 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
1426 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1427 pstate_table->uclk_pstate.curr.min,
1428 pstate_table->uclk_pstate.curr.max);
1429 break;
1430 case SMU_MCLK:
1431 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_UCLK,
1432 &now);
1433 if (ret) {
1434 dev_err(smu->adev->dev,
1435 "Attempt to get current mclk Failed!");
1436 return ret;
1437 }
1438
1439 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1440
1441 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1442 now, "mclk");
1443
1444 case SMU_SOCCLK:
1445 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_SOCCLK,
1446 &now);
1447 if (ret) {
1448 dev_err(smu->adev->dev,
1449 "Attempt to get current socclk Failed!");
1450 return ret;
1451 }
1452
1453 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1454
1455 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1456 now, "socclk");
1457
1458 case SMU_FCLK:
1459 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_FCLK,
1460 &now);
1461 if (ret) {
1462 dev_err(smu->adev->dev,
1463 "Attempt to get current fclk Failed!");
1464 return ret;
1465 }
1466
1467 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1468
1469 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1470 now, "fclk");
1471
1472 case SMU_VCLK:
1473 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_VCLK,
1474 &now);
1475 if (ret) {
1476 dev_err(smu->adev->dev,
1477 "Attempt to get current vclk Failed!");
1478 return ret;
1479 }
1480
1481 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1482
1483 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1484 now, "vclk");
1485
1486 case SMU_DCLK:
1487 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_DCLK,
1488 &now);
1489 if (ret) {
1490 dev_err(smu->adev->dev,
1491 "Attempt to get current dclk Failed!");
1492 return ret;
1493 }
1494
1495 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1496
1497 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1498 now, "dclk");
1499
1500 default:
1501 break;
1502 }
1503
1504 return size;
1505 }
1506
smu_v13_0_6_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)1507 static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max,
1508 uint32_t feature_mask, uint32_t level)
1509 {
1510 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1511 uint32_t freq;
1512 int ret = 0;
1513
1514 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1515 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK))) {
1516 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
1517 ret = smu_cmn_send_smc_msg_with_param(
1518 smu,
1519 (max ? SMU_MSG_SetSoftMaxGfxClk :
1520 SMU_MSG_SetSoftMinGfxclk),
1521 freq & 0xffff, NULL);
1522 if (ret) {
1523 dev_err(smu->adev->dev,
1524 "Failed to set soft %s gfxclk !\n",
1525 max ? "max" : "min");
1526 return ret;
1527 }
1528 }
1529
1530 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1531 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK))) {
1532 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level]
1533 .value;
1534 ret = smu_cmn_send_smc_msg_with_param(
1535 smu,
1536 (max ? SMU_MSG_SetSoftMaxByFreq :
1537 SMU_MSG_SetSoftMinByFreq),
1538 (PPCLK_UCLK << 16) | (freq & 0xffff), NULL);
1539 if (ret) {
1540 dev_err(smu->adev->dev,
1541 "Failed to set soft %s memclk !\n",
1542 max ? "max" : "min");
1543 return ret;
1544 }
1545 }
1546
1547 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1548 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK))) {
1549 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
1550 ret = smu_cmn_send_smc_msg_with_param(
1551 smu,
1552 (max ? SMU_MSG_SetSoftMaxByFreq :
1553 SMU_MSG_SetSoftMinByFreq),
1554 (PPCLK_SOCCLK << 16) | (freq & 0xffff), NULL);
1555 if (ret) {
1556 dev_err(smu->adev->dev,
1557 "Failed to set soft %s socclk !\n",
1558 max ? "max" : "min");
1559 return ret;
1560 }
1561 }
1562
1563 return ret;
1564 }
1565
smu_v13_0_6_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)1566 static int smu_v13_0_6_force_clk_levels(struct smu_context *smu,
1567 enum smu_clk_type type, uint32_t mask)
1568 {
1569 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1570 struct smu_13_0_dpm_table *single_dpm_table = NULL;
1571 uint32_t soft_min_level, soft_max_level;
1572 int ret = 0;
1573
1574 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1575 soft_max_level = mask ? (fls(mask) - 1) : 0;
1576
1577 switch (type) {
1578 case SMU_SCLK:
1579 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1580 if (soft_max_level >= single_dpm_table->count) {
1581 dev_err(smu->adev->dev,
1582 "Clock level specified %d is over max allowed %d\n",
1583 soft_max_level, single_dpm_table->count - 1);
1584 ret = -EINVAL;
1585 break;
1586 }
1587
1588 ret = smu_v13_0_6_upload_dpm_level(
1589 smu, false, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1590 soft_min_level);
1591 if (ret) {
1592 dev_err(smu->adev->dev,
1593 "Failed to upload boot level to lowest!\n");
1594 break;
1595 }
1596
1597 ret = smu_v13_0_6_upload_dpm_level(
1598 smu, true, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1599 soft_max_level);
1600 if (ret)
1601 dev_err(smu->adev->dev,
1602 "Failed to upload dpm max level to highest!\n");
1603
1604 break;
1605
1606 case SMU_MCLK:
1607 case SMU_SOCCLK:
1608 case SMU_FCLK:
1609 /*
1610 * Should not arrive here since smu_13_0_6 does not
1611 * support mclk/socclk/fclk softmin/softmax settings
1612 */
1613 ret = -EINVAL;
1614 break;
1615
1616 default:
1617 break;
1618 }
1619
1620 return ret;
1621 }
1622
smu_v13_0_6_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1623 static int smu_v13_0_6_get_current_activity_percent(struct smu_context *smu,
1624 enum amd_pp_sensors sensor,
1625 uint32_t *value)
1626 {
1627 int ret = 0;
1628
1629 if (!value)
1630 return -EINVAL;
1631
1632 switch (sensor) {
1633 case AMDGPU_PP_SENSOR_GPU_LOAD:
1634 ret = smu_v13_0_6_get_smu_metrics_data(
1635 smu, METRICS_AVERAGE_GFXACTIVITY, value);
1636 break;
1637 case AMDGPU_PP_SENSOR_MEM_LOAD:
1638 ret = smu_v13_0_6_get_smu_metrics_data(
1639 smu, METRICS_AVERAGE_MEMACTIVITY, value);
1640 break;
1641 default:
1642 dev_err(smu->adev->dev,
1643 "Invalid sensor for retrieving clock activity\n");
1644 return -EINVAL;
1645 }
1646
1647 return ret;
1648 }
1649
smu_v13_0_6_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1650 static int smu_v13_0_6_thermal_get_temperature(struct smu_context *smu,
1651 enum amd_pp_sensors sensor,
1652 uint32_t *value)
1653 {
1654 int ret = 0;
1655
1656 if (!value)
1657 return -EINVAL;
1658
1659 switch (sensor) {
1660 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1661 ret = smu_v13_0_6_get_smu_metrics_data(
1662 smu, METRICS_TEMPERATURE_HOTSPOT, value);
1663 break;
1664 case AMDGPU_PP_SENSOR_MEM_TEMP:
1665 ret = smu_v13_0_6_get_smu_metrics_data(
1666 smu, METRICS_TEMPERATURE_MEM, value);
1667 break;
1668 default:
1669 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1670 return -EINVAL;
1671 }
1672
1673 return ret;
1674 }
1675
smu_v13_0_6_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1676 static int smu_v13_0_6_read_sensor(struct smu_context *smu,
1677 enum amd_pp_sensors sensor, void *data,
1678 uint32_t *size)
1679 {
1680 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1681 int ret = 0;
1682
1683 if (amdgpu_ras_intr_triggered())
1684 return 0;
1685
1686 if (!data || !size)
1687 return -EINVAL;
1688
1689 switch (sensor) {
1690 case AMDGPU_PP_SENSOR_MEM_LOAD:
1691 case AMDGPU_PP_SENSOR_GPU_LOAD:
1692 ret = smu_v13_0_6_get_current_activity_percent(smu, sensor,
1693 (uint32_t *)data);
1694 *size = 4;
1695 break;
1696 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1697 ret = smu_v13_0_6_get_smu_metrics_data(smu,
1698 METRICS_CURR_SOCKETPOWER,
1699 (uint32_t *)data);
1700 *size = 4;
1701 break;
1702 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1703 case AMDGPU_PP_SENSOR_MEM_TEMP:
1704 ret = smu_v13_0_6_thermal_get_temperature(smu, sensor,
1705 (uint32_t *)data);
1706 *size = 4;
1707 break;
1708 case AMDGPU_PP_SENSOR_GFX_MCLK:
1709 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1710 smu, SMU_UCLK, (uint32_t *)data);
1711 /* the output clock frequency in 10K unit */
1712 *(uint32_t *)data *= 100;
1713 *size = 4;
1714 break;
1715 case AMDGPU_PP_SENSOR_GFX_SCLK:
1716 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1717 smu, SMU_GFXCLK, (uint32_t *)data);
1718 *(uint32_t *)data *= 100;
1719 *size = 4;
1720 break;
1721 case AMDGPU_PP_SENSOR_VDDGFX:
1722 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1723 *size = 4;
1724 break;
1725 case AMDGPU_PP_SENSOR_VDDBOARD:
1726 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(BOARD_VOLTAGE))) {
1727 *(uint32_t *)data = dpm_context->board_volt;
1728 *size = 4;
1729 break;
1730 } else {
1731 ret = -EOPNOTSUPP;
1732 break;
1733 }
1734 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1735 default:
1736 ret = -EOPNOTSUPP;
1737 break;
1738 }
1739
1740 return ret;
1741 }
1742
smu_v13_0_6_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1743 static int smu_v13_0_6_get_power_limit(struct smu_context *smu,
1744 uint32_t *current_power_limit,
1745 uint32_t *default_power_limit,
1746 uint32_t *max_power_limit,
1747 uint32_t *min_power_limit)
1748 {
1749 struct smu_table_context *smu_table = &smu->smu_table;
1750 struct PPTable_t *pptable =
1751 (struct PPTable_t *)smu_table->driver_pptable;
1752 uint32_t power_limit = 0;
1753 int ret;
1754
1755 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit);
1756
1757 if (ret) {
1758 dev_err(smu->adev->dev, "Couldn't get PPT limit");
1759 return -EINVAL;
1760 }
1761
1762 if (current_power_limit)
1763 *current_power_limit = power_limit;
1764 if (default_power_limit)
1765 *default_power_limit = power_limit;
1766
1767 if (max_power_limit) {
1768 *max_power_limit = pptable->MaxSocketPowerLimit;
1769 }
1770
1771 if (min_power_limit)
1772 *min_power_limit = 0;
1773 return 0;
1774 }
1775
smu_v13_0_6_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1776 static int smu_v13_0_6_set_power_limit(struct smu_context *smu,
1777 enum smu_ppt_limit_type limit_type,
1778 uint32_t limit)
1779 {
1780 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1781 }
1782
smu_v13_0_6_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1783 static int smu_v13_0_6_irq_process(struct amdgpu_device *adev,
1784 struct amdgpu_irq_src *source,
1785 struct amdgpu_iv_entry *entry)
1786 {
1787 struct smu_context *smu = adev->powerplay.pp_handle;
1788 struct smu_power_context *smu_power = &smu->smu_power;
1789 struct smu_13_0_power_context *power_context = smu_power->power_context;
1790 uint32_t client_id = entry->client_id;
1791 uint32_t ctxid = entry->src_data[0];
1792 uint32_t src_id = entry->src_id;
1793 uint32_t data;
1794
1795 if (client_id == SOC15_IH_CLIENTID_MP1) {
1796 if (src_id == IH_INTERRUPT_ID_TO_DRIVER) {
1797 /* ACK SMUToHost interrupt */
1798 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1799 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1800 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1801 /*
1802 * ctxid is used to distinguish different events for SMCToHost
1803 * interrupt.
1804 */
1805 switch (ctxid) {
1806 case IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1807 /*
1808 * Increment the throttle interrupt counter
1809 */
1810 atomic64_inc(&smu->throttle_int_counter);
1811
1812 if (!atomic_read(&adev->throttling_logging_enabled))
1813 return 0;
1814
1815 /* This uses the new method which fixes the
1816 * incorrect throttling status reporting
1817 * through metrics table. For older FWs,
1818 * it will be ignored.
1819 */
1820 if (__ratelimit(&adev->throttling_logging_rs)) {
1821 atomic_set(
1822 &power_context->throttle_status,
1823 entry->src_data[1]);
1824 schedule_work(&smu->throttling_logging_work);
1825 }
1826 break;
1827 default:
1828 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1829 ctxid, client_id);
1830 break;
1831 }
1832 }
1833 }
1834
1835 return 0;
1836 }
1837
smu_v13_0_6_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1838 static int smu_v13_0_6_set_irq_state(struct amdgpu_device *adev,
1839 struct amdgpu_irq_src *source,
1840 unsigned tyep,
1841 enum amdgpu_interrupt_state state)
1842 {
1843 uint32_t val = 0;
1844
1845 switch (state) {
1846 case AMDGPU_IRQ_STATE_DISABLE:
1847 /* For MP1 SW irqs */
1848 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1849 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1850 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1851
1852 break;
1853 case AMDGPU_IRQ_STATE_ENABLE:
1854 /* For MP1 SW irqs */
1855 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1856 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1857 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1858 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1859
1860 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1861 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1862 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1863
1864 break;
1865 default:
1866 break;
1867 }
1868
1869 return 0;
1870 }
1871
1872 static const struct amdgpu_irq_src_funcs smu_v13_0_6_irq_funcs = {
1873 .set = smu_v13_0_6_set_irq_state,
1874 .process = smu_v13_0_6_irq_process,
1875 };
1876
smu_v13_0_6_register_irq_handler(struct smu_context * smu)1877 static int smu_v13_0_6_register_irq_handler(struct smu_context *smu)
1878 {
1879 struct amdgpu_device *adev = smu->adev;
1880 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1881 int ret = 0;
1882
1883 if (amdgpu_sriov_vf(adev))
1884 return 0;
1885
1886 irq_src->num_types = 1;
1887 irq_src->funcs = &smu_v13_0_6_irq_funcs;
1888
1889 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1890 IH_INTERRUPT_ID_TO_DRIVER,
1891 irq_src);
1892 if (ret)
1893 return ret;
1894
1895 return ret;
1896 }
1897
smu_v13_0_6_notify_unload(struct smu_context * smu)1898 static int smu_v13_0_6_notify_unload(struct smu_context *smu)
1899 {
1900 if (amdgpu_in_reset(smu->adev))
1901 return 0;
1902
1903 dev_dbg(smu->adev->dev, "Notify PMFW about driver unload");
1904 /* Ignore return, just intimate FW that driver is not going to be there */
1905 smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
1906
1907 return 0;
1908 }
1909
smu_v13_0_6_mca_set_debug_mode(struct smu_context * smu,bool enable)1910 static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)
1911 {
1912 /* NOTE: this ClearMcaOnRead message is only supported for smu version 85.72.0 or higher */
1913 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(MCA_DEBUG_MODE)))
1914 return 0;
1915
1916 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ClearMcaOnRead,
1917 enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK,
1918 NULL);
1919 }
1920
smu_v13_0_6_system_features_control(struct smu_context * smu,bool enable)1921 static int smu_v13_0_6_system_features_control(struct smu_context *smu,
1922 bool enable)
1923 {
1924 struct amdgpu_device *adev = smu->adev;
1925 int ret = 0;
1926
1927 if (amdgpu_sriov_vf(adev))
1928 return 0;
1929
1930 if (enable) {
1931 if (!(adev->flags & AMD_IS_APU))
1932 ret = smu_v13_0_system_features_control(smu, enable);
1933 } else {
1934 /* Notify FW that the device is no longer driver managed */
1935 smu_v13_0_6_notify_unload(smu);
1936 }
1937
1938 return ret;
1939 }
1940
smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context * smu,uint32_t min,uint32_t max)1941 static int smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context *smu,
1942 uint32_t min,
1943 uint32_t max)
1944 {
1945 int ret;
1946
1947 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1948 max & 0xffff, NULL);
1949 if (ret)
1950 return ret;
1951
1952 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinGfxclk,
1953 min & 0xffff, NULL);
1954
1955 return ret;
1956 }
1957
smu_v13_0_6_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1958 static int smu_v13_0_6_set_performance_level(struct smu_context *smu,
1959 enum amd_dpm_forced_level level)
1960 {
1961 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1962 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1963 struct smu_13_0_dpm_table *gfx_table =
1964 &dpm_context->dpm_tables.gfx_table;
1965 struct smu_13_0_dpm_table *uclk_table =
1966 &dpm_context->dpm_tables.uclk_table;
1967 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1968 int ret;
1969
1970 /* Disable determinism if switching to another mode */
1971 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1972 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1973 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1974 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1975 }
1976
1977 switch (level) {
1978 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1979 return 0;
1980
1981 case AMD_DPM_FORCED_LEVEL_AUTO:
1982 if ((gfx_table->min != pstate_table->gfxclk_pstate.curr.min) ||
1983 (gfx_table->max != pstate_table->gfxclk_pstate.curr.max)) {
1984 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
1985 smu, gfx_table->min, gfx_table->max);
1986 if (ret)
1987 return ret;
1988
1989 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
1990 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1991 }
1992
1993 if (uclk_table->max != pstate_table->uclk_pstate.curr.max) {
1994 /* Min UCLK is not expected to be changed */
1995 ret = smu_v13_0_set_soft_freq_limited_range(
1996 smu, SMU_UCLK, 0, uclk_table->max, false);
1997 if (ret)
1998 return ret;
1999 pstate_table->uclk_pstate.curr.max = uclk_table->max;
2000 }
2001 smu_v13_0_reset_custom_level(smu);
2002
2003 return 0;
2004 case AMD_DPM_FORCED_LEVEL_MANUAL:
2005 return 0;
2006 default:
2007 break;
2008 }
2009
2010 return -EOPNOTSUPP;
2011 }
2012
smu_v13_0_6_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)2013 static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu,
2014 enum smu_clk_type clk_type,
2015 uint32_t min, uint32_t max,
2016 bool automatic)
2017 {
2018 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2019 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2020 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2021 struct amdgpu_device *adev = smu->adev;
2022 uint32_t min_clk;
2023 uint32_t max_clk;
2024 int ret = 0;
2025
2026 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&
2027 clk_type != SMU_UCLK)
2028 return -EINVAL;
2029
2030 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
2031 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
2032 return -EINVAL;
2033
2034 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
2035 if (min >= max) {
2036 dev_err(smu->adev->dev,
2037 "Minimum clk should be less than the maximum allowed clock\n");
2038 return -EINVAL;
2039 }
2040
2041 if (clk_type == SMU_GFXCLK) {
2042 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
2043 (max == pstate_table->gfxclk_pstate.curr.max))
2044 return 0;
2045
2046 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
2047 smu, min, max);
2048 if (!ret) {
2049 pstate_table->gfxclk_pstate.curr.min = min;
2050 pstate_table->gfxclk_pstate.curr.max = max;
2051 }
2052 }
2053
2054 if (clk_type == SMU_UCLK) {
2055 if (max == pstate_table->uclk_pstate.curr.max)
2056 return 0;
2057 /* For VF, only allowed in FW versions 85.102 or greater */
2058 if (!smu_v13_0_6_cap_supported(smu,
2059 SMU_CAP(SET_UCLK_MAX)))
2060 return -EOPNOTSUPP;
2061 /* Only max clock limiting is allowed for UCLK */
2062 ret = smu_v13_0_set_soft_freq_limited_range(
2063 smu, SMU_UCLK, 0, max, false);
2064 if (!ret)
2065 pstate_table->uclk_pstate.curr.max = max;
2066 }
2067
2068 return ret;
2069 }
2070
2071 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2072 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
2073 (max > dpm_context->dpm_tables.gfx_table.max)) {
2074 dev_warn(
2075 adev->dev,
2076 "Invalid max frequency %d MHz specified for determinism\n",
2077 max);
2078 return -EINVAL;
2079 }
2080
2081 /* Restore default min/max clocks and enable determinism */
2082 min_clk = dpm_context->dpm_tables.gfx_table.min;
2083 max_clk = dpm_context->dpm_tables.gfx_table.max;
2084 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(smu, min_clk,
2085 max_clk);
2086 if (!ret) {
2087 usleep_range(500, 1000);
2088 ret = smu_cmn_send_smc_msg_with_param(
2089 smu, SMU_MSG_EnableDeterminism, max, NULL);
2090 if (ret) {
2091 dev_err(adev->dev,
2092 "Failed to enable determinism at GFX clock %d MHz\n",
2093 max);
2094 } else {
2095 pstate_table->gfxclk_pstate.curr.min = min_clk;
2096 pstate_table->gfxclk_pstate.curr.max = max;
2097 }
2098 }
2099 }
2100
2101 return ret;
2102 }
2103
smu_v13_0_6_usr_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2104 static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu,
2105 enum PP_OD_DPM_TABLE_COMMAND type,
2106 long input[], uint32_t size)
2107 {
2108 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2109 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2110 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2111 uint32_t min_clk;
2112 uint32_t max_clk;
2113 int ret = 0;
2114
2115 /* Only allowed in manual or determinism mode */
2116 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
2117 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
2118 return -EINVAL;
2119
2120 switch (type) {
2121 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2122 if (size != 2) {
2123 dev_err(smu->adev->dev,
2124 "Input parameter number not correct\n");
2125 return -EINVAL;
2126 }
2127
2128 if (input[0] == 0) {
2129 if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
2130 dev_warn(
2131 smu->adev->dev,
2132 "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
2133 input[1],
2134 dpm_context->dpm_tables.gfx_table.min);
2135 pstate_table->gfxclk_pstate.custom.min =
2136 pstate_table->gfxclk_pstate.curr.min;
2137 return -EINVAL;
2138 }
2139
2140 pstate_table->gfxclk_pstate.custom.min = input[1];
2141 } else if (input[0] == 1) {
2142 if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
2143 dev_warn(
2144 smu->adev->dev,
2145 "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2146 input[1],
2147 dpm_context->dpm_tables.gfx_table.max);
2148 pstate_table->gfxclk_pstate.custom.max =
2149 pstate_table->gfxclk_pstate.curr.max;
2150 return -EINVAL;
2151 }
2152
2153 pstate_table->gfxclk_pstate.custom.max = input[1];
2154 } else {
2155 return -EINVAL;
2156 }
2157 break;
2158 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2159 if (size != 2) {
2160 dev_err(smu->adev->dev,
2161 "Input parameter number not correct\n");
2162 return -EINVAL;
2163 }
2164
2165 if (!smu_cmn_feature_is_enabled(smu,
2166 SMU_FEATURE_DPM_UCLK_BIT)) {
2167 dev_warn(smu->adev->dev,
2168 "UCLK_LIMITS setting not supported!\n");
2169 return -EOPNOTSUPP;
2170 }
2171
2172 if (input[0] == 0) {
2173 dev_info(smu->adev->dev,
2174 "Setting min UCLK level is not supported");
2175 return -EINVAL;
2176 } else if (input[0] == 1) {
2177 if (input[1] > dpm_context->dpm_tables.uclk_table.max) {
2178 dev_warn(
2179 smu->adev->dev,
2180 "Maximum UCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2181 input[1],
2182 dpm_context->dpm_tables.uclk_table.max);
2183 pstate_table->uclk_pstate.custom.max =
2184 pstate_table->uclk_pstate.curr.max;
2185 return -EINVAL;
2186 }
2187
2188 pstate_table->uclk_pstate.custom.max = input[1];
2189 }
2190 break;
2191
2192 case PP_OD_RESTORE_DEFAULT_TABLE:
2193 if (size != 0) {
2194 dev_err(smu->adev->dev,
2195 "Input parameter number not correct\n");
2196 return -EINVAL;
2197 } else {
2198 /* Use the default frequencies for manual and determinism mode */
2199 min_clk = dpm_context->dpm_tables.gfx_table.min;
2200 max_clk = dpm_context->dpm_tables.gfx_table.max;
2201
2202 ret = smu_v13_0_6_set_soft_freq_limited_range(
2203 smu, SMU_GFXCLK, min_clk, max_clk, false);
2204
2205 if (ret)
2206 return ret;
2207
2208 min_clk = dpm_context->dpm_tables.uclk_table.min;
2209 max_clk = dpm_context->dpm_tables.uclk_table.max;
2210 ret = smu_v13_0_6_set_soft_freq_limited_range(
2211 smu, SMU_UCLK, min_clk, max_clk, false);
2212 if (ret)
2213 return ret;
2214 smu_v13_0_reset_custom_level(smu);
2215 }
2216 break;
2217 case PP_OD_COMMIT_DPM_TABLE:
2218 if (size != 0) {
2219 dev_err(smu->adev->dev,
2220 "Input parameter number not correct\n");
2221 return -EINVAL;
2222 } else {
2223 if (!pstate_table->gfxclk_pstate.custom.min)
2224 pstate_table->gfxclk_pstate.custom.min =
2225 pstate_table->gfxclk_pstate.curr.min;
2226
2227 if (!pstate_table->gfxclk_pstate.custom.max)
2228 pstate_table->gfxclk_pstate.custom.max =
2229 pstate_table->gfxclk_pstate.curr.max;
2230
2231 min_clk = pstate_table->gfxclk_pstate.custom.min;
2232 max_clk = pstate_table->gfxclk_pstate.custom.max;
2233
2234 ret = smu_v13_0_6_set_soft_freq_limited_range(
2235 smu, SMU_GFXCLK, min_clk, max_clk, false);
2236
2237 if (ret)
2238 return ret;
2239
2240 if (!pstate_table->uclk_pstate.custom.max)
2241 return 0;
2242
2243 min_clk = pstate_table->uclk_pstate.curr.min;
2244 max_clk = pstate_table->uclk_pstate.custom.max;
2245 return smu_v13_0_6_set_soft_freq_limited_range(
2246 smu, SMU_UCLK, min_clk, max_clk, false);
2247 }
2248 break;
2249 default:
2250 return -ENOSYS;
2251 }
2252
2253 return ret;
2254 }
2255
smu_v13_0_6_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)2256 static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
2257 uint64_t *feature_mask)
2258 {
2259 int ret;
2260
2261 ret = smu_cmn_get_enabled_mask(smu, feature_mask);
2262
2263 if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
2264 *feature_mask = 0;
2265 ret = 0;
2266 }
2267
2268 return ret;
2269 }
2270
smu_v13_0_6_is_dpm_running(struct smu_context * smu)2271 static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
2272 {
2273 int ret;
2274 uint64_t feature_enabled;
2275
2276 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
2277 return smu_v13_0_12_is_dpm_running(smu);
2278
2279 ret = smu_v13_0_6_get_enabled_mask(smu, &feature_enabled);
2280
2281 if (ret)
2282 return false;
2283
2284 return !!(feature_enabled & SMC_DPM_FEATURE);
2285 }
2286
smu_v13_0_6_request_i2c_xfer(struct smu_context * smu,void * table_data)2287 static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu,
2288 void *table_data)
2289 {
2290 struct smu_table_context *smu_table = &smu->smu_table;
2291 struct smu_table *table = &smu_table->driver_table;
2292 struct amdgpu_device *adev = smu->adev;
2293 uint32_t table_size;
2294 int ret = 0;
2295
2296 if (!table_data)
2297 return -EINVAL;
2298
2299 table_size = smu_table->tables[SMU_TABLE_I2C_COMMANDS].size;
2300
2301 memcpy(table->cpu_addr, table_data, table_size);
2302 /* Flush hdp cache */
2303 amdgpu_asic_flush_hdp(adev, NULL);
2304 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction,
2305 NULL);
2306
2307 return ret;
2308 }
2309
smu_v13_0_6_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2310 static int smu_v13_0_6_i2c_xfer(struct i2c_adapter *i2c_adap,
2311 struct i2c_msg *msg, int num_msgs)
2312 {
2313 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2314 struct amdgpu_device *adev = smu_i2c->adev;
2315 struct smu_context *smu = adev->powerplay.pp_handle;
2316 struct smu_table_context *smu_table = &smu->smu_table;
2317 struct smu_table *table = &smu_table->driver_table;
2318 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2319 int i, j, r, c;
2320 u16 dir;
2321
2322 if (!adev->pm.dpm_enabled)
2323 return -EBUSY;
2324
2325 req = kzalloc(sizeof(*req), GFP_KERNEL);
2326 if (!req)
2327 return -ENOMEM;
2328
2329 req->I2CcontrollerPort = smu_i2c->port;
2330 req->I2CSpeed = I2C_SPEED_FAST_400K;
2331 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2332 dir = msg[0].flags & I2C_M_RD;
2333
2334 for (c = i = 0; i < num_msgs; i++) {
2335 for (j = 0; j < msg[i].len; j++, c++) {
2336 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2337
2338 if (!(msg[i].flags & I2C_M_RD)) {
2339 /* write */
2340 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2341 cmd->ReadWriteData = msg[i].buf[j];
2342 }
2343
2344 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2345 /* The direction changes.
2346 */
2347 dir = msg[i].flags & I2C_M_RD;
2348 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2349 }
2350
2351 req->NumCmds++;
2352
2353 /*
2354 * Insert STOP if we are at the last byte of either last
2355 * message for the transaction or the client explicitly
2356 * requires a STOP at this particular message.
2357 */
2358 if ((j == msg[i].len - 1) &&
2359 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2360 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2361 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2362 }
2363 }
2364 }
2365 mutex_lock(&adev->pm.mutex);
2366 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2367 if (r) {
2368 /* Retry once, in case of an i2c collision */
2369 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2370 if (r)
2371 goto fail;
2372 }
2373
2374 for (c = i = 0; i < num_msgs; i++) {
2375 if (!(msg[i].flags & I2C_M_RD)) {
2376 c += msg[i].len;
2377 continue;
2378 }
2379 for (j = 0; j < msg[i].len; j++, c++) {
2380 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2381
2382 msg[i].buf[j] = cmd->ReadWriteData;
2383 }
2384 }
2385 r = num_msgs;
2386 fail:
2387 mutex_unlock(&adev->pm.mutex);
2388 kfree(req);
2389 return r;
2390 }
2391
smu_v13_0_6_i2c_func(struct i2c_adapter * adap)2392 static u32 smu_v13_0_6_i2c_func(struct i2c_adapter *adap)
2393 {
2394 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2395 }
2396
2397 static const struct i2c_algorithm smu_v13_0_6_i2c_algo = {
2398 .master_xfer = smu_v13_0_6_i2c_xfer,
2399 .functionality = smu_v13_0_6_i2c_func,
2400 };
2401
2402 static const struct i2c_adapter_quirks smu_v13_0_6_i2c_control_quirks = {
2403 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2404 .max_read_len = MAX_SW_I2C_COMMANDS,
2405 .max_write_len = MAX_SW_I2C_COMMANDS,
2406 .max_comb_1st_msg_len = 2,
2407 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2408 };
2409
smu_v13_0_6_i2c_control_init(struct smu_context * smu)2410 static int smu_v13_0_6_i2c_control_init(struct smu_context *smu)
2411 {
2412 struct amdgpu_device *adev = smu->adev;
2413 int res, i;
2414
2415 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2416 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2417 struct i2c_adapter *control = &smu_i2c->adapter;
2418
2419 smu_i2c->adev = adev;
2420 smu_i2c->port = i;
2421 mutex_init(&smu_i2c->mutex);
2422 control->owner = THIS_MODULE;
2423 control->dev.parent = &adev->pdev->dev;
2424 control->algo = &smu_v13_0_6_i2c_algo;
2425 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2426 control->quirks = &smu_v13_0_6_i2c_control_quirks;
2427 i2c_set_adapdata(control, smu_i2c);
2428
2429 res = i2c_add_adapter(control);
2430 if (res) {
2431 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2432 goto Out_err;
2433 }
2434 }
2435
2436 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2437 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2438
2439 return 0;
2440 Out_err:
2441 for ( ; i >= 0; i--) {
2442 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2443 struct i2c_adapter *control = &smu_i2c->adapter;
2444
2445 i2c_del_adapter(control);
2446 }
2447 return res;
2448 }
2449
smu_v13_0_6_i2c_control_fini(struct smu_context * smu)2450 static void smu_v13_0_6_i2c_control_fini(struct smu_context *smu)
2451 {
2452 struct amdgpu_device *adev = smu->adev;
2453 int i;
2454
2455 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2456 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2457 struct i2c_adapter *control = &smu_i2c->adapter;
2458
2459 i2c_del_adapter(control);
2460 }
2461 adev->pm.ras_eeprom_i2c_bus = NULL;
2462 adev->pm.fru_eeprom_i2c_bus = NULL;
2463 }
2464
smu_v13_0_6_get_unique_id(struct smu_context * smu)2465 static void smu_v13_0_6_get_unique_id(struct smu_context *smu)
2466 {
2467 struct amdgpu_device *adev = smu->adev;
2468 struct smu_table_context *smu_table = &smu->smu_table;
2469 struct PPTable_t *pptable =
2470 (struct PPTable_t *)smu_table->driver_pptable;
2471
2472 adev->unique_id = pptable->PublicSerialNumber_AID;
2473 }
2474
smu_v13_0_6_get_bamaco_support(struct smu_context * smu)2475 static int smu_v13_0_6_get_bamaco_support(struct smu_context *smu)
2476 {
2477 /* smu_13_0_6 does not support baco */
2478
2479 return 0;
2480 }
2481
2482 static const char *const throttling_logging_label[] = {
2483 [THROTTLER_PROCHOT_BIT] = "Prochot",
2484 [THROTTLER_PPT_BIT] = "PPT",
2485 [THROTTLER_THERMAL_SOCKET_BIT] = "SOC",
2486 [THROTTLER_THERMAL_VR_BIT] = "VR",
2487 [THROTTLER_THERMAL_HBM_BIT] = "HBM"
2488 };
2489
smu_v13_0_6_log_thermal_throttling_event(struct smu_context * smu)2490 static void smu_v13_0_6_log_thermal_throttling_event(struct smu_context *smu)
2491 {
2492 int throttler_idx, throttling_events = 0, buf_idx = 0;
2493 struct amdgpu_device *adev = smu->adev;
2494 uint32_t throttler_status;
2495 char log_buf[256];
2496
2497 throttler_status = smu_v13_0_6_get_throttler_status(smu);
2498 if (!throttler_status)
2499 return;
2500
2501 memset(log_buf, 0, sizeof(log_buf));
2502 for (throttler_idx = 0;
2503 throttler_idx < ARRAY_SIZE(throttling_logging_label);
2504 throttler_idx++) {
2505 if (throttler_status & (1U << throttler_idx)) {
2506 throttling_events++;
2507 buf_idx += snprintf(
2508 log_buf + buf_idx, sizeof(log_buf) - buf_idx,
2509 "%s%s", throttling_events > 1 ? " and " : "",
2510 throttling_logging_label[throttler_idx]);
2511 if (buf_idx >= sizeof(log_buf)) {
2512 dev_err(adev->dev, "buffer overflow!\n");
2513 log_buf[sizeof(log_buf) - 1] = '\0';
2514 break;
2515 }
2516 }
2517 }
2518
2519 dev_warn(adev->dev,
2520 "WARN: GPU is throttled, expect performance decrease. %s.\n",
2521 log_buf);
2522 kgd2kfd_smi_event_throttle(
2523 smu->adev->kfd.dev,
2524 smu_cmn_get_indep_throttler_status(throttler_status,
2525 smu_v13_0_6_throttler_map));
2526 }
2527
2528 static int
smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context * smu)2529 smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context *smu)
2530 {
2531 struct amdgpu_device *adev = smu->adev;
2532
2533 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL),
2534 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
2535 }
2536
smu_v13_0_6_get_current_pcie_link_speed(struct smu_context * smu)2537 static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
2538 {
2539 struct amdgpu_device *adev = smu->adev;
2540 uint32_t speed_level;
2541 uint32_t esm_ctrl;
2542
2543 /* TODO: confirm this on real target */
2544 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2545 if ((esm_ctrl >> 15) & 0x1)
2546 return (((esm_ctrl >> 8) & 0x7F) + 128);
2547
2548 speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2549 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2550 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2551 if (speed_level > LINK_SPEED_MAX)
2552 speed_level = 0;
2553
2554 return pcie_gen_to_speed(speed_level + 1);
2555 }
2556
smu_v13_0_6_get_xcp_metrics(struct smu_context * smu,int xcp_id,void * table)2557 static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id,
2558 void *table)
2559 {
2560 const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;
2561 int version = smu_v13_0_6_get_metrics_version(smu);
2562 struct amdgpu_partition_metrics_v1_0 *xcp_metrics;
2563 struct amdgpu_device *adev = smu->adev;
2564 int ret, inst, i, j, k, idx;
2565 MetricsTableV0_t *metrics_v0;
2566 MetricsTableV1_t *metrics_v1;
2567 MetricsTableV2_t *metrics_v2;
2568 struct amdgpu_xcp *xcp;
2569 u32 inst_mask;
2570 bool per_inst;
2571
2572 if (!table)
2573 return sizeof(*xcp_metrics);
2574
2575 for_each_xcp(adev->xcp_mgr, xcp, i) {
2576 if (xcp->id == xcp_id)
2577 break;
2578 }
2579 if (i == adev->xcp_mgr->num_xcps)
2580 return -EINVAL;
2581
2582 xcp_metrics = (struct amdgpu_partition_metrics_v1_0 *)table;
2583 smu_cmn_init_partition_metrics(xcp_metrics, 1, 0);
2584
2585 metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
2586 if (!metrics_v0)
2587 return -ENOMEM;
2588
2589 ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false);
2590 if (ret) {
2591 kfree(metrics_v0);
2592 return ret;
2593 }
2594
2595 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
2596 IP_VERSION(13, 0, 12) &&
2597 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
2598 ret = smu_v13_0_12_get_xcp_metrics(smu, xcp, table, metrics_v0);
2599 goto out;
2600 }
2601
2602 metrics_v1 = (MetricsTableV1_t *)metrics_v0;
2603 metrics_v2 = (MetricsTableV2_t *)metrics_v0;
2604
2605 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
2606
2607 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
2608 idx = 0;
2609 for_each_inst(k, inst_mask) {
2610 /* Both JPEG and VCN has same instances */
2611 inst = GET_INST(VCN, k);
2612
2613 for (j = 0; j < num_jpeg_rings; ++j) {
2614 xcp_metrics->jpeg_busy[(idx * num_jpeg_rings) + j] =
2615 SMUQ10_ROUND(GET_METRIC_FIELD(
2616 JpegBusy,
2617 version)[(inst * num_jpeg_rings) + j]);
2618 }
2619 xcp_metrics->vcn_busy[idx] =
2620 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
2621
2622 xcp_metrics->current_vclk0[idx] = SMUQ10_ROUND(
2623 GET_METRIC_FIELD(VclkFrequency, version)[inst]);
2624 xcp_metrics->current_dclk0[idx] = SMUQ10_ROUND(
2625 GET_METRIC_FIELD(DclkFrequency, version)[inst]);
2626 xcp_metrics->current_socclk[idx] = SMUQ10_ROUND(
2627 GET_METRIC_FIELD(SocclkFrequency, version)[inst]);
2628
2629 idx++;
2630 }
2631
2632 xcp_metrics->current_uclk =
2633 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
2634
2635 if (per_inst) {
2636 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
2637 idx = 0;
2638 for_each_inst(k, inst_mask) {
2639 inst = GET_INST(GC, k);
2640 xcp_metrics->current_gfxclk[idx] =
2641 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency,
2642 version)[inst]);
2643
2644 xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(
2645 GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
2646 xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(
2647 GET_GPU_METRIC_FIELD(GfxBusyAcc,
2648 version)[inst]);
2649 if (smu_v13_0_6_cap_supported(
2650 smu, SMU_CAP(HST_LIMIT_METRICS))) {
2651 xcp_metrics->gfx_below_host_limit_ppt_acc
2652 [idx] = SMUQ10_ROUND(
2653 metrics_v0->GfxclkBelowHostLimitPptAcc
2654 [inst]);
2655 xcp_metrics->gfx_below_host_limit_thm_acc
2656 [idx] = SMUQ10_ROUND(
2657 metrics_v0->GfxclkBelowHostLimitThmAcc
2658 [inst]);
2659 xcp_metrics->gfx_low_utilization_acc
2660 [idx] = SMUQ10_ROUND(
2661 metrics_v0
2662 ->GfxclkLowUtilizationAcc[inst]);
2663 xcp_metrics->gfx_below_host_limit_total_acc
2664 [idx] = SMUQ10_ROUND(
2665 metrics_v0->GfxclkBelowHostLimitTotalAcc
2666 [inst]);
2667 }
2668 idx++;
2669 }
2670 }
2671 out:
2672 kfree(metrics_v0);
2673
2674 return sizeof(*xcp_metrics);
2675 }
2676
smu_v13_0_6_get_gpu_metrics(struct smu_context * smu,void ** table)2677 static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)
2678 {
2679 struct smu_table_context *smu_table = &smu->smu_table;
2680 struct gpu_metrics_v1_8 *gpu_metrics =
2681 (struct gpu_metrics_v1_8 *)smu_table->gpu_metrics_table;
2682 int version = smu_v13_0_6_get_metrics_version(smu);
2683 int ret = 0, xcc_id, inst, i, j, k, idx;
2684 struct amdgpu_device *adev = smu->adev;
2685 MetricsTableV0_t *metrics_v0;
2686 MetricsTableV1_t *metrics_v1;
2687 MetricsTableV2_t *metrics_v2;
2688 struct amdgpu_xcp *xcp;
2689 u16 link_width_level;
2690 ssize_t num_bytes;
2691 u8 num_jpeg_rings;
2692 u32 inst_mask;
2693 bool per_inst;
2694
2695 metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
2696 ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false);
2697 if (ret) {
2698 kfree(metrics_v0);
2699 return ret;
2700 }
2701
2702 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
2703 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
2704 num_bytes = smu_v13_0_12_get_gpu_metrics(smu, table, metrics_v0);
2705 kfree(metrics_v0);
2706 return num_bytes;
2707 }
2708
2709 metrics_v1 = (MetricsTableV1_t *)metrics_v0;
2710 metrics_v2 = (MetricsTableV2_t *)metrics_v0;
2711
2712 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 8);
2713
2714 gpu_metrics->temperature_hotspot =
2715 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version));
2716 /* Individual HBM stack temperature is not reported */
2717 gpu_metrics->temperature_mem =
2718 SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version));
2719 /* Reports max temperature of all voltage rails */
2720 gpu_metrics->temperature_vrsoc =
2721 SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version));
2722
2723 gpu_metrics->average_gfx_activity =
2724 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
2725 gpu_metrics->average_umc_activity =
2726 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
2727
2728 gpu_metrics->mem_max_bandwidth =
2729 SMUQ10_ROUND(GET_METRIC_FIELD(MaxDramBandwidth, version));
2730
2731 gpu_metrics->curr_socket_power =
2732 SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version));
2733 /* Energy counter reported in 15.259uJ (2^-16) units */
2734 gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, version);
2735
2736 for (i = 0; i < MAX_GFX_CLKS; i++) {
2737 xcc_id = GET_INST(GC, i);
2738 if (xcc_id >= 0)
2739 gpu_metrics->current_gfxclk[i] =
2740 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
2741
2742 if (i < MAX_CLKS) {
2743 gpu_metrics->current_socclk[i] =
2744 SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[i]);
2745 inst = GET_INST(VCN, i);
2746 if (inst >= 0) {
2747 gpu_metrics->current_vclk0[i] =
2748 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency,
2749 version)[inst]);
2750 gpu_metrics->current_dclk0[i] =
2751 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency,
2752 version)[inst]);
2753 }
2754 }
2755 }
2756
2757 gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
2758
2759 /* Total accumulated cycle counter */
2760 gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, version);
2761
2762 /* Accumulated throttler residencies */
2763 gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, version);
2764 gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, version);
2765 gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, version);
2766 gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, version);
2767 gpu_metrics->hbm_thm_residency_acc =
2768 GET_METRIC_FIELD(HbmThmResidencyAcc, version);
2769
2770 /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
2771 gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak,
2772 version) >> GET_INST(GC, 0);
2773
2774 if (!(adev->flags & AMD_IS_APU)) {
2775 /*Check smu version, PCIE link speed and width will be reported from pmfw metric
2776 * table for both pf & one vf for smu version 85.99.0 or higher else report only
2777 * for pf from registers
2778 */
2779 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PCIE_METRICS))) {
2780 gpu_metrics->pcie_link_width = GET_GPU_METRIC_FIELD(PCIeLinkWidth, version);
2781 gpu_metrics->pcie_link_speed =
2782 pcie_gen_to_speed(GET_GPU_METRIC_FIELD(PCIeLinkSpeed, version));
2783 } else if (!amdgpu_sriov_vf(adev)) {
2784 link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
2785 if (link_width_level > MAX_LINK_WIDTH)
2786 link_width_level = 0;
2787
2788 gpu_metrics->pcie_link_width =
2789 DECODE_LANE_WIDTH(link_width_level);
2790 gpu_metrics->pcie_link_speed =
2791 smu_v13_0_6_get_current_pcie_link_speed(smu);
2792 }
2793
2794 gpu_metrics->pcie_bandwidth_acc =
2795 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidthAcc, version)[0]);
2796 gpu_metrics->pcie_bandwidth_inst =
2797 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidth, version)[0]);
2798 gpu_metrics->pcie_l0_to_recov_count_acc =
2799 GET_GPU_METRIC_FIELD(PCIeL0ToRecoveryCountAcc, version);
2800 gpu_metrics->pcie_replay_count_acc =
2801 GET_GPU_METRIC_FIELD(PCIenReplayAAcc, version);
2802 gpu_metrics->pcie_replay_rover_count_acc =
2803 GET_GPU_METRIC_FIELD(PCIenReplayARolloverCountAcc, version);
2804 gpu_metrics->pcie_nak_sent_count_acc =
2805 GET_GPU_METRIC_FIELD(PCIeNAKSentCountAcc, version);
2806 gpu_metrics->pcie_nak_rcvd_count_acc =
2807 GET_GPU_METRIC_FIELD(PCIeNAKReceivedCountAcc, version);
2808 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(OTHER_END_METRICS)))
2809 gpu_metrics->pcie_lc_perf_other_end_recovery =
2810 GET_GPU_METRIC_FIELD(PCIeOtherEndRecoveryAcc, version);
2811
2812 }
2813
2814 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2815
2816 gpu_metrics->gfx_activity_acc =
2817 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, version));
2818 gpu_metrics->mem_activity_acc =
2819 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, version));
2820
2821 for (i = 0; i < NUM_XGMI_LINKS; i++) {
2822 j = amdgpu_xgmi_get_ext_link(adev, i);
2823 if (j < 0 || j >= NUM_XGMI_LINKS)
2824 continue;
2825 gpu_metrics->xgmi_read_data_acc[j] = SMUQ10_ROUND(
2826 GET_METRIC_FIELD(XgmiReadDataSizeAcc, version)[i]);
2827 gpu_metrics->xgmi_write_data_acc[j] = SMUQ10_ROUND(
2828 GET_METRIC_FIELD(XgmiWriteDataSizeAcc, version)[i]);
2829 ret = amdgpu_get_xgmi_link_status(adev, i);
2830 if (ret >= 0)
2831 gpu_metrics->xgmi_link_status[j] = ret;
2832 }
2833
2834 gpu_metrics->num_partition = adev->xcp_mgr->num_xcps;
2835
2836 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
2837
2838 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;
2839 for_each_xcp(adev->xcp_mgr, xcp, i) {
2840 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
2841 idx = 0;
2842 for_each_inst(k, inst_mask) {
2843 /* Both JPEG and VCN has same instances */
2844 inst = GET_INST(VCN, k);
2845
2846 for (j = 0; j < num_jpeg_rings; ++j) {
2847 gpu_metrics->xcp_stats[i].jpeg_busy
2848 [(idx * num_jpeg_rings) + j] =
2849 SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, version)
2850 [(inst * num_jpeg_rings) + j]);
2851 }
2852 gpu_metrics->xcp_stats[i].vcn_busy[idx] =
2853 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
2854 idx++;
2855
2856 }
2857
2858 if (per_inst) {
2859 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
2860 idx = 0;
2861 for_each_inst(k, inst_mask) {
2862 inst = GET_INST(GC, k);
2863 gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] =
2864 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
2865 gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =
2866 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc,
2867 version)[inst]);
2868 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(HST_LIMIT_METRICS))) {
2869 gpu_metrics->xcp_stats[i].gfx_below_host_limit_ppt_acc[idx] =
2870 SMUQ10_ROUND
2871 (metrics_v0->GfxclkBelowHostLimitPptAcc[inst]);
2872 gpu_metrics->xcp_stats[i].gfx_below_host_limit_thm_acc[idx] =
2873 SMUQ10_ROUND
2874 (metrics_v0->GfxclkBelowHostLimitThmAcc[inst]);
2875 gpu_metrics->xcp_stats[i].gfx_low_utilization_acc[idx] =
2876 SMUQ10_ROUND
2877 (metrics_v0->GfxclkLowUtilizationAcc[inst]);
2878 gpu_metrics->xcp_stats[i].gfx_below_host_limit_total_acc[idx] =
2879 SMUQ10_ROUND
2880 (metrics_v0->GfxclkBelowHostLimitTotalAcc[inst]);
2881 }
2882 idx++;
2883 }
2884 }
2885 }
2886
2887 gpu_metrics->xgmi_link_width = GET_METRIC_FIELD(XgmiWidth, version);
2888 gpu_metrics->xgmi_link_speed = GET_METRIC_FIELD(XgmiBitrate, version);
2889
2890 gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version);
2891
2892 *table = (void *)gpu_metrics;
2893 kfree(metrics_v0);
2894
2895 return sizeof(*gpu_metrics);
2896 }
2897
smu_v13_0_6_restore_pci_config(struct smu_context * smu)2898 static void smu_v13_0_6_restore_pci_config(struct smu_context *smu)
2899 {
2900 struct amdgpu_device *adev = smu->adev;
2901 int i;
2902
2903 for (i = 0; i < 16; i++)
2904 pci_write_config_dword(adev->pdev, i * 4,
2905 adev->pdev->saved_config_space[i]);
2906 pci_restore_msi_state(adev->pdev);
2907 }
2908
smu_v13_0_6_mode2_reset(struct smu_context * smu)2909 static int smu_v13_0_6_mode2_reset(struct smu_context *smu)
2910 {
2911 int ret = 0, index;
2912 struct amdgpu_device *adev = smu->adev;
2913 int timeout = 10;
2914
2915 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2916 SMU_MSG_GfxDeviceDriverReset);
2917 if (index < 0)
2918 return index;
2919
2920 mutex_lock(&smu->message_lock);
2921
2922 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
2923 SMU_RESET_MODE_2);
2924
2925 /* Reset takes a bit longer, wait for 200ms. */
2926 msleep(200);
2927
2928 dev_dbg(smu->adev->dev, "restore config space...\n");
2929 /* Restore the config space saved during init */
2930 amdgpu_device_load_pci_state(adev->pdev);
2931
2932 /* Certain platforms have switches which assign virtual BAR values to
2933 * devices. OS uses the virtual BAR values and device behind the switch
2934 * is assgined another BAR value. When device's config space registers
2935 * are queried, switch returns the virtual BAR values. When mode-2 reset
2936 * is performed, switch is unaware of it, and will continue to return
2937 * the same virtual values to the OS.This affects
2938 * pci_restore_config_space() API as it doesn't write the value saved if
2939 * the current value read from config space is the same as what is
2940 * saved. As a workaround, make sure the config space is restored
2941 * always.
2942 */
2943 if (!(adev->flags & AMD_IS_APU))
2944 smu_v13_0_6_restore_pci_config(smu);
2945
2946 dev_dbg(smu->adev->dev, "wait for reset ack\n");
2947 do {
2948 ret = smu_cmn_wait_for_response(smu);
2949 /* Wait a bit more time for getting ACK */
2950 if (ret == -ETIME) {
2951 --timeout;
2952 usleep_range(500, 1000);
2953 continue;
2954 }
2955
2956 if (ret)
2957 goto out;
2958
2959 } while (ret == -ETIME && timeout);
2960
2961 out:
2962 mutex_unlock(&smu->message_lock);
2963
2964 if (ret)
2965 dev_err(adev->dev, "failed to send mode2 reset, error code %d",
2966 ret);
2967
2968 return ret;
2969 }
2970
smu_v13_0_6_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2971 static int smu_v13_0_6_get_thermal_temperature_range(struct smu_context *smu,
2972 struct smu_temperature_range *range)
2973 {
2974 struct amdgpu_device *adev = smu->adev;
2975 u32 aid_temp, xcd_temp, max_temp;
2976 u32 ccd_temp = 0;
2977 int ret;
2978
2979 if (amdgpu_sriov_vf(smu->adev))
2980 return 0;
2981
2982 if (!range)
2983 return -EINVAL;
2984
2985 /*Check smu version, GetCtfLimit message only supported for smu version 85.69 or higher */
2986 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(CTF_LIMIT)))
2987 return 0;
2988
2989 /* Get SOC Max operating temperature */
2990 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2991 PPSMC_AID_THM_TYPE, &aid_temp);
2992 if (ret)
2993 goto failed;
2994 if (adev->flags & AMD_IS_APU) {
2995 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2996 PPSMC_CCD_THM_TYPE, &ccd_temp);
2997 if (ret)
2998 goto failed;
2999 }
3000 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
3001 PPSMC_XCD_THM_TYPE, &xcd_temp);
3002 if (ret)
3003 goto failed;
3004 range->hotspot_emergency_max = max3(aid_temp, xcd_temp, ccd_temp) *
3005 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3006
3007 /* Get HBM Max operating temperature */
3008 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
3009 PPSMC_HBM_THM_TYPE, &max_temp);
3010 if (ret)
3011 goto failed;
3012 range->mem_emergency_max =
3013 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3014
3015 /* Get SOC thermal throttle limit */
3016 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
3017 PPSMC_THROTTLING_LIMIT_TYPE_SOCKET,
3018 &max_temp);
3019 if (ret)
3020 goto failed;
3021 range->hotspot_crit_max =
3022 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3023
3024 /* Get HBM thermal throttle limit */
3025 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
3026 PPSMC_THROTTLING_LIMIT_TYPE_HBM,
3027 &max_temp);
3028 if (ret)
3029 goto failed;
3030
3031 range->mem_crit_max = max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3032
3033 failed:
3034 return ret;
3035 }
3036
smu_v13_0_6_mode1_reset(struct smu_context * smu)3037 static int smu_v13_0_6_mode1_reset(struct smu_context *smu)
3038 {
3039 struct amdgpu_device *adev = smu->adev;
3040 u32 fatal_err, param;
3041 int ret = 0;
3042
3043 fatal_err = 0;
3044 param = SMU_RESET_MODE_1;
3045
3046 /* fatal error triggered by ras, PMFW supports the flag */
3047 if (amdgpu_ras_get_fed_status(adev))
3048 fatal_err = 1;
3049
3050 param |= (fatal_err << 16);
3051 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
3052 param, NULL);
3053
3054 if (!ret)
3055 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
3056
3057 return ret;
3058 }
3059
smu_v13_0_6_link_reset(struct smu_context * smu)3060 static int smu_v13_0_6_link_reset(struct smu_context *smu)
3061 {
3062 int ret = 0;
3063
3064 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
3065 SMU_RESET_MODE_4, NULL);
3066 return ret;
3067 }
3068
smu_v13_0_6_is_mode1_reset_supported(struct smu_context * smu)3069 static bool smu_v13_0_6_is_mode1_reset_supported(struct smu_context *smu)
3070 {
3071 return true;
3072 }
3073
smu_v13_0_6_is_link_reset_supported(struct smu_context * smu)3074 static inline bool smu_v13_0_6_is_link_reset_supported(struct smu_context *smu)
3075 {
3076 struct amdgpu_device *adev = smu->adev;
3077 int var = (adev->pdev->device & 0xF);
3078
3079 if (var == 0x1)
3080 return true;
3081
3082 return false;
3083 }
3084
smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context * smu,uint32_t size)3085 static int smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context *smu,
3086 uint32_t size)
3087 {
3088 int ret = 0;
3089
3090 /* message SMU to update the bad page number on SMUBUS */
3091 ret = smu_cmn_send_smc_msg_with_param(
3092 smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
3093 if (ret)
3094 dev_err(smu->adev->dev,
3095 "[%s] failed to message SMU to update HBM bad pages number\n",
3096 __func__);
3097
3098 return ret;
3099 }
3100
smu_v13_0_6_send_rma_reason(struct smu_context * smu)3101 static int smu_v13_0_6_send_rma_reason(struct smu_context *smu)
3102 {
3103 int ret;
3104
3105 /* NOTE: the message is only valid on dGPU with pmfw 85.90.0 and above */
3106 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(RMA_MSG)))
3107 return 0;
3108
3109 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RmaDueToBadPageThreshold, NULL);
3110 if (ret)
3111 dev_err(smu->adev->dev,
3112 "[%s] failed to send BadPageThreshold event to SMU\n",
3113 __func__);
3114
3115 return ret;
3116 }
3117
3118 /**
3119 * smu_v13_0_6_reset_sdma_is_supported - Check if SDMA reset is supported
3120 * @smu: smu_context pointer
3121 *
3122 * This function checks if the SMU supports resetting the SDMA engine.
3123 * It returns false if the capability is not supported.
3124 */
smu_v13_0_6_reset_sdma_is_supported(struct smu_context * smu)3125 static bool smu_v13_0_6_reset_sdma_is_supported(struct smu_context *smu)
3126 {
3127 bool ret = true;
3128
3129 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SDMA_RESET))) {
3130 dev_info(smu->adev->dev,
3131 "SDMA reset capability is not supported\n");
3132 ret = false;
3133 }
3134
3135 return ret;
3136 }
3137
smu_v13_0_6_reset_sdma(struct smu_context * smu,uint32_t inst_mask)3138 static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
3139 {
3140 int ret = 0;
3141
3142 if (!smu_v13_0_6_reset_sdma_is_supported(smu))
3143 return -EOPNOTSUPP;
3144
3145 ret = smu_cmn_send_smc_msg_with_param(smu,
3146 SMU_MSG_ResetSDMA, inst_mask, NULL);
3147 if (ret)
3148 dev_err(smu->adev->dev,
3149 "failed to send ResetSDMA event with mask 0x%x\n",
3150 inst_mask);
3151
3152 return ret;
3153 }
3154
smu_v13_0_6_reset_vcn(struct smu_context * smu,uint32_t inst_mask)3155 static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask)
3156 {
3157 int ret = 0;
3158
3159 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ResetVCN, inst_mask, NULL);
3160 if (ret)
3161 dev_err(smu->adev->dev,
3162 "failed to send ResetVCN event with mask 0x%x\n",
3163 inst_mask);
3164 return ret;
3165 }
3166
3167
mca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3168 static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3169 {
3170 struct smu_context *smu = adev->powerplay.pp_handle;
3171
3172 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3173 }
3174
smu_v13_0_6_get_valid_mca_count(struct smu_context * smu,enum amdgpu_mca_error_type type,uint32_t * count)3175 static int smu_v13_0_6_get_valid_mca_count(struct smu_context *smu, enum amdgpu_mca_error_type type, uint32_t *count)
3176 {
3177 uint32_t msg;
3178 int ret;
3179
3180 if (!count)
3181 return -EINVAL;
3182
3183 switch (type) {
3184 case AMDGPU_MCA_ERROR_TYPE_UE:
3185 msg = SMU_MSG_QueryValidMcaCount;
3186 break;
3187 case AMDGPU_MCA_ERROR_TYPE_CE:
3188 msg = SMU_MSG_QueryValidMcaCeCount;
3189 break;
3190 default:
3191 return -EINVAL;
3192 }
3193
3194 ret = smu_cmn_send_smc_msg(smu, msg, count);
3195 if (ret) {
3196 *count = 0;
3197 return ret;
3198 }
3199
3200 return 0;
3201 }
3202
__smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val)3203 static int __smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
3204 int idx, int offset, uint32_t *val)
3205 {
3206 uint32_t msg, param;
3207
3208 switch (type) {
3209 case AMDGPU_MCA_ERROR_TYPE_UE:
3210 msg = SMU_MSG_McaBankDumpDW;
3211 break;
3212 case AMDGPU_MCA_ERROR_TYPE_CE:
3213 msg = SMU_MSG_McaBankCeDumpDW;
3214 break;
3215 default:
3216 return -EINVAL;
3217 }
3218
3219 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3220
3221 return smu_cmn_send_smc_msg_with_param(smu, msg, param, val);
3222 }
3223
smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val,int count)3224 static int smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
3225 int idx, int offset, uint32_t *val, int count)
3226 {
3227 int ret, i;
3228
3229 if (!val)
3230 return -EINVAL;
3231
3232 for (i = 0; i < count; i++) {
3233 ret = __smu_v13_0_6_mca_dump_bank(smu, type, idx, offset + (i << 2), &val[i]);
3234 if (ret)
3235 return ret;
3236 }
3237
3238 return 0;
3239 }
3240
3241 static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT] = {
3242 MCA_BANK_IPID(UMC, 0x96, 0x0),
3243 MCA_BANK_IPID(SMU, 0x01, 0x1),
3244 MCA_BANK_IPID(MP5, 0x01, 0x2),
3245 MCA_BANK_IPID(PCS_XGMI, 0x50, 0x0),
3246 };
3247
mca_bank_entry_info_decode(struct mca_bank_entry * entry,struct mca_bank_info * info)3248 static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
3249 {
3250 u64 ipid = entry->regs[MCA_REG_IDX_IPID];
3251 u32 instidhi, instid;
3252
3253 /* NOTE: All MCA IPID register share the same format,
3254 * so the driver can share the MCMP1 register header file.
3255 * */
3256
3257 info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
3258 info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
3259
3260 /*
3261 * Unfied DieID Format: SAASS. A:AID, S:Socket.
3262 * Unfied DieID[4] = InstanceId[0]
3263 * Unfied DieID[0:3] = InstanceIdHi[0:3]
3264 */
3265 instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
3266 instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
3267 info->aid = ((instidhi >> 2) & 0x03);
3268 info->socket_id = ((instid & 0x1) << 2) | (instidhi & 0x03);
3269 }
3270
mca_bank_read_reg(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,int reg_idx,uint64_t * val)3271 static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
3272 int idx, int reg_idx, uint64_t *val)
3273 {
3274 struct smu_context *smu = adev->powerplay.pp_handle;
3275 uint32_t data[2] = {0, 0};
3276 int ret;
3277
3278 if (!val || reg_idx >= MCA_REG_IDX_COUNT)
3279 return -EINVAL;
3280
3281 ret = smu_v13_0_6_mca_dump_bank(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3282 if (ret)
3283 return ret;
3284
3285 *val = (uint64_t)data[1] << 32 | data[0];
3286
3287 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3288 type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3289
3290 return 0;
3291 }
3292
mca_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3293 static int mca_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
3294 int idx, struct mca_bank_entry *entry)
3295 {
3296 int i, ret;
3297
3298 /* NOTE: populated all mca register by default */
3299 for (i = 0; i < ARRAY_SIZE(entry->regs); i++) {
3300 ret = mca_bank_read_reg(adev, type, idx, i, &entry->regs[i]);
3301 if (ret)
3302 return ret;
3303 }
3304
3305 entry->idx = idx;
3306 entry->type = type;
3307
3308 mca_bank_entry_info_decode(entry, &entry->info);
3309
3310 return 0;
3311 }
3312
mca_decode_ipid_to_hwip(uint64_t val)3313 static int mca_decode_ipid_to_hwip(uint64_t val)
3314 {
3315 const struct mca_bank_ipid *ipid;
3316 uint16_t hwid, mcatype;
3317 int i;
3318
3319 hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
3320 mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
3321
3322 for (i = 0; i < ARRAY_SIZE(smu_v13_0_6_mca_ipid_table); i++) {
3323 ipid = &smu_v13_0_6_mca_ipid_table[i];
3324
3325 if (!ipid->hwid)
3326 continue;
3327
3328 if (ipid->hwid == hwid && ipid->mcatype == mcatype)
3329 return i;
3330 }
3331
3332 return AMDGPU_MCA_IP_UNKNOW;
3333 }
3334
mca_umc_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3335 static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3336 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3337 {
3338 uint64_t status0;
3339 uint32_t ext_error_code;
3340 uint32_t odecc_err_cnt;
3341
3342 status0 = entry->regs[MCA_REG_IDX_STATUS];
3343 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status0);
3344 odecc_err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3345
3346 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3347 *count = 0;
3348 return 0;
3349 }
3350
3351 if (umc_v12_0_is_deferred_error(adev, status0) ||
3352 umc_v12_0_is_uncorrectable_error(adev, status0) ||
3353 umc_v12_0_is_correctable_error(adev, status0))
3354 *count = (ext_error_code == 0) ? odecc_err_cnt : 1;
3355
3356 amdgpu_umc_update_ecc_status(adev,
3357 entry->regs[MCA_REG_IDX_STATUS],
3358 entry->regs[MCA_REG_IDX_IPID],
3359 entry->regs[MCA_REG_IDX_ADDR]);
3360
3361 return 0;
3362 }
3363
mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3364 static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3365 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry,
3366 uint32_t *count)
3367 {
3368 u32 ext_error_code;
3369 u32 err_cnt;
3370
3371 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
3372 err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3373
3374 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3375 (ext_error_code == 0 || ext_error_code == 9))
3376 *count = err_cnt;
3377 else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
3378 *count = err_cnt;
3379
3380 return 0;
3381 }
3382
mca_smu_check_error_code(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,uint32_t errcode)3383 static bool mca_smu_check_error_code(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3384 uint32_t errcode)
3385 {
3386 int i;
3387
3388 if (!mca_ras->err_code_count || !mca_ras->err_code_array)
3389 return true;
3390
3391 for (i = 0; i < mca_ras->err_code_count; i++) {
3392 if (errcode == mca_ras->err_code_array[i])
3393 return true;
3394 }
3395
3396 return false;
3397 }
3398
mca_gfx_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3399 static int mca_gfx_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3400 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3401 {
3402 uint64_t status0, misc0;
3403
3404 status0 = entry->regs[MCA_REG_IDX_STATUS];
3405 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3406 *count = 0;
3407 return 0;
3408 }
3409
3410 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3411 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3412 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3413 *count = 1;
3414 return 0;
3415 } else {
3416 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3417 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3418 }
3419
3420 return 0;
3421 }
3422
mca_smu_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3423 static int mca_smu_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3424 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3425 {
3426 uint64_t status0, misc0;
3427
3428 status0 = entry->regs[MCA_REG_IDX_STATUS];
3429 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3430 *count = 0;
3431 return 0;
3432 }
3433
3434 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3435 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3436 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3437 if (count)
3438 *count = 1;
3439 return 0;
3440 }
3441
3442 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3443 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3444
3445 return 0;
3446 }
3447
mca_gfx_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3448 static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3449 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3450 {
3451 uint32_t instlo;
3452
3453 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3454 instlo &= GENMASK(31, 1);
3455 switch (instlo) {
3456 case 0x36430400: /* SMNAID XCD 0 */
3457 case 0x38430400: /* SMNAID XCD 1 */
3458 case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */
3459 return true;
3460 default:
3461 return false;
3462 }
3463
3464 return false;
3465 };
3466
mca_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3467 static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3468 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3469 {
3470 struct smu_context *smu = adev->powerplay.pp_handle;
3471 uint32_t errcode, instlo;
3472
3473 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3474 instlo &= GENMASK(31, 1);
3475 if (instlo != 0x03b30400)
3476 return false;
3477
3478 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND))) {
3479 errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]);
3480 errcode &= 0xff;
3481 } else {
3482 errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
3483 }
3484
3485 return mca_smu_check_error_code(adev, mca_ras, errcode);
3486 }
3487
3488 static int sdma_err_codes[] = { CODE_SDMA0, CODE_SDMA1, CODE_SDMA2, CODE_SDMA3 };
3489 static int mmhub_err_codes[] = {
3490 CODE_DAGB0, CODE_DAGB0 + 1, CODE_DAGB0 + 2, CODE_DAGB0 + 3, CODE_DAGB0 + 4, /* DAGB0-4 */
3491 CODE_EA0, CODE_EA0 + 1, CODE_EA0 + 2, CODE_EA0 + 3, CODE_EA0 + 4, /* MMEA0-4*/
3492 CODE_VML2, CODE_VML2_WALKER, CODE_MMCANE,
3493 };
3494
3495 static int vcn_err_codes[] = {
3496 CODE_VIDD, CODE_VIDV,
3497 };
3498 static int jpeg_err_codes[] = {
3499 CODE_JPEG0S, CODE_JPEG0D, CODE_JPEG1S, CODE_JPEG1D,
3500 CODE_JPEG2S, CODE_JPEG2D, CODE_JPEG3S, CODE_JPEG3D,
3501 CODE_JPEG4S, CODE_JPEG4D, CODE_JPEG5S, CODE_JPEG5D,
3502 CODE_JPEG6S, CODE_JPEG6D, CODE_JPEG7S, CODE_JPEG7D,
3503 };
3504
3505 static const struct mca_ras_info mca_ras_table[] = {
3506 {
3507 .blkid = AMDGPU_RAS_BLOCK__UMC,
3508 .ip = AMDGPU_MCA_IP_UMC,
3509 .get_err_count = mca_umc_mca_get_err_count,
3510 }, {
3511 .blkid = AMDGPU_RAS_BLOCK__GFX,
3512 .ip = AMDGPU_MCA_IP_SMU,
3513 .get_err_count = mca_gfx_mca_get_err_count,
3514 .bank_is_valid = mca_gfx_smu_bank_is_valid,
3515 }, {
3516 .blkid = AMDGPU_RAS_BLOCK__SDMA,
3517 .ip = AMDGPU_MCA_IP_SMU,
3518 .err_code_array = sdma_err_codes,
3519 .err_code_count = ARRAY_SIZE(sdma_err_codes),
3520 .get_err_count = mca_smu_mca_get_err_count,
3521 .bank_is_valid = mca_smu_bank_is_valid,
3522 }, {
3523 .blkid = AMDGPU_RAS_BLOCK__MMHUB,
3524 .ip = AMDGPU_MCA_IP_SMU,
3525 .err_code_array = mmhub_err_codes,
3526 .err_code_count = ARRAY_SIZE(mmhub_err_codes),
3527 .get_err_count = mca_smu_mca_get_err_count,
3528 .bank_is_valid = mca_smu_bank_is_valid,
3529 }, {
3530 .blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL,
3531 .ip = AMDGPU_MCA_IP_PCS_XGMI,
3532 .get_err_count = mca_pcs_xgmi_mca_get_err_count,
3533 }, {
3534 .blkid = AMDGPU_RAS_BLOCK__VCN,
3535 .ip = AMDGPU_MCA_IP_SMU,
3536 .err_code_array = vcn_err_codes,
3537 .err_code_count = ARRAY_SIZE(vcn_err_codes),
3538 .get_err_count = mca_smu_mca_get_err_count,
3539 .bank_is_valid = mca_smu_bank_is_valid,
3540 }, {
3541 .blkid = AMDGPU_RAS_BLOCK__JPEG,
3542 .ip = AMDGPU_MCA_IP_SMU,
3543 .err_code_array = jpeg_err_codes,
3544 .err_code_count = ARRAY_SIZE(jpeg_err_codes),
3545 .get_err_count = mca_smu_mca_get_err_count,
3546 .bank_is_valid = mca_smu_bank_is_valid,
3547 },
3548 };
3549
mca_get_mca_ras_info(struct amdgpu_device * adev,enum amdgpu_ras_block blkid)3550 static const struct mca_ras_info *mca_get_mca_ras_info(struct amdgpu_device *adev, enum amdgpu_ras_block blkid)
3551 {
3552 int i;
3553
3554 for (i = 0; i < ARRAY_SIZE(mca_ras_table); i++) {
3555 if (mca_ras_table[i].blkid == blkid)
3556 return &mca_ras_table[i];
3557 }
3558
3559 return NULL;
3560 }
3561
mca_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3562 static int mca_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
3563 {
3564 struct smu_context *smu = adev->powerplay.pp_handle;
3565 int ret;
3566
3567 switch (type) {
3568 case AMDGPU_MCA_ERROR_TYPE_UE:
3569 case AMDGPU_MCA_ERROR_TYPE_CE:
3570 ret = smu_v13_0_6_get_valid_mca_count(smu, type, count);
3571 break;
3572 default:
3573 ret = -EINVAL;
3574 break;
3575 }
3576
3577 return ret;
3578 }
3579
mca_bank_is_valid(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3580 static bool mca_bank_is_valid(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3581 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3582 {
3583 if (mca_decode_ipid_to_hwip(entry->regs[MCA_REG_IDX_IPID]) != mca_ras->ip)
3584 return false;
3585
3586 if (mca_ras->bank_is_valid)
3587 return mca_ras->bank_is_valid(mca_ras, adev, type, entry);
3588
3589 return true;
3590 }
3591
mca_smu_parse_mca_error_count(struct amdgpu_device * adev,enum amdgpu_ras_block blk,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3592 static int mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
3593 struct mca_bank_entry *entry, uint32_t *count)
3594 {
3595 const struct mca_ras_info *mca_ras;
3596
3597 if (!entry || !count)
3598 return -EINVAL;
3599
3600 mca_ras = mca_get_mca_ras_info(adev, blk);
3601 if (!mca_ras)
3602 return -EOPNOTSUPP;
3603
3604 if (!mca_bank_is_valid(adev, mca_ras, type, entry)) {
3605 *count = 0;
3606 return 0;
3607 }
3608
3609 return mca_ras->get_err_count(mca_ras, adev, type, entry, count);
3610 }
3611
mca_smu_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3612 static int mca_smu_get_mca_entry(struct amdgpu_device *adev,
3613 enum amdgpu_mca_error_type type, int idx, struct mca_bank_entry *entry)
3614 {
3615 return mca_get_mca_entry(adev, type, idx, entry);
3616 }
3617
mca_smu_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3618 static int mca_smu_get_valid_mca_count(struct amdgpu_device *adev,
3619 enum amdgpu_mca_error_type type, uint32_t *count)
3620 {
3621 return mca_get_valid_mca_count(adev, type, count);
3622 }
3623
3624 static const struct amdgpu_mca_smu_funcs smu_v13_0_6_mca_smu_funcs = {
3625 .max_ue_count = 12,
3626 .max_ce_count = 12,
3627 .mca_set_debug_mode = mca_smu_set_debug_mode,
3628 .mca_parse_mca_error_count = mca_smu_parse_mca_error_count,
3629 .mca_get_mca_entry = mca_smu_get_mca_entry,
3630 .mca_get_valid_mca_count = mca_smu_get_valid_mca_count,
3631 };
3632
aca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3633 static int aca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3634 {
3635 struct smu_context *smu = adev->powerplay.pp_handle;
3636
3637 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3638 }
3639
smu_v13_0_6_get_valid_aca_count(struct smu_context * smu,enum aca_smu_type type,u32 * count)3640 static int smu_v13_0_6_get_valid_aca_count(struct smu_context *smu, enum aca_smu_type type, u32 *count)
3641 {
3642 uint32_t msg;
3643 int ret;
3644
3645 if (!count)
3646 return -EINVAL;
3647
3648 switch (type) {
3649 case ACA_SMU_TYPE_UE:
3650 msg = SMU_MSG_QueryValidMcaCount;
3651 break;
3652 case ACA_SMU_TYPE_CE:
3653 msg = SMU_MSG_QueryValidMcaCeCount;
3654 break;
3655 default:
3656 return -EINVAL;
3657 }
3658
3659 ret = smu_cmn_send_smc_msg(smu, msg, count);
3660 if (ret) {
3661 *count = 0;
3662 return ret;
3663 }
3664
3665 return 0;
3666 }
3667
aca_smu_get_valid_aca_count(struct amdgpu_device * adev,enum aca_smu_type type,u32 * count)3668 static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev,
3669 enum aca_smu_type type, u32 *count)
3670 {
3671 struct smu_context *smu = adev->powerplay.pp_handle;
3672 int ret;
3673
3674 switch (type) {
3675 case ACA_SMU_TYPE_UE:
3676 case ACA_SMU_TYPE_CE:
3677 ret = smu_v13_0_6_get_valid_aca_count(smu, type, count);
3678 break;
3679 default:
3680 ret = -EINVAL;
3681 break;
3682 }
3683
3684 return ret;
3685 }
3686
__smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val)3687 static int __smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3688 int idx, int offset, u32 *val)
3689 {
3690 uint32_t msg, param;
3691
3692 switch (type) {
3693 case ACA_SMU_TYPE_UE:
3694 msg = SMU_MSG_McaBankDumpDW;
3695 break;
3696 case ACA_SMU_TYPE_CE:
3697 msg = SMU_MSG_McaBankCeDumpDW;
3698 break;
3699 default:
3700 return -EINVAL;
3701 }
3702
3703 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3704
3705 return smu_cmn_send_smc_msg_with_param(smu, msg, param, (uint32_t *)val);
3706 }
3707
smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val,int count)3708 static int smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3709 int idx, int offset, u32 *val, int count)
3710 {
3711 int ret, i;
3712
3713 if (!val)
3714 return -EINVAL;
3715
3716 for (i = 0; i < count; i++) {
3717 ret = __smu_v13_0_6_aca_bank_dump(smu, type, idx, offset + (i << 2), &val[i]);
3718 if (ret)
3719 return ret;
3720 }
3721
3722 return 0;
3723 }
3724
aca_bank_read_reg(struct amdgpu_device * adev,enum aca_smu_type type,int idx,int reg_idx,u64 * val)3725 static int aca_bank_read_reg(struct amdgpu_device *adev, enum aca_smu_type type,
3726 int idx, int reg_idx, u64 *val)
3727 {
3728 struct smu_context *smu = adev->powerplay.pp_handle;
3729 u32 data[2] = {0, 0};
3730 int ret;
3731
3732 if (!val || reg_idx >= ACA_REG_IDX_COUNT)
3733 return -EINVAL;
3734
3735 ret = smu_v13_0_6_aca_bank_dump(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3736 if (ret)
3737 return ret;
3738
3739 *val = (u64)data[1] << 32 | data[0];
3740
3741 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3742 type == ACA_SMU_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3743
3744 return 0;
3745 }
3746
aca_smu_get_valid_aca_bank(struct amdgpu_device * adev,enum aca_smu_type type,int idx,struct aca_bank * bank)3747 static int aca_smu_get_valid_aca_bank(struct amdgpu_device *adev,
3748 enum aca_smu_type type, int idx, struct aca_bank *bank)
3749 {
3750 int i, ret, count;
3751
3752 count = min_t(int, 16, ARRAY_SIZE(bank->regs));
3753 for (i = 0; i < count; i++) {
3754 ret = aca_bank_read_reg(adev, type, idx, i, &bank->regs[i]);
3755 if (ret)
3756 return ret;
3757 }
3758
3759 return 0;
3760 }
3761
aca_smu_parse_error_code(struct amdgpu_device * adev,struct aca_bank * bank)3762 static int aca_smu_parse_error_code(struct amdgpu_device *adev, struct aca_bank *bank)
3763 {
3764 struct smu_context *smu = adev->powerplay.pp_handle;
3765 int error_code;
3766
3767 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND)))
3768 error_code = ACA_REG__SYND__ERRORINFORMATION(bank->regs[ACA_REG_IDX_SYND]);
3769 else
3770 error_code = ACA_REG__STATUS__ERRORCODE(bank->regs[ACA_REG_IDX_STATUS]);
3771
3772 return error_code & 0xff;
3773 }
3774
3775 static const struct aca_smu_funcs smu_v13_0_6_aca_smu_funcs = {
3776 .max_ue_bank_count = 12,
3777 .max_ce_bank_count = 12,
3778 .set_debug_mode = aca_smu_set_debug_mode,
3779 .get_valid_aca_count = aca_smu_get_valid_aca_count,
3780 .get_valid_aca_bank = aca_smu_get_valid_aca_bank,
3781 .parse_error_code = aca_smu_parse_error_code,
3782 };
3783
3784 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
3785 /* init dpm */
3786 .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask,
3787 /* dpm/clk tables */
3788 .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table,
3789 .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk,
3790 .print_clk_levels = smu_v13_0_6_print_clk_levels,
3791 .force_clk_levels = smu_v13_0_6_force_clk_levels,
3792 .read_sensor = smu_v13_0_6_read_sensor,
3793 .set_performance_level = smu_v13_0_6_set_performance_level,
3794 .get_power_limit = smu_v13_0_6_get_power_limit,
3795 .is_dpm_running = smu_v13_0_6_is_dpm_running,
3796 .get_unique_id = smu_v13_0_6_get_unique_id,
3797 .init_microcode = smu_v13_0_6_init_microcode,
3798 .fini_microcode = smu_v13_0_fini_microcode,
3799 .init_smc_tables = smu_v13_0_6_init_smc_tables,
3800 .fini_smc_tables = smu_v13_0_fini_smc_tables,
3801 .init_power = smu_v13_0_init_power,
3802 .fini_power = smu_v13_0_fini_power,
3803 .check_fw_status = smu_v13_0_6_check_fw_status,
3804 /* pptable related */
3805 .check_fw_version = smu_v13_0_6_check_fw_version,
3806 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3807 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3808 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3809 .system_features_control = smu_v13_0_6_system_features_control,
3810 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3811 .send_smc_msg = smu_cmn_send_smc_msg,
3812 .get_enabled_mask = smu_v13_0_6_get_enabled_mask,
3813 .feature_is_enabled = smu_cmn_feature_is_enabled,
3814 .set_power_limit = smu_v13_0_6_set_power_limit,
3815 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
3816 .register_irq_handler = smu_v13_0_6_register_irq_handler,
3817 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3818 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3819 .setup_pptable = smu_v13_0_6_setup_pptable,
3820 .get_bamaco_support = smu_v13_0_6_get_bamaco_support,
3821 .get_dpm_ultimate_freq = smu_v13_0_6_get_dpm_ultimate_freq,
3822 .set_soft_freq_limited_range = smu_v13_0_6_set_soft_freq_limited_range,
3823 .od_edit_dpm_table = smu_v13_0_6_usr_edit_dpm_table,
3824 .log_thermal_throttling_event = smu_v13_0_6_log_thermal_throttling_event,
3825 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3826 .get_gpu_metrics = smu_v13_0_6_get_gpu_metrics,
3827 .get_pm_metrics = smu_v13_0_6_get_pm_metrics,
3828 .get_xcp_metrics = smu_v13_0_6_get_xcp_metrics,
3829 .get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range,
3830 .mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported,
3831 .link_reset_is_support = smu_v13_0_6_is_link_reset_supported,
3832 .mode1_reset = smu_v13_0_6_mode1_reset,
3833 .mode2_reset = smu_v13_0_6_mode2_reset,
3834 .link_reset = smu_v13_0_6_link_reset,
3835 .wait_for_event = smu_v13_0_wait_for_event,
3836 .i2c_init = smu_v13_0_6_i2c_control_init,
3837 .i2c_fini = smu_v13_0_6_i2c_control_fini,
3838 .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num,
3839 .send_rma_reason = smu_v13_0_6_send_rma_reason,
3840 .reset_sdma = smu_v13_0_6_reset_sdma,
3841 .reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported,
3842 .dpm_reset_vcn = smu_v13_0_6_reset_vcn,
3843 };
3844
smu_v13_0_6_set_ppt_funcs(struct smu_context * smu)3845 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
3846 {
3847 smu->ppt_funcs = &smu_v13_0_6_ppt_funcs;
3848 smu->message_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?
3849 smu_v13_0_12_message_map : smu_v13_0_6_message_map;
3850 smu->clock_map = smu_v13_0_6_clk_map;
3851 smu->feature_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?
3852 smu_v13_0_12_feature_mask_map : smu_v13_0_6_feature_mask_map;
3853 smu->table_map = smu_v13_0_6_table_map;
3854 smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION;
3855 smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
3856 smu_v13_0_set_smu_mailbox_registers(smu);
3857 amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs);
3858 amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs);
3859 }
3860