1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 12 #include <net/devlink.h> 13 #include <net/ipv6.h> 14 15 #include "hclge_cmd.h" 16 #include "hclge_ptp.h" 17 #include "hnae3.h" 18 #include "hclge_comm_rss.h" 19 #include "hclge_comm_tqp_stats.h" 20 21 #define HCLGE_MOD_VERSION "1.0" 22 #define HCLGE_DRIVER_NAME "hclge" 23 24 #define HCLGE_MAX_PF_NUM 8 25 26 #define HCLGE_VF_VPORT_START_NUM 1 27 28 #define HCLGE_RD_FIRST_STATS_NUM 2 29 #define HCLGE_RD_OTHER_STATS_NUM 4 30 31 #define HCLGE_INVALID_VPORT 0xffff 32 33 #define HCLGE_PF_CFG_BLOCK_SIZE 32 34 #define HCLGE_PF_CFG_DESC_NUM \ 35 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 36 37 #define HCLGE_VECTOR_REG_BASE 0x20000 38 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000 39 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 40 41 #define HCLGE_VECTOR_REG_OFFSET 0x4 42 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000 43 #define HCLGE_VECTOR_VF_OFFSET 0x100000 44 45 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 46 47 /* bar registers for common func */ 48 #define HCLGE_GRO_EN_REG 0x28000 49 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008 50 51 /* bar registers for rcb */ 52 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 53 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 54 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 55 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 56 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 57 #define HCLGE_RING_RX_TAIL_REG 0x80018 58 #define HCLGE_RING_RX_HEAD_REG 0x8001C 59 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 60 #define HCLGE_RING_RX_OFFSET_REG 0x80024 61 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 62 #define HCLGE_RING_RX_STASH_REG 0x80030 63 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 64 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 65 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 66 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 67 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 68 #define HCLGE_RING_TX_TC_REG 0x80050 69 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 70 #define HCLGE_RING_TX_TAIL_REG 0x80058 71 #define HCLGE_RING_TX_HEAD_REG 0x8005C 72 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 73 #define HCLGE_RING_TX_OFFSET_REG 0x80064 74 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 75 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 76 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 77 #define HCLGE_RING_EN_REG 0x80090 78 79 /* bar registers for tqp interrupt */ 80 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 81 #define HCLGE_TQP_INTR_GL0_REG 0x20100 82 #define HCLGE_TQP_INTR_GL1_REG 0x20200 83 #define HCLGE_TQP_INTR_GL2_REG 0x20300 84 #define HCLGE_TQP_INTR_RL_REG 0x20900 85 86 #define HCLGE_RSS_IND_TBL_SIZE 512 87 88 #define HCLGE_RSS_TC_SIZE_0 1 89 #define HCLGE_RSS_TC_SIZE_1 2 90 #define HCLGE_RSS_TC_SIZE_2 4 91 #define HCLGE_RSS_TC_SIZE_3 8 92 #define HCLGE_RSS_TC_SIZE_4 16 93 #define HCLGE_RSS_TC_SIZE_5 32 94 #define HCLGE_RSS_TC_SIZE_6 64 95 #define HCLGE_RSS_TC_SIZE_7 128 96 97 #define HCLGE_UMV_TBL_SIZE 3072 98 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 99 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 100 101 #define HCLGE_TQP_RESET_TRY_TIMES 200 102 103 #define HCLGE_PHY_PAGE_MDIX 0 104 #define HCLGE_PHY_PAGE_COPPER 0 105 106 /* Page Selection Reg. */ 107 #define HCLGE_PHY_PAGE_REG 22 108 109 /* Copper Specific Control Register */ 110 #define HCLGE_PHY_CSC_REG 16 111 112 /* Copper Specific Status Register */ 113 #define HCLGE_PHY_CSS_REG 17 114 115 #define HCLGE_PHY_MDIX_CTRL_S 5 116 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 117 118 #define HCLGE_PHY_MDIX_STATUS_B 6 119 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 120 121 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 122 123 /* Factor used to calculate offset and bitmap of VF num */ 124 #define HCLGE_VF_NUM_PER_CMD 64 125 126 #define HCLGE_MAX_QSET_NUM 1024 127 128 #define HCLGE_DBG_RESET_INFO_LEN 1024 129 130 enum HLCGE_PORT_TYPE { 131 HOST_PORT, 132 NETWORK_PORT 133 }; 134 135 #define PF_VPORT_ID 0 136 137 #define HCLGE_PF_ID_S 0 138 #define HCLGE_PF_ID_M GENMASK(2, 0) 139 #define HCLGE_VF_ID_S 3 140 #define HCLGE_VF_ID_M GENMASK(10, 3) 141 #define HCLGE_PORT_TYPE_B 11 142 #define HCLGE_NETWORK_PORT_ID_S 0 143 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 144 145 /* Reset related Registers */ 146 #define HCLGE_PF_OTHER_INT_REG 0x20600 147 #define HCLGE_MISC_RESET_STS_REG 0x20700 148 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 149 #define HCLGE_GLOBAL_RESET_REG 0x20A00 150 #define HCLGE_GLOBAL_RESET_BIT 0 151 #define HCLGE_CORE_RESET_BIT 1 152 #define HCLGE_IMP_RESET_BIT 2 153 #define HCLGE_RESET_INT_M GENMASK(7, 5) 154 #define HCLGE_FUN_RST_ING 0x20C00 155 #define HCLGE_FUN_RST_ING_B 0 156 157 /* Vector0 register bits define */ 158 #define HCLGE_VECTOR0_REG_PTP_INT_B 0 159 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 160 #define HCLGE_VECTOR0_CORERESET_INT_B 6 161 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 162 163 /* Vector0 interrupt CMDQ event source register(RW) */ 164 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 165 /* CMDQ register bits for RX event(=MBX event) */ 166 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 167 168 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 169 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 170 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 171 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U 172 #define HCLGE_TRIGGER_IMP_RESET_B 7U 173 174 #define HCLGE_TQP_MEM_SIZE 0x10000 175 #define HCLGE_MEM_BAR 4 176 /* in the bar4, the first half is for roce, and the second half is for nic */ 177 #define HCLGE_NIC_MEM_OFFSET(hdev) \ 178 (pci_resource_len((hdev)->pdev, HCLGE_MEM_BAR) >> 1) 179 #define HCLGE_TQP_MEM_OFFSET(hdev, i) \ 180 (HCLGE_NIC_MEM_OFFSET(hdev) + HCLGE_TQP_MEM_SIZE * (i)) 181 182 #define HCLGE_MAC_DEFAULT_FRAME \ 183 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 184 #define HCLGE_MAC_MIN_FRAME 64 185 #define HCLGE_MAC_MAX_FRAME 9728 186 187 #define HCLGE_SUPPORT_1G_BIT BIT(0) 188 #define HCLGE_SUPPORT_10G_BIT BIT(1) 189 #define HCLGE_SUPPORT_25G_BIT BIT(2) 190 #define HCLGE_SUPPORT_50G_R2_BIT BIT(3) 191 #define HCLGE_SUPPORT_100G_R4_BIT BIT(4) 192 /* to be compatible with exsit board */ 193 #define HCLGE_SUPPORT_40G_BIT BIT(5) 194 #define HCLGE_SUPPORT_100M_BIT BIT(6) 195 #define HCLGE_SUPPORT_10M_BIT BIT(7) 196 #define HCLGE_SUPPORT_200G_R4_EXT_BIT BIT(8) 197 #define HCLGE_SUPPORT_50G_R1_BIT BIT(9) 198 #define HCLGE_SUPPORT_100G_R2_BIT BIT(10) 199 #define HCLGE_SUPPORT_200G_R4_BIT BIT(11) 200 201 #define HCLGE_SUPPORT_GE \ 202 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 203 #define HCLGE_SUPPORT_50G_BITS \ 204 (HCLGE_SUPPORT_50G_R2_BIT | HCLGE_SUPPORT_50G_R1_BIT) 205 #define HCLGE_SUPPORT_100G_BITS \ 206 (HCLGE_SUPPORT_100G_R4_BIT | HCLGE_SUPPORT_100G_R2_BIT) 207 #define HCLGE_SUPPORT_200G_BITS \ 208 (HCLGE_SUPPORT_200G_R4_EXT_BIT | HCLGE_SUPPORT_200G_R4_BIT) 209 210 enum HCLGE_DEV_STATE { 211 HCLGE_STATE_REINITING, 212 HCLGE_STATE_DOWN, 213 HCLGE_STATE_DISABLED, 214 HCLGE_STATE_REMOVING, 215 HCLGE_STATE_NIC_REGISTERED, 216 HCLGE_STATE_ROCE_REGISTERED, 217 HCLGE_STATE_SERVICE_INITED, 218 HCLGE_STATE_RST_SERVICE_SCHED, 219 HCLGE_STATE_RST_HANDLING, 220 HCLGE_STATE_MBX_SERVICE_SCHED, 221 HCLGE_STATE_MBX_HANDLING, 222 HCLGE_STATE_ERR_SERVICE_SCHED, 223 HCLGE_STATE_STATISTICS_UPDATING, 224 HCLGE_STATE_LINK_UPDATING, 225 HCLGE_STATE_RST_FAIL, 226 HCLGE_STATE_FD_TBL_CHANGED, 227 HCLGE_STATE_FD_CLEAR_ALL, 228 HCLGE_STATE_FD_USER_DEF_CHANGED, 229 HCLGE_STATE_PTP_EN, 230 HCLGE_STATE_PTP_TX_HANDLING, 231 HCLGE_STATE_FEC_STATS_UPDATING, 232 HCLGE_STATE_MAX 233 }; 234 235 enum hclge_evt_cause { 236 HCLGE_VECTOR0_EVENT_RST, 237 HCLGE_VECTOR0_EVENT_MBX, 238 HCLGE_VECTOR0_EVENT_ERR, 239 HCLGE_VECTOR0_EVENT_PTP, 240 HCLGE_VECTOR0_EVENT_OTHER, 241 }; 242 243 enum HCLGE_MAC_SPEED { 244 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 245 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 246 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 251 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 252 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */ 253 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */ 254 }; 255 256 enum HCLGE_MAC_DUPLEX { 257 HCLGE_MAC_HALF, 258 HCLGE_MAC_FULL 259 }; 260 261 /* hilink version */ 262 enum hclge_hilink_version { 263 HCLGE_HILINK_H32 = 0, 264 HCLGE_HILINK_H60 = 1, 265 }; 266 267 #define QUERY_SFP_SPEED 0 268 #define QUERY_ACTIVE_SPEED 1 269 270 struct hclge_wol_info { 271 u32 wol_support_mode; /* store the wake on lan info */ 272 u32 wol_current_mode; 273 u8 wol_sopass[SOPASS_MAX]; 274 u8 wol_sopass_size; 275 }; 276 277 struct hclge_mac { 278 u8 mac_id; 279 u8 phy_addr; 280 u8 flag; 281 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 282 u8 mac_addr[ETH_ALEN]; 283 u8 autoneg; 284 u8 req_autoneg; 285 u8 duplex; 286 u8 req_duplex; 287 u8 support_autoneg; 288 u8 speed_type; /* 0: sfp speed, 1: active speed */ 289 u8 lane_num; 290 u32 speed; 291 u32 req_speed; 292 u32 max_speed; 293 u32 speed_ability; /* speed ability supported by current media */ 294 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 295 u32 fec_mode; /* active fec mode */ 296 u32 user_fec_mode; 297 u32 fec_ability; 298 int link; /* store the link status of mac & phy (if phy exists) */ 299 struct hclge_wol_info wol; 300 struct phy_device *phydev; 301 struct mii_bus *mdio_bus; 302 phy_interface_t phy_if; 303 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 304 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 305 }; 306 307 struct hclge_hw { 308 struct hclge_comm_hw hw; 309 struct hclge_mac mac; 310 int num_vec; 311 }; 312 313 enum hclge_fc_mode { 314 HCLGE_FC_NONE, 315 HCLGE_FC_RX_PAUSE, 316 HCLGE_FC_TX_PAUSE, 317 HCLGE_FC_FULL, 318 HCLGE_FC_PFC, 319 HCLGE_FC_DEFAULT 320 }; 321 322 #define HCLGE_FILTER_TYPE_VF 0 323 #define HCLGE_FILTER_TYPE_PORT 1 324 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0) 325 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0) 326 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1) 327 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2) 328 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3) 329 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \ 330 | HCLGE_FILTER_FE_ROCE_EGRESS_B) 331 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \ 332 | HCLGE_FILTER_FE_ROCE_INGRESS_B) 333 334 enum hclge_vlan_fltr_cap { 335 HCLGE_VLAN_FLTR_DEF, 336 HCLGE_VLAN_FLTR_CAN_MDF, 337 }; 338 enum hclge_link_fail_code { 339 HCLGE_LF_NORMAL, 340 HCLGE_LF_REF_CLOCK_LOST, 341 HCLGE_LF_XSFP_TX_DISABLE, 342 HCLGE_LF_XSFP_ABSENT, 343 }; 344 345 #define HCLGE_LINK_STATUS_DOWN 0 346 #define HCLGE_LINK_STATUS_UP 1 347 348 #define HCLGE_PG_NUM 4 349 #define HCLGE_SCH_MODE_SP 0 350 #define HCLGE_SCH_MODE_DWRR 1 351 struct hclge_pg_info { 352 u8 pg_id; 353 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 354 u8 tc_bit_map; 355 u32 bw_limit; 356 u8 tc_dwrr[HNAE3_MAX_TC]; 357 }; 358 359 struct hclge_tc_info { 360 u8 tc_id; 361 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 362 u8 pgid; 363 u32 bw_limit; 364 }; 365 366 struct hclge_cfg { 367 u8 tc_num; 368 u8 vlan_fliter_cap; 369 u16 tqp_desc_num; 370 u16 rx_buf_len; 371 u16 vf_rss_size_max; 372 u16 pf_rss_size_max; 373 u8 phy_addr; 374 u8 media_type; 375 u8 mac_addr[ETH_ALEN]; 376 u8 default_speed; 377 u32 numa_node_map; 378 u32 tx_spare_buf_size; 379 u16 speed_ability; 380 u16 umv_space; 381 }; 382 383 struct hclge_tm_info { 384 u8 num_tc; 385 u8 num_pg; /* It must be 1 if vNET-Base schd */ 386 u8 pg_dwrr[HCLGE_PG_NUM]; 387 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 388 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 389 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 390 enum hclge_fc_mode fc_mode; 391 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 392 u8 pfc_en; /* PFC enabled or not for user priority */ 393 }; 394 395 /* max number of mac statistics on each version */ 396 #define HCLGE_MAC_STATS_MAX_NUM_V1 87 397 #define HCLGE_MAC_STATS_MAX_NUM_V2 105 398 399 struct hclge_comm_stats_str { 400 char desc[ETH_GSTRING_LEN]; 401 u32 stats_num; 402 unsigned long offset; 403 }; 404 405 /* mac stats ,opcode id: 0x0032 */ 406 struct hclge_mac_stats { 407 u64 mac_tx_mac_pause_num; 408 u64 mac_rx_mac_pause_num; 409 u64 rsv0; 410 u64 mac_tx_pfc_pri0_pkt_num; 411 u64 mac_tx_pfc_pri1_pkt_num; 412 u64 mac_tx_pfc_pri2_pkt_num; 413 u64 mac_tx_pfc_pri3_pkt_num; 414 u64 mac_tx_pfc_pri4_pkt_num; 415 u64 mac_tx_pfc_pri5_pkt_num; 416 u64 mac_tx_pfc_pri6_pkt_num; 417 u64 mac_tx_pfc_pri7_pkt_num; 418 u64 mac_rx_pfc_pri0_pkt_num; 419 u64 mac_rx_pfc_pri1_pkt_num; 420 u64 mac_rx_pfc_pri2_pkt_num; 421 u64 mac_rx_pfc_pri3_pkt_num; 422 u64 mac_rx_pfc_pri4_pkt_num; 423 u64 mac_rx_pfc_pri5_pkt_num; 424 u64 mac_rx_pfc_pri6_pkt_num; 425 u64 mac_rx_pfc_pri7_pkt_num; 426 u64 mac_tx_total_pkt_num; 427 u64 mac_tx_total_oct_num; 428 u64 mac_tx_good_pkt_num; 429 u64 mac_tx_bad_pkt_num; 430 u64 mac_tx_good_oct_num; 431 u64 mac_tx_bad_oct_num; 432 u64 mac_tx_uni_pkt_num; 433 u64 mac_tx_multi_pkt_num; 434 u64 mac_tx_broad_pkt_num; 435 u64 mac_tx_undersize_pkt_num; 436 u64 mac_tx_oversize_pkt_num; 437 u64 mac_tx_64_oct_pkt_num; 438 u64 mac_tx_65_127_oct_pkt_num; 439 u64 mac_tx_128_255_oct_pkt_num; 440 u64 mac_tx_256_511_oct_pkt_num; 441 u64 mac_tx_512_1023_oct_pkt_num; 442 u64 mac_tx_1024_1518_oct_pkt_num; 443 u64 mac_tx_1519_2047_oct_pkt_num; 444 u64 mac_tx_2048_4095_oct_pkt_num; 445 u64 mac_tx_4096_8191_oct_pkt_num; 446 u64 rsv1; 447 u64 mac_tx_8192_9216_oct_pkt_num; 448 u64 mac_tx_9217_12287_oct_pkt_num; 449 u64 mac_tx_12288_16383_oct_pkt_num; 450 u64 mac_tx_1519_max_good_oct_pkt_num; 451 u64 mac_tx_1519_max_bad_oct_pkt_num; 452 453 u64 mac_rx_total_pkt_num; 454 u64 mac_rx_total_oct_num; 455 u64 mac_rx_good_pkt_num; 456 u64 mac_rx_bad_pkt_num; 457 u64 mac_rx_good_oct_num; 458 u64 mac_rx_bad_oct_num; 459 u64 mac_rx_uni_pkt_num; 460 u64 mac_rx_multi_pkt_num; 461 u64 mac_rx_broad_pkt_num; 462 u64 mac_rx_undersize_pkt_num; 463 u64 mac_rx_oversize_pkt_num; 464 u64 mac_rx_64_oct_pkt_num; 465 u64 mac_rx_65_127_oct_pkt_num; 466 u64 mac_rx_128_255_oct_pkt_num; 467 u64 mac_rx_256_511_oct_pkt_num; 468 u64 mac_rx_512_1023_oct_pkt_num; 469 u64 mac_rx_1024_1518_oct_pkt_num; 470 u64 mac_rx_1519_2047_oct_pkt_num; 471 u64 mac_rx_2048_4095_oct_pkt_num; 472 u64 mac_rx_4096_8191_oct_pkt_num; 473 u64 rsv2; 474 u64 mac_rx_8192_9216_oct_pkt_num; 475 u64 mac_rx_9217_12287_oct_pkt_num; 476 u64 mac_rx_12288_16383_oct_pkt_num; 477 u64 mac_rx_1519_max_good_oct_pkt_num; 478 u64 mac_rx_1519_max_bad_oct_pkt_num; 479 480 u64 mac_tx_fragment_pkt_num; 481 u64 mac_tx_undermin_pkt_num; 482 u64 mac_tx_jabber_pkt_num; 483 u64 mac_tx_err_all_pkt_num; 484 u64 mac_tx_from_app_good_pkt_num; 485 u64 mac_tx_from_app_bad_pkt_num; 486 u64 mac_rx_fragment_pkt_num; 487 u64 mac_rx_undermin_pkt_num; 488 u64 mac_rx_jabber_pkt_num; 489 u64 mac_rx_fcs_err_pkt_num; 490 u64 mac_rx_send_app_good_pkt_num; 491 u64 mac_rx_send_app_bad_pkt_num; 492 u64 mac_tx_pfc_pause_pkt_num; 493 u64 mac_rx_pfc_pause_pkt_num; 494 u64 mac_tx_ctrl_pkt_num; 495 u64 mac_rx_ctrl_pkt_num; 496 497 /* duration of pfc */ 498 u64 mac_tx_pfc_pri0_xoff_time; 499 u64 mac_tx_pfc_pri1_xoff_time; 500 u64 mac_tx_pfc_pri2_xoff_time; 501 u64 mac_tx_pfc_pri3_xoff_time; 502 u64 mac_tx_pfc_pri4_xoff_time; 503 u64 mac_tx_pfc_pri5_xoff_time; 504 u64 mac_tx_pfc_pri6_xoff_time; 505 u64 mac_tx_pfc_pri7_xoff_time; 506 u64 mac_rx_pfc_pri0_xoff_time; 507 u64 mac_rx_pfc_pri1_xoff_time; 508 u64 mac_rx_pfc_pri2_xoff_time; 509 u64 mac_rx_pfc_pri3_xoff_time; 510 u64 mac_rx_pfc_pri4_xoff_time; 511 u64 mac_rx_pfc_pri5_xoff_time; 512 u64 mac_rx_pfc_pri6_xoff_time; 513 u64 mac_rx_pfc_pri7_xoff_time; 514 515 /* duration of pause */ 516 u64 mac_tx_pause_xoff_time; 517 u64 mac_rx_pause_xoff_time; 518 }; 519 520 #define HCLGE_STATS_TIMER_INTERVAL 300UL 521 522 /* fec stats ,opcode id: 0x0316 */ 523 #define HCLGE_FEC_STATS_MAX_LANES 8 524 struct hclge_fec_stats { 525 /* fec rs mode total stats */ 526 u64 rs_corr_blocks; 527 u64 rs_uncorr_blocks; 528 u64 rs_error_blocks; 529 /* fec base-r mode per lanes stats */ 530 u64 base_r_lane_num; 531 u64 base_r_corr_blocks; 532 u64 base_r_uncorr_blocks; 533 union { 534 struct { 535 u64 base_r_corr_per_lanes[HCLGE_FEC_STATS_MAX_LANES]; 536 u64 base_r_uncorr_per_lanes[HCLGE_FEC_STATS_MAX_LANES]; 537 }; 538 u64 per_lanes[HCLGE_FEC_STATS_MAX_LANES * 2]; 539 }; 540 }; 541 542 struct hclge_vlan_type_cfg { 543 u16 rx_ot_fst_vlan_type; 544 u16 rx_ot_sec_vlan_type; 545 u16 rx_in_fst_vlan_type; 546 u16 rx_in_sec_vlan_type; 547 u16 tx_ot_vlan_type; 548 u16 tx_in_vlan_type; 549 }; 550 551 enum HCLGE_FD_MODE { 552 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 553 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 554 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 555 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 556 }; 557 558 enum HCLGE_FD_KEY_TYPE { 559 HCLGE_FD_KEY_BASE_ON_PTYPE, 560 HCLGE_FD_KEY_BASE_ON_TUPLE, 561 }; 562 563 enum HCLGE_FD_STAGE { 564 HCLGE_FD_STAGE_1, 565 HCLGE_FD_STAGE_2, 566 MAX_STAGE_NUM, 567 }; 568 569 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 570 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 571 * tuples of non-tunnel packet 572 */ 573 enum HCLGE_FD_TUPLE { 574 OUTER_DST_MAC, 575 OUTER_SRC_MAC, 576 OUTER_VLAN_TAG_FST, 577 OUTER_VLAN_TAG_SEC, 578 OUTER_ETH_TYPE, 579 OUTER_L2_RSV, 580 OUTER_IP_TOS, 581 OUTER_IP_PROTO, 582 OUTER_SRC_IP, 583 OUTER_DST_IP, 584 OUTER_L3_RSV, 585 OUTER_SRC_PORT, 586 OUTER_DST_PORT, 587 OUTER_L4_RSV, 588 OUTER_TUN_VNI, 589 OUTER_TUN_FLOW_ID, 590 INNER_DST_MAC, 591 INNER_SRC_MAC, 592 INNER_VLAN_TAG_FST, 593 INNER_VLAN_TAG_SEC, 594 INNER_ETH_TYPE, 595 INNER_L2_RSV, 596 INNER_IP_TOS, 597 INNER_IP_PROTO, 598 INNER_SRC_IP, 599 INNER_DST_IP, 600 INNER_L3_RSV, 601 INNER_SRC_PORT, 602 INNER_DST_PORT, 603 INNER_L4_RSV, 604 MAX_TUPLE, 605 }; 606 607 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \ 608 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV)) 609 610 enum HCLGE_FD_META_DATA { 611 PACKET_TYPE_ID, 612 IP_FRAGEMENT, 613 ROCE_TYPE, 614 NEXT_KEY, 615 VLAN_NUMBER, 616 SRC_VPORT, 617 DST_VPORT, 618 TUNNEL_PACKET, 619 MAX_META_DATA, 620 }; 621 622 enum HCLGE_FD_KEY_OPT { 623 KEY_OPT_U8, 624 KEY_OPT_LE16, 625 KEY_OPT_LE32, 626 KEY_OPT_MAC, 627 KEY_OPT_IP, 628 KEY_OPT_VNI, 629 }; 630 631 struct key_info { 632 u8 key_type; 633 u8 key_length; /* use bit as unit */ 634 enum HCLGE_FD_KEY_OPT key_opt; 635 int offset; 636 int moffset; 637 }; 638 639 #define MAX_KEY_LENGTH 400 640 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 641 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 642 #define MAX_META_DATA_LENGTH 32 643 644 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000 645 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0) 646 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0) 647 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0) 648 #define HCLGE_FD_VXLAN_VNI_UNMASK GENMASK(31, 0) 649 650 #define HCLGE_VNI_LENGTH 3 651 652 /* assigned by firmware, the real filter number for each pf may be less */ 653 #define MAX_FD_FILTER_NUM 4096 654 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 655 656 #define hclge_read_dev(a, reg) \ 657 hclge_comm_read_reg((a)->hw.io_base, reg) 658 #define hclge_write_dev(a, reg, value) \ 659 hclge_comm_write_reg((a)->hw.io_base, reg, value) 660 661 enum HCLGE_FD_ACTIVE_RULE_TYPE { 662 HCLGE_FD_RULE_NONE, 663 HCLGE_FD_ARFS_ACTIVE, 664 HCLGE_FD_EP_ACTIVE, 665 HCLGE_FD_TC_FLOWER_ACTIVE, 666 }; 667 668 enum HCLGE_FD_PACKET_TYPE { 669 NIC_PACKET, 670 ROCE_PACKET, 671 }; 672 673 enum HCLGE_FD_ACTION { 674 HCLGE_FD_ACTION_SELECT_QUEUE, 675 HCLGE_FD_ACTION_DROP_PACKET, 676 HCLGE_FD_ACTION_SELECT_TC, 677 }; 678 679 enum HCLGE_FD_NODE_STATE { 680 HCLGE_FD_TO_ADD, 681 HCLGE_FD_TO_DEL, 682 HCLGE_FD_ACTIVE, 683 HCLGE_FD_DELETED, 684 }; 685 686 enum HCLGE_FD_USER_DEF_LAYER { 687 HCLGE_FD_USER_DEF_NONE, 688 HCLGE_FD_USER_DEF_L2, 689 HCLGE_FD_USER_DEF_L3, 690 HCLGE_FD_USER_DEF_L4, 691 }; 692 693 #define HCLGE_FD_USER_DEF_LAYER_NUM 3 694 struct hclge_fd_user_def_cfg { 695 u16 ref_cnt; 696 u16 offset; 697 }; 698 699 struct hclge_fd_user_def_info { 700 enum HCLGE_FD_USER_DEF_LAYER layer; 701 u16 data; 702 u16 data_mask; 703 u16 offset; 704 }; 705 706 struct hclge_fd_key_cfg { 707 u8 key_sel; 708 u8 inner_sipv6_word_en; 709 u8 inner_dipv6_word_en; 710 u8 outer_sipv6_word_en; 711 u8 outer_dipv6_word_en; 712 u32 tuple_active; 713 u32 meta_data_active; 714 }; 715 716 struct hclge_fd_cfg { 717 u8 fd_mode; 718 u16 max_key_length; /* use bit as unit */ 719 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 720 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 721 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 722 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM]; 723 }; 724 725 #define IPV4_INDEX 3 726 727 struct hclge_fd_rule_tuples { 728 u8 src_mac[ETH_ALEN]; 729 u8 dst_mac[ETH_ALEN]; 730 /* Be compatible for ip address of both ipv4 and ipv6. 731 * For ipv4 address, we store it in src/dst_ip[3]. 732 */ 733 u32 src_ip[IPV6_ADDR_WORDS]; 734 u32 dst_ip[IPV6_ADDR_WORDS]; 735 u16 src_port; 736 u16 dst_port; 737 u16 vlan_tag1; 738 u16 ether_proto; 739 u16 l2_user_def; 740 u16 l3_user_def; 741 u32 l4_user_def; 742 u8 ip_tos; 743 u8 ip_proto; 744 u32 outer_tun_vni; 745 }; 746 747 struct hclge_fd_rule { 748 struct hlist_node rule_node; 749 struct hclge_fd_rule_tuples tuples; 750 struct hclge_fd_rule_tuples tuples_mask; 751 u32 unused_tuple; 752 u32 flow_type; 753 union { 754 struct { 755 unsigned long cookie; 756 u8 tc; 757 } cls_flower; 758 struct { 759 u16 flow_id; /* only used for arfs */ 760 } arfs; 761 struct { 762 struct hclge_fd_user_def_info user_def; 763 } ep; 764 }; 765 u16 queue_id; 766 u16 vf_id; 767 u16 location; 768 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 769 enum HCLGE_FD_NODE_STATE state; 770 u8 action; 771 }; 772 773 struct hclge_fd_ad_data { 774 u16 ad_id; 775 u8 drop_packet; 776 u8 forward_to_direct_queue; 777 u16 queue_id; 778 u8 use_counter; 779 u8 counter_id; 780 u8 use_next_stage; 781 u8 write_rule_id_to_bd; 782 u8 next_input_key; 783 u16 rule_id; 784 u16 tc_size; 785 u8 override_tc; 786 }; 787 788 enum HCLGE_MAC_NODE_STATE { 789 HCLGE_MAC_TO_ADD, 790 HCLGE_MAC_TO_DEL, 791 HCLGE_MAC_ACTIVE 792 }; 793 794 struct hclge_mac_node { 795 struct list_head node; 796 enum HCLGE_MAC_NODE_STATE state; 797 u8 mac_addr[ETH_ALEN]; 798 }; 799 800 enum HCLGE_MAC_ADDR_TYPE { 801 HCLGE_MAC_ADDR_UC, 802 HCLGE_MAC_ADDR_MC 803 }; 804 805 struct hclge_vport_vlan_cfg { 806 struct list_head node; 807 int hd_tbl_status; 808 u16 vlan_id; 809 }; 810 811 struct hclge_rst_stats { 812 u32 reset_done_cnt; /* the number of reset has completed */ 813 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 814 u32 pf_rst_cnt; /* the number of PF reset */ 815 u32 flr_rst_cnt; /* the number of FLR */ 816 u32 global_rst_cnt; /* the number of GLOBAL */ 817 u32 imp_rst_cnt; /* the number of IMP reset */ 818 u32 reset_cnt; /* the number of reset */ 819 u32 reset_fail_cnt; /* the number of reset fail */ 820 }; 821 822 /* time and register status when mac tunnel interruption occur */ 823 struct hclge_mac_tnl_stats { 824 u64 time; 825 u32 status; 826 }; 827 828 #define HCLGE_RESET_INTERVAL (10 * HZ) 829 #define HCLGE_WAIT_RESET_DONE 100 830 831 #pragma pack(1) 832 struct hclge_vf_vlan_cfg { 833 u8 mbx_cmd; 834 u8 subcode; 835 union { 836 struct { 837 u8 is_kill; 838 __le16 vlan; 839 __le16 proto; 840 }; 841 u8 enable; 842 }; 843 }; 844 845 #pragma pack() 846 847 /* For each bit of TCAM entry, it uses a pair of 'x' and 848 * 'y' to indicate which value to match, like below: 849 * ---------------------------------- 850 * | bit x | bit y | search value | 851 * ---------------------------------- 852 * | 0 | 0 | always hit | 853 * ---------------------------------- 854 * | 1 | 0 | match '0' | 855 * ---------------------------------- 856 * | 0 | 1 | match '1' | 857 * ---------------------------------- 858 * | 1 | 1 | invalid | 859 * ---------------------------------- 860 * Then for input key(k) and mask(v), we can calculate the value by 861 * the formulae: 862 * x = (~k) & v 863 * y = k & v 864 */ 865 #define calc_x(x, k, v) ((x) = ~(k) & (v)) 866 #define calc_y(y, k, v) ((y) = (k) & (v)) 867 868 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) 869 #define HCLGE_STATS_READ(p, offset) (*(u64 *)((u8 *)(p) + (offset))) 870 871 #define HCLGE_MAC_TNL_LOG_SIZE 8 872 #define HCLGE_VPORT_NUM 256 873 struct hclge_dev { 874 struct pci_dev *pdev; 875 struct hnae3_ae_dev *ae_dev; 876 struct hclge_hw hw; 877 struct hclge_misc_vector misc_vector; 878 struct hclge_mac_stats mac_stats; 879 struct hclge_fec_stats fec_stats; 880 unsigned long state; 881 unsigned long flr_state; 882 unsigned long last_reset_time; 883 884 enum hnae3_reset_type reset_type; 885 enum hnae3_reset_type reset_level; 886 unsigned long default_reset_request; 887 unsigned long reset_request; /* reset has been requested */ 888 unsigned long reset_pending; /* client rst is pending to be served */ 889 struct hclge_rst_stats rst_stats; 890 struct semaphore reset_sem; /* protect reset process */ 891 u32 fw_version; 892 u16 num_tqps; /* Num task queue pairs of this PF */ 893 u16 num_req_vfs; /* Num VFs requested for this PF */ 894 895 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 896 u16 alloc_rss_size; /* Allocated RSS task queue */ 897 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */ 898 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */ 899 u32 tx_spare_buf_size; /* HW defined TX spare buffer size */ 900 901 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 902 u16 num_alloc_vport; /* Num vports this driver supports */ 903 nodemask_t numa_node_mask; 904 u16 rx_buf_len; 905 u16 num_tx_desc; /* desc num of per tx queue */ 906 u16 num_rx_desc; /* desc num of per rx queue */ 907 u8 hw_tc_map; 908 enum hclge_fc_mode fc_mode_last_time; 909 u8 support_sfp_query; 910 911 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 912 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 913 u8 tx_sch_mode; 914 u8 tc_max; 915 u8 pfc_max; 916 917 u8 default_up; 918 u8 dcbx_cap; 919 struct hclge_tm_info tm_info; 920 921 u16 num_msi; 922 u16 num_msi_left; 923 u16 num_msi_used; 924 u16 *vector_status; 925 int *vector_irq; 926 u16 num_nic_msi; /* Num of nic vectors for this PF */ 927 u16 num_roce_msi; /* Num of roce vectors for this PF */ 928 929 unsigned long service_timer_period; 930 unsigned long service_timer_previous; 931 struct timer_list reset_timer; 932 struct delayed_work service_task; 933 934 bool cur_promisc; 935 int num_alloc_vfs; /* Actual number of VFs allocated */ 936 937 struct hclge_comm_tqp *htqp; 938 struct hclge_vport *vport; 939 940 struct dentry *hclge_dbgfs; 941 942 struct hnae3_client *nic_client; 943 struct hnae3_client *roce_client; 944 945 #define HCLGE_FLAG_MAIN BIT(0) 946 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 947 u32 flag; 948 949 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 950 u32 tx_buf_size; /* Tx buffer size for each TC */ 951 u32 dv_buf_size; /* Dv buffer size for each TC */ 952 953 u32 mps; /* Max packet size */ 954 /* vport_lock protect resource shared by vports */ 955 struct mutex vport_lock; 956 957 struct hclge_vlan_type_cfg vlan_type_cfg; 958 959 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 960 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 961 962 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 963 964 struct hclge_fd_cfg fd_cfg; 965 struct hlist_head fd_rule_list; 966 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 967 u16 hclge_fd_rule_num; 968 unsigned long serv_processed_cnt; 969 unsigned long last_serv_processed; 970 unsigned long last_rst_scheduled; 971 unsigned long last_mbx_scheduled; 972 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 973 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 974 u8 fd_en; 975 bool gro_en; 976 977 u16 wanted_umv_size; 978 /* max available unicast mac vlan space */ 979 u16 max_umv_size; 980 /* private unicast mac vlan space, it's same for PF and its VFs */ 981 u16 priv_umv_size; 982 /* unicast mac vlan space shared by PF and its VFs */ 983 u16 share_umv_size; 984 /* multicast mac address number used by PF and its VFs */ 985 u16 used_mc_mac_num; 986 987 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 988 HCLGE_MAC_TNL_LOG_SIZE); 989 990 struct hclge_ptp *ptp; 991 struct devlink *devlink; 992 struct hclge_comm_rss_cfg rss_cfg; 993 }; 994 995 /* VPort level vlan tag configuration for TX direction */ 996 struct hclge_tx_vtag_cfg { 997 bool accept_tag1; /* Whether accept tag1 packet from host */ 998 bool accept_untag1; /* Whether accept untag1 packet from host */ 999 bool accept_tag2; 1000 bool accept_untag2; 1001 bool insert_tag1_en; /* Whether insert inner vlan tag */ 1002 bool insert_tag2_en; /* Whether insert outer vlan tag */ 1003 u16 default_tag1; /* The default inner vlan tag to insert */ 1004 u16 default_tag2; /* The default outer vlan tag to insert */ 1005 bool tag_shift_mode_en; 1006 }; 1007 1008 /* VPort level vlan tag configuration for RX direction */ 1009 struct hclge_rx_vtag_cfg { 1010 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 1011 bool strip_tag1_en; /* Whether strip inner vlan tag */ 1012 bool strip_tag2_en; /* Whether strip outer vlan tag */ 1013 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */ 1014 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */ 1015 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */ 1016 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */ 1017 }; 1018 1019 enum HCLGE_VPORT_STATE { 1020 HCLGE_VPORT_STATE_ALIVE, 1021 HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 1022 HCLGE_VPORT_STATE_PROMISC_CHANGE, 1023 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 1024 HCLGE_VPORT_STATE_INITED, 1025 HCLGE_VPORT_STATE_MAX 1026 }; 1027 1028 enum HCLGE_VPORT_NEED_NOTIFY { 1029 HCLGE_VPORT_NEED_NOTIFY_RESET, 1030 HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 1031 }; 1032 1033 struct hclge_vlan_info { 1034 u16 vlan_proto; /* so far support 802.1Q only */ 1035 u16 qos; 1036 u16 vlan_tag; 1037 }; 1038 1039 struct hclge_port_base_vlan_config { 1040 u16 state; 1041 bool tbl_sta; 1042 struct hclge_vlan_info vlan_info; 1043 struct hclge_vlan_info old_vlan_info; 1044 }; 1045 1046 struct hclge_vf_info { 1047 int link_state; 1048 u8 mac[ETH_ALEN]; 1049 u32 spoofchk; 1050 u32 max_tx_rate; 1051 u32 trusted; 1052 u8 request_uc_en; 1053 u8 request_mc_en; 1054 u8 request_bc_en; 1055 }; 1056 1057 struct hclge_vport { 1058 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 1059 1060 u16 qs_offset; 1061 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 1062 u8 dwrr; 1063 1064 bool req_vlan_fltr_en; 1065 bool cur_vlan_fltr_en; 1066 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 1067 struct hclge_port_base_vlan_config port_base_vlan_cfg; 1068 struct hclge_tx_vtag_cfg txvlan_cfg; 1069 struct hclge_rx_vtag_cfg rxvlan_cfg; 1070 1071 u16 used_umv_num; 1072 1073 u16 vport_id; 1074 struct hclge_dev *back; /* Back reference to associated dev */ 1075 struct hnae3_handle nic; 1076 struct hnae3_handle roce; 1077 1078 unsigned long state; 1079 unsigned long need_notify; 1080 unsigned long last_active_jiffies; 1081 u32 mps; /* Max packet size */ 1082 struct hclge_vf_info vf_info; 1083 1084 u8 overflow_promisc_flags; 1085 u8 last_promisc_flags; 1086 1087 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 1088 struct list_head uc_mac_list; /* Store VF unicast table */ 1089 struct list_head mc_mac_list; /* Store VF multicast table */ 1090 1091 struct list_head vlan_list; /* Store VF vlan table */ 1092 }; 1093 1094 struct hclge_speed_bit_map { 1095 u32 speed; 1096 u32 speed_bit; 1097 }; 1098 1099 struct hclge_mac_speed_map { 1100 u32 speed_drv; /* speed defined in driver */ 1101 u32 speed_fw; /* speed defined in firmware */ 1102 }; 1103 1104 struct hclge_link_mode_bmap { 1105 u16 support_bit; 1106 enum ethtool_link_mode_bit_indices link_mode; 1107 }; 1108 1109 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 1110 bool en_mc_pmc, bool en_bc_pmc); 1111 int hclge_add_uc_addr_common(struct hclge_vport *vport, 1112 const unsigned char *addr); 1113 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 1114 const unsigned char *addr); 1115 int hclge_add_mc_addr_common(struct hclge_vport *vport, 1116 const unsigned char *addr); 1117 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 1118 const unsigned char *addr); 1119 1120 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 1121 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 1122 int vector_id, bool en, 1123 struct hnae3_ring_chain_node *ring_chain); 1124 1125 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 1126 { 1127 struct hclge_comm_tqp *tqp = 1128 container_of(queue, struct hclge_comm_tqp, q); 1129 1130 return tqp->index; 1131 } 1132 1133 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 1134 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num); 1135 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 1136 u16 vlan_id, bool is_kill); 1137 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 1138 1139 int hclge_buffer_alloc(struct hclge_dev *hdev); 1140 int hclge_rss_init_hw(struct hclge_dev *hdev); 1141 1142 void hclge_mbx_handler(struct hclge_dev *hdev); 1143 int hclge_reset_tqp(struct hnae3_handle *handle); 1144 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 1145 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 1146 int hclge_vport_start(struct hclge_vport *vport); 1147 void hclge_vport_stop(struct hclge_vport *vport); 1148 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 1149 int hclge_dbg_get_read_func(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 1150 read_func *func); 1151 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 1152 int hclge_notify_client(struct hclge_dev *hdev, 1153 enum hnae3_reset_notify_type type); 1154 int hclge_update_mac_list(struct hclge_vport *vport, 1155 enum HCLGE_MAC_NODE_STATE state, 1156 enum HCLGE_MAC_ADDR_TYPE mac_type, 1157 const unsigned char *addr); 1158 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 1159 const u8 *old_addr, const u8 *new_addr); 1160 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 1161 enum HCLGE_MAC_ADDR_TYPE mac_type); 1162 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 1163 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 1164 void hclge_restore_mac_table_common(struct hclge_vport *vport); 1165 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev); 1166 void hclge_restore_vport_vlan_table(struct hclge_vport *vport); 1167 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 1168 struct hclge_vlan_info *vlan_info); 1169 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 1170 u16 state, 1171 struct hclge_vlan_info *vlan_info); 1172 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 1173 void hclge_report_hw_error(struct hclge_dev *hdev, 1174 enum hnae3_hw_error_type type); 1175 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len); 1176 int hclge_push_vf_link_status(struct hclge_vport *vport); 1177 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en); 1178 int hclge_mac_update_stats(struct hclge_dev *hdev); 1179 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf); 1180 int hclge_inform_vf_reset(struct hclge_vport *vport, u16 reset_type); 1181 int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version); 1182 u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 1183 u8 vf_id, u8 network_port_id); 1184 #endif 1185