1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/gpio/driver.h> 8 #include <linux/interrupt.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_irq.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/seq_file.h> 15 #include <linux/slab.h> 16 #include <linux/spmi.h> 17 #include <linux/string_choices.h> 18 #include <linux/types.h> 19 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinmux.h> 23 24 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 25 26 #include "../core.h" 27 #include "../pinctrl-utils.h" 28 29 #define PMIC_GPIO_ADDRESS_RANGE 0x100 30 31 /* type and subtype registers base address offsets */ 32 #define PMIC_GPIO_REG_TYPE 0x4 33 #define PMIC_GPIO_REG_SUBTYPE 0x5 34 35 /* GPIO peripheral type and subtype out_values */ 36 #define PMIC_GPIO_TYPE 0x10 37 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1 38 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5 39 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9 40 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd 41 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10 42 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11 43 #define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2 0x12 44 #define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3 0x13 45 #define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2_CLK 0x14 46 #define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3_CLK 0x15 47 48 #define PMIC_MPP_REG_RT_STS 0x10 49 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 50 51 /* control register base address offsets */ 52 #define PMIC_GPIO_REG_MODE_CTL 0x40 53 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41 54 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42 55 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44 56 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43 57 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45 58 #define PMIC_GPIO_REG_EN_CTL 0x46 59 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A 60 61 /* PMIC_GPIO_REG_MODE_CTL */ 62 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1 63 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1 64 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7 65 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4 66 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7 67 68 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0 69 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1 70 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2 71 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3 72 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3 73 74 /* PMIC_GPIO_REG_DIG_VIN_CTL */ 75 #define PMIC_GPIO_REG_VIN_SHIFT 0 76 #define PMIC_GPIO_REG_VIN_MASK 0x7 77 78 /* PMIC_GPIO_REG_DIG_PULL_CTL */ 79 #define PMIC_GPIO_REG_PULL_SHIFT 0 80 #define PMIC_GPIO_REG_PULL_MASK 0x7 81 82 #define PMIC_GPIO_PULL_DOWN 4 83 #define PMIC_GPIO_PULL_DISABLE 5 84 85 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */ 86 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80 87 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7 88 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF 89 90 /* PMIC_GPIO_REG_DIG_IN_CTL */ 91 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80 92 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7 93 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf 94 95 /* PMIC_GPIO_REG_DIG_OUT_CTL */ 96 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0 97 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3 98 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4 99 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3 100 101 /* 102 * Output type - indicates pin should be configured as push-pull, 103 * open drain or open source. 104 */ 105 #define PMIC_GPIO_OUT_BUF_CMOS 0 106 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1 107 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2 108 109 #define PMIC_GPIO_OUT_STRENGTH_LOW 1 110 #define PMIC_GPIO_OUT_STRENGTH_HIGH 3 111 112 /* PMIC_GPIO_REG_EN_CTL */ 113 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7 114 115 #define PMIC_GPIO_PHYSICAL_OFFSET 1 116 117 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */ 118 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3 119 120 /* Qualcomm specific pin configurations */ 121 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1) 122 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2) 123 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3) 124 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4) 125 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5) 126 127 /* The index of each function in pmic_gpio_functions[] array */ 128 enum pmic_gpio_func_index { 129 PMIC_GPIO_FUNC_INDEX_NORMAL, 130 PMIC_GPIO_FUNC_INDEX_PAIRED, 131 PMIC_GPIO_FUNC_INDEX_FUNC1, 132 PMIC_GPIO_FUNC_INDEX_FUNC2, 133 PMIC_GPIO_FUNC_INDEX_FUNC3, 134 PMIC_GPIO_FUNC_INDEX_FUNC4, 135 PMIC_GPIO_FUNC_INDEX_DTEST1, 136 PMIC_GPIO_FUNC_INDEX_DTEST2, 137 PMIC_GPIO_FUNC_INDEX_DTEST3, 138 PMIC_GPIO_FUNC_INDEX_DTEST4, 139 }; 140 141 /** 142 * struct pmic_gpio_pad - keep current GPIO settings 143 * @base: Address base in SPMI device. 144 * @is_enabled: Set to false when GPIO should be put in high Z state. 145 * @out_value: Cached pin output value 146 * @have_buffer: Set to true if GPIO output could be configured in push-pull, 147 * open-drain or open-source mode. 148 * @output_enabled: Set to true if GPIO output logic is enabled. 149 * @input_enabled: Set to true if GPIO input buffer logic is enabled. 150 * @analog_pass: Set to true if GPIO is in analog-pass-through mode. 151 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11). 152 * @num_sources: Number of power-sources supported by this GPIO. 153 * @power_source: Current power-source used. 154 * @buffer_type: Push-pull, open-drain or open-source. 155 * @pullup: Constant current which flow trough GPIO output buffer. 156 * @strength: No, Low, Medium, High 157 * @function: See pmic_gpio_functions[] 158 * @atest: the ATEST selection for GPIO analog-pass-through mode 159 * @dtest_buffer: the DTEST buffer selection for digital input mode. 160 */ 161 struct pmic_gpio_pad { 162 u16 base; 163 bool is_enabled; 164 bool out_value; 165 bool have_buffer; 166 bool output_enabled; 167 bool input_enabled; 168 bool analog_pass; 169 bool lv_mv_type; 170 unsigned int num_sources; 171 unsigned int power_source; 172 unsigned int buffer_type; 173 unsigned int pullup; 174 unsigned int strength; 175 unsigned int function; 176 unsigned int atest; 177 unsigned int dtest_buffer; 178 }; 179 180 struct pmic_gpio_state { 181 struct device *dev; 182 struct regmap *map; 183 struct pinctrl_dev *ctrl; 184 struct gpio_chip chip; 185 u8 usid; 186 u8 pid_base; 187 }; 188 189 static const struct pinconf_generic_params pmic_gpio_bindings[] = { 190 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, 191 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, 192 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0}, 193 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0}, 194 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0}, 195 }; 196 197 #ifdef CONFIG_DEBUG_FS 198 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { 199 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), 200 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true), 201 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true), 202 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true), 203 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true), 204 }; 205 #endif 206 207 static const char *const pmic_gpio_groups[] = { 208 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 209 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", 210 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 211 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 212 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", 213 }; 214 215 static const char *const pmic_gpio_functions[] = { 216 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL, 217 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED, 218 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1, 219 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2, 220 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3, 221 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4, 222 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1, 223 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2, 224 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3, 225 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4, 226 }; 227 228 static int pmic_gpio_read(struct pmic_gpio_state *state, 229 struct pmic_gpio_pad *pad, unsigned int addr) 230 { 231 unsigned int val; 232 int ret; 233 234 ret = regmap_read(state->map, pad->base + addr, &val); 235 if (ret < 0) 236 dev_err(state->dev, "read 0x%x failed\n", addr); 237 else 238 ret = val; 239 240 return ret; 241 } 242 243 static int pmic_gpio_write(struct pmic_gpio_state *state, 244 struct pmic_gpio_pad *pad, unsigned int addr, 245 unsigned int val) 246 { 247 int ret; 248 249 ret = regmap_write(state->map, pad->base + addr, val); 250 if (ret < 0) 251 dev_err(state->dev, "write 0x%x failed\n", addr); 252 253 return ret; 254 } 255 256 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev) 257 { 258 /* Every PIN is a group */ 259 return pctldev->desc->npins; 260 } 261 262 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev, 263 unsigned pin) 264 { 265 return pctldev->desc->pins[pin].name; 266 } 267 268 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, 269 const unsigned **pins, unsigned *num_pins) 270 { 271 *pins = &pctldev->desc->pins[pin].number; 272 *num_pins = 1; 273 return 0; 274 } 275 276 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = { 277 .get_groups_count = pmic_gpio_get_groups_count, 278 .get_group_name = pmic_gpio_get_group_name, 279 .get_group_pins = pmic_gpio_get_group_pins, 280 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 281 .dt_free_map = pinctrl_utils_free_map, 282 }; 283 284 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev) 285 { 286 return ARRAY_SIZE(pmic_gpio_functions); 287 } 288 289 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev, 290 unsigned function) 291 { 292 return pmic_gpio_functions[function]; 293 } 294 295 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev, 296 unsigned function, 297 const char *const **groups, 298 unsigned *const num_qgroups) 299 { 300 *groups = pmic_gpio_groups; 301 *num_qgroups = pctldev->desc->npins; 302 return 0; 303 } 304 305 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function, 306 unsigned pin) 307 { 308 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 309 struct pmic_gpio_pad *pad; 310 unsigned int val; 311 int ret; 312 313 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) { 314 pr_err("function: %d is not defined\n", function); 315 return -EINVAL; 316 } 317 318 pad = pctldev->desc->pins[pin].drv_data; 319 /* 320 * Non-LV/MV subtypes only support 2 special functions, 321 * offsetting the dtestx function values by 2 322 */ 323 if (!pad->lv_mv_type) { 324 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 || 325 function == PMIC_GPIO_FUNC_INDEX_FUNC4) { 326 pr_err("LV/MV subtype doesn't have func3/func4\n"); 327 return -EINVAL; 328 } 329 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1) 330 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 - 331 PMIC_GPIO_FUNC_INDEX_FUNC3); 332 } 333 334 pad->function = function; 335 336 if (pad->analog_pass) 337 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; 338 else if (pad->output_enabled && pad->input_enabled) 339 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; 340 else if (pad->output_enabled) 341 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; 342 else 343 val = PMIC_GPIO_MODE_DIGITAL_INPUT; 344 345 if (pad->lv_mv_type) { 346 ret = pmic_gpio_write(state, pad, 347 PMIC_GPIO_REG_MODE_CTL, val); 348 if (ret < 0) 349 return ret; 350 351 val = pad->atest - 1; 352 ret = pmic_gpio_write(state, pad, 353 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); 354 if (ret < 0) 355 return ret; 356 357 val = pad->out_value 358 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; 359 val |= pad->function 360 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 361 ret = pmic_gpio_write(state, pad, 362 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); 363 if (ret < 0) 364 return ret; 365 } else { 366 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; 367 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 368 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 369 370 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 371 if (ret < 0) 372 return ret; 373 } 374 375 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; 376 377 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); 378 } 379 380 static const struct pinmux_ops pmic_gpio_pinmux_ops = { 381 .get_functions_count = pmic_gpio_get_functions_count, 382 .get_function_name = pmic_gpio_get_function_name, 383 .get_function_groups = pmic_gpio_get_function_groups, 384 .set_mux = pmic_gpio_set_mux, 385 }; 386 387 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev, 388 unsigned int pin, unsigned long *config) 389 { 390 unsigned param = pinconf_to_config_param(*config); 391 struct pmic_gpio_pad *pad; 392 unsigned arg; 393 394 pad = pctldev->desc->pins[pin].drv_data; 395 396 switch (param) { 397 case PIN_CONFIG_DRIVE_PUSH_PULL: 398 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS) 399 return -EINVAL; 400 arg = 1; 401 break; 402 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 403 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS) 404 return -EINVAL; 405 arg = 1; 406 break; 407 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 408 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS) 409 return -EINVAL; 410 arg = 1; 411 break; 412 case PIN_CONFIG_BIAS_PULL_DOWN: 413 if (pad->pullup != PMIC_GPIO_PULL_DOWN) 414 return -EINVAL; 415 arg = 1; 416 break; 417 case PIN_CONFIG_BIAS_DISABLE: 418 if (pad->pullup != PMIC_GPIO_PULL_DISABLE) 419 return -EINVAL; 420 arg = 1; 421 break; 422 case PIN_CONFIG_BIAS_PULL_UP: 423 if (pad->pullup != PMIC_GPIO_PULL_UP_30) 424 return -EINVAL; 425 arg = 1; 426 break; 427 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 428 if (pad->is_enabled) 429 return -EINVAL; 430 arg = 1; 431 break; 432 case PIN_CONFIG_POWER_SOURCE: 433 arg = pad->power_source; 434 break; 435 case PIN_CONFIG_INPUT_ENABLE: 436 if (!pad->input_enabled) 437 return -EINVAL; 438 arg = 1; 439 break; 440 case PIN_CONFIG_OUTPUT_ENABLE: 441 arg = pad->output_enabled; 442 break; 443 case PIN_CONFIG_LEVEL: 444 arg = pad->out_value; 445 break; 446 case PMIC_GPIO_CONF_PULL_UP: 447 arg = pad->pullup; 448 break; 449 case PMIC_GPIO_CONF_STRENGTH: 450 switch (pad->strength) { 451 case PMIC_GPIO_OUT_STRENGTH_HIGH: 452 arg = PMIC_GPIO_STRENGTH_HIGH; 453 break; 454 case PMIC_GPIO_OUT_STRENGTH_LOW: 455 arg = PMIC_GPIO_STRENGTH_LOW; 456 break; 457 default: 458 arg = pad->strength; 459 break; 460 } 461 break; 462 case PMIC_GPIO_CONF_ATEST: 463 arg = pad->atest; 464 break; 465 case PMIC_GPIO_CONF_ANALOG_PASS: 466 arg = pad->analog_pass; 467 break; 468 case PMIC_GPIO_CONF_DTEST_BUFFER: 469 arg = pad->dtest_buffer; 470 break; 471 default: 472 return -EINVAL; 473 } 474 475 *config = pinconf_to_config_packed(param, arg); 476 return 0; 477 } 478 479 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 480 unsigned long *configs, unsigned nconfs) 481 { 482 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 483 struct pmic_gpio_pad *pad; 484 unsigned param, arg; 485 unsigned int val; 486 int i, ret; 487 488 pad = pctldev->desc->pins[pin].drv_data; 489 490 pad->is_enabled = true; 491 for (i = 0; i < nconfs; i++) { 492 param = pinconf_to_config_param(configs[i]); 493 arg = pinconf_to_config_argument(configs[i]); 494 495 switch (param) { 496 case PIN_CONFIG_DRIVE_PUSH_PULL: 497 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; 498 break; 499 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 500 if (!pad->have_buffer) 501 return -EINVAL; 502 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; 503 break; 504 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 505 if (!pad->have_buffer) 506 return -EINVAL; 507 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; 508 break; 509 case PIN_CONFIG_BIAS_DISABLE: 510 pad->pullup = PMIC_GPIO_PULL_DISABLE; 511 break; 512 case PIN_CONFIG_BIAS_PULL_UP: 513 pad->pullup = PMIC_GPIO_PULL_UP_30; 514 break; 515 case PIN_CONFIG_BIAS_PULL_DOWN: 516 if (arg) 517 pad->pullup = PMIC_GPIO_PULL_DOWN; 518 else 519 pad->pullup = PMIC_GPIO_PULL_DISABLE; 520 break; 521 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 522 pad->is_enabled = false; 523 break; 524 case PIN_CONFIG_POWER_SOURCE: 525 if (arg >= pad->num_sources) 526 return -EINVAL; 527 pad->power_source = arg; 528 break; 529 case PIN_CONFIG_INPUT_ENABLE: 530 pad->input_enabled = arg ? true : false; 531 break; 532 case PIN_CONFIG_OUTPUT_ENABLE: 533 pad->output_enabled = arg ? true : false; 534 break; 535 case PIN_CONFIG_LEVEL: 536 pad->output_enabled = true; 537 pad->out_value = arg; 538 break; 539 case PMIC_GPIO_CONF_PULL_UP: 540 if (arg > PMIC_GPIO_PULL_UP_1P5_30) 541 return -EINVAL; 542 pad->pullup = arg; 543 break; 544 case PMIC_GPIO_CONF_STRENGTH: 545 if (arg > PMIC_GPIO_STRENGTH_LOW) 546 return -EINVAL; 547 switch (arg) { 548 case PMIC_GPIO_STRENGTH_HIGH: 549 pad->strength = PMIC_GPIO_OUT_STRENGTH_HIGH; 550 break; 551 case PMIC_GPIO_STRENGTH_LOW: 552 pad->strength = PMIC_GPIO_OUT_STRENGTH_LOW; 553 break; 554 default: 555 pad->strength = arg; 556 break; 557 } 558 break; 559 case PMIC_GPIO_CONF_ATEST: 560 if (!pad->lv_mv_type || arg > 4) 561 return -EINVAL; 562 pad->atest = arg; 563 break; 564 case PMIC_GPIO_CONF_ANALOG_PASS: 565 if (!pad->lv_mv_type) 566 return -EINVAL; 567 pad->analog_pass = true; 568 break; 569 case PMIC_GPIO_CONF_DTEST_BUFFER: 570 if (arg > 4) 571 return -EINVAL; 572 pad->dtest_buffer = arg; 573 break; 574 default: 575 return -EINVAL; 576 } 577 } 578 579 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT; 580 581 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val); 582 if (ret < 0) 583 return ret; 584 585 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT; 586 587 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val); 588 if (ret < 0) 589 return ret; 590 591 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT; 592 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 593 594 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val); 595 if (ret < 0) 596 return ret; 597 598 if (pad->dtest_buffer == 0) { 599 val = 0; 600 } else { 601 if (pad->lv_mv_type) { 602 val = pad->dtest_buffer - 1; 603 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN; 604 } else { 605 val = BIT(pad->dtest_buffer - 1); 606 } 607 } 608 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val); 609 if (ret < 0) 610 return ret; 611 612 if (pad->analog_pass) 613 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; 614 else if (pad->output_enabled && pad->input_enabled) 615 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; 616 else if (pad->output_enabled) 617 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; 618 else 619 val = PMIC_GPIO_MODE_DIGITAL_INPUT; 620 621 if (pad->lv_mv_type) { 622 ret = pmic_gpio_write(state, pad, 623 PMIC_GPIO_REG_MODE_CTL, val); 624 if (ret < 0) 625 return ret; 626 627 val = pad->atest - 1; 628 ret = pmic_gpio_write(state, pad, 629 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); 630 if (ret < 0) 631 return ret; 632 633 val = pad->out_value 634 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; 635 val |= pad->function 636 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 637 ret = pmic_gpio_write(state, pad, 638 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); 639 if (ret < 0) 640 return ret; 641 } else { 642 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; 643 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 644 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 645 646 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 647 if (ret < 0) 648 return ret; 649 } 650 651 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; 652 653 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); 654 655 return ret; 656 } 657 658 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, 659 struct seq_file *s, unsigned pin) 660 { 661 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 662 struct pmic_gpio_pad *pad; 663 int ret, val, function; 664 665 static const char *const biases[] = { 666 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", 667 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" 668 }; 669 static const char *const buffer_types[] = { 670 "push-pull", "open-drain", "open-source" 671 }; 672 static const char *const strengths[] = { 673 "no", "low", "medium", "high" 674 }; 675 676 pad = pctldev->desc->pins[pin].drv_data; 677 678 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET); 679 680 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL); 681 682 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { 683 seq_puts(s, " ---"); 684 } else { 685 if (pad->input_enabled) { 686 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 687 if (ret < 0) 688 return; 689 690 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; 691 pad->out_value = ret; 692 } 693 /* 694 * For the non-LV/MV subtypes only 2 special functions are 695 * available, offsetting the dtest function values by 2. 696 */ 697 function = pad->function; 698 if (!pad->lv_mv_type && 699 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3) 700 function += PMIC_GPIO_FUNC_INDEX_DTEST1 - 701 PMIC_GPIO_FUNC_INDEX_FUNC3; 702 703 if (pad->analog_pass) 704 seq_puts(s, " analog-pass"); 705 else 706 seq_printf(s, " %-4s", 707 pad->output_enabled ? "out" : "in"); 708 seq_printf(s, " %-4s", str_high_low(pad->out_value)); 709 seq_printf(s, " %-7s", pmic_gpio_functions[function]); 710 seq_printf(s, " vin-%d", pad->power_source); 711 seq_printf(s, " %-27s", biases[pad->pullup]); 712 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]); 713 seq_printf(s, " %-7s", strengths[pad->strength]); 714 seq_printf(s, " atest-%d", pad->atest); 715 seq_printf(s, " dtest-%d", pad->dtest_buffer); 716 } 717 } 718 719 static const struct pinconf_ops pmic_gpio_pinconf_ops = { 720 .is_generic = true, 721 .pin_config_group_get = pmic_gpio_config_get, 722 .pin_config_group_set = pmic_gpio_config_set, 723 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show, 724 }; 725 726 static int pmic_gpio_get_direction(struct gpio_chip *chip, unsigned pin) 727 { 728 struct pmic_gpio_state *state = gpiochip_get_data(chip); 729 struct pmic_gpio_pad *pad; 730 731 pad = state->ctrl->desc->pins[pin].drv_data; 732 733 if (!pad->is_enabled || pad->analog_pass || 734 (!pad->input_enabled && !pad->output_enabled)) 735 return -EINVAL; 736 737 /* 738 * An open-drain or open-source pad keeps its input buffer enabled while 739 * driving, so the output buffer is what tells the direction. 740 */ 741 return pad->output_enabled ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 742 } 743 744 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 745 { 746 struct pmic_gpio_state *state = gpiochip_get_data(chip); 747 unsigned long configs[2]; 748 749 configs[0] = pinconf_to_config_packed(PIN_CONFIG_OUTPUT_ENABLE, 0); 750 configs[1] = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 751 752 return pmic_gpio_config_set(state->ctrl, pin, configs, 753 ARRAY_SIZE(configs)); 754 } 755 756 static int pmic_gpio_direction_output(struct gpio_chip *chip, 757 unsigned pin, int val) 758 { 759 struct pmic_gpio_state *state = gpiochip_get_data(chip); 760 struct pmic_gpio_pad *pad = state->ctrl->desc->pins[pin].drv_data; 761 unsigned long configs[2]; 762 763 /* 764 * An open-drain or open-source pad only ever drives one rail, so the 765 * line can still be sampled while the pad is an output. Keep the input 766 * buffer enabled for those, so that pmic_gpio_get() reports what is on 767 * the wire rather than the value last written, and disable it for a 768 * CMOS pad, so that the pad ends up in DIGITAL_OUTPUT rather than 769 * DIGITAL_INPUT_OUTPUT. Program it either way, as the buffer may have 770 * been left in the opposite state by the bootloader or by an earlier 771 * direction change with a different buffer type. gpiolib applies 772 * PIN_CONFIG_DRIVE_OPEN_DRAIN before calling this, so buffer_type is 773 * already up to date here. 774 */ 775 configs[0] = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 776 pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS); 777 configs[1] = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val); 778 779 return pmic_gpio_config_set(state->ctrl, pin, configs, 780 ARRAY_SIZE(configs)); 781 } 782 783 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin) 784 { 785 struct pmic_gpio_state *state = gpiochip_get_data(chip); 786 struct pmic_gpio_pad *pad; 787 int ret; 788 789 pad = state->ctrl->desc->pins[pin].drv_data; 790 791 if (!pad->is_enabled) 792 return -EINVAL; 793 794 if (pad->input_enabled) { 795 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 796 if (ret < 0) 797 return ret; 798 799 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; 800 } 801 802 return !!pad->out_value; 803 } 804 805 static int pmic_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 806 { 807 struct pmic_gpio_state *state = gpiochip_get_data(chip); 808 unsigned long config; 809 810 config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value); 811 812 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); 813 } 814 815 static int pmic_gpio_of_xlate(struct gpio_chip *chip, 816 const struct of_phandle_args *gpio_desc, 817 u32 *flags) 818 { 819 if (chip->of_gpio_n_cells < 2) 820 return -EINVAL; 821 822 if (flags) 823 *flags = gpio_desc->args[1]; 824 825 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET; 826 } 827 828 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 829 { 830 struct pmic_gpio_state *state = gpiochip_get_data(chip); 831 unsigned i; 832 833 for (i = 0; i < chip->ngpio; i++) { 834 pmic_gpio_config_dbg_show(state->ctrl, s, i); 835 seq_puts(s, "\n"); 836 } 837 } 838 839 static const struct gpio_chip pmic_gpio_gpio_template = { 840 .get_direction = pmic_gpio_get_direction, 841 .direction_input = pmic_gpio_direction_input, 842 .direction_output = pmic_gpio_direction_output, 843 .get = pmic_gpio_get, 844 .set = pmic_gpio_set, 845 .request = gpiochip_generic_request, 846 .free = gpiochip_generic_free, 847 .of_xlate = pmic_gpio_of_xlate, 848 .dbg_show = pmic_gpio_dbg_show, 849 }; 850 851 static int pmic_gpio_populate(struct pmic_gpio_state *state, 852 struct pmic_gpio_pad *pad) 853 { 854 int type, subtype, val, dir; 855 856 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE); 857 if (type < 0) 858 return type; 859 860 if (type != PMIC_GPIO_TYPE) { 861 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", 862 type, pad->base); 863 return -ENODEV; 864 } 865 866 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE); 867 if (subtype < 0) 868 return subtype; 869 870 switch (subtype) { 871 case PMIC_GPIO_SUBTYPE_GPIO_4CH: 872 pad->have_buffer = true; 873 fallthrough; 874 case PMIC_GPIO_SUBTYPE_GPIOC_4CH: 875 pad->num_sources = 4; 876 break; 877 case PMIC_GPIO_SUBTYPE_GPIO_8CH: 878 pad->have_buffer = true; 879 fallthrough; 880 case PMIC_GPIO_SUBTYPE_GPIOC_8CH: 881 pad->num_sources = 8; 882 break; 883 case PMIC_GPIO_SUBTYPE_GPIO_LV: 884 pad->num_sources = 1; 885 pad->have_buffer = true; 886 pad->lv_mv_type = true; 887 break; 888 case PMIC_GPIO_SUBTYPE_GPIO_MV: 889 pad->num_sources = 2; 890 pad->have_buffer = true; 891 pad->lv_mv_type = true; 892 break; 893 case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2: 894 case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2_CLK: 895 pad->num_sources = 2; 896 pad->have_buffer = true; 897 pad->lv_mv_type = true; 898 break; 899 case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3: 900 case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3_CLK: 901 pad->num_sources = 3; 902 pad->have_buffer = true; 903 pad->lv_mv_type = true; 904 break; 905 default: 906 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype); 907 return -ENODEV; 908 } 909 910 if (pad->lv_mv_type) { 911 val = pmic_gpio_read(state, pad, 912 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL); 913 if (val < 0) 914 return val; 915 916 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT); 917 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 918 919 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); 920 if (val < 0) 921 return val; 922 923 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK; 924 } else { 925 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); 926 if (val < 0) 927 return val; 928 929 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 930 931 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; 932 dir &= PMIC_GPIO_REG_MODE_DIR_MASK; 933 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 934 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; 935 } 936 937 switch (dir) { 938 case PMIC_GPIO_MODE_DIGITAL_INPUT: 939 pad->input_enabled = true; 940 pad->output_enabled = false; 941 break; 942 case PMIC_GPIO_MODE_DIGITAL_OUTPUT: 943 pad->input_enabled = false; 944 pad->output_enabled = true; 945 break; 946 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT: 947 pad->input_enabled = true; 948 pad->output_enabled = true; 949 break; 950 case PMIC_GPIO_MODE_ANALOG_PASS_THRU: 951 if (!pad->lv_mv_type) 952 return -ENODEV; 953 pad->analog_pass = true; 954 break; 955 default: 956 dev_err(state->dev, "unknown GPIO direction\n"); 957 return -ENODEV; 958 } 959 960 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL); 961 if (val < 0) 962 return val; 963 964 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT; 965 pad->power_source &= PMIC_GPIO_REG_VIN_MASK; 966 967 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL); 968 if (val < 0) 969 return val; 970 971 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; 972 pad->pullup &= PMIC_GPIO_REG_PULL_MASK; 973 974 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL); 975 if (val < 0) 976 return val; 977 978 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN)) 979 pad->dtest_buffer = 980 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1; 981 else if (!pad->lv_mv_type) 982 pad->dtest_buffer = ffs(val); 983 else 984 pad->dtest_buffer = 0; 985 986 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL); 987 if (val < 0) 988 return val; 989 990 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 991 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK; 992 993 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; 994 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK; 995 996 if (pad->lv_mv_type) { 997 val = pmic_gpio_read(state, pad, 998 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL); 999 if (val < 0) 1000 return val; 1001 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1; 1002 } 1003 1004 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ 1005 pad->is_enabled = true; 1006 return 0; 1007 } 1008 1009 static int pmic_gpio_domain_translate(struct irq_domain *domain, 1010 struct irq_fwspec *fwspec, 1011 unsigned long *hwirq, 1012 unsigned int *type) 1013 { 1014 struct pmic_gpio_state *state = container_of(domain->host_data, 1015 struct pmic_gpio_state, 1016 chip); 1017 1018 if (fwspec->param_count != 2 || 1019 fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio) 1020 return -EINVAL; 1021 1022 *hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET; 1023 *type = fwspec->param[1]; 1024 1025 return 0; 1026 } 1027 1028 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip, 1029 unsigned int offset) 1030 { 1031 return offset + PMIC_GPIO_PHYSICAL_OFFSET; 1032 } 1033 1034 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 1035 unsigned int child_hwirq, 1036 unsigned int child_type, 1037 unsigned int *parent_hwirq, 1038 unsigned int *parent_type) 1039 { 1040 struct pmic_gpio_state *state = gpiochip_get_data(chip); 1041 1042 *parent_hwirq = child_hwirq + state->pid_base; 1043 *parent_type = child_type; 1044 1045 return 0; 1046 } 1047 1048 static int pmic_gpio_populate_parent_fwspec(struct gpio_chip *chip, 1049 union gpio_irq_fwspec *gfwspec, 1050 unsigned int parent_hwirq, 1051 unsigned int parent_type) 1052 { 1053 struct pmic_gpio_state *state = gpiochip_get_data(chip); 1054 struct irq_fwspec *fwspec = &gfwspec->fwspec; 1055 1056 fwspec->fwnode = chip->irq.parent_domain->fwnode; 1057 1058 fwspec->param_count = 4; 1059 fwspec->param[0] = state->usid; 1060 fwspec->param[1] = parent_hwirq; 1061 /* param[2] must be left as 0 */ 1062 fwspec->param[3] = parent_type; 1063 1064 return 0; 1065 } 1066 1067 static void pmic_gpio_irq_mask(struct irq_data *data) 1068 { 1069 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1070 1071 irq_chip_mask_parent(data); 1072 gpiochip_disable_irq(gc, data->hwirq); 1073 } 1074 1075 static void pmic_gpio_irq_unmask(struct irq_data *data) 1076 { 1077 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1078 1079 gpiochip_enable_irq(gc, data->hwirq); 1080 irq_chip_unmask_parent(data); 1081 } 1082 1083 static const struct irq_chip spmi_gpio_irq_chip = { 1084 .name = "spmi-gpio", 1085 .irq_ack = irq_chip_ack_parent, 1086 .irq_mask = pmic_gpio_irq_mask, 1087 .irq_unmask = pmic_gpio_irq_unmask, 1088 .irq_set_type = irq_chip_set_type_parent, 1089 .irq_set_wake = irq_chip_set_wake_parent, 1090 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND, 1091 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1092 }; 1093 1094 static int pmic_gpio_probe(struct platform_device *pdev) 1095 { 1096 struct irq_domain *parent_domain; 1097 struct device_node *parent_node; 1098 struct device *dev = &pdev->dev; 1099 struct pinctrl_pin_desc *pindesc; 1100 struct pinctrl_desc *pctrldesc; 1101 struct pmic_gpio_pad *pad, *pads; 1102 struct pmic_gpio_state *state; 1103 struct gpio_irq_chip *girq; 1104 const struct spmi_device *parent_spmi_dev; 1105 int ret, npins, i; 1106 u32 reg; 1107 1108 ret = of_property_read_u32(dev->of_node, "reg", ®); 1109 if (ret < 0) { 1110 dev_err(dev, "missing base address"); 1111 return ret; 1112 } 1113 1114 npins = (uintptr_t) device_get_match_data(&pdev->dev); 1115 1116 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 1117 if (!state) 1118 return -ENOMEM; 1119 1120 platform_set_drvdata(pdev, state); 1121 1122 state->dev = &pdev->dev; 1123 state->map = dev_get_regmap(dev->parent, NULL); 1124 parent_spmi_dev = to_spmi_device(dev->parent); 1125 state->usid = parent_spmi_dev->usid; 1126 state->pid_base = reg >> 8; 1127 1128 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); 1129 if (!pindesc) 1130 return -ENOMEM; 1131 1132 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); 1133 if (!pads) 1134 return -ENOMEM; 1135 1136 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); 1137 if (!pctrldesc) 1138 return -ENOMEM; 1139 1140 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops; 1141 pctrldesc->pmxops = &pmic_gpio_pinmux_ops; 1142 pctrldesc->confops = &pmic_gpio_pinconf_ops; 1143 pctrldesc->owner = THIS_MODULE; 1144 pctrldesc->name = dev_name(dev); 1145 pctrldesc->pins = pindesc; 1146 pctrldesc->npins = npins; 1147 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings); 1148 pctrldesc->custom_params = pmic_gpio_bindings; 1149 #ifdef CONFIG_DEBUG_FS 1150 pctrldesc->custom_conf_items = pmic_conf_items; 1151 #endif 1152 1153 for (i = 0; i < npins; i++, pindesc++) { 1154 pad = &pads[i]; 1155 pindesc->drv_data = pad; 1156 pindesc->number = i; 1157 pindesc->name = pmic_gpio_groups[i]; 1158 1159 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE; 1160 1161 ret = pmic_gpio_populate(state, pad); 1162 if (ret < 0) 1163 return ret; 1164 } 1165 1166 state->chip = pmic_gpio_gpio_template; 1167 state->chip.parent = dev; 1168 state->chip.base = -1; 1169 state->chip.ngpio = npins; 1170 state->chip.label = dev_name(dev); 1171 state->chip.of_gpio_n_cells = 2; 1172 state->chip.can_sleep = false; 1173 1174 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state); 1175 if (IS_ERR(state->ctrl)) 1176 return PTR_ERR(state->ctrl); 1177 1178 parent_node = of_irq_find_parent(state->dev->of_node); 1179 if (!parent_node) 1180 return -ENXIO; 1181 1182 parent_domain = irq_find_host(parent_node); 1183 of_node_put(parent_node); 1184 if (!parent_domain) 1185 return -ENXIO; 1186 1187 girq = &state->chip.irq; 1188 gpio_irq_chip_set_chip(girq, &spmi_gpio_irq_chip); 1189 girq->default_type = IRQ_TYPE_NONE; 1190 girq->handler = handle_level_irq; 1191 girq->fwnode = dev_fwnode(state->dev); 1192 girq->parent_domain = parent_domain; 1193 girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq; 1194 girq->populate_parent_alloc_arg = pmic_gpio_populate_parent_fwspec; 1195 girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq; 1196 girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate; 1197 1198 ret = gpiochip_add_data(&state->chip, state); 1199 if (ret) { 1200 dev_err(state->dev, "can't add gpio chip\n"); 1201 return ret; 1202 } 1203 1204 /* 1205 * For DeviceTree-supported systems, the gpio core checks the 1206 * pinctrl's device node for the "gpio-ranges" property. 1207 * If it is present, it takes care of adding the pin ranges 1208 * for the driver. In this case the driver can skip ahead. 1209 * 1210 * In order to remain compatible with older, existing DeviceTree 1211 * files which don't set the "gpio-ranges" property or systems that 1212 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 1213 */ 1214 if (!of_property_present(dev->of_node, "gpio-ranges")) { 1215 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, 1216 npins); 1217 if (ret) { 1218 dev_err(dev, "failed to add pin range\n"); 1219 goto err_range; 1220 } 1221 } 1222 1223 return 0; 1224 1225 err_range: 1226 gpiochip_remove(&state->chip); 1227 return ret; 1228 } 1229 1230 static void pmic_gpio_remove(struct platform_device *pdev) 1231 { 1232 struct pmic_gpio_state *state = platform_get_drvdata(pdev); 1233 1234 gpiochip_remove(&state->chip); 1235 } 1236 1237 static const struct of_device_id pmic_gpio_of_match[] = { 1238 { .compatible = "qcom,pm2250-gpio", .data = (void *) 10 }, 1239 /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */ 1240 { .compatible = "qcom,pm660-gpio", .data = (void *) 13 }, 1241 /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */ 1242 { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 }, 1243 { .compatible = "qcom,pm6125-gpio", .data = (void *) 9 }, 1244 { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, 1245 { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 }, 1246 { .compatible = "qcom,pm6350-gpio", .data = (void *) 9 }, 1247 { .compatible = "qcom,pm6450-gpio", .data = (void *) 9 }, 1248 { .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 }, 1249 { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, 1250 { .compatible = "qcom,pm7550-gpio", .data = (void *) 12 }, 1251 { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8}, 1252 { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, 1253 { .compatible = "qcom,pm8010-gpio", .data = (void *) 2 }, 1254 { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 }, 1255 /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ 1256 { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, 1257 { .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 }, 1258 /* pm8150b has 12 GPIOs with holes on 3, r and 7 */ 1259 { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 }, 1260 /* pm8150l has 12 GPIOs with holes on 7 */ 1261 { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 }, 1262 { .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 }, 1263 { .compatible = "qcom,pm8226-gpio", .data = (void *) 8 }, 1264 { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 }, 1265 { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 }, 1266 { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 }, 1267 { .compatible = "qcom,pm8450-gpio", .data = (void *) 4 }, 1268 { .compatible = "qcom,pm8550-gpio", .data = (void *) 12 }, 1269 { .compatible = "qcom,pm8550b-gpio", .data = (void *) 12 }, 1270 { .compatible = "qcom,pm8550ve-gpio", .data = (void *) 8 }, 1271 { .compatible = "qcom,pm8550vs-gpio", .data = (void *) 6 }, 1272 { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 }, 1273 /* pm8937 has 8 GPIOs with holes on 3, 4 and 6 */ 1274 { .compatible = "qcom,pm8937-gpio", .data = (void *) 8 }, 1275 { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 }, 1276 /* pm8950 has 8 GPIOs with holes on 3 */ 1277 { .compatible = "qcom,pm8950-gpio", .data = (void *) 8 }, 1278 /* pm8953 has 8 GPIOs with holes on 3 and 6 */ 1279 { .compatible = "qcom,pm8953-gpio", .data = (void *) 8 }, 1280 { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 }, 1281 { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 }, 1282 { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 }, 1283 { .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 }, 1284 { .compatible = "qcom,pmcx0102-gpio", .data = (void *)14 }, 1285 { .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 }, 1286 { .compatible = "qcom,pmg1110-gpio", .data = (void *) 4 }, 1287 { .compatible = "qcom,pmh0101-gpio", .data = (void *)18 }, 1288 { .compatible = "qcom,pmh0104-gpio", .data = (void *)8 }, 1289 { .compatible = "qcom,pmh0110-gpio", .data = (void *)14 }, 1290 { .compatible = "qcom,pmi632-gpio", .data = (void *) 8 }, 1291 { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 }, 1292 { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 }, 1293 { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, 1294 { .compatible = "qcom,pmih0108-gpio", .data = (void *) 18 }, 1295 { .compatible = "qcom,pmiv0104-gpio", .data = (void *) 10 }, 1296 { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, 1297 { .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 }, 1298 { .compatible = "qcom,pmk8850-gpio", .data = (void *)8 }, 1299 { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 }, 1300 { .compatible = "qcom,pmm8654au-gpio", .data = (void *) 12 }, 1301 /* pmp8074 has 12 GPIOs with holes on 1 and 12 */ 1302 { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 }, 1303 { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 }, 1304 { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 }, 1305 { .compatible = "qcom,pmr735d-gpio", .data = (void *) 2 }, 1306 /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */ 1307 { .compatible = "qcom,pms405-gpio", .data = (void *) 12 }, 1308 /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */ 1309 { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 }, 1310 { .compatible = "qcom,pmx65-gpio", .data = (void *) 16 }, 1311 { .compatible = "qcom,pmx75-gpio", .data = (void *) 16 }, 1312 { .compatible = "qcom,pmxr2230-gpio", .data = (void *) 12 }, 1313 { }, 1314 }; 1315 1316 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match); 1317 1318 static struct platform_driver pmic_gpio_driver = { 1319 .driver = { 1320 .name = "qcom-spmi-gpio", 1321 .of_match_table = pmic_gpio_of_match, 1322 }, 1323 .probe = pmic_gpio_probe, 1324 .remove = pmic_gpio_remove, 1325 }; 1326 1327 module_platform_driver(pmic_gpio_driver); 1328 1329 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); 1330 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver"); 1331 MODULE_ALIAS("platform:qcom-spmi-gpio"); 1332 MODULE_LICENSE("GPL v2"); 1333