1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wm8962.c -- WM8962 ALSA SoC Audio driver 4 * 5 * Copyright 2010-2 Wolfson Microelectronics plc 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/init.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/gcd.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/i2c.h> 19 #include <linux/input.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <linux/workqueue.h> 25 #include <linux/mutex.h> 26 #include <sound/core.h> 27 #include <sound/jack.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <sound/wm8962.h> 34 #include <trace/events/asoc.h> 35 36 #include "wm8962.h" 37 38 #define WM8962_NUM_SUPPLIES 8 39 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = { 40 "DCVDD", 41 "DBVDD", 42 "AVDD", 43 "CPVDD", 44 "MICVDD", 45 "PLLVDD", 46 "SPKVDD1", 47 "SPKVDD2", 48 }; 49 50 /* codec private data */ 51 struct wm8962_priv { 52 struct wm8962_pdata pdata; 53 struct regmap *regmap; 54 struct snd_soc_component *component; 55 56 int sysclk; 57 int sysclk_rate; 58 59 int bclk; /* Desired BCLK */ 60 int lrclk; 61 62 struct completion fll_lock; 63 int fll_src; 64 int fll_fref; 65 int fll_fout; 66 67 struct mutex dsp2_ena_lock; 68 u16 dsp2_ena; 69 70 int mic_status; 71 72 struct delayed_work mic_work; 73 struct snd_soc_jack *jack; 74 75 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES]; 76 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES]; 77 78 struct input_dev *beep; 79 struct work_struct beep_work; 80 int beep_rate; 81 82 #ifdef CONFIG_GPIOLIB 83 struct gpio_chip gpio_chip; 84 #endif 85 86 int irq; 87 bool master_flag; 88 int tdm_width; 89 int tdm_slots; 90 }; 91 92 /* We can't use the same notifier block for more than one supply and 93 * there's no way I can see to get from a callback to the caller 94 * except container_of(). 95 */ 96 #define WM8962_REGULATOR_EVENT(n) \ 97 static int wm8962_regulator_event_##n(struct notifier_block *nb, \ 98 unsigned long event, void *data) \ 99 { \ 100 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \ 101 disable_nb[n]); \ 102 if (event & REGULATOR_EVENT_DISABLE) { \ 103 regcache_mark_dirty(wm8962->regmap); \ 104 } \ 105 return 0; \ 106 } 107 108 WM8962_REGULATOR_EVENT(0) 109 WM8962_REGULATOR_EVENT(1) 110 WM8962_REGULATOR_EVENT(2) 111 WM8962_REGULATOR_EVENT(3) 112 WM8962_REGULATOR_EVENT(4) 113 WM8962_REGULATOR_EVENT(5) 114 WM8962_REGULATOR_EVENT(6) 115 WM8962_REGULATOR_EVENT(7) 116 117 static const struct reg_default wm8962_reg[] = { 118 { 0, 0x009F }, /* R0 - Left Input volume */ 119 { 1, 0x049F }, /* R1 - Right Input volume */ 120 { 2, 0x0000 }, /* R2 - HPOUTL volume */ 121 { 3, 0x0000 }, /* R3 - HPOUTR volume */ 122 123 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */ 124 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */ 125 { 7, 0x000A }, /* R7 - Audio Interface 0 */ 126 { 8, 0x01E4 }, /* R8 - Clocking2 */ 127 { 9, 0x0300 }, /* R9 - Audio Interface 1 */ 128 { 10, 0x00C0 }, /* R10 - Left DAC volume */ 129 { 11, 0x00C0 }, /* R11 - Right DAC volume */ 130 131 { 14, 0x0040 }, /* R14 - Audio Interface 2 */ 132 { 15, 0x6243 }, /* R15 - Software Reset */ 133 134 { 17, 0x007B }, /* R17 - ALC1 */ 135 { 18, 0x0000 }, /* R18 - ALC2 */ 136 { 19, 0x1C32 }, /* R19 - ALC3 */ 137 { 20, 0x3200 }, /* R20 - Noise Gate */ 138 { 21, 0x00C0 }, /* R21 - Left ADC volume */ 139 { 22, 0x00C0 }, /* R22 - Right ADC volume */ 140 { 23, 0x0160 }, /* R23 - Additional control(1) */ 141 { 24, 0x0000 }, /* R24 - Additional control(2) */ 142 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */ 143 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */ 144 { 27, 0x0010 }, /* R27 - Additional Control (3) */ 145 { 28, 0x0000 }, /* R28 - Anti-pop */ 146 147 { 30, 0x005E }, /* R30 - Clocking 3 */ 148 { 31, 0x0000 }, /* R31 - Input mixer control (1) */ 149 { 32, 0x0145 }, /* R32 - Left input mixer volume */ 150 { 33, 0x0145 }, /* R33 - Right input mixer volume */ 151 { 34, 0x0009 }, /* R34 - Input mixer control (2) */ 152 { 35, 0x0003 }, /* R35 - Input bias control */ 153 { 37, 0x0008 }, /* R37 - Left input PGA control */ 154 { 38, 0x0008 }, /* R38 - Right input PGA control */ 155 156 { 40, 0x0000 }, /* R40 - SPKOUTL volume */ 157 { 41, 0x0000 }, /* R41 - SPKOUTR volume */ 158 159 { 49, 0x0010 }, /* R49 - Class D Control 1 */ 160 { 51, 0x0003 }, /* R51 - Class D Control 2 */ 161 162 { 56, 0x0506 }, /* R56 - Clocking 4 */ 163 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */ 164 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */ 165 166 { 60, 0x0300 }, /* R60 - DC Servo 0 */ 167 { 61, 0x0300 }, /* R61 - DC Servo 1 */ 168 169 { 64, 0x0810 }, /* R64 - DC Servo 4 */ 170 171 { 68, 0x001B }, /* R68 - Analogue PGA Bias */ 172 { 69, 0x0000 }, /* R69 - Analogue HP 0 */ 173 174 { 71, 0x01FB }, /* R71 - Analogue HP 2 */ 175 { 72, 0x0000 }, /* R72 - Charge Pump 1 */ 176 177 { 82, 0x0004 }, /* R82 - Charge Pump B */ 178 179 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */ 180 181 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */ 182 183 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */ 184 { 94, 0x0000 }, /* R94 - Control Interface */ 185 186 { 99, 0x0000 }, /* R99 - Mixer Enables */ 187 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */ 188 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */ 189 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */ 190 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */ 191 192 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */ 193 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */ 194 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */ 195 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */ 196 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */ 197 { 110, 0x0002 }, /* R110 - Beep Generator (1) */ 198 199 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */ 200 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */ 201 202 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */ 203 204 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */ 205 { 125, 0x004B }, /* R125 - Analogue Clocking2 */ 206 { 126, 0x000D }, /* R126 - Analogue Clocking3 */ 207 { 127, 0x0000 }, /* R127 - PLL Software Reset */ 208 209 { 131, 0x0000 }, /* R131 - PLL 4 */ 210 211 { 136, 0x0067 }, /* R136 - PLL 9 */ 212 { 137, 0x001C }, /* R137 - PLL 10 */ 213 { 138, 0x0071 }, /* R138 - PLL 11 */ 214 { 139, 0x00C7 }, /* R139 - PLL 12 */ 215 { 140, 0x0067 }, /* R140 - PLL 13 */ 216 { 141, 0x0048 }, /* R141 - PLL 14 */ 217 { 142, 0x0022 }, /* R142 - PLL 15 */ 218 { 143, 0x0097 }, /* R143 - PLL 16 */ 219 220 { 155, 0x000C }, /* R155 - FLL Control (1) */ 221 { 156, 0x0039 }, /* R156 - FLL Control (2) */ 222 { 157, 0x0180 }, /* R157 - FLL Control (3) */ 223 224 { 159, 0x0032 }, /* R159 - FLL Control (5) */ 225 { 160, 0x0018 }, /* R160 - FLL Control (6) */ 226 { 161, 0x007D }, /* R161 - FLL Control (7) */ 227 { 162, 0x0008 }, /* R162 - FLL Control (8) */ 228 229 { 252, 0x0005 }, /* R252 - General test 1 */ 230 231 { 256, 0x0000 }, /* R256 - DF1 */ 232 { 257, 0x0000 }, /* R257 - DF2 */ 233 { 258, 0x0000 }, /* R258 - DF3 */ 234 { 259, 0x0000 }, /* R259 - DF4 */ 235 { 260, 0x0000 }, /* R260 - DF5 */ 236 { 261, 0x0000 }, /* R261 - DF6 */ 237 { 262, 0x0000 }, /* R262 - DF7 */ 238 239 { 264, 0x0000 }, /* R264 - LHPF1 */ 240 { 265, 0x0000 }, /* R265 - LHPF2 */ 241 242 { 268, 0x0000 }, /* R268 - THREED1 */ 243 { 269, 0x0000 }, /* R269 - THREED2 */ 244 { 270, 0x0000 }, /* R270 - THREED3 */ 245 { 271, 0x0000 }, /* R271 - THREED4 */ 246 247 { 276, 0x000C }, /* R276 - DRC 1 */ 248 { 277, 0x0925 }, /* R277 - DRC 2 */ 249 { 278, 0x0000 }, /* R278 - DRC 3 */ 250 { 279, 0x0000 }, /* R279 - DRC 4 */ 251 { 280, 0x0000 }, /* R280 - DRC 5 */ 252 253 { 285, 0x0000 }, /* R285 - Tloopback */ 254 255 { 335, 0x0004 }, /* R335 - EQ1 */ 256 { 336, 0x6318 }, /* R336 - EQ2 */ 257 { 337, 0x6300 }, /* R337 - EQ3 */ 258 { 338, 0x0FCA }, /* R338 - EQ4 */ 259 { 339, 0x0400 }, /* R339 - EQ5 */ 260 { 340, 0x00D8 }, /* R340 - EQ6 */ 261 { 341, 0x1EB5 }, /* R341 - EQ7 */ 262 { 342, 0xF145 }, /* R342 - EQ8 */ 263 { 343, 0x0B75 }, /* R343 - EQ9 */ 264 { 344, 0x01C5 }, /* R344 - EQ10 */ 265 { 345, 0x1C58 }, /* R345 - EQ11 */ 266 { 346, 0xF373 }, /* R346 - EQ12 */ 267 { 347, 0x0A54 }, /* R347 - EQ13 */ 268 { 348, 0x0558 }, /* R348 - EQ14 */ 269 { 349, 0x168E }, /* R349 - EQ15 */ 270 { 350, 0xF829 }, /* R350 - EQ16 */ 271 { 351, 0x07AD }, /* R351 - EQ17 */ 272 { 352, 0x1103 }, /* R352 - EQ18 */ 273 { 353, 0x0564 }, /* R353 - EQ19 */ 274 { 354, 0x0559 }, /* R354 - EQ20 */ 275 { 355, 0x4000 }, /* R355 - EQ21 */ 276 { 356, 0x6318 }, /* R356 - EQ22 */ 277 { 357, 0x6300 }, /* R357 - EQ23 */ 278 { 358, 0x0FCA }, /* R358 - EQ24 */ 279 { 359, 0x0400 }, /* R359 - EQ25 */ 280 { 360, 0x00D8 }, /* R360 - EQ26 */ 281 { 361, 0x1EB5 }, /* R361 - EQ27 */ 282 { 362, 0xF145 }, /* R362 - EQ28 */ 283 { 363, 0x0B75 }, /* R363 - EQ29 */ 284 { 364, 0x01C5 }, /* R364 - EQ30 */ 285 { 365, 0x1C58 }, /* R365 - EQ31 */ 286 { 366, 0xF373 }, /* R366 - EQ32 */ 287 { 367, 0x0A54 }, /* R367 - EQ33 */ 288 { 368, 0x0558 }, /* R368 - EQ34 */ 289 { 369, 0x168E }, /* R369 - EQ35 */ 290 { 370, 0xF829 }, /* R370 - EQ36 */ 291 { 371, 0x07AD }, /* R371 - EQ37 */ 292 { 372, 0x1103 }, /* R372 - EQ38 */ 293 { 373, 0x0564 }, /* R373 - EQ39 */ 294 { 374, 0x0559 }, /* R374 - EQ40 */ 295 { 375, 0x4000 }, /* R375 - EQ41 */ 296 297 { 513, 0x0000 }, /* R513 - GPIO 2 */ 298 { 514, 0x0000 }, /* R514 - GPIO 3 */ 299 300 { 516, 0x8100 }, /* R516 - GPIO 5 */ 301 { 517, 0x8100 }, /* R517 - GPIO 6 */ 302 303 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */ 304 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */ 305 306 { 576, 0x0000 }, /* R576 - Interrupt Control */ 307 308 { 584, 0x002D }, /* R584 - IRQ Debounce */ 309 310 { 586, 0x0000 }, /* R586 - MICINT Source Pol */ 311 312 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */ 313 314 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */ 315 316 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */ 317 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */ 318 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */ 319 320 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */ 321 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */ 322 323 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */ 324 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */ 325 326 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */ 327 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */ 328 329 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */ 330 331 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */ 332 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */ 333 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */ 334 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */ 335 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */ 336 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */ 337 338 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */ 339 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */ 340 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */ 341 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */ 342 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */ 343 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */ 344 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */ 345 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */ 346 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */ 347 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */ 348 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */ 349 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */ 350 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */ 351 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */ 352 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */ 353 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */ 354 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */ 355 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */ 356 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */ 357 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */ 358 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */ 359 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */ 360 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */ 361 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */ 362 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */ 363 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */ 364 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */ 365 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */ 366 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */ 367 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */ 368 369 { 17408, 0x0083 }, /* R17408 - HPF_C_1 */ 370 { 17409, 0x98AD }, /* R17409 - HPF_C_0 */ 371 372 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */ 373 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */ 374 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */ 375 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */ 376 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */ 377 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */ 378 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */ 379 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */ 380 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */ 381 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */ 382 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */ 383 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */ 384 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */ 385 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */ 386 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */ 387 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */ 388 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */ 389 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */ 390 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */ 391 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */ 392 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */ 393 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */ 394 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */ 395 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */ 396 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */ 397 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */ 398 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */ 399 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */ 400 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */ 401 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */ 402 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */ 403 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */ 404 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */ 405 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */ 406 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */ 407 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */ 408 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */ 409 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */ 410 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */ 411 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */ 412 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */ 413 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */ 414 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */ 415 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */ 416 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */ 417 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */ 418 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */ 419 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */ 420 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */ 421 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */ 422 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */ 423 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */ 424 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */ 425 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */ 426 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */ 427 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */ 428 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */ 429 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */ 430 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */ 431 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */ 432 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */ 433 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */ 434 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */ 435 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */ 436 437 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */ 438 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */ 439 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */ 440 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */ 441 442 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */ 443 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */ 444 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */ 445 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */ 446 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */ 447 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */ 448 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */ 449 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */ 450 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */ 451 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */ 452 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */ 453 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */ 454 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */ 455 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */ 456 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */ 457 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */ 458 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */ 459 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */ 460 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */ 461 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */ 462 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */ 463 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */ 464 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */ 465 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */ 466 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */ 467 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */ 468 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */ 469 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */ 470 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */ 471 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */ 472 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */ 473 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */ 474 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */ 475 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */ 476 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */ 477 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */ 478 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */ 479 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */ 480 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */ 481 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */ 482 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */ 483 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */ 484 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */ 485 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */ 486 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */ 487 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */ 488 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */ 489 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */ 490 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */ 491 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */ 492 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */ 493 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */ 494 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */ 495 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */ 496 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */ 497 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */ 498 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */ 499 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */ 500 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */ 501 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */ 502 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */ 503 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */ 504 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */ 505 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */ 506 507 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */ 508 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */ 509 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */ 510 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */ 511 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */ 512 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */ 513 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */ 514 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */ 515 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */ 516 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */ 517 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */ 518 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */ 519 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */ 520 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */ 521 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */ 522 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */ 523 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */ 524 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */ 525 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */ 526 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */ 527 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */ 528 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */ 529 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */ 530 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */ 531 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */ 532 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */ 533 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */ 534 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */ 535 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */ 536 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */ 537 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */ 538 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */ 539 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */ 540 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */ 541 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */ 542 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */ 543 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */ 544 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */ 545 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */ 546 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */ 547 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */ 548 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */ 549 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */ 550 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */ 551 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */ 552 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */ 553 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */ 554 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */ 555 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */ 556 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */ 557 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */ 558 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */ 559 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */ 560 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */ 561 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */ 562 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */ 563 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */ 564 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */ 565 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */ 566 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */ 567 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */ 568 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */ 569 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */ 570 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */ 571 572 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */ 573 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */ 574 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */ 575 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */ 576 577 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */ 578 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */ 579 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */ 580 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */ 581 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */ 582 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */ 583 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */ 584 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */ 585 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */ 586 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */ 587 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */ 588 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */ 589 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */ 590 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */ 591 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */ 592 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */ 593 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */ 594 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */ 595 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */ 596 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */ 597 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */ 598 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */ 599 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */ 600 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */ 601 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */ 602 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */ 603 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */ 604 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */ 605 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */ 606 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */ 607 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */ 608 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */ 609 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */ 610 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */ 611 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */ 612 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */ 613 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */ 614 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */ 615 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */ 616 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */ 617 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */ 618 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */ 619 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */ 620 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */ 621 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */ 622 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */ 623 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */ 624 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */ 625 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */ 626 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */ 627 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */ 628 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */ 629 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */ 630 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */ 631 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */ 632 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */ 633 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */ 634 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */ 635 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */ 636 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */ 637 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */ 638 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */ 639 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */ 640 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */ 641 642 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */ 643 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */ 644 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */ 645 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */ 646 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */ 647 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */ 648 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */ 649 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */ 650 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */ 651 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */ 652 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */ 653 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */ 654 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */ 655 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */ 656 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */ 657 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */ 658 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */ 659 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */ 660 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */ 661 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */ 662 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */ 663 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */ 664 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */ 665 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */ 666 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */ 667 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */ 668 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */ 669 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */ 670 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */ 671 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */ 672 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */ 673 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */ 674 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */ 675 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */ 676 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */ 677 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */ 678 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */ 679 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */ 680 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */ 681 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */ 682 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */ 683 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */ 684 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */ 685 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */ 686 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */ 687 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */ 688 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */ 689 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */ 690 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */ 691 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */ 692 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */ 693 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */ 694 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */ 695 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */ 696 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */ 697 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */ 698 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */ 699 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */ 700 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */ 701 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */ 702 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */ 703 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */ 704 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */ 705 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */ 706 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */ 707 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */ 708 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */ 709 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */ 710 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */ 711 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */ 712 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */ 713 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */ 714 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */ 715 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */ 716 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */ 717 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */ 718 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */ 719 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */ 720 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */ 721 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */ 722 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */ 723 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */ 724 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */ 725 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */ 726 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */ 727 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */ 728 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */ 729 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */ 730 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */ 731 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */ 732 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */ 733 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */ 734 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */ 735 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */ 736 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */ 737 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */ 738 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */ 739 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */ 740 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */ 741 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */ 742 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */ 743 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */ 744 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */ 745 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */ 746 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */ 747 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */ 748 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */ 749 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */ 750 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */ 751 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */ 752 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */ 753 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */ 754 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */ 755 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */ 756 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */ 757 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */ 758 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */ 759 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */ 760 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */ 761 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */ 762 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */ 763 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */ 764 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */ 765 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */ 766 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */ 767 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */ 768 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */ 769 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */ 770 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */ 771 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */ 772 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */ 773 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */ 774 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */ 775 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */ 776 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */ 777 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */ 778 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */ 779 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */ 780 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */ 781 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */ 782 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */ 783 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */ 784 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */ 785 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */ 786 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */ 787 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */ 788 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */ 789 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */ 790 }; 791 792 static bool wm8962_volatile_register(struct device *dev, unsigned int reg) 793 { 794 switch (reg) { 795 case WM8962_CLOCKING1: 796 case WM8962_SOFTWARE_RESET: 797 case WM8962_THERMAL_SHUTDOWN_STATUS: 798 case WM8962_ADDITIONAL_CONTROL_4: 799 case WM8962_DC_SERVO_6: 800 case WM8962_INTERRUPT_STATUS_1: 801 case WM8962_INTERRUPT_STATUS_2: 802 case WM8962_DSP2_EXECCONTROL: 803 return true; 804 default: 805 return false; 806 } 807 } 808 809 static bool wm8962_readable_register(struct device *dev, unsigned int reg) 810 { 811 switch (reg) { 812 case WM8962_LEFT_INPUT_VOLUME: 813 case WM8962_RIGHT_INPUT_VOLUME: 814 case WM8962_HPOUTL_VOLUME: 815 case WM8962_HPOUTR_VOLUME: 816 case WM8962_CLOCKING1: 817 case WM8962_ADC_DAC_CONTROL_1: 818 case WM8962_ADC_DAC_CONTROL_2: 819 case WM8962_AUDIO_INTERFACE_0: 820 case WM8962_CLOCKING2: 821 case WM8962_AUDIO_INTERFACE_1: 822 case WM8962_LEFT_DAC_VOLUME: 823 case WM8962_RIGHT_DAC_VOLUME: 824 case WM8962_AUDIO_INTERFACE_2: 825 case WM8962_SOFTWARE_RESET: 826 case WM8962_ALC1: 827 case WM8962_ALC2: 828 case WM8962_ALC3: 829 case WM8962_NOISE_GATE: 830 case WM8962_LEFT_ADC_VOLUME: 831 case WM8962_RIGHT_ADC_VOLUME: 832 case WM8962_ADDITIONAL_CONTROL_1: 833 case WM8962_ADDITIONAL_CONTROL_2: 834 case WM8962_PWR_MGMT_1: 835 case WM8962_PWR_MGMT_2: 836 case WM8962_ADDITIONAL_CONTROL_3: 837 case WM8962_ANTI_POP: 838 case WM8962_CLOCKING_3: 839 case WM8962_INPUT_MIXER_CONTROL_1: 840 case WM8962_LEFT_INPUT_MIXER_VOLUME: 841 case WM8962_RIGHT_INPUT_MIXER_VOLUME: 842 case WM8962_INPUT_MIXER_CONTROL_2: 843 case WM8962_INPUT_BIAS_CONTROL: 844 case WM8962_LEFT_INPUT_PGA_CONTROL: 845 case WM8962_RIGHT_INPUT_PGA_CONTROL: 846 case WM8962_SPKOUTL_VOLUME: 847 case WM8962_SPKOUTR_VOLUME: 848 case WM8962_THERMAL_SHUTDOWN_STATUS: 849 case WM8962_ADDITIONAL_CONTROL_4: 850 case WM8962_CLASS_D_CONTROL_1: 851 case WM8962_CLASS_D_CONTROL_2: 852 case WM8962_CLOCKING_4: 853 case WM8962_DAC_DSP_MIXING_1: 854 case WM8962_DAC_DSP_MIXING_2: 855 case WM8962_DC_SERVO_0: 856 case WM8962_DC_SERVO_1: 857 case WM8962_DC_SERVO_4: 858 case WM8962_DC_SERVO_6: 859 case WM8962_ANALOGUE_PGA_BIAS: 860 case WM8962_ANALOGUE_HP_0: 861 case WM8962_ANALOGUE_HP_2: 862 case WM8962_CHARGE_PUMP_1: 863 case WM8962_CHARGE_PUMP_B: 864 case WM8962_WRITE_SEQUENCER_CONTROL_1: 865 case WM8962_WRITE_SEQUENCER_CONTROL_2: 866 case WM8962_WRITE_SEQUENCER_CONTROL_3: 867 case WM8962_CONTROL_INTERFACE: 868 case WM8962_MIXER_ENABLES: 869 case WM8962_HEADPHONE_MIXER_1: 870 case WM8962_HEADPHONE_MIXER_2: 871 case WM8962_HEADPHONE_MIXER_3: 872 case WM8962_HEADPHONE_MIXER_4: 873 case WM8962_SPEAKER_MIXER_1: 874 case WM8962_SPEAKER_MIXER_2: 875 case WM8962_SPEAKER_MIXER_3: 876 case WM8962_SPEAKER_MIXER_4: 877 case WM8962_SPEAKER_MIXER_5: 878 case WM8962_BEEP_GENERATOR_1: 879 case WM8962_OSCILLATOR_TRIM_3: 880 case WM8962_OSCILLATOR_TRIM_4: 881 case WM8962_OSCILLATOR_TRIM_7: 882 case WM8962_ANALOGUE_CLOCKING1: 883 case WM8962_ANALOGUE_CLOCKING2: 884 case WM8962_ANALOGUE_CLOCKING3: 885 case WM8962_PLL_SOFTWARE_RESET: 886 case WM8962_PLL2: 887 case WM8962_PLL_4: 888 case WM8962_PLL_9: 889 case WM8962_PLL_10: 890 case WM8962_PLL_11: 891 case WM8962_PLL_12: 892 case WM8962_PLL_13: 893 case WM8962_PLL_14: 894 case WM8962_PLL_15: 895 case WM8962_PLL_16: 896 case WM8962_FLL_CONTROL_1: 897 case WM8962_FLL_CONTROL_2: 898 case WM8962_FLL_CONTROL_3: 899 case WM8962_FLL_CONTROL_5: 900 case WM8962_FLL_CONTROL_6: 901 case WM8962_FLL_CONTROL_7: 902 case WM8962_FLL_CONTROL_8: 903 case WM8962_GENERAL_TEST_1: 904 case WM8962_DF1: 905 case WM8962_DF2: 906 case WM8962_DF3: 907 case WM8962_DF4: 908 case WM8962_DF5: 909 case WM8962_DF6: 910 case WM8962_DF7: 911 case WM8962_LHPF1: 912 case WM8962_LHPF2: 913 case WM8962_THREED1: 914 case WM8962_THREED2: 915 case WM8962_THREED3: 916 case WM8962_THREED4: 917 case WM8962_DRC_1: 918 case WM8962_DRC_2: 919 case WM8962_DRC_3: 920 case WM8962_DRC_4: 921 case WM8962_DRC_5: 922 case WM8962_TLOOPBACK: 923 case WM8962_EQ1: 924 case WM8962_EQ2: 925 case WM8962_EQ3: 926 case WM8962_EQ4: 927 case WM8962_EQ5: 928 case WM8962_EQ6: 929 case WM8962_EQ7: 930 case WM8962_EQ8: 931 case WM8962_EQ9: 932 case WM8962_EQ10: 933 case WM8962_EQ11: 934 case WM8962_EQ12: 935 case WM8962_EQ13: 936 case WM8962_EQ14: 937 case WM8962_EQ15: 938 case WM8962_EQ16: 939 case WM8962_EQ17: 940 case WM8962_EQ18: 941 case WM8962_EQ19: 942 case WM8962_EQ20: 943 case WM8962_EQ21: 944 case WM8962_EQ22: 945 case WM8962_EQ23: 946 case WM8962_EQ24: 947 case WM8962_EQ25: 948 case WM8962_EQ26: 949 case WM8962_EQ27: 950 case WM8962_EQ28: 951 case WM8962_EQ29: 952 case WM8962_EQ30: 953 case WM8962_EQ31: 954 case WM8962_EQ32: 955 case WM8962_EQ33: 956 case WM8962_EQ34: 957 case WM8962_EQ35: 958 case WM8962_EQ36: 959 case WM8962_EQ37: 960 case WM8962_EQ38: 961 case WM8962_EQ39: 962 case WM8962_EQ40: 963 case WM8962_EQ41: 964 case WM8962_GPIO_2: 965 case WM8962_GPIO_3: 966 case WM8962_GPIO_5: 967 case WM8962_GPIO_6: 968 case WM8962_INTERRUPT_STATUS_1: 969 case WM8962_INTERRUPT_STATUS_2: 970 case WM8962_INTERRUPT_STATUS_1_MASK: 971 case WM8962_INTERRUPT_STATUS_2_MASK: 972 case WM8962_INTERRUPT_CONTROL: 973 case WM8962_IRQ_DEBOUNCE: 974 case WM8962_MICINT_SOURCE_POL: 975 case WM8962_DSP2_POWER_MANAGEMENT: 976 case WM8962_DSP2_EXECCONTROL: 977 case WM8962_DSP2_INSTRUCTION_RAM_0: 978 case WM8962_DSP2_ADDRESS_RAM_2: 979 case WM8962_DSP2_ADDRESS_RAM_1: 980 case WM8962_DSP2_ADDRESS_RAM_0: 981 case WM8962_DSP2_DATA1_RAM_1: 982 case WM8962_DSP2_DATA1_RAM_0: 983 case WM8962_DSP2_DATA2_RAM_1: 984 case WM8962_DSP2_DATA2_RAM_0: 985 case WM8962_DSP2_DATA3_RAM_1: 986 case WM8962_DSP2_DATA3_RAM_0: 987 case WM8962_DSP2_COEFF_RAM_0: 988 case WM8962_RETUNEADC_SHARED_COEFF_1: 989 case WM8962_RETUNEADC_SHARED_COEFF_0: 990 case WM8962_RETUNEDAC_SHARED_COEFF_1: 991 case WM8962_RETUNEDAC_SHARED_COEFF_0: 992 case WM8962_SOUNDSTAGE_ENABLES_1: 993 case WM8962_SOUNDSTAGE_ENABLES_0: 994 case WM8962_HDBASS_AI_1: 995 case WM8962_HDBASS_AI_0: 996 case WM8962_HDBASS_AR_1: 997 case WM8962_HDBASS_AR_0: 998 case WM8962_HDBASS_B_1: 999 case WM8962_HDBASS_B_0: 1000 case WM8962_HDBASS_K_1: 1001 case WM8962_HDBASS_K_0: 1002 case WM8962_HDBASS_N1_1: 1003 case WM8962_HDBASS_N1_0: 1004 case WM8962_HDBASS_N2_1: 1005 case WM8962_HDBASS_N2_0: 1006 case WM8962_HDBASS_N3_1: 1007 case WM8962_HDBASS_N3_0: 1008 case WM8962_HDBASS_N4_1: 1009 case WM8962_HDBASS_N4_0: 1010 case WM8962_HDBASS_N5_1: 1011 case WM8962_HDBASS_N5_0: 1012 case WM8962_HDBASS_X1_1: 1013 case WM8962_HDBASS_X1_0: 1014 case WM8962_HDBASS_X2_1: 1015 case WM8962_HDBASS_X2_0: 1016 case WM8962_HDBASS_X3_1: 1017 case WM8962_HDBASS_X3_0: 1018 case WM8962_HDBASS_ATK_1: 1019 case WM8962_HDBASS_ATK_0: 1020 case WM8962_HDBASS_DCY_1: 1021 case WM8962_HDBASS_DCY_0: 1022 case WM8962_HDBASS_PG_1: 1023 case WM8962_HDBASS_PG_0: 1024 case WM8962_HPF_C_1: 1025 case WM8962_HPF_C_0: 1026 case WM8962_ADCL_RETUNE_C1_1: 1027 case WM8962_ADCL_RETUNE_C1_0: 1028 case WM8962_ADCL_RETUNE_C2_1: 1029 case WM8962_ADCL_RETUNE_C2_0: 1030 case WM8962_ADCL_RETUNE_C3_1: 1031 case WM8962_ADCL_RETUNE_C3_0: 1032 case WM8962_ADCL_RETUNE_C4_1: 1033 case WM8962_ADCL_RETUNE_C4_0: 1034 case WM8962_ADCL_RETUNE_C5_1: 1035 case WM8962_ADCL_RETUNE_C5_0: 1036 case WM8962_ADCL_RETUNE_C6_1: 1037 case WM8962_ADCL_RETUNE_C6_0: 1038 case WM8962_ADCL_RETUNE_C7_1: 1039 case WM8962_ADCL_RETUNE_C7_0: 1040 case WM8962_ADCL_RETUNE_C8_1: 1041 case WM8962_ADCL_RETUNE_C8_0: 1042 case WM8962_ADCL_RETUNE_C9_1: 1043 case WM8962_ADCL_RETUNE_C9_0: 1044 case WM8962_ADCL_RETUNE_C10_1: 1045 case WM8962_ADCL_RETUNE_C10_0: 1046 case WM8962_ADCL_RETUNE_C11_1: 1047 case WM8962_ADCL_RETUNE_C11_0: 1048 case WM8962_ADCL_RETUNE_C12_1: 1049 case WM8962_ADCL_RETUNE_C12_0: 1050 case WM8962_ADCL_RETUNE_C13_1: 1051 case WM8962_ADCL_RETUNE_C13_0: 1052 case WM8962_ADCL_RETUNE_C14_1: 1053 case WM8962_ADCL_RETUNE_C14_0: 1054 case WM8962_ADCL_RETUNE_C15_1: 1055 case WM8962_ADCL_RETUNE_C15_0: 1056 case WM8962_ADCL_RETUNE_C16_1: 1057 case WM8962_ADCL_RETUNE_C16_0: 1058 case WM8962_ADCL_RETUNE_C17_1: 1059 case WM8962_ADCL_RETUNE_C17_0: 1060 case WM8962_ADCL_RETUNE_C18_1: 1061 case WM8962_ADCL_RETUNE_C18_0: 1062 case WM8962_ADCL_RETUNE_C19_1: 1063 case WM8962_ADCL_RETUNE_C19_0: 1064 case WM8962_ADCL_RETUNE_C20_1: 1065 case WM8962_ADCL_RETUNE_C20_0: 1066 case WM8962_ADCL_RETUNE_C21_1: 1067 case WM8962_ADCL_RETUNE_C21_0: 1068 case WM8962_ADCL_RETUNE_C22_1: 1069 case WM8962_ADCL_RETUNE_C22_0: 1070 case WM8962_ADCL_RETUNE_C23_1: 1071 case WM8962_ADCL_RETUNE_C23_0: 1072 case WM8962_ADCL_RETUNE_C24_1: 1073 case WM8962_ADCL_RETUNE_C24_0: 1074 case WM8962_ADCL_RETUNE_C25_1: 1075 case WM8962_ADCL_RETUNE_C25_0: 1076 case WM8962_ADCL_RETUNE_C26_1: 1077 case WM8962_ADCL_RETUNE_C26_0: 1078 case WM8962_ADCL_RETUNE_C27_1: 1079 case WM8962_ADCL_RETUNE_C27_0: 1080 case WM8962_ADCL_RETUNE_C28_1: 1081 case WM8962_ADCL_RETUNE_C28_0: 1082 case WM8962_ADCL_RETUNE_C29_1: 1083 case WM8962_ADCL_RETUNE_C29_0: 1084 case WM8962_ADCL_RETUNE_C30_1: 1085 case WM8962_ADCL_RETUNE_C30_0: 1086 case WM8962_ADCL_RETUNE_C31_1: 1087 case WM8962_ADCL_RETUNE_C31_0: 1088 case WM8962_ADCL_RETUNE_C32_1: 1089 case WM8962_ADCL_RETUNE_C32_0: 1090 case WM8962_RETUNEADC_PG2_1: 1091 case WM8962_RETUNEADC_PG2_0: 1092 case WM8962_RETUNEADC_PG_1: 1093 case WM8962_RETUNEADC_PG_0: 1094 case WM8962_ADCR_RETUNE_C1_1: 1095 case WM8962_ADCR_RETUNE_C1_0: 1096 case WM8962_ADCR_RETUNE_C2_1: 1097 case WM8962_ADCR_RETUNE_C2_0: 1098 case WM8962_ADCR_RETUNE_C3_1: 1099 case WM8962_ADCR_RETUNE_C3_0: 1100 case WM8962_ADCR_RETUNE_C4_1: 1101 case WM8962_ADCR_RETUNE_C4_0: 1102 case WM8962_ADCR_RETUNE_C5_1: 1103 case WM8962_ADCR_RETUNE_C5_0: 1104 case WM8962_ADCR_RETUNE_C6_1: 1105 case WM8962_ADCR_RETUNE_C6_0: 1106 case WM8962_ADCR_RETUNE_C7_1: 1107 case WM8962_ADCR_RETUNE_C7_0: 1108 case WM8962_ADCR_RETUNE_C8_1: 1109 case WM8962_ADCR_RETUNE_C8_0: 1110 case WM8962_ADCR_RETUNE_C9_1: 1111 case WM8962_ADCR_RETUNE_C9_0: 1112 case WM8962_ADCR_RETUNE_C10_1: 1113 case WM8962_ADCR_RETUNE_C10_0: 1114 case WM8962_ADCR_RETUNE_C11_1: 1115 case WM8962_ADCR_RETUNE_C11_0: 1116 case WM8962_ADCR_RETUNE_C12_1: 1117 case WM8962_ADCR_RETUNE_C12_0: 1118 case WM8962_ADCR_RETUNE_C13_1: 1119 case WM8962_ADCR_RETUNE_C13_0: 1120 case WM8962_ADCR_RETUNE_C14_1: 1121 case WM8962_ADCR_RETUNE_C14_0: 1122 case WM8962_ADCR_RETUNE_C15_1: 1123 case WM8962_ADCR_RETUNE_C15_0: 1124 case WM8962_ADCR_RETUNE_C16_1: 1125 case WM8962_ADCR_RETUNE_C16_0: 1126 case WM8962_ADCR_RETUNE_C17_1: 1127 case WM8962_ADCR_RETUNE_C17_0: 1128 case WM8962_ADCR_RETUNE_C18_1: 1129 case WM8962_ADCR_RETUNE_C18_0: 1130 case WM8962_ADCR_RETUNE_C19_1: 1131 case WM8962_ADCR_RETUNE_C19_0: 1132 case WM8962_ADCR_RETUNE_C20_1: 1133 case WM8962_ADCR_RETUNE_C20_0: 1134 case WM8962_ADCR_RETUNE_C21_1: 1135 case WM8962_ADCR_RETUNE_C21_0: 1136 case WM8962_ADCR_RETUNE_C22_1: 1137 case WM8962_ADCR_RETUNE_C22_0: 1138 case WM8962_ADCR_RETUNE_C23_1: 1139 case WM8962_ADCR_RETUNE_C23_0: 1140 case WM8962_ADCR_RETUNE_C24_1: 1141 case WM8962_ADCR_RETUNE_C24_0: 1142 case WM8962_ADCR_RETUNE_C25_1: 1143 case WM8962_ADCR_RETUNE_C25_0: 1144 case WM8962_ADCR_RETUNE_C26_1: 1145 case WM8962_ADCR_RETUNE_C26_0: 1146 case WM8962_ADCR_RETUNE_C27_1: 1147 case WM8962_ADCR_RETUNE_C27_0: 1148 case WM8962_ADCR_RETUNE_C28_1: 1149 case WM8962_ADCR_RETUNE_C28_0: 1150 case WM8962_ADCR_RETUNE_C29_1: 1151 case WM8962_ADCR_RETUNE_C29_0: 1152 case WM8962_ADCR_RETUNE_C30_1: 1153 case WM8962_ADCR_RETUNE_C30_0: 1154 case WM8962_ADCR_RETUNE_C31_1: 1155 case WM8962_ADCR_RETUNE_C31_0: 1156 case WM8962_ADCR_RETUNE_C32_1: 1157 case WM8962_ADCR_RETUNE_C32_0: 1158 case WM8962_DACL_RETUNE_C1_1: 1159 case WM8962_DACL_RETUNE_C1_0: 1160 case WM8962_DACL_RETUNE_C2_1: 1161 case WM8962_DACL_RETUNE_C2_0: 1162 case WM8962_DACL_RETUNE_C3_1: 1163 case WM8962_DACL_RETUNE_C3_0: 1164 case WM8962_DACL_RETUNE_C4_1: 1165 case WM8962_DACL_RETUNE_C4_0: 1166 case WM8962_DACL_RETUNE_C5_1: 1167 case WM8962_DACL_RETUNE_C5_0: 1168 case WM8962_DACL_RETUNE_C6_1: 1169 case WM8962_DACL_RETUNE_C6_0: 1170 case WM8962_DACL_RETUNE_C7_1: 1171 case WM8962_DACL_RETUNE_C7_0: 1172 case WM8962_DACL_RETUNE_C8_1: 1173 case WM8962_DACL_RETUNE_C8_0: 1174 case WM8962_DACL_RETUNE_C9_1: 1175 case WM8962_DACL_RETUNE_C9_0: 1176 case WM8962_DACL_RETUNE_C10_1: 1177 case WM8962_DACL_RETUNE_C10_0: 1178 case WM8962_DACL_RETUNE_C11_1: 1179 case WM8962_DACL_RETUNE_C11_0: 1180 case WM8962_DACL_RETUNE_C12_1: 1181 case WM8962_DACL_RETUNE_C12_0: 1182 case WM8962_DACL_RETUNE_C13_1: 1183 case WM8962_DACL_RETUNE_C13_0: 1184 case WM8962_DACL_RETUNE_C14_1: 1185 case WM8962_DACL_RETUNE_C14_0: 1186 case WM8962_DACL_RETUNE_C15_1: 1187 case WM8962_DACL_RETUNE_C15_0: 1188 case WM8962_DACL_RETUNE_C16_1: 1189 case WM8962_DACL_RETUNE_C16_0: 1190 case WM8962_DACL_RETUNE_C17_1: 1191 case WM8962_DACL_RETUNE_C17_0: 1192 case WM8962_DACL_RETUNE_C18_1: 1193 case WM8962_DACL_RETUNE_C18_0: 1194 case WM8962_DACL_RETUNE_C19_1: 1195 case WM8962_DACL_RETUNE_C19_0: 1196 case WM8962_DACL_RETUNE_C20_1: 1197 case WM8962_DACL_RETUNE_C20_0: 1198 case WM8962_DACL_RETUNE_C21_1: 1199 case WM8962_DACL_RETUNE_C21_0: 1200 case WM8962_DACL_RETUNE_C22_1: 1201 case WM8962_DACL_RETUNE_C22_0: 1202 case WM8962_DACL_RETUNE_C23_1: 1203 case WM8962_DACL_RETUNE_C23_0: 1204 case WM8962_DACL_RETUNE_C24_1: 1205 case WM8962_DACL_RETUNE_C24_0: 1206 case WM8962_DACL_RETUNE_C25_1: 1207 case WM8962_DACL_RETUNE_C25_0: 1208 case WM8962_DACL_RETUNE_C26_1: 1209 case WM8962_DACL_RETUNE_C26_0: 1210 case WM8962_DACL_RETUNE_C27_1: 1211 case WM8962_DACL_RETUNE_C27_0: 1212 case WM8962_DACL_RETUNE_C28_1: 1213 case WM8962_DACL_RETUNE_C28_0: 1214 case WM8962_DACL_RETUNE_C29_1: 1215 case WM8962_DACL_RETUNE_C29_0: 1216 case WM8962_DACL_RETUNE_C30_1: 1217 case WM8962_DACL_RETUNE_C30_0: 1218 case WM8962_DACL_RETUNE_C31_1: 1219 case WM8962_DACL_RETUNE_C31_0: 1220 case WM8962_DACL_RETUNE_C32_1: 1221 case WM8962_DACL_RETUNE_C32_0: 1222 case WM8962_RETUNEDAC_PG2_1: 1223 case WM8962_RETUNEDAC_PG2_0: 1224 case WM8962_RETUNEDAC_PG_1: 1225 case WM8962_RETUNEDAC_PG_0: 1226 case WM8962_DACR_RETUNE_C1_1: 1227 case WM8962_DACR_RETUNE_C1_0: 1228 case WM8962_DACR_RETUNE_C2_1: 1229 case WM8962_DACR_RETUNE_C2_0: 1230 case WM8962_DACR_RETUNE_C3_1: 1231 case WM8962_DACR_RETUNE_C3_0: 1232 case WM8962_DACR_RETUNE_C4_1: 1233 case WM8962_DACR_RETUNE_C4_0: 1234 case WM8962_DACR_RETUNE_C5_1: 1235 case WM8962_DACR_RETUNE_C5_0: 1236 case WM8962_DACR_RETUNE_C6_1: 1237 case WM8962_DACR_RETUNE_C6_0: 1238 case WM8962_DACR_RETUNE_C7_1: 1239 case WM8962_DACR_RETUNE_C7_0: 1240 case WM8962_DACR_RETUNE_C8_1: 1241 case WM8962_DACR_RETUNE_C8_0: 1242 case WM8962_DACR_RETUNE_C9_1: 1243 case WM8962_DACR_RETUNE_C9_0: 1244 case WM8962_DACR_RETUNE_C10_1: 1245 case WM8962_DACR_RETUNE_C10_0: 1246 case WM8962_DACR_RETUNE_C11_1: 1247 case WM8962_DACR_RETUNE_C11_0: 1248 case WM8962_DACR_RETUNE_C12_1: 1249 case WM8962_DACR_RETUNE_C12_0: 1250 case WM8962_DACR_RETUNE_C13_1: 1251 case WM8962_DACR_RETUNE_C13_0: 1252 case WM8962_DACR_RETUNE_C14_1: 1253 case WM8962_DACR_RETUNE_C14_0: 1254 case WM8962_DACR_RETUNE_C15_1: 1255 case WM8962_DACR_RETUNE_C15_0: 1256 case WM8962_DACR_RETUNE_C16_1: 1257 case WM8962_DACR_RETUNE_C16_0: 1258 case WM8962_DACR_RETUNE_C17_1: 1259 case WM8962_DACR_RETUNE_C17_0: 1260 case WM8962_DACR_RETUNE_C18_1: 1261 case WM8962_DACR_RETUNE_C18_0: 1262 case WM8962_DACR_RETUNE_C19_1: 1263 case WM8962_DACR_RETUNE_C19_0: 1264 case WM8962_DACR_RETUNE_C20_1: 1265 case WM8962_DACR_RETUNE_C20_0: 1266 case WM8962_DACR_RETUNE_C21_1: 1267 case WM8962_DACR_RETUNE_C21_0: 1268 case WM8962_DACR_RETUNE_C22_1: 1269 case WM8962_DACR_RETUNE_C22_0: 1270 case WM8962_DACR_RETUNE_C23_1: 1271 case WM8962_DACR_RETUNE_C23_0: 1272 case WM8962_DACR_RETUNE_C24_1: 1273 case WM8962_DACR_RETUNE_C24_0: 1274 case WM8962_DACR_RETUNE_C25_1: 1275 case WM8962_DACR_RETUNE_C25_0: 1276 case WM8962_DACR_RETUNE_C26_1: 1277 case WM8962_DACR_RETUNE_C26_0: 1278 case WM8962_DACR_RETUNE_C27_1: 1279 case WM8962_DACR_RETUNE_C27_0: 1280 case WM8962_DACR_RETUNE_C28_1: 1281 case WM8962_DACR_RETUNE_C28_0: 1282 case WM8962_DACR_RETUNE_C29_1: 1283 case WM8962_DACR_RETUNE_C29_0: 1284 case WM8962_DACR_RETUNE_C30_1: 1285 case WM8962_DACR_RETUNE_C30_0: 1286 case WM8962_DACR_RETUNE_C31_1: 1287 case WM8962_DACR_RETUNE_C31_0: 1288 case WM8962_DACR_RETUNE_C32_1: 1289 case WM8962_DACR_RETUNE_C32_0: 1290 case WM8962_VSS_XHD2_1: 1291 case WM8962_VSS_XHD2_0: 1292 case WM8962_VSS_XHD3_1: 1293 case WM8962_VSS_XHD3_0: 1294 case WM8962_VSS_XHN1_1: 1295 case WM8962_VSS_XHN1_0: 1296 case WM8962_VSS_XHN2_1: 1297 case WM8962_VSS_XHN2_0: 1298 case WM8962_VSS_XHN3_1: 1299 case WM8962_VSS_XHN3_0: 1300 case WM8962_VSS_XLA_1: 1301 case WM8962_VSS_XLA_0: 1302 case WM8962_VSS_XLB_1: 1303 case WM8962_VSS_XLB_0: 1304 case WM8962_VSS_XLG_1: 1305 case WM8962_VSS_XLG_0: 1306 case WM8962_VSS_PG2_1: 1307 case WM8962_VSS_PG2_0: 1308 case WM8962_VSS_PG_1: 1309 case WM8962_VSS_PG_0: 1310 case WM8962_VSS_XTD1_1: 1311 case WM8962_VSS_XTD1_0: 1312 case WM8962_VSS_XTD2_1: 1313 case WM8962_VSS_XTD2_0: 1314 case WM8962_VSS_XTD3_1: 1315 case WM8962_VSS_XTD3_0: 1316 case WM8962_VSS_XTD4_1: 1317 case WM8962_VSS_XTD4_0: 1318 case WM8962_VSS_XTD5_1: 1319 case WM8962_VSS_XTD5_0: 1320 case WM8962_VSS_XTD6_1: 1321 case WM8962_VSS_XTD6_0: 1322 case WM8962_VSS_XTD7_1: 1323 case WM8962_VSS_XTD7_0: 1324 case WM8962_VSS_XTD8_1: 1325 case WM8962_VSS_XTD8_0: 1326 case WM8962_VSS_XTD9_1: 1327 case WM8962_VSS_XTD9_0: 1328 case WM8962_VSS_XTD10_1: 1329 case WM8962_VSS_XTD10_0: 1330 case WM8962_VSS_XTD11_1: 1331 case WM8962_VSS_XTD11_0: 1332 case WM8962_VSS_XTD12_1: 1333 case WM8962_VSS_XTD12_0: 1334 case WM8962_VSS_XTD13_1: 1335 case WM8962_VSS_XTD13_0: 1336 case WM8962_VSS_XTD14_1: 1337 case WM8962_VSS_XTD14_0: 1338 case WM8962_VSS_XTD15_1: 1339 case WM8962_VSS_XTD15_0: 1340 case WM8962_VSS_XTD16_1: 1341 case WM8962_VSS_XTD16_0: 1342 case WM8962_VSS_XTD17_1: 1343 case WM8962_VSS_XTD17_0: 1344 case WM8962_VSS_XTD18_1: 1345 case WM8962_VSS_XTD18_0: 1346 case WM8962_VSS_XTD19_1: 1347 case WM8962_VSS_XTD19_0: 1348 case WM8962_VSS_XTD20_1: 1349 case WM8962_VSS_XTD20_0: 1350 case WM8962_VSS_XTD21_1: 1351 case WM8962_VSS_XTD21_0: 1352 case WM8962_VSS_XTD22_1: 1353 case WM8962_VSS_XTD22_0: 1354 case WM8962_VSS_XTD23_1: 1355 case WM8962_VSS_XTD23_0: 1356 case WM8962_VSS_XTD24_1: 1357 case WM8962_VSS_XTD24_0: 1358 case WM8962_VSS_XTD25_1: 1359 case WM8962_VSS_XTD25_0: 1360 case WM8962_VSS_XTD26_1: 1361 case WM8962_VSS_XTD26_0: 1362 case WM8962_VSS_XTD27_1: 1363 case WM8962_VSS_XTD27_0: 1364 case WM8962_VSS_XTD28_1: 1365 case WM8962_VSS_XTD28_0: 1366 case WM8962_VSS_XTD29_1: 1367 case WM8962_VSS_XTD29_0: 1368 case WM8962_VSS_XTD30_1: 1369 case WM8962_VSS_XTD30_0: 1370 case WM8962_VSS_XTD31_1: 1371 case WM8962_VSS_XTD31_0: 1372 case WM8962_VSS_XTD32_1: 1373 case WM8962_VSS_XTD32_0: 1374 case WM8962_VSS_XTS1_1: 1375 case WM8962_VSS_XTS1_0: 1376 case WM8962_VSS_XTS2_1: 1377 case WM8962_VSS_XTS2_0: 1378 case WM8962_VSS_XTS3_1: 1379 case WM8962_VSS_XTS3_0: 1380 case WM8962_VSS_XTS4_1: 1381 case WM8962_VSS_XTS4_0: 1382 case WM8962_VSS_XTS5_1: 1383 case WM8962_VSS_XTS5_0: 1384 case WM8962_VSS_XTS6_1: 1385 case WM8962_VSS_XTS6_0: 1386 case WM8962_VSS_XTS7_1: 1387 case WM8962_VSS_XTS7_0: 1388 case WM8962_VSS_XTS8_1: 1389 case WM8962_VSS_XTS8_0: 1390 case WM8962_VSS_XTS9_1: 1391 case WM8962_VSS_XTS9_0: 1392 case WM8962_VSS_XTS10_1: 1393 case WM8962_VSS_XTS10_0: 1394 case WM8962_VSS_XTS11_1: 1395 case WM8962_VSS_XTS11_0: 1396 case WM8962_VSS_XTS12_1: 1397 case WM8962_VSS_XTS12_0: 1398 case WM8962_VSS_XTS13_1: 1399 case WM8962_VSS_XTS13_0: 1400 case WM8962_VSS_XTS14_1: 1401 case WM8962_VSS_XTS14_0: 1402 case WM8962_VSS_XTS15_1: 1403 case WM8962_VSS_XTS15_0: 1404 case WM8962_VSS_XTS16_1: 1405 case WM8962_VSS_XTS16_0: 1406 case WM8962_VSS_XTS17_1: 1407 case WM8962_VSS_XTS17_0: 1408 case WM8962_VSS_XTS18_1: 1409 case WM8962_VSS_XTS18_0: 1410 case WM8962_VSS_XTS19_1: 1411 case WM8962_VSS_XTS19_0: 1412 case WM8962_VSS_XTS20_1: 1413 case WM8962_VSS_XTS20_0: 1414 case WM8962_VSS_XTS21_1: 1415 case WM8962_VSS_XTS21_0: 1416 case WM8962_VSS_XTS22_1: 1417 case WM8962_VSS_XTS22_0: 1418 case WM8962_VSS_XTS23_1: 1419 case WM8962_VSS_XTS23_0: 1420 case WM8962_VSS_XTS24_1: 1421 case WM8962_VSS_XTS24_0: 1422 case WM8962_VSS_XTS25_1: 1423 case WM8962_VSS_XTS25_0: 1424 case WM8962_VSS_XTS26_1: 1425 case WM8962_VSS_XTS26_0: 1426 case WM8962_VSS_XTS27_1: 1427 case WM8962_VSS_XTS27_0: 1428 case WM8962_VSS_XTS28_1: 1429 case WM8962_VSS_XTS28_0: 1430 case WM8962_VSS_XTS29_1: 1431 case WM8962_VSS_XTS29_0: 1432 case WM8962_VSS_XTS30_1: 1433 case WM8962_VSS_XTS30_0: 1434 case WM8962_VSS_XTS31_1: 1435 case WM8962_VSS_XTS31_0: 1436 case WM8962_VSS_XTS32_1: 1437 case WM8962_VSS_XTS32_0: 1438 return true; 1439 default: 1440 return false; 1441 } 1442 } 1443 1444 static int wm8962_reset(struct wm8962_priv *wm8962) 1445 { 1446 int ret; 1447 1448 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243); 1449 if (ret != 0) 1450 return ret; 1451 1452 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0); 1453 } 1454 1455 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0); 1456 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0); 1457 static const DECLARE_TLV_DB_RANGE(mixinpga_tlv, 1458 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0), 1459 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0), 1460 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0), 1461 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0), 1462 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0) 1463 ); 1464 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1); 1465 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 1466 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 1467 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0); 1468 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); 1469 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); 1470 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0); 1471 static const DECLARE_TLV_DB_RANGE(classd_tlv, 1472 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0), 1473 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0) 1474 ); 1475 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 1476 1477 static int wm8962_dsp2_write_config(struct snd_soc_component *component) 1478 { 1479 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 1480 1481 return regcache_sync_region(wm8962->regmap, 1482 WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER); 1483 } 1484 1485 static int wm8962_dsp2_set_enable(struct snd_soc_component *component, u16 val) 1486 { 1487 u16 adcl = snd_soc_component_read(component, WM8962_LEFT_ADC_VOLUME); 1488 u16 adcr = snd_soc_component_read(component, WM8962_RIGHT_ADC_VOLUME); 1489 u16 dac = snd_soc_component_read(component, WM8962_ADC_DAC_CONTROL_1); 1490 1491 /* Mute the ADCs and DACs */ 1492 snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, 0); 1493 snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU); 1494 snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1, 1495 WM8962_DAC_MUTE, WM8962_DAC_MUTE); 1496 1497 snd_soc_component_write(component, WM8962_SOUNDSTAGE_ENABLES_0, val); 1498 1499 /* Restore the ADCs and DACs */ 1500 snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, adcl); 1501 snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, adcr); 1502 snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1, 1503 WM8962_DAC_MUTE, dac); 1504 1505 return 0; 1506 } 1507 1508 static int wm8962_dsp2_start(struct snd_soc_component *component) 1509 { 1510 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 1511 1512 wm8962_dsp2_write_config(component); 1513 1514 snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR); 1515 1516 wm8962_dsp2_set_enable(component, wm8962->dsp2_ena); 1517 1518 return 0; 1519 } 1520 1521 static int wm8962_dsp2_stop(struct snd_soc_component *component) 1522 { 1523 wm8962_dsp2_set_enable(component, 0); 1524 1525 snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP); 1526 1527 return 0; 1528 } 1529 1530 #define WM8962_DSP2_ENABLE(xname, xshift) \ 1531 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1532 .info = wm8962_dsp2_ena_info, \ 1533 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \ 1534 .private_value = xshift } 1535 1536 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol, 1537 struct snd_ctl_elem_info *uinfo) 1538 { 1539 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1540 1541 uinfo->count = 1; 1542 uinfo->value.integer.min = 0; 1543 uinfo->value.integer.max = 1; 1544 1545 return 0; 1546 } 1547 1548 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol, 1549 struct snd_ctl_elem_value *ucontrol) 1550 { 1551 int shift = kcontrol->private_value; 1552 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1553 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 1554 1555 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift); 1556 1557 return 0; 1558 } 1559 1560 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol, 1561 struct snd_ctl_elem_value *ucontrol) 1562 { 1563 int shift = kcontrol->private_value; 1564 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1565 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 1566 int old = wm8962->dsp2_ena; 1567 int ret = 0; 1568 int dsp2_running = snd_soc_component_read(component, WM8962_DSP2_POWER_MANAGEMENT) & 1569 WM8962_DSP2_ENA; 1570 1571 mutex_lock(&wm8962->dsp2_ena_lock); 1572 1573 if (ucontrol->value.integer.value[0]) 1574 wm8962->dsp2_ena |= 1 << shift; 1575 else 1576 wm8962->dsp2_ena &= ~(1 << shift); 1577 1578 if (wm8962->dsp2_ena == old) 1579 goto out; 1580 1581 ret = 1; 1582 1583 if (dsp2_running) { 1584 if (wm8962->dsp2_ena) 1585 wm8962_dsp2_set_enable(component, wm8962->dsp2_ena); 1586 else 1587 wm8962_dsp2_stop(component); 1588 } 1589 1590 out: 1591 mutex_unlock(&wm8962->dsp2_ena_lock); 1592 1593 return ret; 1594 } 1595 1596 /* The VU bits for the headphones are in a different register to the mute 1597 * bits and only take effect on the PGA if it is actually powered. 1598 */ 1599 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol, 1600 struct snd_ctl_elem_value *ucontrol) 1601 { 1602 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1603 int ret; 1604 1605 /* Apply the update (if any) */ 1606 ret = snd_soc_put_volsw(kcontrol, ucontrol); 1607 if (ret == 0) 1608 return 0; 1609 1610 /* If the left PGA is enabled hit that VU bit... */ 1611 ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2); 1612 if (ret & WM8962_HPOUTL_PGA_ENA) { 1613 snd_soc_component_write(component, WM8962_HPOUTL_VOLUME, 1614 snd_soc_component_read(component, WM8962_HPOUTL_VOLUME)); 1615 return 1; 1616 } 1617 1618 /* ...otherwise the right. The VU is stereo. */ 1619 if (ret & WM8962_HPOUTR_PGA_ENA) 1620 snd_soc_component_write(component, WM8962_HPOUTR_VOLUME, 1621 snd_soc_component_read(component, WM8962_HPOUTR_VOLUME)); 1622 1623 return 1; 1624 } 1625 1626 /* The VU bits for the speakers are in a different register to the mute 1627 * bits and only take effect on the PGA if it is actually powered. 1628 */ 1629 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol, 1630 struct snd_ctl_elem_value *ucontrol) 1631 { 1632 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1633 int ret; 1634 1635 /* Apply the update (if any) */ 1636 ret = snd_soc_put_volsw(kcontrol, ucontrol); 1637 if (ret == 0) 1638 return 0; 1639 1640 /* If the left PGA is enabled hit that VU bit... */ 1641 ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2); 1642 if (ret & WM8962_SPKOUTL_PGA_ENA) { 1643 snd_soc_component_write(component, WM8962_SPKOUTL_VOLUME, 1644 snd_soc_component_read(component, WM8962_SPKOUTL_VOLUME)); 1645 return 1; 1646 } 1647 1648 /* ...otherwise the right. The VU is stereo. */ 1649 if (ret & WM8962_SPKOUTR_PGA_ENA) 1650 snd_soc_component_write(component, WM8962_SPKOUTR_VOLUME, 1651 snd_soc_component_read(component, WM8962_SPKOUTR_VOLUME)); 1652 1653 return 1; 1654 } 1655 1656 static const char *cap_hpf_mode_text[] = { 1657 "Hi-fi", "Application" 1658 }; 1659 1660 static SOC_ENUM_SINGLE_DECL(cap_hpf_mode, 1661 WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text); 1662 1663 1664 static const char *cap_lhpf_mode_text[] = { 1665 "LPF", "HPF" 1666 }; 1667 1668 static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode, 1669 WM8962_LHPF1, 1, cap_lhpf_mode_text); 1670 1671 static const struct snd_kcontrol_new wm8962_snd_controls[] = { 1672 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1), 1673 1674 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0, 1675 mixin_tlv), 1676 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0, 1677 mixinpga_tlv), 1678 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0, 1679 mixin_tlv), 1680 1681 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0, 1682 mixin_tlv), 1683 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0, 1684 mixinpga_tlv), 1685 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0, 1686 mixin_tlv), 1687 1688 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME, 1689 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv), 1690 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME, 1691 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv), 1692 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME, 1693 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1), 1694 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME, 1695 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1), 1696 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1), 1697 SOC_ENUM("Capture HPF Mode", cap_hpf_mode), 1698 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0), 1699 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0), 1700 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode), 1701 1702 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1, 1703 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv), 1704 1705 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME, 1706 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv), 1707 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0), 1708 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0), 1709 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0), 1710 SOC_SINGLE("DAC Monomix Switch", WM8962_DAC_DSP_MIXING_1, WM8962_DAC_MONOMIX_SHIFT, 1, 0), 1711 SOC_SINGLE("ADC Monomix Switch", WM8962_THREED1, WM8962_ADC_MONOMIX_SHIFT, 1, 0), 1712 1713 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1, 1714 5, 1, 0), 1715 1716 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv), 1717 1718 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME, 1719 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv), 1720 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1, 1721 snd_soc_get_volsw, wm8962_put_hp_sw), 1722 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME, 1723 7, 1, 0), 1724 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0, 1725 hp_tlv), 1726 1727 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3, 1728 WM8962_HEADPHONE_MIXER_4, 8, 1, 1), 1729 1730 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3, 1731 3, 7, 0, bypass_tlv), 1732 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3, 1733 0, 7, 0, bypass_tlv), 1734 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3, 1735 7, 1, 1, inmix_tlv), 1736 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3, 1737 6, 1, 1, inmix_tlv), 1738 1739 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4, 1740 3, 7, 0, bypass_tlv), 1741 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4, 1742 0, 7, 0, bypass_tlv), 1743 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4, 1744 7, 1, 1, inmix_tlv), 1745 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4, 1746 6, 1, 1, inmix_tlv), 1747 1748 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0, 1749 classd_tlv), 1750 1751 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0), 1752 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22, 1753 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv), 1754 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22, 1755 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv), 1756 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22, 1757 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv), 1758 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23, 1759 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv), 1760 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23, 1761 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv), 1762 SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18), 1763 SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18), 1764 1765 1766 SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0), 1767 SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA | WM8962_ADC_MONOMIX), 1768 1769 SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0), 1770 SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA), 1771 1772 SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0), 1773 SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA), 1774 1775 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT), 1776 SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148), 1777 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT), 1778 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT), 1779 SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1), 1780 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT), 1781 SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30), 1782 1783 SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT, 1784 WM8962_ALCR_ENA_SHIFT, 1, 0), 1785 SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4, 1786 WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK), 1787 }; 1788 1789 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = { 1790 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv), 1791 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1, 1792 snd_soc_get_volsw, wm8962_put_spk_sw), 1793 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0), 1794 1795 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1), 1796 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, 1797 3, 7, 0, bypass_tlv), 1798 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, 1799 0, 7, 0, bypass_tlv), 1800 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, 1801 7, 1, 1, inmix_tlv), 1802 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, 1803 6, 1, 1, inmix_tlv), 1804 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 1805 7, 1, 0, inmix_tlv), 1806 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 1807 6, 1, 0, inmix_tlv), 1808 }; 1809 1810 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = { 1811 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 1812 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv), 1813 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1, 1814 snd_soc_get_volsw, wm8962_put_spk_sw), 1815 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME, 1816 7, 1, 0), 1817 1818 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 1819 WM8962_SPEAKER_MIXER_4, 8, 1, 1), 1820 1821 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, 1822 3, 7, 0, bypass_tlv), 1823 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, 1824 0, 7, 0, bypass_tlv), 1825 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, 1826 7, 1, 1, inmix_tlv), 1827 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, 1828 6, 1, 1, inmix_tlv), 1829 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 1830 7, 1, 0, inmix_tlv), 1831 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 1832 6, 1, 0, inmix_tlv), 1833 1834 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4, 1835 3, 7, 0, bypass_tlv), 1836 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4, 1837 0, 7, 0, bypass_tlv), 1838 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4, 1839 7, 1, 1, inmix_tlv), 1840 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4, 1841 6, 1, 1, inmix_tlv), 1842 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 1843 5, 1, 0, inmix_tlv), 1844 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 1845 4, 1, 0, inmix_tlv), 1846 }; 1847 1848 static int tp_event(struct snd_soc_dapm_widget *w, 1849 struct snd_kcontrol *kcontrol, int event) 1850 { 1851 int ret, reg, val, mask; 1852 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1853 1854 ret = pm_runtime_resume_and_get(component->dev); 1855 if (ret < 0) { 1856 dev_err(component->dev, "Failed to resume device: %d\n", ret); 1857 return ret; 1858 } 1859 1860 reg = WM8962_ADDITIONAL_CONTROL_4; 1861 1862 if (!snd_soc_dapm_widget_name_cmp(w, "TEMP_HP")) { 1863 mask = WM8962_TEMP_ENA_HP_MASK; 1864 val = WM8962_TEMP_ENA_HP; 1865 } else if (!snd_soc_dapm_widget_name_cmp(w, "TEMP_SPK")) { 1866 mask = WM8962_TEMP_ENA_SPK_MASK; 1867 val = WM8962_TEMP_ENA_SPK; 1868 } else { 1869 pm_runtime_put(component->dev); 1870 return -EINVAL; 1871 } 1872 1873 switch (event) { 1874 case SND_SOC_DAPM_POST_PMD: 1875 val = 0; 1876 fallthrough; 1877 case SND_SOC_DAPM_POST_PMU: 1878 ret = snd_soc_component_update_bits(component, reg, mask, val); 1879 break; 1880 default: 1881 WARN(1, "Invalid event %d\n", event); 1882 pm_runtime_put(component->dev); 1883 return -EINVAL; 1884 } 1885 1886 pm_runtime_put(component->dev); 1887 1888 return 0; 1889 } 1890 1891 static int cp_event(struct snd_soc_dapm_widget *w, 1892 struct snd_kcontrol *kcontrol, int event) 1893 { 1894 switch (event) { 1895 case SND_SOC_DAPM_POST_PMU: 1896 msleep(5); 1897 break; 1898 1899 default: 1900 WARN(1, "Invalid event %d\n", event); 1901 return -EINVAL; 1902 } 1903 1904 return 0; 1905 } 1906 1907 static int hp_event(struct snd_soc_dapm_widget *w, 1908 struct snd_kcontrol *kcontrol, int event) 1909 { 1910 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1911 int timeout; 1912 int reg; 1913 int expected = (WM8962_DCS_STARTUP_DONE_HP1L | 1914 WM8962_DCS_STARTUP_DONE_HP1R); 1915 1916 switch (event) { 1917 case SND_SOC_DAPM_POST_PMU: 1918 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1919 WM8962_HP1L_ENA | WM8962_HP1R_ENA, 1920 WM8962_HP1L_ENA | WM8962_HP1R_ENA); 1921 udelay(20); 1922 1923 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1924 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY, 1925 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY); 1926 1927 /* Start the DC servo */ 1928 snd_soc_component_update_bits(component, WM8962_DC_SERVO_1, 1929 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 1930 WM8962_HP1L_DCS_STARTUP | 1931 WM8962_HP1R_DCS_STARTUP, 1932 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 1933 WM8962_HP1L_DCS_STARTUP | 1934 WM8962_HP1R_DCS_STARTUP); 1935 1936 /* Wait for it to complete, should be well under 100ms */ 1937 timeout = 0; 1938 do { 1939 msleep(1); 1940 reg = snd_soc_component_read(component, WM8962_DC_SERVO_6); 1941 if (reg < 0) { 1942 dev_err(component->dev, 1943 "Failed to read DCS status: %d\n", 1944 reg); 1945 continue; 1946 } 1947 dev_dbg(component->dev, "DCS status: %x\n", reg); 1948 } while (++timeout < 200 && (reg & expected) != expected); 1949 1950 if ((reg & expected) != expected) 1951 dev_err(component->dev, "DC servo timed out\n"); 1952 else 1953 dev_dbg(component->dev, "DC servo complete after %dms\n", 1954 timeout); 1955 1956 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1957 WM8962_HP1L_ENA_OUTP | 1958 WM8962_HP1R_ENA_OUTP, 1959 WM8962_HP1L_ENA_OUTP | 1960 WM8962_HP1R_ENA_OUTP); 1961 udelay(20); 1962 1963 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1964 WM8962_HP1L_RMV_SHORT | 1965 WM8962_HP1R_RMV_SHORT, 1966 WM8962_HP1L_RMV_SHORT | 1967 WM8962_HP1R_RMV_SHORT); 1968 break; 1969 1970 case SND_SOC_DAPM_PRE_PMD: 1971 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1972 WM8962_HP1L_RMV_SHORT | 1973 WM8962_HP1R_RMV_SHORT, 0); 1974 1975 udelay(20); 1976 1977 snd_soc_component_update_bits(component, WM8962_DC_SERVO_1, 1978 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 1979 WM8962_HP1L_DCS_STARTUP | 1980 WM8962_HP1R_DCS_STARTUP, 1981 0); 1982 1983 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, 1984 WM8962_HP1L_ENA | WM8962_HP1R_ENA | 1985 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY | 1986 WM8962_HP1L_ENA_OUTP | 1987 WM8962_HP1R_ENA_OUTP, 0); 1988 1989 break; 1990 1991 default: 1992 WARN(1, "Invalid event %d\n", event); 1993 return -EINVAL; 1994 1995 } 1996 1997 return 0; 1998 } 1999 2000 /* VU bits for the output PGAs only take effect while the PGA is powered */ 2001 static int out_pga_event(struct snd_soc_dapm_widget *w, 2002 struct snd_kcontrol *kcontrol, int event) 2003 { 2004 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2005 int reg; 2006 2007 switch (w->shift) { 2008 case WM8962_HPOUTR_PGA_ENA_SHIFT: 2009 reg = WM8962_HPOUTR_VOLUME; 2010 break; 2011 case WM8962_HPOUTL_PGA_ENA_SHIFT: 2012 reg = WM8962_HPOUTL_VOLUME; 2013 break; 2014 case WM8962_SPKOUTR_PGA_ENA_SHIFT: 2015 reg = WM8962_SPKOUTR_VOLUME; 2016 break; 2017 case WM8962_SPKOUTL_PGA_ENA_SHIFT: 2018 reg = WM8962_SPKOUTL_VOLUME; 2019 break; 2020 default: 2021 WARN(1, "Invalid shift %d\n", w->shift); 2022 return -EINVAL; 2023 } 2024 2025 switch (event) { 2026 case SND_SOC_DAPM_POST_PMU: 2027 return snd_soc_component_write(component, reg, 2028 snd_soc_component_read(component, reg)); 2029 default: 2030 WARN(1, "Invalid event %d\n", event); 2031 return -EINVAL; 2032 } 2033 } 2034 2035 static int dsp2_event(struct snd_soc_dapm_widget *w, 2036 struct snd_kcontrol *kcontrol, int event) 2037 { 2038 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2039 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2040 2041 switch (event) { 2042 case SND_SOC_DAPM_POST_PMU: 2043 if (wm8962->dsp2_ena) 2044 wm8962_dsp2_start(component); 2045 break; 2046 2047 case SND_SOC_DAPM_PRE_PMD: 2048 if (wm8962->dsp2_ena) 2049 wm8962_dsp2_stop(component); 2050 break; 2051 2052 default: 2053 WARN(1, "Invalid event %d\n", event); 2054 return -EINVAL; 2055 } 2056 2057 return 0; 2058 } 2059 2060 static const char *st_text[] = { "None", "Left", "Right" }; 2061 2062 static SOC_ENUM_SINGLE_DECL(str_enum, 2063 WM8962_DAC_DSP_MIXING_1, 2, st_text); 2064 2065 static const struct snd_kcontrol_new str_mux = 2066 SOC_DAPM_ENUM("Right Sidetone", str_enum); 2067 2068 static SOC_ENUM_SINGLE_DECL(stl_enum, 2069 WM8962_DAC_DSP_MIXING_2, 2, st_text); 2070 2071 static const struct snd_kcontrol_new stl_mux = 2072 SOC_DAPM_ENUM("Left Sidetone", stl_enum); 2073 2074 static const char *outmux_text[] = { "DAC", "Mixer" }; 2075 2076 static SOC_ENUM_SINGLE_DECL(spkoutr_enum, 2077 WM8962_SPEAKER_MIXER_2, 7, outmux_text); 2078 2079 static const struct snd_kcontrol_new spkoutr_mux = 2080 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum); 2081 2082 static SOC_ENUM_SINGLE_DECL(spkoutl_enum, 2083 WM8962_SPEAKER_MIXER_1, 7, outmux_text); 2084 2085 static const struct snd_kcontrol_new spkoutl_mux = 2086 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum); 2087 2088 static SOC_ENUM_SINGLE_DECL(hpoutr_enum, 2089 WM8962_HEADPHONE_MIXER_2, 7, outmux_text); 2090 2091 static const struct snd_kcontrol_new hpoutr_mux = 2092 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum); 2093 2094 static SOC_ENUM_SINGLE_DECL(hpoutl_enum, 2095 WM8962_HEADPHONE_MIXER_1, 7, outmux_text); 2096 2097 static const struct snd_kcontrol_new hpoutl_mux = 2098 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum); 2099 2100 static const char * const input_mode_text[] = { "Analog", "Digital" }; 2101 2102 static SOC_ENUM_SINGLE_VIRT_DECL(input_mode_enum, input_mode_text); 2103 2104 static const struct snd_kcontrol_new input_mode_mux = 2105 SOC_DAPM_ENUM("Input Mode", input_mode_enum); 2106 2107 static const struct snd_kcontrol_new inpgal[] = { 2108 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0), 2109 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0), 2110 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0), 2111 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0), 2112 }; 2113 2114 static const struct snd_kcontrol_new inpgar[] = { 2115 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0), 2116 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0), 2117 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0), 2118 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0), 2119 }; 2120 2121 static const struct snd_kcontrol_new mixinl[] = { 2122 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0), 2123 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0), 2124 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0), 2125 }; 2126 2127 static const struct snd_kcontrol_new mixinr[] = { 2128 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0), 2129 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0), 2130 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0), 2131 }; 2132 2133 static const struct snd_kcontrol_new hpmixl[] = { 2134 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0), 2135 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0), 2136 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0), 2137 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0), 2138 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0), 2139 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0), 2140 }; 2141 2142 static const struct snd_kcontrol_new hpmixr[] = { 2143 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0), 2144 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0), 2145 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0), 2146 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0), 2147 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0), 2148 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0), 2149 }; 2150 2151 static const struct snd_kcontrol_new spkmixl[] = { 2152 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0), 2153 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0), 2154 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0), 2155 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0), 2156 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0), 2157 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0), 2158 }; 2159 2160 static const struct snd_kcontrol_new spkmixr[] = { 2161 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0), 2162 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0), 2163 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0), 2164 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0), 2165 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0), 2166 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0), 2167 }; 2168 2169 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = { 2170 SND_SOC_DAPM_INPUT("IN1L"), 2171 SND_SOC_DAPM_INPUT("IN1R"), 2172 SND_SOC_DAPM_INPUT("IN2L"), 2173 SND_SOC_DAPM_INPUT("IN2R"), 2174 SND_SOC_DAPM_INPUT("IN3L"), 2175 SND_SOC_DAPM_INPUT("IN3R"), 2176 SND_SOC_DAPM_INPUT("IN4L"), 2177 SND_SOC_DAPM_INPUT("IN4R"), 2178 SND_SOC_DAPM_SIGGEN("Beep"), 2179 SND_SOC_DAPM_INPUT("DMICDAT"), 2180 2181 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0), 2182 2183 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0), 2184 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0), 2185 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event, 2186 SND_SOC_DAPM_POST_PMU), 2187 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0), 2188 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT, 2189 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event, 2190 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2191 SND_SOC_DAPM_SUPPLY("TEMP_HP", SND_SOC_NOPM, 0, 0, tp_event, 2192 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 2193 SND_SOC_DAPM_SUPPLY("TEMP_SPK", SND_SOC_NOPM, 0, 0, tp_event, 2194 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 2195 2196 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0, 2197 inpgal, ARRAY_SIZE(inpgal)), 2198 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0, 2199 inpgar, ARRAY_SIZE(inpgar)), 2200 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0, 2201 mixinl, ARRAY_SIZE(mixinl)), 2202 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0, 2203 mixinr, ARRAY_SIZE(mixinr)), 2204 2205 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0), 2206 2207 SND_SOC_DAPM_MUX("Input Mode L", SND_SOC_NOPM, 0, 0, &input_mode_mux), 2208 SND_SOC_DAPM_MUX("Input Mode R", SND_SOC_NOPM, 0, 0, &input_mode_mux), 2209 2210 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0), 2211 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0), 2212 2213 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux), 2214 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux), 2215 2216 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0), 2217 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0), 2218 2219 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 2220 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 2221 2222 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0, 2223 hpmixl, ARRAY_SIZE(hpmixl)), 2224 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0, 2225 hpmixr, ARRAY_SIZE(hpmixr)), 2226 2227 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux, 2228 out_pga_event, SND_SOC_DAPM_POST_PMU), 2229 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux, 2230 out_pga_event, SND_SOC_DAPM_POST_PMU), 2231 2232 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event, 2233 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2234 2235 SND_SOC_DAPM_OUTPUT("HPOUTL"), 2236 SND_SOC_DAPM_OUTPUT("HPOUTR"), 2237 2238 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0), 2239 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), 2240 }; 2241 2242 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = { 2243 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0, 2244 spkmixl, ARRAY_SIZE(spkmixl)), 2245 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, 2246 out_pga_event, SND_SOC_DAPM_POST_PMU), 2247 SND_SOC_DAPM_OUTPUT("SPKOUT"), 2248 }; 2249 2250 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = { 2251 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0, 2252 spkmixl, ARRAY_SIZE(spkmixl)), 2253 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0, 2254 spkmixr, ARRAY_SIZE(spkmixr)), 2255 2256 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, 2257 out_pga_event, SND_SOC_DAPM_POST_PMU), 2258 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux, 2259 out_pga_event, SND_SOC_DAPM_POST_PMU), 2260 2261 SND_SOC_DAPM_OUTPUT("SPKOUTL"), 2262 SND_SOC_DAPM_OUTPUT("SPKOUTR"), 2263 }; 2264 2265 static const struct snd_soc_dapm_route wm8962_intercon[] = { 2266 { "INPGAL", "IN1L Switch", "IN1L" }, 2267 { "INPGAL", "IN2L Switch", "IN2L" }, 2268 { "INPGAL", "IN3L Switch", "IN3L" }, 2269 { "INPGAL", "IN4L Switch", "IN4L" }, 2270 2271 { "INPGAR", "IN1R Switch", "IN1R" }, 2272 { "INPGAR", "IN2R Switch", "IN2R" }, 2273 { "INPGAR", "IN3R Switch", "IN3R" }, 2274 { "INPGAR", "IN4R Switch", "IN4R" }, 2275 2276 { "MIXINL", "IN2L Switch", "IN2L" }, 2277 { "MIXINL", "IN3L Switch", "IN3L" }, 2278 { "MIXINL", "PGA Switch", "INPGAL" }, 2279 2280 { "MIXINR", "IN2R Switch", "IN2R" }, 2281 { "MIXINR", "IN3R Switch", "IN3R" }, 2282 { "MIXINR", "PGA Switch", "INPGAR" }, 2283 2284 { "MICBIAS", NULL, "SYSCLK" }, 2285 2286 { "DMIC_ENA", NULL, "DMICDAT" }, 2287 2288 { "Input Mode L", "Analog", "MIXINL" }, 2289 { "Input Mode L", "Digital", "DMIC_ENA" }, 2290 { "Input Mode R", "Analog", "MIXINR" }, 2291 { "Input Mode R", "Digital", "DMIC_ENA" }, 2292 2293 { "ADCL", NULL, "SYSCLK" }, 2294 { "ADCL", NULL, "TOCLK" }, 2295 { "ADCL", NULL, "Input Mode L" }, 2296 { "ADCL", NULL, "DSP2" }, 2297 2298 { "ADCR", NULL, "SYSCLK" }, 2299 { "ADCR", NULL, "TOCLK" }, 2300 { "ADCR", NULL, "Input Mode R" }, 2301 { "ADCR", NULL, "DSP2" }, 2302 2303 { "STL", "Left", "ADCL" }, 2304 { "STL", "Right", "ADCR" }, 2305 { "STL", NULL, "Class G" }, 2306 2307 { "STR", "Left", "ADCL" }, 2308 { "STR", "Right", "ADCR" }, 2309 { "STR", NULL, "Class G" }, 2310 2311 { "DACL", NULL, "SYSCLK" }, 2312 { "DACL", NULL, "TOCLK" }, 2313 { "DACL", NULL, "Beep" }, 2314 { "DACL", NULL, "STL" }, 2315 { "DACL", NULL, "DSP2" }, 2316 2317 { "DACR", NULL, "SYSCLK" }, 2318 { "DACR", NULL, "TOCLK" }, 2319 { "DACR", NULL, "Beep" }, 2320 { "DACR", NULL, "STR" }, 2321 { "DACR", NULL, "DSP2" }, 2322 2323 { "HPMIXL", "IN4L Switch", "IN4L" }, 2324 { "HPMIXL", "IN4R Switch", "IN4R" }, 2325 { "HPMIXL", "DACL Switch", "DACL" }, 2326 { "HPMIXL", "DACR Switch", "DACR" }, 2327 { "HPMIXL", "MIXINL Switch", "MIXINL" }, 2328 { "HPMIXL", "MIXINR Switch", "MIXINR" }, 2329 2330 { "HPMIXR", "IN4L Switch", "IN4L" }, 2331 { "HPMIXR", "IN4R Switch", "IN4R" }, 2332 { "HPMIXR", "DACL Switch", "DACL" }, 2333 { "HPMIXR", "DACR Switch", "DACR" }, 2334 { "HPMIXR", "MIXINL Switch", "MIXINL" }, 2335 { "HPMIXR", "MIXINR Switch", "MIXINR" }, 2336 2337 { "Left Bypass", NULL, "HPMIXL" }, 2338 { "Left Bypass", NULL, "Class G" }, 2339 2340 { "Right Bypass", NULL, "HPMIXR" }, 2341 { "Right Bypass", NULL, "Class G" }, 2342 2343 { "HPOUTL PGA", "Mixer", "Left Bypass" }, 2344 { "HPOUTL PGA", "DAC", "DACL" }, 2345 2346 { "HPOUTR PGA", "Mixer", "Right Bypass" }, 2347 { "HPOUTR PGA", "DAC", "DACR" }, 2348 2349 { "HPOUT", NULL, "HPOUTL PGA" }, 2350 { "HPOUT", NULL, "HPOUTR PGA" }, 2351 { "HPOUT", NULL, "Charge Pump" }, 2352 { "HPOUT", NULL, "SYSCLK" }, 2353 { "HPOUT", NULL, "TOCLK" }, 2354 2355 { "HPOUTL", NULL, "HPOUT" }, 2356 { "HPOUTR", NULL, "HPOUT" }, 2357 2358 { "HPOUTL", NULL, "TEMP_HP" }, 2359 { "HPOUTR", NULL, "TEMP_HP" }, 2360 }; 2361 2362 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = { 2363 { "Speaker Mixer", "IN4L Switch", "IN4L" }, 2364 { "Speaker Mixer", "IN4R Switch", "IN4R" }, 2365 { "Speaker Mixer", "DACL Switch", "DACL" }, 2366 { "Speaker Mixer", "DACR Switch", "DACR" }, 2367 { "Speaker Mixer", "MIXINL Switch", "MIXINL" }, 2368 { "Speaker Mixer", "MIXINR Switch", "MIXINR" }, 2369 2370 { "Speaker PGA", "Mixer", "Speaker Mixer" }, 2371 { "Speaker PGA", "DAC", "DACL" }, 2372 2373 { "SPKOUTL Output", NULL, "Speaker PGA" }, 2374 { "SPKOUTL Output", NULL, "SYSCLK" }, 2375 { "SPKOUTL Output", NULL, "TOCLK" }, 2376 { "SPKOUTL Output", NULL, "TEMP_SPK" }, 2377 2378 { "SPKOUTR Output", NULL, "Speaker PGA" }, 2379 { "SPKOUTR Output", NULL, "SYSCLK" }, 2380 { "SPKOUTR Output", NULL, "TOCLK" }, 2381 { "SPKOUTR Output", NULL, "TEMP_SPK" }, 2382 2383 { "SPKOUT", NULL, "SPKOUTL Output" }, 2384 { "SPKOUT", NULL, "SPKOUTR Output" }, 2385 }; 2386 2387 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = { 2388 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" }, 2389 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" }, 2390 { "SPKOUTL Mixer", "DACL Switch", "DACL" }, 2391 { "SPKOUTL Mixer", "DACR Switch", "DACR" }, 2392 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" }, 2393 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" }, 2394 2395 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" }, 2396 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" }, 2397 { "SPKOUTR Mixer", "DACL Switch", "DACL" }, 2398 { "SPKOUTR Mixer", "DACR Switch", "DACR" }, 2399 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" }, 2400 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" }, 2401 2402 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" }, 2403 { "SPKOUTL PGA", "DAC", "DACL" }, 2404 2405 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" }, 2406 { "SPKOUTR PGA", "DAC", "DACR" }, 2407 2408 { "SPKOUTL Output", NULL, "SPKOUTL PGA" }, 2409 { "SPKOUTL Output", NULL, "SYSCLK" }, 2410 { "SPKOUTL Output", NULL, "TOCLK" }, 2411 { "SPKOUTL Output", NULL, "TEMP_SPK" }, 2412 2413 { "SPKOUTR Output", NULL, "SPKOUTR PGA" }, 2414 { "SPKOUTR Output", NULL, "SYSCLK" }, 2415 { "SPKOUTR Output", NULL, "TOCLK" }, 2416 { "SPKOUTR Output", NULL, "TEMP_SPK" }, 2417 2418 { "SPKOUTL", NULL, "SPKOUTL Output" }, 2419 { "SPKOUTR", NULL, "SPKOUTR Output" }, 2420 }; 2421 2422 static int wm8962_add_widgets(struct snd_soc_component *component) 2423 { 2424 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2425 struct wm8962_pdata *pdata = &wm8962->pdata; 2426 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2427 2428 snd_soc_add_component_controls(component, wm8962_snd_controls, 2429 ARRAY_SIZE(wm8962_snd_controls)); 2430 if (pdata->spk_mono) 2431 snd_soc_add_component_controls(component, wm8962_spk_mono_controls, 2432 ARRAY_SIZE(wm8962_spk_mono_controls)); 2433 else 2434 snd_soc_add_component_controls(component, wm8962_spk_stereo_controls, 2435 ARRAY_SIZE(wm8962_spk_stereo_controls)); 2436 2437 2438 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets, 2439 ARRAY_SIZE(wm8962_dapm_widgets)); 2440 if (pdata->spk_mono) 2441 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets, 2442 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets)); 2443 else 2444 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets, 2445 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets)); 2446 2447 snd_soc_dapm_add_routes(dapm, wm8962_intercon, 2448 ARRAY_SIZE(wm8962_intercon)); 2449 if (pdata->spk_mono) 2450 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon, 2451 ARRAY_SIZE(wm8962_spk_mono_intercon)); 2452 else 2453 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon, 2454 ARRAY_SIZE(wm8962_spk_stereo_intercon)); 2455 2456 2457 snd_soc_dapm_disable_pin(dapm, "Beep"); 2458 2459 return 0; 2460 } 2461 2462 /* -1 for reserved values */ 2463 static const int bclk_divs[] = { 2464 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32 2465 }; 2466 2467 static const int sysclk_rates[] = { 2468 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144 2469 }; 2470 2471 static void wm8962_configure_bclk(struct snd_soc_component *component) 2472 { 2473 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2474 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2475 int best, min_diff, diff; 2476 int dspclk, i; 2477 int clocking2 = 0; 2478 int clocking4 = 0; 2479 int aif2 = 0; 2480 2481 if (!wm8962->sysclk_rate) { 2482 dev_dbg(component->dev, "No SYSCLK configured\n"); 2483 return; 2484 } 2485 2486 if (!wm8962->bclk || !wm8962->lrclk) { 2487 dev_dbg(component->dev, "No audio clocks configured\n"); 2488 return; 2489 } 2490 2491 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) { 2492 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) { 2493 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT; 2494 break; 2495 } 2496 } 2497 2498 if (i == ARRAY_SIZE(sysclk_rates)) { 2499 dev_err(component->dev, "Unsupported sysclk ratio %d\n", 2500 wm8962->sysclk_rate / wm8962->lrclk); 2501 return; 2502 } 2503 2504 dev_dbg(component->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]); 2505 2506 snd_soc_component_update_bits(component, WM8962_CLOCKING_4, 2507 WM8962_SYSCLK_RATE_MASK, clocking4); 2508 2509 /* DSPCLK_DIV can be only generated correctly after enabling SYSCLK. 2510 * So we here provisionally enable it and then disable it afterward 2511 * if current bias_level hasn't reached SND_SOC_BIAS_ON. 2512 */ 2513 if (snd_soc_dapm_get_bias_level(dapm) != SND_SOC_BIAS_ON) 2514 snd_soc_component_update_bits(component, WM8962_CLOCKING2, 2515 WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA); 2516 2517 /* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate 2518 * correct frequency of LRCLK and BCLK. Sometimes the read-only value 2519 * can't be updated timely after enabling SYSCLK. This results in wrong 2520 * calculation values. Delay is introduced here to wait for newest 2521 * value from register. The time of the delay should be at least 2522 * 500~1000us according to test. 2523 */ 2524 usleep_range(500, 1000); 2525 dspclk = snd_soc_component_read(component, WM8962_CLOCKING1); 2526 2527 if (snd_soc_dapm_get_bias_level(dapm) != SND_SOC_BIAS_ON) 2528 snd_soc_component_update_bits(component, WM8962_CLOCKING2, 2529 WM8962_SYSCLK_ENA_MASK, 0); 2530 2531 if (dspclk < 0) { 2532 dev_err(component->dev, "Failed to read DSPCLK: %d\n", dspclk); 2533 return; 2534 } 2535 2536 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT; 2537 switch (dspclk) { 2538 case 0: 2539 dspclk = wm8962->sysclk_rate; 2540 break; 2541 case 1: 2542 dspclk = wm8962->sysclk_rate / 2; 2543 break; 2544 case 2: 2545 dspclk = wm8962->sysclk_rate / 4; 2546 break; 2547 default: 2548 dev_warn(component->dev, "Unknown DSPCLK divisor read back\n"); 2549 dspclk = wm8962->sysclk_rate; 2550 } 2551 2552 dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); 2553 2554 /* Search a proper bclk, not exact match. */ 2555 best = 0; 2556 min_diff = INT_MAX; 2557 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 2558 if (bclk_divs[i] < 0) 2559 continue; 2560 2561 diff = (dspclk / bclk_divs[i]) - wm8962->bclk; 2562 if (diff < 0) /* Table is sorted */ 2563 break; 2564 if (diff < min_diff) { 2565 best = i; 2566 min_diff = diff; 2567 } 2568 } 2569 wm8962->bclk = dspclk / bclk_divs[best]; 2570 clocking2 |= best; 2571 dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n", 2572 bclk_divs[best], wm8962->bclk); 2573 2574 aif2 |= wm8962->bclk / wm8962->lrclk; 2575 dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n", 2576 wm8962->bclk / wm8962->lrclk, wm8962->lrclk); 2577 2578 snd_soc_component_update_bits(component, WM8962_CLOCKING2, 2579 WM8962_BCLK_DIV_MASK, clocking2); 2580 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_2, 2581 WM8962_AIF_RATE_MASK, aif2); 2582 } 2583 2584 static int wm8962_set_bias_level(struct snd_soc_component *component, 2585 enum snd_soc_bias_level level) 2586 { 2587 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2588 2589 switch (level) { 2590 case SND_SOC_BIAS_ON: 2591 break; 2592 2593 case SND_SOC_BIAS_PREPARE: 2594 /* VMID 2*50k */ 2595 snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1, 2596 WM8962_VMID_SEL_MASK, 0x80); 2597 2598 wm8962_configure_bclk(component); 2599 break; 2600 2601 case SND_SOC_BIAS_STANDBY: 2602 /* VMID 2*250k */ 2603 snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1, 2604 WM8962_VMID_SEL_MASK, 0x100); 2605 2606 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) 2607 msleep(100); 2608 break; 2609 2610 case SND_SOC_BIAS_OFF: 2611 break; 2612 } 2613 2614 return 0; 2615 } 2616 2617 static int wm8962_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2618 unsigned int rx_mask, int slots, int slot_width) 2619 { 2620 struct snd_soc_component *component = dai->component; 2621 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2622 2623 wm8962->tdm_width = slot_width; 2624 /* External is one slot one channel, but internal is one slot two channels */ 2625 wm8962->tdm_slots = slots / 2; 2626 2627 return 0; 2628 } 2629 2630 static const struct { 2631 int rate; 2632 int reg; 2633 } sr_vals[] = { 2634 { 48000, 0 }, 2635 { 44100, 0 }, 2636 { 32000, 1 }, 2637 { 22050, 2 }, 2638 { 24000, 2 }, 2639 { 16000, 3 }, 2640 { 11025, 4 }, 2641 { 12000, 4 }, 2642 { 8000, 5 }, 2643 { 88200, 6 }, 2644 { 96000, 6 }, 2645 }; 2646 2647 static int wm8962_hw_params(struct snd_pcm_substream *substream, 2648 struct snd_pcm_hw_params *params, 2649 struct snd_soc_dai *dai) 2650 { 2651 struct snd_soc_component *component = dai->component; 2652 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2653 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2654 int i; 2655 int aif0 = 0; 2656 int adctl3 = 0; 2657 int width; 2658 2659 if (wm8962->tdm_width && wm8962->tdm_slots) { 2660 wm8962->bclk = snd_soc_calc_bclk(params_rate(params), 2661 wm8962->tdm_width, 2662 params_channels(params), 2663 wm8962->tdm_slots); 2664 width = wm8962->tdm_width; 2665 } else { 2666 wm8962->bclk = snd_soc_params_to_bclk(params); 2667 width = params_width(params); 2668 2669 if (params_channels(params) == 1) 2670 wm8962->bclk *= 2; 2671 } 2672 2673 wm8962->lrclk = params_rate(params); 2674 2675 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) { 2676 if (sr_vals[i].rate == wm8962->lrclk) { 2677 adctl3 |= sr_vals[i].reg; 2678 break; 2679 } 2680 } 2681 if (i == ARRAY_SIZE(sr_vals)) { 2682 dev_err(component->dev, "Unsupported rate %dHz\n", wm8962->lrclk); 2683 return -EINVAL; 2684 } 2685 2686 if (wm8962->lrclk % 8000 == 0) 2687 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE; 2688 2689 switch (width) { 2690 case 16: 2691 break; 2692 case 20: 2693 aif0 |= 0x4; 2694 break; 2695 case 24: 2696 aif0 |= 0x8; 2697 break; 2698 case 32: 2699 aif0 |= 0xc; 2700 break; 2701 default: 2702 return -EINVAL; 2703 } 2704 2705 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0, 2706 WM8962_WL_MASK, aif0); 2707 snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_3, 2708 WM8962_SAMPLE_RATE_INT_MODE | 2709 WM8962_SAMPLE_RATE_MASK, adctl3); 2710 2711 dev_dbg(component->dev, "hw_params set BCLK %dHz LRCLK %dHz\n", 2712 wm8962->bclk, wm8962->lrclk); 2713 2714 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_ON) 2715 wm8962_configure_bclk(component); 2716 2717 return 0; 2718 } 2719 2720 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 2721 unsigned int freq, int dir) 2722 { 2723 struct snd_soc_component *component = dai->component; 2724 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2725 int src; 2726 2727 switch (clk_id) { 2728 case WM8962_SYSCLK_MCLK: 2729 wm8962->sysclk = WM8962_SYSCLK_MCLK; 2730 src = 0; 2731 break; 2732 case WM8962_SYSCLK_FLL: 2733 wm8962->sysclk = WM8962_SYSCLK_FLL; 2734 src = 1 << WM8962_SYSCLK_SRC_SHIFT; 2735 break; 2736 default: 2737 return -EINVAL; 2738 } 2739 2740 snd_soc_component_update_bits(component, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK, 2741 src); 2742 2743 wm8962->sysclk_rate = freq; 2744 2745 return 0; 2746 } 2747 2748 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2749 { 2750 struct snd_soc_component *component = dai->component; 2751 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2752 int aif0 = 0; 2753 2754 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2755 case SND_SOC_DAIFMT_DSP_B: 2756 aif0 |= WM8962_LRCLK_INV | 3; 2757 fallthrough; 2758 case SND_SOC_DAIFMT_DSP_A: 2759 aif0 |= 3; 2760 2761 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2762 case SND_SOC_DAIFMT_NB_NF: 2763 case SND_SOC_DAIFMT_IB_NF: 2764 break; 2765 default: 2766 return -EINVAL; 2767 } 2768 break; 2769 2770 case SND_SOC_DAIFMT_RIGHT_J: 2771 break; 2772 case SND_SOC_DAIFMT_LEFT_J: 2773 aif0 |= 1; 2774 break; 2775 case SND_SOC_DAIFMT_I2S: 2776 aif0 |= 2; 2777 break; 2778 default: 2779 return -EINVAL; 2780 } 2781 2782 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2783 case SND_SOC_DAIFMT_NB_NF: 2784 break; 2785 case SND_SOC_DAIFMT_IB_NF: 2786 aif0 |= WM8962_BCLK_INV; 2787 break; 2788 case SND_SOC_DAIFMT_NB_IF: 2789 aif0 |= WM8962_LRCLK_INV; 2790 break; 2791 case SND_SOC_DAIFMT_IB_IF: 2792 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV; 2793 break; 2794 default: 2795 return -EINVAL; 2796 } 2797 2798 wm8962->master_flag = false; 2799 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2800 case SND_SOC_DAIFMT_CBP_CFP: 2801 aif0 |= WM8962_MSTR; 2802 wm8962->master_flag = true; 2803 break; 2804 case SND_SOC_DAIFMT_CBC_CFC: 2805 break; 2806 default: 2807 return -EINVAL; 2808 } 2809 2810 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0, 2811 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR | 2812 WM8962_LRCLK_INV, aif0); 2813 2814 return 0; 2815 } 2816 2817 struct _fll_div { 2818 u16 fll_fratio; 2819 u16 fll_outdiv; 2820 u16 fll_refclk_div; 2821 u16 n; 2822 u16 theta; 2823 u16 lambda; 2824 }; 2825 2826 /* The size in bits of the FLL divide multiplied by 10 2827 * to allow rounding later */ 2828 #define FIXED_FLL_SIZE ((1 << 16) * 10) 2829 2830 static struct { 2831 unsigned int min; 2832 unsigned int max; 2833 u16 fll_fratio; 2834 int ratio; 2835 } fll_fratios[] = { 2836 { 0, 64000, 4, 16 }, 2837 { 64000, 128000, 3, 8 }, 2838 { 128000, 256000, 2, 4 }, 2839 { 256000, 1000000, 1, 2 }, 2840 { 1000000, 13500000, 0, 1 }, 2841 }; 2842 2843 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 2844 unsigned int Fout) 2845 { 2846 unsigned int target; 2847 unsigned int div; 2848 unsigned int fratio, gcd_fll; 2849 int i; 2850 2851 /* Fref must be <=13.5MHz */ 2852 div = 1; 2853 fll_div->fll_refclk_div = 0; 2854 while ((Fref / div) > 13500000) { 2855 div *= 2; 2856 fll_div->fll_refclk_div++; 2857 2858 if (div > 4) { 2859 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 2860 Fref); 2861 return -EINVAL; 2862 } 2863 } 2864 2865 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); 2866 2867 /* Apply the division for our remaining calculations */ 2868 Fref /= div; 2869 2870 /* Fvco should be 90-100MHz; don't check the upper bound */ 2871 div = 2; 2872 while (Fout * div < 90000000) { 2873 div++; 2874 if (div > 64) { 2875 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 2876 Fout); 2877 return -EINVAL; 2878 } 2879 } 2880 target = Fout * div; 2881 fll_div->fll_outdiv = div - 1; 2882 2883 pr_debug("FLL Fvco=%dHz\n", target); 2884 2885 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 2886 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 2887 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 2888 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 2889 fratio = fll_fratios[i].ratio; 2890 break; 2891 } 2892 } 2893 if (i == ARRAY_SIZE(fll_fratios)) { 2894 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 2895 return -EINVAL; 2896 } 2897 2898 fll_div->n = target / (fratio * Fref); 2899 2900 if (target % Fref == 0) { 2901 fll_div->theta = 0; 2902 fll_div->lambda = 1; 2903 } else { 2904 gcd_fll = gcd(target, fratio * Fref); 2905 2906 fll_div->theta = (target - (fll_div->n * fratio * Fref)) 2907 / gcd_fll; 2908 fll_div->lambda = (fratio * Fref) / gcd_fll; 2909 } 2910 2911 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", 2912 fll_div->n, fll_div->theta, fll_div->lambda); 2913 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", 2914 fll_div->fll_fratio, fll_div->fll_outdiv, 2915 fll_div->fll_refclk_div); 2916 2917 return 0; 2918 } 2919 2920 static int wm8962_set_fll(struct snd_soc_component *component, int fll_id, int source, 2921 unsigned int Fref, unsigned int Fout) 2922 { 2923 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 2924 struct _fll_div fll_div; 2925 unsigned long time_left; 2926 int ret; 2927 int fll1 = 0; 2928 2929 /* Any change? */ 2930 if (source == wm8962->fll_src && Fref == wm8962->fll_fref && 2931 Fout == wm8962->fll_fout) 2932 return 0; 2933 2934 if (Fout == 0) { 2935 dev_dbg(component->dev, "FLL disabled\n"); 2936 2937 wm8962->fll_fref = 0; 2938 wm8962->fll_fout = 0; 2939 2940 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, 2941 WM8962_FLL_ENA, 0); 2942 2943 pm_runtime_put(component->dev); 2944 2945 return 0; 2946 } 2947 2948 ret = fll_factors(&fll_div, Fref, Fout); 2949 if (ret != 0) 2950 return ret; 2951 2952 /* Parameters good, disable so we can reprogram */ 2953 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0); 2954 2955 switch (fll_id) { 2956 case WM8962_FLL_MCLK: 2957 case WM8962_FLL_BCLK: 2958 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; 2959 break; 2960 case WM8962_FLL_OSC: 2961 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; 2962 snd_soc_component_update_bits(component, WM8962_PLL2, 2963 WM8962_OSC_ENA, WM8962_OSC_ENA); 2964 break; 2965 case WM8962_FLL_INT: 2966 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, 2967 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA); 2968 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_5, 2969 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO); 2970 break; 2971 default: 2972 dev_err(component->dev, "Unknown FLL source %d\n", source); 2973 return -EINVAL; 2974 } 2975 2976 if (fll_div.theta) 2977 fll1 |= WM8962_FLL_FRAC; 2978 2979 /* Stop the FLL while we reconfigure */ 2980 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0); 2981 2982 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_2, 2983 WM8962_FLL_OUTDIV_MASK | 2984 WM8962_FLL_REFCLK_DIV_MASK, 2985 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) | 2986 (fll_div.fll_refclk_div)); 2987 2988 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_3, 2989 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio); 2990 2991 snd_soc_component_write(component, WM8962_FLL_CONTROL_6, fll_div.theta); 2992 snd_soc_component_write(component, WM8962_FLL_CONTROL_7, fll_div.lambda); 2993 snd_soc_component_write(component, WM8962_FLL_CONTROL_8, fll_div.n); 2994 2995 reinit_completion(&wm8962->fll_lock); 2996 2997 ret = pm_runtime_resume_and_get(component->dev); 2998 if (ret < 0) { 2999 dev_err(component->dev, "Failed to resume device: %d\n", ret); 3000 return ret; 3001 } 3002 3003 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, 3004 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK | 3005 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA); 3006 3007 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 3008 3009 /* This should be a massive overestimate but go even 3010 * higher if we'll error out 3011 */ 3012 if (wm8962->irq) 3013 time_left = msecs_to_jiffies(5); 3014 else 3015 time_left = msecs_to_jiffies(1); 3016 3017 time_left = wait_for_completion_timeout(&wm8962->fll_lock, 3018 time_left); 3019 3020 if (time_left == 0 && wm8962->irq) { 3021 dev_err(component->dev, "FLL lock timed out"); 3022 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, 3023 WM8962_FLL_ENA, 0); 3024 pm_runtime_put(component->dev); 3025 return -ETIMEDOUT; 3026 } 3027 3028 wm8962->fll_fref = Fref; 3029 wm8962->fll_fout = Fout; 3030 wm8962->fll_src = source; 3031 3032 return 0; 3033 } 3034 3035 static int wm8962_mute(struct snd_soc_dai *dai, int mute, int direction) 3036 { 3037 struct snd_soc_component *component = dai->component; 3038 int val, ret; 3039 3040 if (mute) 3041 val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT; 3042 else 3043 val = 0; 3044 3045 /** 3046 * The DAC mute bit is mirrored in two registers, update both to keep 3047 * the register cache consistent. 3048 */ 3049 ret = snd_soc_component_update_bits(component, WM8962_CLASS_D_CONTROL_1, 3050 WM8962_DAC_MUTE_ALT, val); 3051 if (ret < 0) 3052 return ret; 3053 3054 return snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1, 3055 WM8962_DAC_MUTE, val); 3056 } 3057 3058 #define WM8962_RATES (SNDRV_PCM_RATE_8000_48000 |\ 3059 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) 3060 3061 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 3062 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 3063 3064 static const struct snd_soc_dai_ops wm8962_dai_ops = { 3065 .hw_params = wm8962_hw_params, 3066 .set_sysclk = wm8962_set_dai_sysclk, 3067 .set_fmt = wm8962_set_dai_fmt, 3068 .set_tdm_slot = wm8962_set_tdm_slot, 3069 .mute_stream = wm8962_mute, 3070 .no_capture_mute = 1, 3071 }; 3072 3073 static struct snd_soc_dai_driver wm8962_dai = { 3074 .name = "wm8962", 3075 .playback = { 3076 .stream_name = "Playback", 3077 .channels_min = 1, 3078 .channels_max = 2, 3079 .rates = WM8962_RATES, 3080 .formats = WM8962_FORMATS, 3081 }, 3082 .capture = { 3083 .stream_name = "Capture", 3084 .channels_min = 1, 3085 .channels_max = 2, 3086 .rates = WM8962_RATES, 3087 .formats = WM8962_FORMATS, 3088 }, 3089 .ops = &wm8962_dai_ops, 3090 .symmetric_rate = 1, 3091 }; 3092 3093 static void wm8962_mic_work(struct work_struct *work) 3094 { 3095 struct wm8962_priv *wm8962 = container_of(work, 3096 struct wm8962_priv, 3097 mic_work.work); 3098 struct snd_soc_component *component = wm8962->component; 3099 int status = 0; 3100 int irq_pol = 0; 3101 int reg; 3102 3103 reg = snd_soc_component_read(component, WM8962_ADDITIONAL_CONTROL_4); 3104 3105 if (reg & WM8962_MICDET_STS) { 3106 status |= SND_JACK_MICROPHONE; 3107 irq_pol |= WM8962_MICD_IRQ_POL; 3108 } 3109 3110 if (reg & WM8962_MICSHORT_STS) { 3111 status |= SND_JACK_BTN_0; 3112 irq_pol |= WM8962_MICSCD_IRQ_POL; 3113 3114 /* Don't report a microphone if it's shorted right after 3115 * plugging in, as this may be a TRS plug in a TRRS socket. 3116 */ 3117 if (!(wm8962->mic_status & WM8962_MICDET_STS)) 3118 status = 0; 3119 } 3120 3121 wm8962->mic_status = status; 3122 3123 snd_soc_jack_report(wm8962->jack, status, 3124 SND_JACK_MICROPHONE | SND_JACK_BTN_0); 3125 3126 snd_soc_component_update_bits(component, WM8962_MICINT_SOURCE_POL, 3127 WM8962_MICSCD_IRQ_POL | 3128 WM8962_MICD_IRQ_POL, irq_pol); 3129 } 3130 3131 static irqreturn_t wm8962_irq(int irq, void *data) 3132 { 3133 struct device *dev = data; 3134 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3135 unsigned int mask; 3136 unsigned int active; 3137 int reg, ret; 3138 3139 ret = pm_runtime_resume_and_get(dev); 3140 if (ret < 0) { 3141 dev_err(dev, "Failed to resume: %d\n", ret); 3142 return IRQ_NONE; 3143 } 3144 3145 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK, 3146 &mask); 3147 if (ret != 0) { 3148 pm_runtime_put(dev); 3149 dev_err(dev, "Failed to read interrupt mask: %d\n", 3150 ret); 3151 return IRQ_NONE; 3152 } 3153 3154 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active); 3155 if (ret != 0) { 3156 pm_runtime_put(dev); 3157 dev_err(dev, "Failed to read interrupt: %d\n", ret); 3158 return IRQ_NONE; 3159 } 3160 3161 active &= ~mask; 3162 3163 if (!active) { 3164 pm_runtime_put(dev); 3165 return IRQ_NONE; 3166 } 3167 3168 /* Acknowledge the interrupts */ 3169 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active); 3170 if (ret != 0) 3171 dev_warn(dev, "Failed to ack interrupt: %d\n", ret); 3172 3173 if (active & WM8962_FLL_LOCK_EINT) { 3174 dev_dbg(dev, "FLL locked\n"); 3175 complete(&wm8962->fll_lock); 3176 } 3177 3178 if (active & WM8962_FIFOS_ERR_EINT) 3179 dev_err(dev, "FIFO error\n"); 3180 3181 if (active & WM8962_TEMP_SHUT_EINT) { 3182 dev_crit(dev, "Thermal shutdown\n"); 3183 3184 ret = regmap_read(wm8962->regmap, 3185 WM8962_THERMAL_SHUTDOWN_STATUS, ®); 3186 if (ret != 0) { 3187 dev_warn(dev, "Failed to read thermal status: %d\n", 3188 ret); 3189 reg = 0; 3190 } 3191 3192 if (reg & WM8962_TEMP_ERR_HP) 3193 dev_crit(dev, "Headphone thermal error\n"); 3194 if (reg & WM8962_TEMP_WARN_HP) 3195 dev_crit(dev, "Headphone thermal warning\n"); 3196 if (reg & WM8962_TEMP_ERR_SPK) 3197 dev_crit(dev, "Speaker thermal error\n"); 3198 if (reg & WM8962_TEMP_WARN_SPK) 3199 dev_crit(dev, "Speaker thermal warning\n"); 3200 } 3201 3202 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { 3203 dev_dbg(dev, "Microphone event detected\n"); 3204 3205 #ifndef CONFIG_SND_SOC_WM8962_MODULE 3206 trace_snd_soc_jack_irq(dev_name(dev)); 3207 #endif 3208 3209 pm_wakeup_event(dev, 300); 3210 3211 queue_delayed_work(system_power_efficient_wq, 3212 &wm8962->mic_work, 3213 msecs_to_jiffies(250)); 3214 } 3215 3216 pm_runtime_put(dev); 3217 3218 return IRQ_HANDLED; 3219 } 3220 3221 /** 3222 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ 3223 * 3224 * @component: WM8962 component 3225 * @jack: jack to report detection events on 3226 * 3227 * Enable microphone detection via IRQ on the WM8962. If GPIOs are 3228 * being used to bring out signals to the processor then only platform 3229 * data configuration is needed for WM8962 and processor GPIOs should 3230 * be configured using snd_soc_jack_add_gpios() instead. 3231 * 3232 * If no jack is supplied detection will be disabled. 3233 */ 3234 int wm8962_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack) 3235 { 3236 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3237 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3238 int irq_mask, enable; 3239 3240 wm8962->jack = jack; 3241 if (jack) { 3242 irq_mask = 0; 3243 enable = WM8962_MICDET_ENA; 3244 } else { 3245 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT; 3246 enable = 0; 3247 } 3248 3249 snd_soc_component_update_bits(component, WM8962_INTERRUPT_STATUS_2_MASK, 3250 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask); 3251 snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_4, 3252 WM8962_MICDET_ENA, enable); 3253 3254 /* Send an initial empty report */ 3255 snd_soc_jack_report(wm8962->jack, 0, 3256 SND_JACK_MICROPHONE | SND_JACK_BTN_0); 3257 3258 snd_soc_dapm_mutex_lock(dapm); 3259 3260 if (jack) { 3261 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK"); 3262 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 3263 } else { 3264 snd_soc_dapm_disable_pin_unlocked(dapm, "SYSCLK"); 3265 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 3266 } 3267 3268 snd_soc_dapm_mutex_unlock(dapm); 3269 3270 return 0; 3271 } 3272 EXPORT_SYMBOL_GPL(wm8962_mic_detect); 3273 3274 static int beep_rates[] = { 3275 500, 1000, 2000, 4000, 3276 }; 3277 3278 static void wm8962_beep_work(struct work_struct *work) 3279 { 3280 struct wm8962_priv *wm8962 = 3281 container_of(work, struct wm8962_priv, beep_work); 3282 struct snd_soc_component *component = wm8962->component; 3283 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3284 int i; 3285 int reg = 0; 3286 int best = 0; 3287 3288 if (wm8962->beep_rate) { 3289 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) { 3290 if (abs(wm8962->beep_rate - beep_rates[i]) < 3291 abs(wm8962->beep_rate - beep_rates[best])) 3292 best = i; 3293 } 3294 3295 dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n", 3296 beep_rates[best], wm8962->beep_rate); 3297 3298 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT); 3299 3300 snd_soc_dapm_enable_pin(dapm, "Beep"); 3301 } else { 3302 dev_dbg(component->dev, "Disabling beep\n"); 3303 snd_soc_dapm_disable_pin(dapm, "Beep"); 3304 } 3305 3306 snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, 3307 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg); 3308 3309 snd_soc_dapm_sync(dapm); 3310 } 3311 3312 /* For usability define a way of injecting beep events for the device - 3313 * many systems will not have a keyboard. 3314 */ 3315 static int wm8962_beep_event(struct input_dev *dev, unsigned int type, 3316 unsigned int code, int hz) 3317 { 3318 struct snd_soc_component *component = input_get_drvdata(dev); 3319 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3320 3321 dev_dbg(component->dev, "Beep event %x %x\n", code, hz); 3322 3323 switch (code) { 3324 case SND_BELL: 3325 if (hz) 3326 hz = 1000; 3327 fallthrough; 3328 case SND_TONE: 3329 break; 3330 default: 3331 return -1; 3332 } 3333 3334 /* Kick the beep from a workqueue */ 3335 wm8962->beep_rate = hz; 3336 schedule_work(&wm8962->beep_work); 3337 return 0; 3338 } 3339 3340 static ssize_t beep_store(struct device *dev, struct device_attribute *attr, 3341 const char *buf, size_t count) 3342 { 3343 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3344 long int time; 3345 int ret; 3346 3347 ret = kstrtol(buf, 10, &time); 3348 if (ret != 0) 3349 return ret; 3350 3351 input_event(wm8962->beep, EV_SND, SND_TONE, time); 3352 3353 return count; 3354 } 3355 3356 static DEVICE_ATTR_WO(beep); 3357 3358 static void wm8962_init_beep(struct snd_soc_component *component) 3359 { 3360 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3361 int ret; 3362 3363 wm8962->beep = devm_input_allocate_device(component->dev); 3364 if (!wm8962->beep) { 3365 dev_err(component->dev, "Failed to allocate beep device\n"); 3366 return; 3367 } 3368 3369 INIT_WORK(&wm8962->beep_work, wm8962_beep_work); 3370 wm8962->beep_rate = 0; 3371 3372 wm8962->beep->name = "WM8962 Beep Generator"; 3373 wm8962->beep->phys = dev_name(component->dev); 3374 wm8962->beep->id.bustype = BUS_I2C; 3375 3376 wm8962->beep->evbit[0] = BIT_MASK(EV_SND); 3377 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); 3378 wm8962->beep->event = wm8962_beep_event; 3379 wm8962->beep->dev.parent = component->dev; 3380 input_set_drvdata(wm8962->beep, component); 3381 3382 ret = input_register_device(wm8962->beep); 3383 if (ret != 0) { 3384 wm8962->beep = NULL; 3385 dev_err(component->dev, "Failed to register beep device\n"); 3386 } 3387 3388 ret = device_create_file(component->dev, &dev_attr_beep); 3389 if (ret != 0) { 3390 dev_err(component->dev, "Failed to create keyclick file: %d\n", 3391 ret); 3392 } 3393 } 3394 3395 static void wm8962_free_beep(struct snd_soc_component *component) 3396 { 3397 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3398 3399 device_remove_file(component->dev, &dev_attr_beep); 3400 cancel_work_sync(&wm8962->beep_work); 3401 wm8962->beep = NULL; 3402 3403 snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0); 3404 } 3405 3406 static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio) 3407 { 3408 int mask = 0; 3409 int val = 0; 3410 3411 /* Some of the GPIOs are behind MFP configuration and need to 3412 * be put into GPIO mode. */ 3413 switch (gpio) { 3414 case 2: 3415 mask = WM8962_CLKOUT2_SEL_MASK; 3416 val = 1 << WM8962_CLKOUT2_SEL_SHIFT; 3417 break; 3418 case 3: 3419 mask = WM8962_CLKOUT3_SEL_MASK; 3420 val = 1 << WM8962_CLKOUT3_SEL_SHIFT; 3421 break; 3422 default: 3423 break; 3424 } 3425 3426 if (mask) 3427 regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1, 3428 mask, val); 3429 } 3430 3431 #ifdef CONFIG_GPIOLIB 3432 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset) 3433 { 3434 struct wm8962_priv *wm8962 = gpiochip_get_data(chip); 3435 3436 /* The WM8962 GPIOs aren't linearly numbered. For simplicity 3437 * we export linear numbers and error out if the unsupported 3438 * ones are requsted. 3439 */ 3440 switch (offset + 1) { 3441 case 2: 3442 case 3: 3443 case 5: 3444 case 6: 3445 break; 3446 default: 3447 return -EINVAL; 3448 } 3449 3450 wm8962_set_gpio_mode(wm8962, offset + 1); 3451 3452 return 0; 3453 } 3454 3455 static int wm8962_gpio_set(struct gpio_chip *chip, unsigned int offset, 3456 int value) 3457 { 3458 struct wm8962_priv *wm8962 = gpiochip_get_data(chip); 3459 struct snd_soc_component *component = wm8962->component; 3460 3461 return snd_soc_component_update_bits(component, 3462 WM8962_GPIO_BASE + offset, 3463 WM8962_GP2_LVL, 3464 !!value << WM8962_GP2_LVL_SHIFT); 3465 } 3466 3467 static int wm8962_gpio_direction_out(struct gpio_chip *chip, 3468 unsigned offset, int value) 3469 { 3470 struct wm8962_priv *wm8962 = gpiochip_get_data(chip); 3471 struct snd_soc_component *component = wm8962->component; 3472 int ret, val; 3473 3474 /* Force function 1 (logic output) */ 3475 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT); 3476 3477 ret = snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset, 3478 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val); 3479 if (ret < 0) 3480 return ret; 3481 3482 return 0; 3483 } 3484 3485 static const struct gpio_chip wm8962_template_chip = { 3486 .label = "wm8962", 3487 .owner = THIS_MODULE, 3488 .request = wm8962_gpio_request, 3489 .direction_output = wm8962_gpio_direction_out, 3490 .set = wm8962_gpio_set, 3491 .can_sleep = 1, 3492 }; 3493 3494 static void wm8962_init_gpio(struct snd_soc_component *component) 3495 { 3496 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3497 struct wm8962_pdata *pdata = &wm8962->pdata; 3498 int ret; 3499 3500 wm8962->gpio_chip = wm8962_template_chip; 3501 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO; 3502 wm8962->gpio_chip.parent = component->dev; 3503 3504 if (pdata->gpio_base) 3505 wm8962->gpio_chip.base = pdata->gpio_base; 3506 else 3507 wm8962->gpio_chip.base = -1; 3508 3509 ret = gpiochip_add_data(&wm8962->gpio_chip, wm8962); 3510 if (ret != 0) 3511 dev_err(component->dev, "Failed to add GPIOs: %d\n", ret); 3512 } 3513 3514 static void wm8962_free_gpio(struct snd_soc_component *component) 3515 { 3516 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3517 3518 gpiochip_remove(&wm8962->gpio_chip); 3519 } 3520 #else 3521 static void wm8962_init_gpio(struct snd_soc_component *component) 3522 { 3523 } 3524 3525 static void wm8962_free_gpio(struct snd_soc_component *component) 3526 { 3527 } 3528 #endif 3529 3530 static int wm8962_probe(struct snd_soc_component *component) 3531 { 3532 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3533 int ret; 3534 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3535 int i; 3536 bool dmicclk, dmicdat; 3537 3538 wm8962->component = component; 3539 3540 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0; 3541 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1; 3542 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2; 3543 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3; 3544 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4; 3545 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5; 3546 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6; 3547 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7; 3548 3549 /* This should really be moved into the regulator core */ 3550 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) { 3551 ret = devm_regulator_register_notifier( 3552 wm8962->supplies[i].consumer, 3553 &wm8962->disable_nb[i]); 3554 if (ret != 0) { 3555 dev_err(component->dev, 3556 "Failed to register regulator notifier: %d\n", 3557 ret); 3558 } 3559 } 3560 3561 wm8962_add_widgets(component); 3562 3563 /* Save boards having to disable DMIC when not in use */ 3564 dmicclk = false; 3565 dmicdat = false; 3566 for (i = 1; i < WM8962_MAX_GPIO; i++) { 3567 /* 3568 * Register 515 (WM8962_GPIO_BASE + 3) does not exist, 3569 * so skip its access 3570 */ 3571 if (i == 3) 3572 continue; 3573 switch (snd_soc_component_read(component, WM8962_GPIO_BASE + i) 3574 & WM8962_GP2_FN_MASK) { 3575 case WM8962_GPIO_FN_DMICCLK: 3576 dmicclk = true; 3577 break; 3578 case WM8962_GPIO_FN_DMICDAT: 3579 dmicdat = true; 3580 break; 3581 default: 3582 break; 3583 } 3584 } 3585 if (!dmicclk || !dmicdat) { 3586 dev_dbg(component->dev, "DMIC not in use, disabling\n"); 3587 snd_soc_dapm_disable_pin(dapm, "DMICDAT"); 3588 } 3589 if (dmicclk != dmicdat) 3590 dev_warn(component->dev, "DMIC GPIOs partially configured\n"); 3591 3592 wm8962_init_beep(component); 3593 wm8962_init_gpio(component); 3594 3595 return 0; 3596 } 3597 3598 static void wm8962_remove(struct snd_soc_component *component) 3599 { 3600 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); 3601 3602 cancel_delayed_work_sync(&wm8962->mic_work); 3603 3604 wm8962_free_gpio(component); 3605 wm8962_free_beep(component); 3606 } 3607 3608 static const struct snd_soc_component_driver soc_component_dev_wm8962 = { 3609 .probe = wm8962_probe, 3610 .remove = wm8962_remove, 3611 .set_bias_level = wm8962_set_bias_level, 3612 .set_pll = wm8962_set_fll, 3613 .use_pmdown_time = 1, 3614 .endianness = 1, 3615 }; 3616 3617 /* Improve power consumption for IN4 DC measurement mode */ 3618 static const struct reg_sequence wm8962_dc_measure[] = { 3619 { 0xfd, 0x1 }, 3620 { 0xcc, 0x40 }, 3621 { 0xfd, 0 }, 3622 }; 3623 3624 static const struct regmap_config wm8962_regmap = { 3625 .reg_bits = 16, 3626 .val_bits = 16, 3627 3628 .max_register = WM8962_MAX_REGISTER, 3629 .reg_defaults = wm8962_reg, 3630 .num_reg_defaults = ARRAY_SIZE(wm8962_reg), 3631 .volatile_reg = wm8962_volatile_register, 3632 .readable_reg = wm8962_readable_register, 3633 .cache_type = REGCACHE_MAPLE, 3634 }; 3635 3636 static int wm8962_set_pdata_from_of(struct i2c_client *i2c, 3637 struct wm8962_pdata *pdata) 3638 { 3639 const struct device_node *np = i2c->dev.of_node; 3640 u32 val32; 3641 int i; 3642 3643 if (of_property_read_bool(np, "spk-mono")) 3644 pdata->spk_mono = true; 3645 3646 if (of_property_read_u32(np, "mic-cfg", &val32) >= 0) 3647 pdata->mic_cfg = val32; 3648 3649 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init, 3650 ARRAY_SIZE(pdata->gpio_init)) >= 0) 3651 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) { 3652 /* 3653 * The range of GPIO register value is [0x0, 0xffff] 3654 * While the default value of each register is 0x0 3655 * Any other value will be regarded as default value 3656 */ 3657 if (pdata->gpio_init[i] > 0xffff) 3658 pdata->gpio_init[i] = 0x0; 3659 } 3660 3661 pdata->mclk = devm_clk_get_optional(&i2c->dev, NULL); 3662 return PTR_ERR_OR_ZERO(pdata->mclk); 3663 } 3664 3665 static int wm8962_i2c_probe(struct i2c_client *i2c) 3666 { 3667 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev); 3668 struct wm8962_priv *wm8962; 3669 unsigned int reg; 3670 int ret, i, irq_pol, trigger; 3671 3672 wm8962 = devm_kzalloc(&i2c->dev, sizeof(*wm8962), GFP_KERNEL); 3673 if (wm8962 == NULL) 3674 return -ENOMEM; 3675 3676 mutex_init(&wm8962->dsp2_ena_lock); 3677 3678 i2c_set_clientdata(i2c, wm8962); 3679 3680 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work); 3681 init_completion(&wm8962->fll_lock); 3682 wm8962->irq = i2c->irq; 3683 3684 /* If platform data was supplied, update the default data in priv */ 3685 if (pdata) { 3686 memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata)); 3687 } else if (i2c->dev.of_node) { 3688 ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata); 3689 if (ret != 0) 3690 return ret; 3691 } 3692 3693 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) 3694 wm8962->supplies[i].supply = wm8962_supply_names[i]; 3695 3696 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies), 3697 wm8962->supplies); 3698 if (ret != 0) { 3699 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3700 goto err; 3701 } 3702 3703 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), 3704 wm8962->supplies); 3705 if (ret != 0) { 3706 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3707 return ret; 3708 } 3709 3710 wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap); 3711 if (IS_ERR(wm8962->regmap)) { 3712 ret = PTR_ERR(wm8962->regmap); 3713 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 3714 goto err_enable; 3715 } 3716 3717 /* 3718 * We haven't marked the chip revision as volatile due to 3719 * sharing a register with the right input volume; explicitly 3720 * bypass the cache to read it. 3721 */ 3722 regcache_cache_bypass(wm8962->regmap, true); 3723 3724 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, ®); 3725 if (ret < 0) { 3726 dev_err(&i2c->dev, "Failed to read ID register\n"); 3727 goto err_enable; 3728 } 3729 if (reg != 0x6243) { 3730 dev_err(&i2c->dev, 3731 "Device is not a WM8962, ID %x != 0x6243\n", reg); 3732 ret = -EINVAL; 3733 goto err_enable; 3734 } 3735 3736 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, ®); 3737 if (ret < 0) { 3738 dev_err(&i2c->dev, "Failed to read device revision: %d\n", 3739 ret); 3740 goto err_enable; 3741 } 3742 3743 dev_info(&i2c->dev, "customer id %x revision %c\n", 3744 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT, 3745 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT) 3746 + 'A'); 3747 3748 regcache_cache_bypass(wm8962->regmap, false); 3749 3750 ret = wm8962_reset(wm8962); 3751 if (ret < 0) { 3752 dev_err(&i2c->dev, "Failed to issue reset\n"); 3753 goto err_enable; 3754 } 3755 3756 /* SYSCLK defaults to on; make sure it is off so we can safely 3757 * write to registers if the device is declocked. 3758 */ 3759 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, 3760 WM8962_SYSCLK_ENA, 0); 3761 3762 /* Ensure we have soft control over all registers */ 3763 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, 3764 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD); 3765 3766 /* Ensure that the oscillator and PLLs are disabled */ 3767 regmap_update_bits(wm8962->regmap, WM8962_PLL2, 3768 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA, 3769 0); 3770 3771 /* Apply static configuration for GPIOs */ 3772 for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++) 3773 if (wm8962->pdata.gpio_init[i]) { 3774 wm8962_set_gpio_mode(wm8962, i + 1); 3775 regmap_write(wm8962->regmap, 0x200 + i, 3776 wm8962->pdata.gpio_init[i] & 0xffff); 3777 } 3778 3779 3780 /* Put the speakers into mono mode? */ 3781 if (wm8962->pdata.spk_mono) 3782 regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2, 3783 WM8962_SPK_MONO_MASK, WM8962_SPK_MONO); 3784 3785 /* Micbias setup, detection enable and detection 3786 * threasholds. */ 3787 if (wm8962->pdata.mic_cfg) 3788 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, 3789 WM8962_MICDET_ENA | 3790 WM8962_MICDET_THR_MASK | 3791 WM8962_MICSHORT_THR_MASK | 3792 WM8962_MICBIAS_LVL, 3793 wm8962->pdata.mic_cfg); 3794 3795 /* Latch volume update bits */ 3796 regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME, 3797 WM8962_IN_VU, WM8962_IN_VU); 3798 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, 3799 WM8962_IN_VU, WM8962_IN_VU); 3800 regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME, 3801 WM8962_ADC_VU, WM8962_ADC_VU); 3802 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME, 3803 WM8962_ADC_VU, WM8962_ADC_VU); 3804 regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME, 3805 WM8962_DAC_VU, WM8962_DAC_VU); 3806 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME, 3807 WM8962_DAC_VU, WM8962_DAC_VU); 3808 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME, 3809 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); 3810 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME, 3811 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); 3812 regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME, 3813 WM8962_HPOUT_VU, WM8962_HPOUT_VU); 3814 regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME, 3815 WM8962_HPOUT_VU, WM8962_HPOUT_VU); 3816 3817 /* Stereo control for EQ */ 3818 regmap_update_bits(wm8962->regmap, WM8962_EQ1, 3819 WM8962_EQ_SHARED_COEFF, 0); 3820 3821 /* Don't debouce interrupts so we don't need SYSCLK */ 3822 regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE, 3823 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB | 3824 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB, 3825 0); 3826 3827 if (wm8962->pdata.in4_dc_measure) { 3828 ret = regmap_register_patch(wm8962->regmap, 3829 wm8962_dc_measure, 3830 ARRAY_SIZE(wm8962_dc_measure)); 3831 if (ret != 0) 3832 dev_err(&i2c->dev, 3833 "Failed to configure for DC measurement: %d\n", 3834 ret); 3835 } 3836 3837 if (wm8962->irq) { 3838 if (wm8962->pdata.irq_active_low) { 3839 trigger = IRQF_TRIGGER_LOW; 3840 irq_pol = WM8962_IRQ_POL; 3841 } else { 3842 trigger = IRQF_TRIGGER_HIGH; 3843 irq_pol = 0; 3844 } 3845 3846 regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL, 3847 WM8962_IRQ_POL, irq_pol); 3848 3849 ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL, 3850 wm8962_irq, 3851 trigger | IRQF_ONESHOT, 3852 "wm8962", &i2c->dev); 3853 if (ret != 0) { 3854 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n", 3855 wm8962->irq, ret); 3856 wm8962->irq = 0; 3857 /* Non-fatal */ 3858 } else { 3859 /* Enable some IRQs by default */ 3860 regmap_update_bits(wm8962->regmap, 3861 WM8962_INTERRUPT_STATUS_2_MASK, 3862 WM8962_FLL_LOCK_EINT | 3863 WM8962_TEMP_SHUT_EINT | 3864 WM8962_FIFOS_ERR_EINT, 0); 3865 } 3866 } 3867 3868 pm_runtime_enable(&i2c->dev); 3869 pm_request_idle(&i2c->dev); 3870 3871 ret = devm_snd_soc_register_component(&i2c->dev, 3872 &soc_component_dev_wm8962, &wm8962_dai, 1); 3873 if (ret < 0) 3874 goto err_pm_runtime; 3875 3876 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, 3877 WM8962_TEMP_ENA_HP_MASK, 0); 3878 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, 3879 WM8962_TEMP_ENA_SPK_MASK, 0); 3880 3881 regcache_cache_only(wm8962->regmap, true); 3882 3883 /* The drivers should power up as needed */ 3884 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 3885 3886 return 0; 3887 3888 err_pm_runtime: 3889 pm_runtime_disable(&i2c->dev); 3890 err_enable: 3891 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 3892 err: 3893 return ret; 3894 } 3895 3896 static void wm8962_i2c_remove(struct i2c_client *client) 3897 { 3898 pm_runtime_disable(&client->dev); 3899 } 3900 3901 static int wm8962_runtime_resume(struct device *dev) 3902 { 3903 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3904 int ret; 3905 3906 ret = clk_prepare_enable(wm8962->pdata.mclk); 3907 if (ret) { 3908 dev_err(dev, "Failed to enable MCLK: %d\n", ret); 3909 return ret; 3910 } 3911 3912 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), 3913 wm8962->supplies); 3914 if (ret != 0) { 3915 dev_err(dev, "Failed to enable supplies: %d\n", ret); 3916 goto disable_clock; 3917 } 3918 3919 regcache_cache_only(wm8962->regmap, false); 3920 3921 wm8962_reset(wm8962); 3922 3923 regcache_mark_dirty(wm8962->regmap); 3924 3925 /* SYSCLK defaults to on; make sure it is off so we can safely 3926 * write to registers if the device is declocked. 3927 */ 3928 regmap_write_bits(wm8962->regmap, WM8962_CLOCKING2, 3929 WM8962_SYSCLK_ENA, 0); 3930 3931 /* Ensure we have soft control over all registers */ 3932 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, 3933 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD); 3934 3935 /* Ensure that the oscillator and PLLs are disabled */ 3936 regmap_update_bits(wm8962->regmap, WM8962_PLL2, 3937 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA, 3938 0); 3939 3940 regcache_sync(wm8962->regmap); 3941 3942 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP, 3943 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA, 3944 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA); 3945 3946 /* Bias enable at 2*5k (fast start-up) */ 3947 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1, 3948 WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK, 3949 WM8962_BIAS_ENA | 0x180); 3950 3951 if (wm8962->master_flag) 3952 regmap_update_bits(wm8962->regmap, WM8962_AUDIO_INTERFACE_0, 3953 WM8962_MSTR, WM8962_MSTR); 3954 msleep(5); 3955 3956 return 0; 3957 3958 disable_clock: 3959 clk_disable_unprepare(wm8962->pdata.mclk); 3960 return ret; 3961 } 3962 3963 static int wm8962_runtime_suspend(struct device *dev) 3964 { 3965 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3966 3967 if (wm8962->master_flag) 3968 regmap_update_bits(wm8962->regmap, WM8962_AUDIO_INTERFACE_0, 3969 WM8962_MSTR, 0); 3970 3971 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1, 3972 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0); 3973 3974 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP, 3975 WM8962_STARTUP_BIAS_ENA | 3976 WM8962_VMID_BUF_ENA, 0); 3977 3978 regcache_cache_only(wm8962->regmap, true); 3979 3980 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), 3981 wm8962->supplies); 3982 3983 clk_disable_unprepare(wm8962->pdata.mclk); 3984 3985 return 0; 3986 } 3987 3988 static const struct dev_pm_ops wm8962_pm = { 3989 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 3990 RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL) 3991 }; 3992 3993 static const struct i2c_device_id wm8962_i2c_id[] = { 3994 { "wm8962" }, 3995 { } 3996 }; 3997 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id); 3998 3999 static const struct of_device_id wm8962_of_match[] = { 4000 { .compatible = "wlf,wm8962", }, 4001 { } 4002 }; 4003 MODULE_DEVICE_TABLE(of, wm8962_of_match); 4004 4005 static struct i2c_driver wm8962_i2c_driver = { 4006 .driver = { 4007 .name = "wm8962", 4008 .of_match_table = wm8962_of_match, 4009 .pm = pm_ptr(&wm8962_pm), 4010 }, 4011 .probe = wm8962_i2c_probe, 4012 .remove = wm8962_i2c_remove, 4013 .id_table = wm8962_i2c_id, 4014 }; 4015 4016 module_i2c_driver(wm8962_i2c_driver); 4017 4018 MODULE_DESCRIPTION("ASoC WM8962 driver"); 4019 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 4020 MODULE_LICENSE("GPL"); 4021