1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ata_piix.c - Intel PATA/SATA controllers 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * Copyright header from piix.c: 13 * 14 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 15 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 16 * Copyright (C) 2003 Red Hat Inc 17 * 18 * libata documentation is available via 'make {ps|pdf}docs', 19 * as Documentation/driver-api/libata.rst 20 * 21 * Hardware documentation available at http://developer.intel.com/ 22 * 23 * Documentation 24 * Publicly available from Intel web site. Errata documentation 25 * is also publicly available. As an aide to anyone hacking on this 26 * driver the list of errata that are relevant is below, going back to 27 * PIIX4. Older device documentation is now a bit tricky to find. 28 * 29 * The chipsets all follow very much the same design. The original Triton 30 * series chipsets do _not_ support independent device timings, but this 31 * is fixed in Triton II. With the odd mobile exception the chips then 32 * change little except in gaining more modes until SATA arrives. This 33 * driver supports only the chips with independent timing (that is those 34 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 35 * for the early chip drivers. 36 * 37 * Errata of note: 38 * 39 * Unfixable 40 * PIIX4 errata #9 - Only on ultra obscure hw 41 * ICH3 errata #13 - Not observed to affect real hw 42 * by Intel 43 * 44 * Things we must deal with 45 * PIIX4 errata #10 - BM IDE hang with non UDMA 46 * (must stop/start dma to recover) 47 * 440MX errata #15 - As PIIX4 errata #10 48 * PIIX4 errata #15 - Must not read control registers 49 * during a PIO transfer 50 * 440MX errata #13 - As PIIX4 errata #15 51 * ICH2 errata #21 - DMA mode 0 doesn't work right 52 * ICH0/1 errata #55 - As ICH2 errata #21 53 * ICH2 spec c #9 - Extra operations needed to handle 54 * drive hotswap [NOT YET SUPPORTED] 55 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 56 * and must be dword aligned 57 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 58 * ICH7 errata #16 - MWDMA1 timings are incorrect 59 * 60 * Should have been BIOS fixed: 61 * 450NX: errata #19 - DMA hangs on old 450NX 62 * 450NX: errata #20 - DMA hangs on old 450NX 63 * 450NX: errata #25 - Corruption with DMA on old 450NX 64 * ICH3 errata #15 - IDE deadlock under high load 65 * (BIOS must set dev 31 fn 0 bit 23) 66 * ICH3 errata #18 - Don't use native mode 67 */ 68 69 #include <linux/kernel.h> 70 #include <linux/module.h> 71 #include <linux/pci.h> 72 #include <linux/init.h> 73 #include <linux/blkdev.h> 74 #include <linux/delay.h> 75 #include <linux/device.h> 76 #include <linux/gfp.h> 77 #include <scsi/scsi_host.h> 78 #include <linux/libata.h> 79 #include <linux/dmi.h> 80 #include <trace/events/libata.h> 81 82 #define DRV_NAME "ata_piix" 83 #define DRV_VERSION "2.13" 84 85 enum { 86 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 87 ICH5_PMR = 0x90, /* address map register */ 88 ICH5_PCS = 0x92, /* port control and status */ 89 PIIX_SIDPR_BAR = 5, 90 PIIX_SIDPR_LEN = 16, 91 PIIX_SIDPR_IDX = 0, 92 PIIX_SIDPR_DATA = 4, 93 94 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 95 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ 96 97 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 98 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 99 100 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/ 101 102 PIIX_80C_PRI = (1 << 5) | (1 << 4), 103 PIIX_80C_SEC = (1 << 7) | (1 << 6), 104 105 /* constants for mapping table */ 106 P0 = 0, /* port 0 */ 107 P1 = 1, /* port 1 */ 108 P2 = 2, /* port 2 */ 109 P3 = 3, /* port 3 */ 110 IDE = -1, /* IDE */ 111 NA = -2, /* not available */ 112 RV = -3, /* reserved */ 113 114 PIIX_AHCI_DEVICE = 6, 115 116 /* host->flags bits */ 117 PIIX_HOST_BROKEN_SUSPEND = (1 << 24), 118 }; 119 120 enum piix_controller_ids { 121 /* controller IDs */ 122 piix_pata_mwdma, /* PIIX3 MWDMA only */ 123 piix_pata_33, /* PIIX4 at 33Mhz */ 124 ich_pata_33, /* ICH up to UDMA 33 only */ 125 ich_pata_66, /* ICH up to 66 Mhz */ 126 ich_pata_100, /* ICH up to UDMA 100 */ 127 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/ 128 ich5_sata, 129 ich6_sata, 130 ich6m_sata, 131 ich8_sata, 132 ich8_2port_sata, 133 ich8m_apple_sata, /* locks up on second port enable */ 134 tolapai_sata, 135 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ 136 ich8_sata_snb, 137 ich8_2port_sata_snb, 138 ich8_2port_sata_byt, 139 }; 140 141 struct piix_map_db { 142 const u32 mask; 143 const u16 port_enable; 144 const int map[][4]; 145 }; 146 147 struct piix_host_priv { 148 const int *map; 149 u32 saved_iocfg; 150 void __iomem *sidpr; 151 }; 152 153 static unsigned int in_module_init = 1; 154 155 static const struct pci_device_id piix_pci_tbl[] = { 156 /* Intel PIIX3 for the 430HX etc */ 157 { 158 PCI_DEVICE(0x8086, 0x7010), 159 .driver_data = piix_pata_mwdma, 160 }, { 161 /* VMware ICH4 */ 162 PCI_DEVICE_SUB(0x8086, 0x7111, 0x15ad, 0x1976), 163 .driver_data = piix_pata_vmw, 164 }, { 165 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 166 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 167 PCI_DEVICE(0x8086, 0x7111), 168 .driver_data = piix_pata_33, 169 }, { 170 /* Intel PIIX4 */ 171 PCI_DEVICE(0x8086, 0x7199), 172 .driver_data = piix_pata_33, 173 }, { 174 /* Intel PIIX4 */ 175 PCI_DEVICE(0x8086, 0x7601), 176 .driver_data = piix_pata_33, 177 }, { 178 /* Intel PIIX */ 179 PCI_DEVICE(0x8086, 0x84CA), 180 .driver_data = piix_pata_33, 181 }, { 182 /* Intel ICH (i810, i815, i840) UDMA 66*/ 183 PCI_DEVICE(0x8086, 0x2411), 184 .driver_data = ich_pata_66, 185 }, { 186 /* Intel ICH0 : UDMA 33*/ 187 PCI_DEVICE(0x8086, 0x2421), 188 .driver_data = ich_pata_33, 189 }, { 190 /* Intel ICH2M */ 191 PCI_DEVICE(0x8086, 0x244A), 192 .driver_data = ich_pata_100, 193 }, { 194 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 195 PCI_DEVICE(0x8086, 0x244B), 196 .driver_data = ich_pata_100, 197 }, { 198 /* Intel ICH3M */ 199 PCI_DEVICE(0x8086, 0x248A), 200 .driver_data = ich_pata_100, 201 }, { 202 /* Intel ICH3 (E7500/1) UDMA 100 */ 203 PCI_DEVICE(0x8086, 0x248B), 204 .driver_data = ich_pata_100, 205 }, { 206 /* Intel ICH4-L */ 207 PCI_DEVICE(0x8086, 0x24C1), 208 .driver_data = ich_pata_100, 209 }, { 210 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 211 PCI_DEVICE(0x8086, 0x24CA), 212 .driver_data = ich_pata_100, 213 }, { 214 PCI_DEVICE(0x8086, 0x24CB), 215 .driver_data = ich_pata_100, 216 }, { 217 /* Intel ICH5 */ 218 PCI_DEVICE(0x8086, 0x24DB), 219 .driver_data = ich_pata_100, 220 }, { 221 /* C-ICH (i810E2) */ 222 PCI_DEVICE(0x8086, 0x245B), 223 .driver_data = ich_pata_100, 224 }, { 225 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 226 PCI_DEVICE(0x8086, 0x25A2), 227 .driver_data = ich_pata_100, 228 }, { 229 /* ICH6 (and 6) (i915) UDMA 100 */ 230 PCI_DEVICE(0x8086, 0x266F), 231 .driver_data = ich_pata_100, 232 }, { 233 /* ICH7/7-R (i945, i975) UDMA 100*/ 234 PCI_DEVICE(0x8086, 0x27DF), 235 .driver_data = ich_pata_100_nomwdma1, 236 }, { 237 PCI_DEVICE(0x8086, 0x269E), 238 .driver_data = ich_pata_100_nomwdma1, 239 }, { 240 /* ICH8 Mobile PATA Controller */ 241 PCI_DEVICE(0x8086, 0x2850), 242 .driver_data = ich_pata_100, 243 }, 244 245 /* SATA ports */ 246 { 247 /* 82801EB (ICH5) */ 248 PCI_DEVICE(0x8086, 0x24d1), 249 .driver_data = ich5_sata, 250 }, { 251 /* 82801EB (ICH5) */ 252 PCI_DEVICE(0x8086, 0x24df), 253 .driver_data = ich5_sata, 254 }, { 255 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 256 PCI_DEVICE(0x8086, 0x25a3), 257 .driver_data = ich5_sata, 258 }, { 259 /* 6300ESB pretending RAID */ 260 PCI_DEVICE(0x8086, 0x25b0), 261 .driver_data = ich5_sata, 262 }, { 263 /* 82801FB/FW (ICH6/ICH6W) */ 264 PCI_DEVICE(0x8086, 0x2651), 265 .driver_data = ich6_sata, 266 }, { 267 /* 82801FR/FRW (ICH6R/ICH6RW) */ 268 PCI_DEVICE(0x8086, 0x2652), 269 .driver_data = ich6_sata, 270 }, { 271 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). 272 * Attach iff the controller is in IDE mode. */ 273 PCI_DEVICE(0x8086, 0x2653), 274 .class = PCI_CLASS_STORAGE_IDE << 8, 275 .class_mask = 0xffff00, 276 .driver_data = ich6m_sata, 277 }, { 278 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 279 PCI_DEVICE(0x8086, 0x27c0), 280 .driver_data = ich6_sata, 281 }, { 282 /* 82801GBM/GHM (ICH7M, identical to ICH6M) */ 283 PCI_DEVICE(0x8086, 0x27c4), 284 .driver_data = ich6m_sata, 285 }, { 286 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 287 PCI_DEVICE(0x8086, 0x2680), 288 .driver_data = ich6_sata, 289 }, { 290 /* SATA Controller 1 IDE (ICH8) */ 291 PCI_DEVICE(0x8086, 0x2820), 292 .driver_data = ich8_sata, 293 }, { 294 /* SATA Controller 2 IDE (ICH8) */ 295 PCI_DEVICE(0x8086, 0x2825), 296 .driver_data = ich8_2port_sata, 297 }, { 298 /* Mobile SATA Controller IDE (ICH8M), Apple */ 299 PCI_DEVICE_SUB(0x8086, 0x2828, 0x106b, 0x00a0), 300 .driver_data = ich8m_apple_sata, 301 }, { 302 PCI_DEVICE_SUB(0x8086, 0x2828, 0x106b, 0x00a1), 303 .driver_data = ich8m_apple_sata, 304 }, { 305 PCI_DEVICE_SUB(0x8086, 0x2828, 0x106b, 0x00a3), 306 .driver_data = ich8m_apple_sata, 307 }, { 308 /* Mobile SATA Controller IDE (ICH8M) */ 309 PCI_DEVICE(0x8086, 0x2828), 310 .driver_data = ich8_sata, 311 }, { 312 /* SATA Controller IDE (ICH9) */ 313 PCI_DEVICE(0x8086, 0x2920), 314 .driver_data = ich8_sata, 315 }, { 316 /* SATA Controller IDE (ICH9) */ 317 PCI_DEVICE(0x8086, 0x2921), 318 .driver_data = ich8_2port_sata, 319 }, { 320 /* SATA Controller IDE (ICH9) */ 321 PCI_DEVICE(0x8086, 0x2926), 322 .driver_data = ich8_2port_sata, 323 }, { 324 /* SATA Controller IDE (ICH9M) */ 325 PCI_DEVICE(0x8086, 0x2928), 326 .driver_data = ich8_2port_sata, 327 }, { 328 /* SATA Controller IDE (ICH9M) */ 329 PCI_DEVICE(0x8086, 0x292d), 330 .driver_data = ich8_2port_sata, 331 }, { 332 /* SATA Controller IDE (ICH9M) */ 333 PCI_DEVICE(0x8086, 0x292e), 334 .driver_data = ich8_sata, 335 }, { 336 /* SATA Controller IDE (Tolapai) */ 337 PCI_DEVICE(0x8086, 0x5028), 338 .driver_data = tolapai_sata, 339 }, { 340 /* SATA Controller IDE (ICH10) */ 341 PCI_DEVICE(0x8086, 0x3a00), 342 .driver_data = ich8_sata, 343 }, { 344 /* SATA Controller IDE (ICH10) */ 345 PCI_DEVICE(0x8086, 0x3a06), 346 .driver_data = ich8_2port_sata, 347 }, { 348 /* SATA Controller IDE (ICH10) */ 349 PCI_DEVICE(0x8086, 0x3a20), 350 .driver_data = ich8_sata, 351 }, { 352 /* SATA Controller IDE (ICH10) */ 353 PCI_DEVICE(0x8086, 0x3a26), 354 .driver_data = ich8_2port_sata, 355 }, { 356 /* SATA Controller IDE (PCH) */ 357 PCI_DEVICE(0x8086, 0x3b20), 358 .driver_data = ich8_sata, 359 }, { 360 /* SATA Controller IDE (PCH) */ 361 PCI_DEVICE(0x8086, 0x3b21), 362 .driver_data = ich8_2port_sata, 363 }, { 364 /* SATA Controller IDE (PCH) */ 365 PCI_DEVICE(0x8086, 0x3b26), 366 .driver_data = ich8_2port_sata, 367 }, { 368 /* SATA Controller IDE (PCH) */ 369 PCI_DEVICE(0x8086, 0x3b28), 370 .driver_data = ich8_sata, 371 }, { 372 /* SATA Controller IDE (PCH) */ 373 PCI_DEVICE(0x8086, 0x3b2d), 374 .driver_data = ich8_2port_sata, 375 }, { 376 /* SATA Controller IDE (PCH) */ 377 PCI_DEVICE(0x8086, 0x3b2e), 378 .driver_data = ich8_sata, 379 }, { 380 /* SATA Controller IDE (CPT) */ 381 PCI_DEVICE(0x8086, 0x1c00), 382 .driver_data = ich8_sata_snb, 383 }, { 384 /* SATA Controller IDE (CPT) */ 385 PCI_DEVICE(0x8086, 0x1c01), 386 .driver_data = ich8_sata_snb, 387 }, { 388 /* SATA Controller IDE (CPT) */ 389 PCI_DEVICE(0x8086, 0x1c08), 390 .driver_data = ich8_2port_sata, 391 }, { 392 /* SATA Controller IDE (CPT) */ 393 PCI_DEVICE(0x8086, 0x1c09), 394 .driver_data = ich8_2port_sata, 395 }, { 396 /* SATA Controller IDE (PBG) */ 397 PCI_DEVICE(0x8086, 0x1d00), 398 .driver_data = ich8_sata_snb, 399 }, { 400 /* SATA Controller IDE (PBG) */ 401 PCI_DEVICE(0x8086, 0x1d08), 402 .driver_data = ich8_2port_sata, 403 }, { 404 /* SATA Controller IDE (Panther Point) */ 405 PCI_DEVICE(0x8086, 0x1e00), 406 .driver_data = ich8_sata_snb, 407 }, { 408 /* SATA Controller IDE (Panther Point) */ 409 PCI_DEVICE(0x8086, 0x1e01), 410 .driver_data = ich8_sata_snb, 411 }, { 412 /* SATA Controller IDE (Panther Point) */ 413 PCI_DEVICE(0x8086, 0x1e08), 414 .driver_data = ich8_2port_sata, 415 }, { 416 /* SATA Controller IDE (Panther Point) */ 417 PCI_DEVICE(0x8086, 0x1e09), 418 .driver_data = ich8_2port_sata, 419 }, { 420 /* SATA Controller IDE (Lynx Point) */ 421 PCI_DEVICE(0x8086, 0x8c00), 422 .driver_data = ich8_sata_snb, 423 }, { 424 /* SATA Controller IDE (Lynx Point) */ 425 PCI_DEVICE(0x8086, 0x8c01), 426 .driver_data = ich8_sata_snb, 427 }, { 428 /* SATA Controller IDE (Lynx Point) */ 429 PCI_DEVICE(0x8086, 0x8c08), 430 .driver_data = ich8_2port_sata_snb, 431 }, { 432 /* SATA Controller IDE (Lynx Point) */ 433 PCI_DEVICE(0x8086, 0x8c09), 434 .driver_data = ich8_2port_sata, 435 }, { 436 /* SATA Controller IDE (Lynx Point-LP) */ 437 PCI_DEVICE(0x8086, 0x9c00), 438 .driver_data = ich8_sata_snb, 439 }, { 440 /* SATA Controller IDE (Lynx Point-LP) */ 441 PCI_DEVICE(0x8086, 0x9c01), 442 .driver_data = ich8_sata_snb, 443 }, { 444 /* SATA Controller IDE (Lynx Point-LP) */ 445 PCI_DEVICE(0x8086, 0x9c08), 446 .driver_data = ich8_2port_sata, 447 }, { 448 /* SATA Controller IDE (Lynx Point-LP) */ 449 PCI_DEVICE(0x8086, 0x9c09), 450 .driver_data = ich8_2port_sata, 451 }, { 452 /* SATA Controller IDE (DH89xxCC) */ 453 PCI_DEVICE(0x8086, 0x2326), 454 .driver_data = ich8_2port_sata, 455 }, { 456 /* SATA Controller IDE (Avoton) */ 457 PCI_DEVICE(0x8086, 0x1f20), 458 .driver_data = ich8_sata_snb, 459 }, { 460 /* SATA Controller IDE (Avoton) */ 461 PCI_DEVICE(0x8086, 0x1f21), 462 .driver_data = ich8_sata_snb, 463 }, { 464 /* SATA Controller IDE (Avoton) */ 465 PCI_DEVICE(0x8086, 0x1f30), 466 .driver_data = ich8_2port_sata, 467 }, { 468 /* SATA Controller IDE (Avoton) */ 469 PCI_DEVICE(0x8086, 0x1f31), 470 .driver_data = ich8_2port_sata, 471 }, { 472 /* SATA Controller IDE (Wellsburg) */ 473 PCI_DEVICE(0x8086, 0x8d00), 474 .driver_data = ich8_sata_snb, 475 }, { 476 /* SATA Controller IDE (Wellsburg) */ 477 PCI_DEVICE(0x8086, 0x8d08), 478 .driver_data = ich8_2port_sata_snb, 479 }, { 480 /* SATA Controller IDE (Wellsburg) */ 481 PCI_DEVICE(0x8086, 0x8d60), 482 .driver_data = ich8_sata_snb, 483 }, { 484 /* SATA Controller IDE (Wellsburg) */ 485 PCI_DEVICE(0x8086, 0x8d68), 486 .driver_data = ich8_2port_sata, 487 }, { 488 /* SATA Controller IDE (BayTrail) */ 489 PCI_DEVICE(0x8086, 0x0F20), 490 .driver_data = ich8_2port_sata_byt, 491 }, { 492 PCI_DEVICE(0x8086, 0x0F21), 493 .driver_data = ich8_2port_sata_byt, 494 }, { 495 /* SATA Controller IDE (Coleto Creek) */ 496 PCI_DEVICE(0x8086, 0x23a6), 497 .driver_data = ich8_2port_sata, 498 }, { 499 /* SATA Controller IDE (9 Series) */ 500 PCI_DEVICE(0x8086, 0x8c88), 501 .driver_data = ich8_2port_sata_snb, 502 }, { 503 /* SATA Controller IDE (9 Series) */ 504 PCI_DEVICE(0x8086, 0x8c89), 505 .driver_data = ich8_2port_sata_snb, 506 }, { 507 /* SATA Controller IDE (9 Series) */ 508 PCI_DEVICE(0x8086, 0x8c80), 509 .driver_data = ich8_sata_snb, 510 }, { 511 /* SATA Controller IDE (9 Series) */ 512 PCI_DEVICE(0x8086, 0x8c81), 513 .driver_data = ich8_sata_snb, 514 }, 515 516 { } /* terminate list */ 517 }; 518 519 static const struct piix_map_db ich5_map_db = { 520 .mask = 0x7, 521 .port_enable = 0x3, 522 .map = { 523 /* PM PS SM SS MAP */ 524 { P0, NA, P1, NA }, /* 000b */ 525 { P1, NA, P0, NA }, /* 001b */ 526 { RV, RV, RV, RV }, 527 { RV, RV, RV, RV }, 528 { P0, P1, IDE, IDE }, /* 100b */ 529 { P1, P0, IDE, IDE }, /* 101b */ 530 { IDE, IDE, P0, P1 }, /* 110b */ 531 { IDE, IDE, P1, P0 }, /* 111b */ 532 }, 533 }; 534 535 static const struct piix_map_db ich6_map_db = { 536 .mask = 0x3, 537 .port_enable = 0xf, 538 .map = { 539 /* PM PS SM SS MAP */ 540 { P0, P2, P1, P3 }, /* 00b */ 541 { IDE, IDE, P1, P3 }, /* 01b */ 542 { P0, P2, IDE, IDE }, /* 10b */ 543 { RV, RV, RV, RV }, 544 }, 545 }; 546 547 static const struct piix_map_db ich6m_map_db = { 548 .mask = 0x3, 549 .port_enable = 0x5, 550 551 /* Map 01b isn't specified in the doc but some notebooks use 552 * it anyway. MAP 01b have been spotted on both ICH6M and 553 * ICH7M. 554 */ 555 .map = { 556 /* PM PS SM SS MAP */ 557 { P0, P2, NA, NA }, /* 00b */ 558 { IDE, IDE, P1, P3 }, /* 01b */ 559 { P0, P2, IDE, IDE }, /* 10b */ 560 { RV, RV, RV, RV }, 561 }, 562 }; 563 564 static const struct piix_map_db ich8_map_db = { 565 .mask = 0x3, 566 .port_enable = 0xf, 567 .map = { 568 /* PM PS SM SS MAP */ 569 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 570 { RV, RV, RV, RV }, 571 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ 572 { RV, RV, RV, RV }, 573 }, 574 }; 575 576 static const struct piix_map_db ich8_2port_map_db = { 577 .mask = 0x3, 578 .port_enable = 0x3, 579 .map = { 580 /* PM PS SM SS MAP */ 581 { P0, NA, P1, NA }, /* 00b */ 582 { RV, RV, RV, RV }, /* 01b */ 583 { RV, RV, RV, RV }, /* 10b */ 584 { RV, RV, RV, RV }, 585 }, 586 }; 587 588 static const struct piix_map_db ich8m_apple_map_db = { 589 .mask = 0x3, 590 .port_enable = 0x1, 591 .map = { 592 /* PM PS SM SS MAP */ 593 { P0, NA, NA, NA }, /* 00b */ 594 { RV, RV, RV, RV }, 595 { P0, P2, IDE, IDE }, /* 10b */ 596 { RV, RV, RV, RV }, 597 }, 598 }; 599 600 static const struct piix_map_db tolapai_map_db = { 601 .mask = 0x3, 602 .port_enable = 0x3, 603 .map = { 604 /* PM PS SM SS MAP */ 605 { P0, NA, P1, NA }, /* 00b */ 606 { RV, RV, RV, RV }, /* 01b */ 607 { RV, RV, RV, RV }, /* 10b */ 608 { RV, RV, RV, RV }, 609 }, 610 }; 611 612 static const struct piix_map_db *piix_map_db_table[] = { 613 [ich5_sata] = &ich5_map_db, 614 [ich6_sata] = &ich6_map_db, 615 [ich6m_sata] = &ich6m_map_db, 616 [ich8_sata] = &ich8_map_db, 617 [ich8_2port_sata] = &ich8_2port_map_db, 618 [ich8m_apple_sata] = &ich8m_apple_map_db, 619 [tolapai_sata] = &tolapai_map_db, 620 [ich8_sata_snb] = &ich8_map_db, 621 [ich8_2port_sata_snb] = &ich8_2port_map_db, 622 [ich8_2port_sata_byt] = &ich8_2port_map_db, 623 }; 624 625 static const struct pci_bits piix_enable_bits[] = { 626 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 627 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 628 }; 629 630 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 631 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 632 MODULE_LICENSE("GPL"); 633 MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 634 MODULE_VERSION(DRV_VERSION); 635 636 struct ich_laptop { 637 u16 device; 638 u16 subvendor; 639 u16 subdevice; 640 }; 641 642 /* 643 * List of laptops that use short cables rather than 80 wire 644 */ 645 646 static const struct ich_laptop ich_laptop[] = { 647 /* devid, subvendor, subdev */ 648 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 649 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ 650 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 651 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */ 652 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 653 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 654 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */ 655 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */ 656 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */ 657 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 658 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ 659 { 0x24CA, 0x10CF, 0x11AB }, /* ICH4M on Fujitsu-Siemens Lifebook S6120 */ 660 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ 661 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ 662 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */ 663 /* end marker */ 664 { 0, } 665 }; 666 667 static int piix_port_start(struct ata_port *ap) 668 { 669 if (!(ap->flags & PIIX_FLAG_PIO16)) 670 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; 671 672 return ata_bmdma_port_start(ap); 673 } 674 675 /** 676 * ich_pata_cable_detect - Probe host controller cable detect info 677 * @ap: Port for which cable detect info is desired 678 * 679 * Read 80c cable indicator from ATA PCI device's PCI config 680 * register. This register is normally set by firmware (BIOS). 681 * 682 * LOCKING: 683 * None (inherited from caller). 684 */ 685 686 static int ich_pata_cable_detect(struct ata_port *ap) 687 { 688 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 689 struct piix_host_priv *hpriv = ap->host->private_data; 690 const struct ich_laptop *lap = &ich_laptop[0]; 691 u8 mask; 692 693 /* Check for specials */ 694 while (lap->device) { 695 if (lap->device == pdev->device && 696 lap->subvendor == pdev->subsystem_vendor && 697 lap->subdevice == pdev->subsystem_device) 698 return ATA_CBL_PATA40_SHORT; 699 700 lap++; 701 } 702 703 /* check BIOS cable detect results */ 704 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 705 if ((hpriv->saved_iocfg & mask) == 0) 706 return ATA_CBL_PATA40; 707 return ATA_CBL_PATA80; 708 } 709 710 /** 711 * piix_pata_prereset - prereset for PATA host controller 712 * @link: Target link 713 * @deadline: deadline jiffies for the operation 714 * 715 * LOCKING: 716 * None (inherited from caller). 717 */ 718 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) 719 { 720 struct ata_port *ap = link->ap; 721 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 722 723 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 724 return -ENOENT; 725 return ata_sff_prereset(link, deadline); 726 } 727 728 static DEFINE_SPINLOCK(piix_lock); 729 730 static void piix_set_timings(struct ata_port *ap, struct ata_device *adev, 731 u8 pio) 732 { 733 struct pci_dev *dev = to_pci_dev(ap->host->dev); 734 unsigned long flags; 735 unsigned int is_slave = (adev->devno != 0); 736 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 737 unsigned int slave_port = 0x44; 738 u16 master_data; 739 u8 slave_data; 740 u8 udma_enable; 741 int control = 0; 742 743 /* 744 * See Intel Document 298600-004 for the timing programing rules 745 * for ICH controllers. 746 */ 747 748 static const /* ISP RTC */ 749 u8 timings[][2] = { { 0, 0 }, 750 { 0, 0 }, 751 { 1, 0 }, 752 { 2, 1 }, 753 { 2, 3 }, }; 754 755 if (pio >= 2) 756 control |= 1; /* TIME1 enable */ 757 if (ata_pio_need_iordy(adev)) 758 control |= 2; /* IE enable */ 759 /* Intel specifies that the PPE functionality is for disk only */ 760 if (adev->class == ATA_DEV_ATA) 761 control |= 4; /* PPE enable */ 762 /* 763 * If the drive MWDMA is faster than it can do PIO then 764 * we must force PIO into PIO0 765 */ 766 if (adev->pio_mode < XFER_PIO_0 + pio) 767 /* Enable DMA timing only */ 768 control |= 8; /* PIO cycles in PIO0 */ 769 770 spin_lock_irqsave(&piix_lock, flags); 771 772 /* PIO configuration clears DTE unconditionally. It will be 773 * programmed in set_dmamode which is guaranteed to be called 774 * after set_piomode if any DMA mode is available. 775 */ 776 pci_read_config_word(dev, master_port, &master_data); 777 if (is_slave) { 778 /* clear TIME1|IE1|PPE1|DTE1 */ 779 master_data &= 0xff0f; 780 /* enable PPE1, IE1 and TIME1 as needed */ 781 master_data |= (control << 4); 782 pci_read_config_byte(dev, slave_port, &slave_data); 783 slave_data &= (ap->port_no ? 0x0f : 0xf0); 784 /* Load the timing nibble for this slave */ 785 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 786 << (ap->port_no ? 4 : 0); 787 } else { 788 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 789 master_data &= 0xccf0; 790 /* Enable PPE, IE and TIME as appropriate */ 791 master_data |= control; 792 /* load ISP and RCT */ 793 master_data |= 794 (timings[pio][0] << 12) | 795 (timings[pio][1] << 8); 796 } 797 798 /* Enable SITRE (separate slave timing register) */ 799 master_data |= 0x4000; 800 pci_write_config_word(dev, master_port, master_data); 801 if (is_slave) 802 pci_write_config_byte(dev, slave_port, slave_data); 803 804 /* Ensure the UDMA bit is off - it will be turned back on if 805 UDMA is selected */ 806 807 if (ap->udma_mask) { 808 pci_read_config_byte(dev, 0x48, &udma_enable); 809 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 810 pci_write_config_byte(dev, 0x48, udma_enable); 811 } 812 813 spin_unlock_irqrestore(&piix_lock, flags); 814 } 815 816 /** 817 * piix_set_piomode - Initialize host controller PATA PIO timings 818 * @ap: Port whose timings we are configuring 819 * @adev: Drive in question 820 * 821 * Set PIO mode for device, in host controller PCI config space. 822 * 823 * LOCKING: 824 * None (inherited from caller). 825 */ 826 827 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) 828 { 829 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0); 830 } 831 832 /** 833 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 834 * @ap: Port whose timings we are configuring 835 * @adev: Drive in question 836 * @isich: set if the chip is an ICH device 837 * 838 * Set UDMA mode for device, in host controller PCI config space. 839 * 840 * LOCKING: 841 * None (inherited from caller). 842 */ 843 844 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) 845 { 846 struct pci_dev *dev = to_pci_dev(ap->host->dev); 847 unsigned long flags; 848 u8 speed = adev->dma_mode; 849 int devid = adev->devno + 2 * ap->port_no; 850 u8 udma_enable = 0; 851 852 if (speed >= XFER_UDMA_0) { 853 unsigned int udma = speed - XFER_UDMA_0; 854 u16 udma_timing; 855 u16 ideconf; 856 int u_clock, u_speed; 857 858 spin_lock_irqsave(&piix_lock, flags); 859 860 pci_read_config_byte(dev, 0x48, &udma_enable); 861 862 /* 863 * UDMA is handled by a combination of clock switching and 864 * selection of dividers 865 * 866 * Handy rule: Odd modes are UDMATIMx 01, even are 02 867 * except UDMA0 which is 00 868 */ 869 u_speed = min(2 - (udma & 1), udma); 870 if (udma == 5) 871 u_clock = 0x1000; /* 100Mhz */ 872 else if (udma > 2) 873 u_clock = 1; /* 66Mhz */ 874 else 875 u_clock = 0; /* 33Mhz */ 876 877 udma_enable |= (1 << devid); 878 879 /* Load the CT/RP selection */ 880 pci_read_config_word(dev, 0x4A, &udma_timing); 881 udma_timing &= ~(3 << (4 * devid)); 882 udma_timing |= u_speed << (4 * devid); 883 pci_write_config_word(dev, 0x4A, udma_timing); 884 885 if (isich) { 886 /* Select a 33/66/100Mhz clock */ 887 pci_read_config_word(dev, 0x54, &ideconf); 888 ideconf &= ~(0x1001 << devid); 889 ideconf |= u_clock << devid; 890 /* For ICH or later we should set bit 10 for better 891 performance (WR_PingPong_En) */ 892 pci_write_config_word(dev, 0x54, ideconf); 893 } 894 895 pci_write_config_byte(dev, 0x48, udma_enable); 896 897 spin_unlock_irqrestore(&piix_lock, flags); 898 } else { 899 /* MWDMA is driven by the PIO timings. */ 900 unsigned int mwdma = speed - XFER_MW_DMA_0; 901 const unsigned int needed_pio[3] = { 902 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 903 }; 904 int pio = needed_pio[mwdma] - XFER_PIO_0; 905 906 /* XFER_PIO_0 is never used currently */ 907 piix_set_timings(ap, adev, pio); 908 } 909 } 910 911 /** 912 * piix_set_dmamode - Initialize host controller PATA DMA timings 913 * @ap: Port whose timings we are configuring 914 * @adev: um 915 * 916 * Set MW/UDMA mode for device, in host controller PCI config space. 917 * 918 * LOCKING: 919 * None (inherited from caller). 920 */ 921 922 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) 923 { 924 do_pata_set_dmamode(ap, adev, 0); 925 } 926 927 /** 928 * ich_set_dmamode - Initialize host controller PATA DMA timings 929 * @ap: Port whose timings we are configuring 930 * @adev: um 931 * 932 * Set MW/UDMA mode for device, in host controller PCI config space. 933 * 934 * LOCKING: 935 * None (inherited from caller). 936 */ 937 938 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) 939 { 940 do_pata_set_dmamode(ap, adev, 1); 941 } 942 943 /* 944 * Serial ATA Index/Data Pair Superset Registers access 945 * 946 * Beginning from ICH8, there's a sane way to access SCRs using index 947 * and data register pair located at BAR5 which means that we have 948 * separate SCRs for master and slave. This is handled using libata 949 * slave_link facility. 950 */ 951 static const int piix_sidx_map[] = { 952 [SCR_STATUS] = 0, 953 [SCR_ERROR] = 2, 954 [SCR_CONTROL] = 1, 955 }; 956 957 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) 958 { 959 struct ata_port *ap = link->ap; 960 struct piix_host_priv *hpriv = ap->host->private_data; 961 962 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], 963 hpriv->sidpr + PIIX_SIDPR_IDX); 964 } 965 966 static int piix_sidpr_scr_read(struct ata_link *link, 967 unsigned int reg, u32 *val) 968 { 969 struct piix_host_priv *hpriv = link->ap->host->private_data; 970 971 if (reg >= ARRAY_SIZE(piix_sidx_map)) 972 return -EINVAL; 973 974 piix_sidpr_sel(link, reg); 975 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); 976 return 0; 977 } 978 979 static int piix_sidpr_scr_write(struct ata_link *link, 980 unsigned int reg, u32 val) 981 { 982 struct piix_host_priv *hpriv = link->ap->host->private_data; 983 984 if (reg >= ARRAY_SIZE(piix_sidx_map)) 985 return -EINVAL; 986 987 piix_sidpr_sel(link, reg); 988 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); 989 return 0; 990 } 991 992 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 993 unsigned hints) 994 { 995 return sata_link_scr_lpm(link, policy, false); 996 } 997 998 static bool piix_irq_check(struct ata_port *ap) 999 { 1000 unsigned char host_stat; 1001 1002 if (unlikely(!ap->ioaddr.bmdma_addr)) 1003 return false; 1004 1005 host_stat = ap->ops->bmdma_status(ap); 1006 trace_ata_bmdma_status(ap, host_stat); 1007 1008 return host_stat & ATA_DMA_INTR; 1009 } 1010 1011 #ifdef CONFIG_PM_SLEEP 1012 static int piix_broken_suspend(void) 1013 { 1014 static const struct dmi_system_id sysids[] = { 1015 { 1016 .ident = "TECRA M3", 1017 .matches = { 1018 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1019 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), 1020 }, 1021 }, 1022 { 1023 .ident = "TECRA M3", 1024 .matches = { 1025 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1026 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), 1027 }, 1028 }, 1029 { 1030 .ident = "TECRA M3", 1031 .matches = { 1032 DMI_MATCH(DMI_OEM_STRING, "Tecra M3,"), 1033 }, 1034 }, 1035 { 1036 .ident = "TECRA M4", 1037 .matches = { 1038 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1039 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), 1040 }, 1041 }, 1042 { 1043 .ident = "TECRA M4", 1044 .matches = { 1045 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1046 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), 1047 }, 1048 }, 1049 { 1050 .ident = "TECRA M5", 1051 .matches = { 1052 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1053 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), 1054 }, 1055 }, 1056 { 1057 .ident = "TECRA M6", 1058 .matches = { 1059 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1060 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), 1061 }, 1062 }, 1063 { 1064 .ident = "TECRA M7", 1065 .matches = { 1066 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1067 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), 1068 }, 1069 }, 1070 { 1071 .ident = "TECRA A8", 1072 .matches = { 1073 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1074 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), 1075 }, 1076 }, 1077 { 1078 .ident = "Satellite R20", 1079 .matches = { 1080 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1081 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), 1082 }, 1083 }, 1084 { 1085 .ident = "Satellite R25", 1086 .matches = { 1087 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1088 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), 1089 }, 1090 }, 1091 { 1092 .ident = "Satellite U200", 1093 .matches = { 1094 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1095 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 1096 }, 1097 }, 1098 { 1099 .ident = "Satellite U200", 1100 .matches = { 1101 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1102 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), 1103 }, 1104 }, 1105 { 1106 .ident = "Satellite Pro U200", 1107 .matches = { 1108 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1109 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), 1110 }, 1111 }, 1112 { 1113 .ident = "Satellite U205", 1114 .matches = { 1115 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1116 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), 1117 }, 1118 }, 1119 { 1120 .ident = "SATELLITE U205", 1121 .matches = { 1122 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1123 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), 1124 }, 1125 }, 1126 { 1127 .ident = "Satellite Pro A120", 1128 .matches = { 1129 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1130 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"), 1131 }, 1132 }, 1133 { 1134 .ident = "Portege M500", 1135 .matches = { 1136 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1137 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), 1138 }, 1139 }, 1140 { 1141 .ident = "VGN-BX297XP", 1142 .matches = { 1143 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"), 1144 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"), 1145 }, 1146 }, 1147 1148 { } /* terminate list */ 1149 }; 1150 1151 if (dmi_check_system(sysids)) 1152 return 1; 1153 1154 /* TECRA M4 sometimes forgets its identify and reports bogus 1155 * DMI information. As the bogus information is a bit 1156 * generic, match as many entries as possible. This manual 1157 * matching is necessary because dmi_system_id.matches is 1158 * limited to four entries. 1159 */ 1160 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") && 1161 dmi_match(DMI_PRODUCT_NAME, "000000") && 1162 dmi_match(DMI_PRODUCT_VERSION, "000000") && 1163 dmi_match(DMI_PRODUCT_SERIAL, "000000") && 1164 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") && 1165 dmi_match(DMI_BOARD_NAME, "Portable PC") && 1166 dmi_match(DMI_BOARD_VERSION, "Version A0")) 1167 return 1; 1168 1169 return 0; 1170 } 1171 1172 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 1173 { 1174 struct ata_host *host = pci_get_drvdata(pdev); 1175 unsigned long flags; 1176 1177 ata_host_suspend(host, mesg); 1178 1179 /* Some braindamaged ACPI suspend implementations expect the 1180 * controller to be awake on entry; otherwise, it burns cpu 1181 * cycles and power trying to do something to the sleeping 1182 * beauty. 1183 */ 1184 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { 1185 pci_save_state(pdev); 1186 1187 /* mark its power state as "unknown", since we don't 1188 * know if e.g. the BIOS will change its device state 1189 * when we suspend. 1190 */ 1191 if (pdev->current_state == PCI_D0) 1192 pdev->current_state = PCI_UNKNOWN; 1193 1194 /* tell resume that it's waking up from broken suspend */ 1195 spin_lock_irqsave(&host->lock, flags); 1196 host->flags |= PIIX_HOST_BROKEN_SUSPEND; 1197 spin_unlock_irqrestore(&host->lock, flags); 1198 } else 1199 ata_pci_device_do_suspend(pdev, mesg); 1200 1201 return 0; 1202 } 1203 1204 static int piix_pci_device_resume(struct pci_dev *pdev) 1205 { 1206 struct ata_host *host = pci_get_drvdata(pdev); 1207 unsigned long flags; 1208 int rc; 1209 1210 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { 1211 spin_lock_irqsave(&host->lock, flags); 1212 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; 1213 spin_unlock_irqrestore(&host->lock, flags); 1214 1215 pci_set_power_state(pdev, PCI_D0); 1216 pci_restore_state(pdev); 1217 1218 /* PCI device wasn't disabled during suspend. Use 1219 * pci_reenable_device() to avoid affecting the enable 1220 * count. 1221 */ 1222 rc = pci_reenable_device(pdev); 1223 if (rc) 1224 dev_err(&pdev->dev, 1225 "failed to enable device after resume (%d)\n", 1226 rc); 1227 } else 1228 rc = ata_pci_device_do_resume(pdev); 1229 1230 if (rc == 0) 1231 ata_host_resume(host); 1232 1233 return rc; 1234 } 1235 #endif 1236 1237 static u8 piix_vmw_bmdma_status(struct ata_port *ap) 1238 { 1239 return ata_bmdma_status(ap) & ~ATA_DMA_ERR; 1240 } 1241 1242 static const struct scsi_host_template piix_sht = { 1243 ATA_BMDMA_SHT(DRV_NAME), 1244 }; 1245 1246 static struct ata_port_operations piix_sata_ops = { 1247 .inherits = &ata_bmdma32_port_ops, 1248 .sff_irq_check = piix_irq_check, 1249 .port_start = piix_port_start, 1250 }; 1251 1252 static struct ata_port_operations piix_pata_ops = { 1253 .inherits = &piix_sata_ops, 1254 .cable_detect = ata_cable_40wire, 1255 .set_piomode = piix_set_piomode, 1256 .set_dmamode = piix_set_dmamode, 1257 .reset.prereset = piix_pata_prereset, 1258 }; 1259 1260 static struct ata_port_operations piix_vmw_ops = { 1261 .inherits = &piix_pata_ops, 1262 .bmdma_status = piix_vmw_bmdma_status, 1263 }; 1264 1265 static struct ata_port_operations ich_pata_ops = { 1266 .inherits = &piix_pata_ops, 1267 .cable_detect = ich_pata_cable_detect, 1268 .set_dmamode = ich_set_dmamode, 1269 }; 1270 1271 static struct attribute *piix_sidpr_shost_attrs[] = { 1272 &dev_attr_link_power_management_supported.attr, 1273 &dev_attr_link_power_management_policy.attr, 1274 NULL 1275 }; 1276 1277 ATTRIBUTE_GROUPS(piix_sidpr_shost); 1278 1279 static const struct scsi_host_template piix_sidpr_sht = { 1280 ATA_BMDMA_SHT(DRV_NAME), 1281 .shost_groups = piix_sidpr_shost_groups, 1282 }; 1283 1284 static struct ata_port_operations piix_sidpr_sata_ops = { 1285 .inherits = &piix_sata_ops, 1286 .reset.hardreset = sata_std_hardreset, 1287 .scr_read = piix_sidpr_scr_read, 1288 .scr_write = piix_sidpr_scr_write, 1289 .set_lpm = piix_sidpr_set_lpm, 1290 }; 1291 1292 static struct ata_port_info piix_port_info[] = { 1293 [piix_pata_mwdma] = /* PIIX3 MWDMA only */ 1294 { 1295 .flags = PIIX_PATA_FLAGS, 1296 .pio_mask = ATA_PIO4, 1297 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 1298 .port_ops = &piix_pata_ops, 1299 }, 1300 1301 [piix_pata_33] = /* PIIX4 at 33MHz */ 1302 { 1303 .flags = PIIX_PATA_FLAGS, 1304 .pio_mask = ATA_PIO4, 1305 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 1306 .udma_mask = ATA_UDMA2, 1307 .port_ops = &piix_pata_ops, 1308 }, 1309 1310 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ 1311 { 1312 .flags = PIIX_PATA_FLAGS, 1313 .pio_mask = ATA_PIO4, 1314 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */ 1315 .udma_mask = ATA_UDMA2, 1316 .port_ops = &ich_pata_ops, 1317 }, 1318 1319 [ich_pata_66] = /* ICH controllers up to 66MHz */ 1320 { 1321 .flags = PIIX_PATA_FLAGS, 1322 .pio_mask = ATA_PIO4, 1323 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */ 1324 .udma_mask = ATA_UDMA4, 1325 .port_ops = &ich_pata_ops, 1326 }, 1327 1328 [ich_pata_100] = 1329 { 1330 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 1331 .pio_mask = ATA_PIO4, 1332 .mwdma_mask = ATA_MWDMA12_ONLY, 1333 .udma_mask = ATA_UDMA5, 1334 .port_ops = &ich_pata_ops, 1335 }, 1336 1337 [ich_pata_100_nomwdma1] = 1338 { 1339 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 1340 .pio_mask = ATA_PIO4, 1341 .mwdma_mask = ATA_MWDMA2_ONLY, 1342 .udma_mask = ATA_UDMA5, 1343 .port_ops = &ich_pata_ops, 1344 }, 1345 1346 [ich5_sata] = 1347 { 1348 .flags = PIIX_SATA_FLAGS, 1349 .pio_mask = ATA_PIO4, 1350 .mwdma_mask = ATA_MWDMA2, 1351 .udma_mask = ATA_UDMA6, 1352 .port_ops = &piix_sata_ops, 1353 }, 1354 1355 [ich6_sata] = 1356 { 1357 .flags = PIIX_SATA_FLAGS, 1358 .pio_mask = ATA_PIO4, 1359 .mwdma_mask = ATA_MWDMA2, 1360 .udma_mask = ATA_UDMA6, 1361 .port_ops = &piix_sata_ops, 1362 }, 1363 1364 [ich6m_sata] = 1365 { 1366 .flags = PIIX_SATA_FLAGS, 1367 .pio_mask = ATA_PIO4, 1368 .mwdma_mask = ATA_MWDMA2, 1369 .udma_mask = ATA_UDMA6, 1370 .port_ops = &piix_sata_ops, 1371 }, 1372 1373 [ich8_sata] = 1374 { 1375 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 1376 .pio_mask = ATA_PIO4, 1377 .mwdma_mask = ATA_MWDMA2, 1378 .udma_mask = ATA_UDMA6, 1379 .port_ops = &piix_sata_ops, 1380 }, 1381 1382 [ich8_2port_sata] = 1383 { 1384 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 1385 .pio_mask = ATA_PIO4, 1386 .mwdma_mask = ATA_MWDMA2, 1387 .udma_mask = ATA_UDMA6, 1388 .port_ops = &piix_sata_ops, 1389 }, 1390 1391 [tolapai_sata] = 1392 { 1393 .flags = PIIX_SATA_FLAGS, 1394 .pio_mask = ATA_PIO4, 1395 .mwdma_mask = ATA_MWDMA2, 1396 .udma_mask = ATA_UDMA6, 1397 .port_ops = &piix_sata_ops, 1398 }, 1399 1400 [ich8m_apple_sata] = 1401 { 1402 .flags = PIIX_SATA_FLAGS, 1403 .pio_mask = ATA_PIO4, 1404 .mwdma_mask = ATA_MWDMA2, 1405 .udma_mask = ATA_UDMA6, 1406 .port_ops = &piix_sata_ops, 1407 }, 1408 1409 [piix_pata_vmw] = 1410 { 1411 .flags = PIIX_PATA_FLAGS, 1412 .pio_mask = ATA_PIO4, 1413 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 1414 .udma_mask = ATA_UDMA2, 1415 .port_ops = &piix_vmw_ops, 1416 }, 1417 1418 /* 1419 * some Sandybridge chipsets have broken 32 mode up to now, 1420 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592 1421 */ 1422 [ich8_sata_snb] = 1423 { 1424 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16, 1425 .pio_mask = ATA_PIO4, 1426 .mwdma_mask = ATA_MWDMA2, 1427 .udma_mask = ATA_UDMA6, 1428 .port_ops = &piix_sata_ops, 1429 }, 1430 1431 [ich8_2port_sata_snb] = 1432 { 1433 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR 1434 | PIIX_FLAG_PIO16, 1435 .pio_mask = ATA_PIO4, 1436 .mwdma_mask = ATA_MWDMA2, 1437 .udma_mask = ATA_UDMA6, 1438 .port_ops = &piix_sata_ops, 1439 }, 1440 1441 [ich8_2port_sata_byt] = 1442 { 1443 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16, 1444 .pio_mask = ATA_PIO4, 1445 .mwdma_mask = ATA_MWDMA2, 1446 .udma_mask = ATA_UDMA6, 1447 .port_ops = &piix_sata_ops, 1448 }, 1449 1450 }; 1451 1452 #define AHCI_PCI_BAR 5 1453 #define AHCI_GLOBAL_CTL 0x04 1454 #define AHCI_ENABLE (1 << 31) 1455 static int piix_disable_ahci(struct pci_dev *pdev) 1456 { 1457 void __iomem *mmio; 1458 u32 tmp; 1459 int rc = 0; 1460 1461 /* BUG: pci_enable_device has not yet been called. This 1462 * works because this device is usually set up by BIOS. 1463 */ 1464 1465 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 1466 !pci_resource_len(pdev, AHCI_PCI_BAR)) 1467 return 0; 1468 1469 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 1470 if (!mmio) 1471 return -ENOMEM; 1472 1473 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1474 if (tmp & AHCI_ENABLE) { 1475 tmp &= ~AHCI_ENABLE; 1476 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); 1477 1478 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1479 if (tmp & AHCI_ENABLE) 1480 rc = -EIO; 1481 } 1482 1483 pci_iounmap(pdev, mmio); 1484 return rc; 1485 } 1486 1487 /** 1488 * piix_check_450nx_errata - Check for problem 450NX setup 1489 * @ata_dev: the PCI device to check 1490 * 1491 * Check for the present of 450NX errata #19 and errata #25. If 1492 * they are found return an error code so we can turn off DMA 1493 */ 1494 1495 static int piix_check_450nx_errata(struct pci_dev *ata_dev) 1496 { 1497 struct pci_dev *pdev = NULL; 1498 u16 cfg; 1499 int no_piix_dma = 0; 1500 1501 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { 1502 /* Look for 450NX PXB. Check for problem configurations 1503 A PCI quirk checks bit 6 already */ 1504 pci_read_config_word(pdev, 0x41, &cfg); 1505 /* Only on the original revision: IDE DMA can hang */ 1506 if (pdev->revision == 0x00) 1507 no_piix_dma = 1; 1508 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 1509 else if (cfg & (1<<14) && pdev->revision < 5) 1510 no_piix_dma = 2; 1511 } 1512 if (no_piix_dma) 1513 dev_warn(&ata_dev->dev, 1514 "450NX errata present, disabling IDE DMA%s\n", 1515 no_piix_dma == 2 ? " - a BIOS update may resolve this" 1516 : ""); 1517 1518 return no_piix_dma; 1519 } 1520 1521 static void piix_init_pcs(struct ata_host *host, 1522 const struct piix_map_db *map_db) 1523 { 1524 struct pci_dev *pdev = to_pci_dev(host->dev); 1525 u16 pcs, new_pcs; 1526 1527 pci_read_config_word(pdev, ICH5_PCS, &pcs); 1528 1529 new_pcs = pcs | map_db->port_enable; 1530 1531 if (new_pcs != pcs) { 1532 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 1533 msleep(150); 1534 } 1535 } 1536 1537 static const int *piix_init_sata_map(struct pci_dev *pdev, 1538 struct ata_port_info *pinfo, 1539 const struct piix_map_db *map_db) 1540 { 1541 const int *map; 1542 int i, invalid_map = 0; 1543 u8 map_value; 1544 char buf[32]; 1545 char *p = buf, *end = buf + sizeof(buf); 1546 1547 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1548 1549 map = map_db->map[map_value & map_db->mask]; 1550 1551 for (i = 0; i < 4; i++) { 1552 switch (map[i]) { 1553 case RV: 1554 invalid_map = 1; 1555 p += scnprintf(p, end - p, " XX"); 1556 break; 1557 1558 case NA: 1559 p += scnprintf(p, end - p, " --"); 1560 break; 1561 1562 case IDE: 1563 WARN_ON((i & 1) || map[i + 1] != IDE); 1564 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1565 i++; 1566 p += scnprintf(p, end - p, " IDE IDE"); 1567 break; 1568 1569 default: 1570 p += scnprintf(p, end - p, " P%d", map[i]); 1571 if (i & 1) 1572 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1573 break; 1574 } 1575 } 1576 dev_info(&pdev->dev, "MAP [%s ]\n", buf); 1577 1578 if (invalid_map) 1579 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value); 1580 1581 return map; 1582 } 1583 1584 static bool piix_no_sidpr(struct ata_host *host) 1585 { 1586 struct pci_dev *pdev = to_pci_dev(host->dev); 1587 1588 /* 1589 * Samsung DB-P70 only has three ATA ports exposed and 1590 * curiously the unconnected first port reports link online 1591 * while not responding to SRST protocol causing excessive 1592 * detection delay. 1593 * 1594 * Unfortunately, the system doesn't carry enough DMI 1595 * information to identify the machine but does have subsystem 1596 * vendor and device set. As it's unclear whether the 1597 * subsystem vendor/device is used only for this specific 1598 * board, the port can't be disabled solely with the 1599 * information; however, turning off SIDPR access works around 1600 * the problem. Turn it off. 1601 * 1602 * This problem is reported in bnc#441240. 1603 * 1604 * https://bugzilla.novell.com/show_bug.cgi?id=441420 1605 */ 1606 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && 1607 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && 1608 pdev->subsystem_device == 0xb049) { 1609 dev_warn(host->dev, 1610 "Samsung DB-P70 detected, disabling SIDPR\n"); 1611 return true; 1612 } 1613 1614 return false; 1615 } 1616 1617 static int piix_init_sidpr(struct ata_host *host) 1618 { 1619 struct pci_dev *pdev = to_pci_dev(host->dev); 1620 struct piix_host_priv *hpriv = host->private_data; 1621 struct ata_link *link0 = &host->ports[0]->link; 1622 u32 scontrol; 1623 int i, rc; 1624 1625 /* check for availability */ 1626 for (i = 0; i < 4; i++) 1627 if (hpriv->map[i] == IDE) 1628 return 0; 1629 1630 if (piix_no_sidpr(host)) 1631 return 0; 1632 1633 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) 1634 return 0; 1635 1636 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || 1637 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) 1638 return 0; 1639 1640 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) 1641 return 0; 1642 1643 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; 1644 1645 /* SCR access via SIDPR doesn't work on some configurations. 1646 * Give it a test drive by inhibiting power save modes which 1647 * we'll do anyway. 1648 */ 1649 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1650 1651 /* if IPM is already 3, SCR access is probably working. Don't 1652 * un-inhibit power save modes as BIOS might have inhibited 1653 * them for a reason. 1654 */ 1655 if ((scontrol & 0xf00) != 0x300) { 1656 scontrol |= 0x300; 1657 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol); 1658 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1659 1660 if ((scontrol & 0xf00) != 0x300) { 1661 dev_info(host->dev, 1662 "SCR access via SIDPR is available but doesn't work\n"); 1663 return 0; 1664 } 1665 } 1666 1667 /* okay, SCRs available, set ops and ask libata for slave_link */ 1668 for (i = 0; i < 2; i++) { 1669 struct ata_port *ap = host->ports[i]; 1670 1671 ap->ops = &piix_sidpr_sata_ops; 1672 1673 if (ap->flags & ATA_FLAG_SLAVE_POSS) { 1674 rc = ata_slave_link_init(ap); 1675 if (rc) 1676 return rc; 1677 } 1678 } 1679 1680 return 0; 1681 } 1682 1683 static void piix_iocfg_bit18_quirk(struct ata_host *host) 1684 { 1685 static const struct dmi_system_id sysids[] = { 1686 { 1687 /* Clevo M570U sets IOCFG bit 18 if the cdrom 1688 * isn't used to boot the system which 1689 * disables the channel. 1690 */ 1691 .ident = "M570U", 1692 .matches = { 1693 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), 1694 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), 1695 }, 1696 }, 1697 1698 { } /* terminate list */ 1699 }; 1700 struct pci_dev *pdev = to_pci_dev(host->dev); 1701 struct piix_host_priv *hpriv = host->private_data; 1702 1703 if (!dmi_check_system(sysids)) 1704 return; 1705 1706 /* The datasheet says that bit 18 is NOOP but certain systems 1707 * seem to use it to disable a channel. Clear the bit on the 1708 * affected systems. 1709 */ 1710 if (hpriv->saved_iocfg & (1 << 18)) { 1711 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n"); 1712 pci_write_config_dword(pdev, PIIX_IOCFG, 1713 hpriv->saved_iocfg & ~(1 << 18)); 1714 } 1715 } 1716 1717 static bool piix_broken_system_poweroff(struct pci_dev *pdev) 1718 { 1719 static const struct dmi_system_id broken_systems[] = { 1720 { 1721 .ident = "HP Compaq 2510p", 1722 .matches = { 1723 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1724 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"), 1725 }, 1726 /* PCI slot number of the controller */ 1727 .driver_data = (void *)0x1FUL, 1728 }, 1729 { 1730 .ident = "HP Compaq nc6000", 1731 .matches = { 1732 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1733 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"), 1734 }, 1735 /* PCI slot number of the controller */ 1736 .driver_data = (void *)0x1FUL, 1737 }, 1738 1739 { } /* terminate list */ 1740 }; 1741 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1742 1743 if (dmi) { 1744 unsigned long slot = (unsigned long)dmi->driver_data; 1745 /* apply the quirk only to on-board controllers */ 1746 return slot == PCI_SLOT(pdev->devfn); 1747 } 1748 1749 return false; 1750 } 1751 1752 static int prefer_ms_hyperv = 1; 1753 module_param(prefer_ms_hyperv, int, 0); 1754 MODULE_PARM_DESC(prefer_ms_hyperv, 1755 "Prefer Hyper-V paravirtualization drivers instead of ATA, " 1756 "0 - Use ATA drivers, " 1757 "1 (Default) - Use the paravirtualization drivers."); 1758 1759 static void piix_ignore_devices_quirk(struct ata_host *host) 1760 { 1761 #if IS_ENABLED(CONFIG_HYPERV_STORAGE) 1762 static const struct dmi_system_id ignore_hyperv[] = { 1763 { 1764 /* On Hyper-V hypervisors the disks are exposed on 1765 * both the emulated SATA controller and on the 1766 * paravirtualised drivers. The CD/DVD devices 1767 * are only exposed on the emulated controller. 1768 * Request we ignore ATA devices on this host. 1769 */ 1770 .ident = "Hyper-V Virtual Machine", 1771 .matches = { 1772 DMI_MATCH(DMI_SYS_VENDOR, 1773 "Microsoft Corporation"), 1774 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"), 1775 }, 1776 }, 1777 { } /* terminate list */ 1778 }; 1779 static const struct dmi_system_id allow_virtual_pc[] = { 1780 { 1781 /* In MS Virtual PC guests the DMI ident is nearly 1782 * identical to a Hyper-V guest. One difference is the 1783 * product version which is used here to identify 1784 * a Virtual PC guest. This entry allows ata_piix to 1785 * drive the emulated hardware. 1786 */ 1787 .ident = "MS Virtual PC 2007", 1788 .matches = { 1789 DMI_MATCH(DMI_SYS_VENDOR, 1790 "Microsoft Corporation"), 1791 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"), 1792 DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"), 1793 }, 1794 }, 1795 { } /* terminate list */ 1796 }; 1797 const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv); 1798 const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc); 1799 1800 if (ignore && !allow && prefer_ms_hyperv) { 1801 host->flags |= ATA_HOST_IGNORE_ATA; 1802 dev_info(host->dev, "%s detected, ATA device ignore set\n", 1803 ignore->ident); 1804 } 1805 #endif 1806 } 1807 1808 /** 1809 * piix_init_one - Register PIIX ATA PCI device with kernel services 1810 * @pdev: PCI device to register 1811 * @ent: Entry in piix_pci_tbl matching with @pdev 1812 * 1813 * Called from kernel PCI layer. We probe for combined mode (sigh), 1814 * and then hand over control to libata, for it to do the rest. 1815 * 1816 * LOCKING: 1817 * Inherited from PCI layer (may sleep). 1818 * 1819 * RETURNS: 1820 * Zero on success, or -ERRNO value. 1821 */ 1822 1823 static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1824 { 1825 struct device *dev = &pdev->dev; 1826 struct ata_port_info port_info[2]; 1827 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1828 const struct scsi_host_template *sht = &piix_sht; 1829 unsigned long port_flags; 1830 struct ata_host *host; 1831 struct piix_host_priv *hpriv; 1832 int rc; 1833 1834 ata_print_version_once(&pdev->dev, DRV_VERSION); 1835 1836 /* no hotplugging support for later devices (FIXME) */ 1837 if (!in_module_init && ent->driver_data >= ich5_sata) 1838 return -ENODEV; 1839 1840 if (piix_broken_system_poweroff(pdev)) { 1841 piix_port_info[ent->driver_data].flags |= 1842 ATA_FLAG_NO_POWEROFF_SPINDOWN | 1843 ATA_FLAG_NO_HIBERNATE_SPINDOWN; 1844 dev_info(&pdev->dev, "quirky BIOS, skipping spindown " 1845 "on poweroff and hibernation\n"); 1846 } 1847 1848 port_info[0] = piix_port_info[ent->driver_data]; 1849 port_info[1] = piix_port_info[ent->driver_data]; 1850 1851 port_flags = port_info[0].flags; 1852 1853 /* enable device and prepare host */ 1854 rc = pcim_enable_device(pdev); 1855 if (rc) 1856 return rc; 1857 1858 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1859 if (!hpriv) 1860 return -ENOMEM; 1861 1862 /* Save IOCFG, this will be used for cable detection, quirk 1863 * detection and restoration on detach. This is necessary 1864 * because some ACPI implementations mess up cable related 1865 * bits on _STM. Reported on kernel bz#11879. 1866 */ 1867 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg); 1868 1869 /* ICH6R may be driven by either ata_piix or ahci driver 1870 * regardless of BIOS configuration. Make sure AHCI mode is 1871 * off. 1872 */ 1873 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { 1874 rc = piix_disable_ahci(pdev); 1875 if (rc) 1876 return rc; 1877 } 1878 1879 /* SATA map init can change port_info, do it before prepping host */ 1880 if (port_flags & ATA_FLAG_SATA) 1881 hpriv->map = piix_init_sata_map(pdev, port_info, 1882 piix_map_db_table[ent->driver_data]); 1883 1884 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); 1885 if (rc) 1886 return rc; 1887 host->private_data = hpriv; 1888 1889 /* initialize controller */ 1890 if (port_flags & ATA_FLAG_SATA) { 1891 piix_init_pcs(host, piix_map_db_table[ent->driver_data]); 1892 rc = piix_init_sidpr(host); 1893 if (rc) 1894 return rc; 1895 if (host->ports[0]->ops == &piix_sidpr_sata_ops) 1896 sht = &piix_sidpr_sht; 1897 } 1898 1899 /* apply IOCFG bit18 quirk */ 1900 piix_iocfg_bit18_quirk(host); 1901 1902 /* On ICH5, some BIOSen disable the interrupt using the 1903 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1904 * On ICH6, this bit has the same effect, but only when 1905 * MSI is disabled (and it is disabled, as we don't use 1906 * message-signalled interrupts currently). 1907 */ 1908 if (port_flags & PIIX_FLAG_CHECKINTR) 1909 pcim_intx(pdev, 1); 1910 1911 if (piix_check_450nx_errata(pdev)) { 1912 /* This writes into the master table but it does not 1913 really matter for this errata as we will apply it to 1914 all the PIIX devices on the board */ 1915 host->ports[0]->mwdma_mask = 0; 1916 host->ports[0]->udma_mask = 0; 1917 host->ports[1]->mwdma_mask = 0; 1918 host->ports[1]->udma_mask = 0; 1919 } 1920 host->flags |= ATA_HOST_PARALLEL_SCAN; 1921 1922 /* Allow hosts to specify device types to ignore when scanning. */ 1923 piix_ignore_devices_quirk(host); 1924 1925 pci_set_master(pdev); 1926 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); 1927 } 1928 1929 static void piix_remove_one(struct pci_dev *pdev) 1930 { 1931 struct ata_host *host = pci_get_drvdata(pdev); 1932 struct piix_host_priv *hpriv = host->private_data; 1933 1934 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg); 1935 1936 ata_pci_remove_one(pdev); 1937 } 1938 1939 static struct pci_driver piix_pci_driver = { 1940 .name = DRV_NAME, 1941 .id_table = piix_pci_tbl, 1942 .probe = piix_init_one, 1943 .remove = piix_remove_one, 1944 #ifdef CONFIG_PM_SLEEP 1945 .suspend = piix_pci_device_suspend, 1946 .resume = piix_pci_device_resume, 1947 #endif 1948 }; 1949 1950 static int __init piix_init(void) 1951 { 1952 int rc; 1953 1954 rc = pci_register_driver(&piix_pci_driver); 1955 if (rc) 1956 return rc; 1957 1958 in_module_init = 0; 1959 1960 return 0; 1961 } 1962 1963 static void __exit piix_exit(void) 1964 { 1965 pci_unregister_driver(&piix_pci_driver); 1966 } 1967 1968 module_init(piix_init); 1969 module_exit(piix_exit); 1970