1 /* 2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_ESWITCH_H__ 34 #define __MLX5_ESWITCH_H__ 35 36 #include <linux/if_ether.h> 37 #include <linux/if_link.h> 38 #include <linux/atomic.h> 39 #include <linux/wait.h> 40 #include <linux/xarray.h> 41 #include <net/devlink.h> 42 #include <linux/mlx5/device.h> 43 #include <linux/mlx5/eswitch.h> 44 #include <linux/mlx5/vport.h> 45 #include <linux/mlx5/fs.h> 46 #include "lib/mpfs.h" 47 #include "lib/fs_chains.h" 48 #include "sf/sf.h" 49 #include "en/tc_ct.h" 50 #include "en/tc/sample.h" 51 52 enum mlx5_mapped_obj_type { 53 MLX5_MAPPED_OBJ_CHAIN, 54 MLX5_MAPPED_OBJ_SAMPLE, 55 MLX5_MAPPED_OBJ_INT_PORT_METADATA, 56 MLX5_MAPPED_OBJ_ACT_MISS, 57 }; 58 59 struct mlx5_mapped_obj { 60 enum mlx5_mapped_obj_type type; 61 union { 62 u32 chain; 63 u64 act_miss_cookie; 64 struct { 65 u32 group_id; 66 u32 rate; 67 u32 trunc_size; 68 u32 tunnel_id; 69 } sample; 70 u32 int_port_metadata; 71 }; 72 }; 73 74 struct mlx5_esw_pf_info { 75 bool pf_not_exist; 76 bool pf_disabled; 77 u16 num_of_vfs; 78 u16 total_vfs; 79 u16 host_number; 80 u16 pf_num; 81 }; 82 83 #ifdef CONFIG_MLX5_ESWITCH 84 85 #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15 86 87 #define MLX5_MAX_UC_PER_VPORT(dev) \ 88 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) 89 90 #define MLX5_MAX_MC_PER_VPORT(dev) \ 91 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) 92 93 #define mlx5_esw_has_fwd_fdb(dev) \ 94 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) 95 96 #define esw_chains(esw) \ 97 ((esw)->fdb_table.offloads.esw_chains_priv) 98 99 enum { 100 MAPPING_TYPE_CHAIN, 101 MAPPING_TYPE_TUNNEL, 102 MAPPING_TYPE_TUNNEL_ENC_OPTS, 103 MAPPING_TYPE_LABELS, 104 MAPPING_TYPE_ZONE, 105 MAPPING_TYPE_INT_PORT, 106 }; 107 108 struct vport_ingress { 109 struct mlx5_flow_table *acl; 110 struct mlx5_flow_handle *allow_rule; 111 struct { 112 struct mlx5_flow_group *allow_spoofchk_only_grp; 113 struct mlx5_flow_group *allow_untagged_spoofchk_grp; 114 struct mlx5_flow_group *allow_untagged_only_grp; 115 struct mlx5_flow_group *drop_grp; 116 struct mlx5_flow_handle *drop_rule; 117 struct mlx5_fc *drop_counter; 118 } legacy; 119 struct { 120 /* Optional group to add an FTE to do internal priority 121 * tagging on ingress packets. 122 */ 123 struct mlx5_flow_group *metadata_prio_tag_grp; 124 /* Group to add default match-all FTE entry to tag ingress 125 * packet with metadata. 126 */ 127 struct mlx5_flow_group *metadata_allmatch_grp; 128 /* Optional group to add a drop all rule */ 129 struct mlx5_flow_group *drop_grp; 130 struct mlx5_modify_hdr *modify_metadata; 131 struct mlx5_flow_handle *modify_metadata_rule; 132 struct mlx5_flow_handle *drop_rule; 133 } offloads; 134 }; 135 136 enum vport_egress_acl_type { 137 VPORT_EGRESS_ACL_TYPE_DEFAULT, 138 VPORT_EGRESS_ACL_TYPE_SHARED_FDB, 139 }; 140 141 struct vport_egress { 142 struct mlx5_flow_table *acl; 143 enum vport_egress_acl_type type; 144 struct mlx5_flow_handle *allowed_vlan; 145 struct mlx5_flow_group *vlan_grp; 146 union { 147 struct { 148 struct mlx5_flow_group *drop_grp; 149 struct mlx5_flow_handle *drop_rule; 150 struct mlx5_fc *drop_counter; 151 } legacy; 152 struct { 153 struct mlx5_flow_group *fwd_grp; 154 struct mlx5_flow_handle *fwd_rule; 155 struct xarray bounce_rules; 156 struct mlx5_flow_group *bounce_grp; 157 } offloads; 158 }; 159 }; 160 161 struct mlx5_vport_drop_stats { 162 u64 rx_dropped; 163 u64 tx_dropped; 164 }; 165 166 struct mlx5_vport_info { 167 u8 mac[ETH_ALEN]; 168 u16 vlan; 169 u64 node_guid; 170 int link_state; 171 u8 qos; 172 u8 spoofchk: 1; 173 u8 trusted: 1; 174 u8 roce_enabled: 1; 175 u8 mig_enabled: 1; 176 u8 ipsec_crypto_enabled: 1; 177 u8 ipsec_packet_enabled: 1; 178 }; 179 180 /* Vport context events */ 181 enum mlx5_eswitch_vport_event { 182 MLX5_VPORT_UC_ADDR_CHANGE = BIT(0), 183 MLX5_VPORT_MC_ADDR_CHANGE = BIT(1), 184 MLX5_VPORT_PROMISC_CHANGE = BIT(3), 185 }; 186 187 struct mlx5_vport; 188 189 struct mlx5_devlink_port { 190 struct devlink_port dl_port; 191 struct mlx5_vport *vport; 192 }; 193 194 static inline void mlx5_devlink_port_init(struct mlx5_devlink_port *dl_port, 195 struct mlx5_vport *vport) 196 { 197 dl_port->vport = vport; 198 } 199 200 static inline struct mlx5_devlink_port *mlx5_devlink_port_get(struct devlink_port *dl_port) 201 { 202 return container_of(dl_port, struct mlx5_devlink_port, dl_port); 203 } 204 205 static inline struct mlx5_vport *mlx5_devlink_port_vport_get(struct devlink_port *dl_port) 206 { 207 return mlx5_devlink_port_get(dl_port)->vport; 208 } 209 210 #define MLX5_VHCA_ID_INVALID (-1) 211 212 #define MLX5_VPORT_INVAL_VHCA_ID(vport) \ 213 ((vport)->vhca_id == MLX5_VHCA_ID_INVALID) 214 215 struct mlx5_vport { 216 struct mlx5_core_dev *dev; 217 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; 218 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; 219 struct mlx5_flow_handle *promisc_rule; 220 struct mlx5_flow_handle *allmulti_rule; 221 struct work_struct vport_change_handler; 222 223 struct vport_ingress ingress; 224 struct vport_egress egress; 225 u32 default_metadata; 226 u32 metadata; 227 int vhca_id; 228 229 bool adjacent; /* delegated vhca from adjacent function */ 230 struct { 231 u16 parent_pci_devfn; /* Adjacent parent PCI device function */ 232 u16 function_id; /* Function ID of the delegated VPort */ 233 } adj_info; 234 235 struct mlx5_vport_info info; 236 237 /* Protected with the E-Switch qos domain lock. The Vport QoS can 238 * either be disabled (sched_node is NULL) or in one of three states: 239 * 1. Regular QoS (sched_node is a vport node). 240 * 2. TC QoS enabled on the vport (sched_node is a TC arbiter). 241 * 3. TC QoS enabled on the vport's parent node 242 * (sched_node is a rate limit node). 243 * When TC is enabled in either mode, the vport owns vport TC scheduling 244 * nodes. 245 */ 246 struct { 247 /* Vport scheduling node. */ 248 struct mlx5_esw_sched_node *sched_node; 249 /* Array of vport traffic class scheduling nodes. */ 250 struct mlx5_esw_sched_node **sched_nodes; 251 } qos; 252 253 u16 vport; 254 bool enabled; 255 bool max_eqs_set; 256 bool pf_activated; 257 enum mlx5_eswitch_vport_event enabled_events; 258 int index; 259 struct mlx5_devlink_port *dl_port; 260 u32 agg_max_tx_speed; 261 }; 262 263 struct mlx5_esw_indir_table; 264 265 struct mlx5_eswitch_fdb { 266 union { 267 struct legacy_fdb { 268 struct mlx5_flow_table *fdb; 269 struct mlx5_flow_group *addr_grp; 270 struct mlx5_flow_group *allmulti_grp; 271 struct mlx5_flow_group *promisc_grp; 272 struct mlx5_flow_table *vepa_fdb; 273 struct mlx5_flow_handle *vepa_uplink_rule; 274 struct mlx5_flow_handle *vepa_star_rule; 275 } legacy; 276 277 struct offloads_fdb { 278 struct mlx5_flow_namespace *ns; 279 struct mlx5_flow_table *drop_root; 280 struct mlx5_flow_handle *drop_root_rule; 281 struct mlx5_fc *drop_root_fc; 282 struct mlx5_flow_table *tc_miss_table; 283 struct mlx5_flow_table *slow_fdb; 284 struct mlx5_flow_group *send_to_vport_grp; 285 struct mlx5_flow_group *send_to_vport_meta_grp; 286 struct mlx5_flow_group *peer_miss_grp; 287 struct xarray peer_miss_rules; 288 struct mlx5_flow_group *miss_grp; 289 struct mlx5_flow_handle **send_to_vport_meta_rules; 290 struct mlx5_flow_handle *miss_rule_uni; 291 struct mlx5_flow_handle *miss_rule_multi; 292 293 struct mlx5_fs_chains *esw_chains_priv; 294 struct { 295 DECLARE_HASHTABLE(table, 8); 296 /* Protects vports.table */ 297 struct mutex lock; 298 } vports; 299 300 struct mlx5_esw_indir_table *indir; 301 302 } offloads; 303 }; 304 u32 flags; 305 }; 306 307 struct mlx5_esw_offload { 308 struct mlx5_flow_table *ft_offloads_restore; 309 struct mlx5_flow_group *restore_group; 310 struct mlx5_modify_hdr *restore_copy_hdr_id; 311 struct mapping_ctx *reg_c0_obj_pool; 312 313 struct mlx5_flow_table *ft_offloads; 314 struct mlx5_flow_group *vport_rx_group; 315 struct mlx5_flow_group *vport_rx_drop_group; 316 struct mlx5_flow_handle *vport_rx_drop_rule; 317 struct mlx5_flow_table *ft_ipsec_tx_pol; 318 struct xarray vport_reps; 319 struct list_head peer_flows[MLX5_MAX_PORTS]; 320 struct mutex peer_mutex; 321 struct mutex encap_tbl_lock; /* protects encap_tbl */ 322 DECLARE_HASHTABLE(encap_tbl, 8); 323 struct mutex decap_tbl_lock; /* protects decap_tbl */ 324 DECLARE_HASHTABLE(decap_tbl, 8); 325 struct mod_hdr_tbl mod_hdr; 326 DECLARE_HASHTABLE(termtbl_tbl, 8); 327 struct mutex termtbl_mutex; /* protects termtbl hash */ 328 struct xarray vhca_map; 329 struct mutex reps_lock; /* protects representor load/unload/register */ 330 const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; 331 u8 inline_mode; 332 atomic64_t num_flows; 333 u64 num_block_encap; 334 u64 num_block_mode; 335 enum devlink_eswitch_encap_mode encap; 336 struct ida vport_metadata_ida; 337 }; 338 339 /* E-Switch MC FDB table hash node */ 340 struct esw_mc_addr { /* SRIOV only */ 341 struct l2addr_node node; 342 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ 343 u32 refcnt; 344 }; 345 346 struct mlx5_host_work { 347 struct work_struct work; 348 struct mlx5_eswitch *esw; 349 int work_gen; 350 void (*func)(struct mlx5_eswitch *esw); 351 }; 352 353 struct mlx5_esw_spf { 354 u16 vport_num; 355 u16 vhca_id; 356 u16 host_number; 357 u16 pf_num; 358 }; 359 360 struct mlx5_esw_functions { 361 struct mlx5_nb nb; 362 bool host_funcs_disabled; 363 u16 num_vfs; 364 u16 num_ec_vfs; 365 u16 hpf_host_number; 366 u16 hpf_pf_num; 367 bool has_spf_sfs; 368 struct mlx5_esw_spf *spfs; 369 int num_spfs; 370 }; 371 372 enum { 373 MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), 374 MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1), 375 MLX5_ESWITCH_VPORT_ACL_NS_CREATED = BIT(2), 376 }; 377 378 struct mlx5_esw_bridge_offloads; 379 380 enum { 381 MLX5_ESW_FDB_CREATED = BIT(0), 382 }; 383 384 struct dentry; 385 struct mlx5_qos_domain; 386 387 struct mlx5_eswitch { 388 struct mlx5_core_dev *dev; 389 struct mlx5_nb nb; 390 struct mlx5_eswitch_fdb fdb_table; 391 /* legacy data structures */ 392 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; 393 struct esw_mc_addr mc_promisc; 394 /* end of legacy */ 395 struct dentry *debugfs_root; 396 struct workqueue_struct *work_queue; 397 struct xarray vports; 398 struct xarray vhca_type_map; 399 u32 flags; 400 int total_vports; 401 int enabled_vports; 402 /* Synchronize between vport change events 403 * and async SRIOV admin state changes 404 */ 405 struct mutex state_lock; 406 407 /* Protects eswitch mode change that occurs via one or more 408 * user commands, i.e. sriov state change, devlink commands. 409 */ 410 struct rw_semaphore mode_lock; 411 atomic64_t user_count; 412 wait_queue_head_t work_queue_wait; 413 414 /* Protected with the E-Switch qos domain lock. */ 415 struct { 416 /* Initially 0, meaning no QoS users and QoS is disabled. */ 417 refcount_t refcnt; 418 u32 root_tsar_ix; 419 struct mlx5_qos_domain *domain; 420 } qos; 421 422 struct mlx5_esw_bridge_offloads *br_offloads; 423 struct mlx5_esw_offload offloads; 424 u32 last_vport_idx; 425 int mode; 426 bool offloads_inactive; 427 u16 manager_vport; 428 u16 first_host_vport; 429 u8 num_peers; 430 struct mlx5_esw_functions esw_funcs; 431 struct { 432 u32 large_group_num; 433 } params; 434 struct xarray paired; 435 struct mlx5_devcom_comp_dev *devcom; 436 u16 enabled_ipsec_vf_count; 437 bool eswitch_operation_in_progress; 438 atomic_t generation; 439 }; 440 441 void esw_offloads_disable(struct mlx5_eswitch *esw); 442 int esw_offloads_enable(struct mlx5_eswitch *esw); 443 int mlx5_esw_offloads_init_deferred_metadata(struct mlx5_eswitch *esw); 444 void esw_offloads_cleanup(struct mlx5_eswitch *esw); 445 int esw_offloads_init(struct mlx5_eswitch *esw); 446 447 struct mlx5_flow_handle * 448 mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num); 449 void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule); 450 451 bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw); 452 u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw); 453 void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata); 454 455 int mlx5_esw_qos_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, u32 rate_mbps); 456 457 /* E-Switch API */ 458 int mlx5_eswitch_init(struct mlx5_core_dev *dev); 459 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); 460 int mlx5_esw_vport_alloc(struct mlx5_eswitch *esw, int index, u16 vport_num); 461 void mlx5_esw_vport_free(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 462 463 #define MLX5_ESWITCH_IGNORE_NUM_VFS (-1) 464 int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int num_vfs); 465 int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs); 466 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf); 467 void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw); 468 void mlx5_eswitch_disable(struct mlx5_eswitch *esw); 469 void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw, 470 const struct mlx5_devcom_match_attr *attr); 471 void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw); 472 bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw); 473 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, 474 u16 vport, const u8 *mac); 475 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, 476 u16 vport, int link_state); 477 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, 478 u16 vport, u16 vlan, u8 qos); 479 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, 480 u16 vport, bool spoofchk); 481 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, 482 u16 vport_num, bool setting); 483 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, 484 u32 max_rate, u32 min_rate); 485 int mlx5_esw_qos_vport_update_parent(struct mlx5_vport *vport, struct mlx5_esw_sched_node *node, 486 struct netlink_ext_ack *extack); 487 int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); 488 int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); 489 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, 490 u16 vport, struct ifla_vf_info *ivi); 491 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, 492 u16 vport, 493 struct ifla_vf_stats *vf_stats); 494 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); 495 496 int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport, 497 bool other_vport, void *in); 498 499 struct mlx5_flow_spec; 500 struct mlx5_esw_flow_attr; 501 struct mlx5_termtbl_handle; 502 503 bool 504 mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw, 505 struct mlx5_flow_attr *attr, 506 struct mlx5_flow_act *flow_act, 507 struct mlx5_flow_spec *spec); 508 509 struct mlx5_flow_handle * 510 mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw, 511 struct mlx5_flow_table *ft, 512 struct mlx5_flow_spec *spec, 513 struct mlx5_esw_flow_attr *attr, 514 struct mlx5_flow_act *flow_act, 515 struct mlx5_flow_destination *dest, 516 int num_dest); 517 518 void 519 mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw, 520 struct mlx5_termtbl_handle *tt); 521 522 void 523 mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec); 524 525 struct mlx5_flow_handle * 526 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, 527 struct mlx5_flow_spec *spec, 528 struct mlx5_flow_attr *attr); 529 struct mlx5_flow_handle * 530 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, 531 struct mlx5_flow_spec *spec, 532 struct mlx5_flow_attr *attr); 533 void 534 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, 535 struct mlx5_flow_handle *rule, 536 struct mlx5_flow_attr *attr); 537 void 538 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, 539 struct mlx5_flow_handle *rule, 540 struct mlx5_flow_attr *attr); 541 542 struct mlx5_flow_handle * 543 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, 544 struct mlx5_flow_destination *dest); 545 546 enum { 547 SET_VLAN_STRIP = BIT(0), 548 SET_VLAN_INSERT = BIT(1) 549 }; 550 551 enum mlx5_flow_match_level { 552 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, 553 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, 554 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, 555 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, 556 }; 557 558 /* current maximum for flow based vport multicasting */ 559 #define MLX5_MAX_FLOW_FWD_VPORTS 32 560 561 enum { 562 MLX5_ESW_DEST_ENCAP = BIT(0), 563 MLX5_ESW_DEST_ENCAP_VALID = BIT(1), 564 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE = BIT(2), 565 }; 566 567 struct mlx5_esw_flow_attr { 568 struct mlx5_eswitch_rep *in_rep; 569 struct mlx5_core_dev *in_mdev; 570 struct mlx5_core_dev *counter_dev; 571 struct mlx5e_tc_int_port *dest_int_port; 572 struct mlx5e_tc_int_port *int_port; 573 574 int split_count; 575 int out_count; 576 577 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; 578 u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; 579 u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; 580 u8 total_vlan; 581 struct { 582 u32 flags; 583 bool vport_valid; 584 u16 vport; 585 struct mlx5_pkt_reformat *pkt_reformat; 586 struct mlx5_core_dev *mdev; 587 struct mlx5_termtbl_handle *termtbl; 588 int src_port_rewrite_act_id; 589 } dests[MLX5_MAX_FLOW_FWD_VPORTS]; 590 struct mlx5_rx_tun_attr *rx_tun_attr; 591 struct ethhdr eth; 592 struct mlx5_pkt_reformat *decap_pkt_reformat; 593 }; 594 595 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, 596 struct netlink_ext_ack *extack); 597 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); 598 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, 599 struct netlink_ext_ack *extack); 600 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); 601 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, 602 enum devlink_eswitch_encap_mode encap, 603 struct netlink_ext_ack *extack); 604 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, 605 enum devlink_eswitch_encap_mode *encap); 606 int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port, 607 u8 *hw_addr, int *hw_addr_len, 608 struct netlink_ext_ack *extack); 609 int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port, 610 const u8 *hw_addr, int hw_addr_len, 611 struct netlink_ext_ack *extack); 612 int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled, 613 struct netlink_ext_ack *extack); 614 int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable, 615 struct netlink_ext_ack *extack); 616 int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled, 617 struct netlink_ext_ack *extack); 618 int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable, 619 struct netlink_ext_ack *extack); 620 int mlx5_devlink_pf_port_fn_state_get(struct devlink_port *port, 621 enum devlink_port_fn_state *state, 622 enum devlink_port_fn_opstate *opstate, 623 struct netlink_ext_ack *extack); 624 int mlx5_devlink_pf_port_fn_state_set(struct devlink_port *port, 625 enum devlink_port_fn_state state, 626 struct netlink_ext_ack *extack); 627 #ifdef CONFIG_XFRM_OFFLOAD 628 int mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port *port, bool *is_enabled, 629 struct netlink_ext_ack *extack); 630 int mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port *port, bool enable, 631 struct netlink_ext_ack *extack); 632 int mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port *port, bool *is_enabled, 633 struct netlink_ext_ack *extack); 634 int mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port *port, bool enable, 635 struct netlink_ext_ack *extack); 636 #endif /* CONFIG_XFRM_OFFLOAD */ 637 int mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port *port, 638 u32 *max_io_eqs, 639 struct netlink_ext_ack *extack); 640 int mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port, 641 u32 max_io_eqs, 642 struct netlink_ext_ack *extack); 643 int mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port *port, 644 struct netlink_ext_ack *extack); 645 646 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); 647 648 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, 649 u16 vport, u16 vlan, u8 qos, u8 set_flags); 650 651 static inline bool esw_vst_mode_is_steering(struct mlx5_eswitch *esw) 652 { 653 return (MLX5_CAP_ESW_EGRESS_ACL(esw->dev, pop_vlan) && 654 MLX5_CAP_ESW_INGRESS_ACL(esw->dev, push_vlan)); 655 } 656 657 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, 658 u8 vlan_depth) 659 { 660 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && 661 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); 662 663 if (vlan_depth == 1) 664 return ret; 665 666 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && 667 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); 668 } 669 670 bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, 671 struct mlx5_core_dev *dev1); 672 673 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); 674 struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(struct mlx5_core_dev *dev, 675 const u32 *out); 676 bool mlx5_esw_get_spf_disabled(struct mlx5_core_dev *dev, const u32 *out, 677 u16 vhca_id); 678 int mlx5_esw_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num); 679 int mlx5_esw_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_num); 680 int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev); 681 int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev); 682 683 void mlx5_esw_adjacent_vhcas_setup(struct mlx5_eswitch *esw); 684 void mlx5_esw_adjacent_vhcas_cleanup(struct mlx5_eswitch *esw); 685 int mlx5_esw_adj_vport_modify(struct mlx5_core_dev *dev, u16 vport, 686 bool connect); 687 int mlx5_esw_create_esw_vport(struct mlx5_core_dev *dev, u16 vhca_id, 688 u16 *vport_num); 689 void mlx5_esw_destroy_esw_vport(struct mlx5_core_dev *dev, u16 vport); 690 691 #define MLX5_DEBUG_ESWITCH_MASK BIT(3) 692 693 #define esw_info(__dev, format, ...) \ 694 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) 695 696 #define esw_warn(__dev, format, ...) \ 697 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) 698 699 #define esw_debug(dev, format, ...) \ 700 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) 701 702 static inline bool mlx5_esw_allowed(const struct mlx5_eswitch *esw) 703 { 704 return esw && MLX5_ESWITCH_MANAGER(esw->dev); 705 } 706 707 static inline bool 708 mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num) 709 { 710 return esw->manager_vport == vport_num; 711 } 712 713 static inline bool mlx5_esw_is_owner(struct mlx5_eswitch *esw, u16 vport_num, 714 u16 esw_owner_vhca_id) 715 { 716 return esw_owner_vhca_id == MLX5_CAP_GEN(esw->dev, vhca_id) || 717 (vport_num == MLX5_VPORT_UPLINK && mlx5_lag_is_master(esw->dev)); 718 } 719 720 static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev) 721 { 722 return mlx5_core_is_ecpf_esw_manager(dev) ? 723 MLX5_VPORT_HOST_PF : MLX5_VPORT_FIRST_HOST_VF; 724 } 725 726 static inline bool mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev *dev) 727 { 728 return mlx5_core_is_ecpf_esw_manager(dev); 729 } 730 731 static inline unsigned int 732 mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, 733 u16 vport_num) 734 { 735 return (MLX5_CAP_GEN(dev, vhca_id) << 16) | vport_num; 736 } 737 738 static inline u16 739 mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index) 740 { 741 return dl_port_index & 0xffff; 742 } 743 744 static inline bool mlx5_esw_is_fdb_created(struct mlx5_eswitch *esw) 745 { 746 return esw->fdb_table.flags & MLX5_ESW_FDB_CREATED; 747 } 748 749 /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ 750 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); 751 752 /* Each mark identifies eswitch vport type. 753 * MLX5_ESW_VPT_HOST_FN is used to identify both PF and VF ports using 754 * a single mark. 755 * MLX5_ESW_VPT_VF identifies a SRIOV VF vport. 756 * MLX5_ESW_VPT_SF identifies SF vport. 757 */ 758 #define MLX5_ESW_VPT_HOST_FN XA_MARK_0 759 #define MLX5_ESW_VPT_VF XA_MARK_1 760 #define MLX5_ESW_VPT_SF XA_MARK_2 761 762 /* The vport iterator is valid only after vport are initialized in mlx5_eswitch_init. 763 * Borrowed the idea from xa_for_each_marked() but with support for desired last element. 764 */ 765 766 #define mlx5_esw_for_each_vport(esw, index, vport) \ 767 xa_for_each(&((esw)->vports), index, vport) 768 769 #define mlx5_esw_for_each_entry_marked(xa, index, entry, last, filter) \ 770 for (index = 0, entry = xa_find(xa, &index, last, filter); \ 771 entry; entry = xa_find_after(xa, &index, last, filter)) 772 773 #define mlx5_esw_for_each_vport_marked(esw, index, vport, last, filter) \ 774 mlx5_esw_for_each_entry_marked(&((esw)->vports), index, vport, last, filter) 775 776 #define mlx5_esw_for_each_vf_vport(esw, index, vport, last) \ 777 mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_VF) 778 779 #define mlx5_esw_for_each_host_func_vport(esw, index, vport, last) \ 780 mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_HOST_FN) 781 782 /* This macro should only be used if EC SRIOV is enabled. 783 * 784 * Because there were no more marks available on the xarray this uses a 785 * for_each_range approach. The range is only valid when EC SRIOV is enabled 786 */ 787 #define mlx5_esw_for_each_ec_vf_vport(esw, index, vport, last) \ 788 xa_for_each_range(&((esw)->vports), \ 789 index, \ 790 vport, \ 791 MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base), \ 792 MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base) +\ 793 (last) - 1) 794 795 /* SPF vport numbers are not contiguous, iterate via the spfs array 796 * and look up each vport in the xarray. 797 */ 798 #define mlx5_esw_for_each_spf_vport(esw, index, vport) \ 799 for ((index) = 0; \ 800 (index) < (esw)->esw_funcs.num_spfs && \ 801 ((vport) = xa_load(&(esw)->vports, \ 802 (esw)->esw_funcs.spfs[(index)].vport_num)); \ 803 (index)++) 804 805 #define mlx5_esw_for_each_rep(esw, i, rep) \ 806 xa_for_each(&((esw)->offloads.vport_reps), i, rep) 807 808 struct mlx5_eswitch *__must_check 809 mlx5_devlink_eswitch_get(struct devlink *devlink); 810 811 struct mlx5_eswitch *mlx5_devlink_eswitch_nocheck_get(struct devlink *devlink); 812 813 struct mlx5_vport *__must_check 814 mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); 815 816 bool mlx5_eswitch_is_vf_vport(struct mlx5_eswitch *esw, u16 vport_num); 817 int mlx5_esw_spf_vport_to_idx(struct mlx5_eswitch *esw, u16 vport_num); 818 bool mlx5_esw_is_spf_vport(struct mlx5_eswitch *esw, u16 vport_num); 819 bool mlx5_eswitch_is_pf_vf_vport(struct mlx5_eswitch *esw, u16 vport_num); 820 bool mlx5_esw_is_sf_vport(struct mlx5_eswitch *esw, u16 vport_num); 821 822 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data); 823 824 int 825 mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, 826 enum mlx5_eswitch_vport_event enabled_events); 827 void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw); 828 829 int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 830 enum mlx5_eswitch_vport_event enabled_events); 831 void mlx5_esw_vport_disable(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 832 833 int 834 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, 835 struct mlx5_vport *vport); 836 void 837 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw, 838 struct mlx5_vport *vport); 839 840 struct esw_vport_tbl_namespace { 841 int max_fte; 842 int max_num_groups; 843 u32 flags; 844 }; 845 846 struct mlx5_vport_tbl_attr { 847 u32 chain; 848 u16 prio; 849 u16 vport; 850 struct esw_vport_tbl_namespace *vport_ns; 851 }; 852 853 struct mlx5_flow_table * 854 mlx5_esw_vporttbl_get(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); 855 void 856 mlx5_esw_vporttbl_put(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); 857 858 struct mlx5_flow_handle * 859 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag); 860 861 void mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw, 862 u32 *flow_group_in, 863 int match_params); 864 865 void mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw, 866 u16 vport, 867 struct mlx5_flow_spec *spec); 868 869 int mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 870 void mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 871 872 int mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 873 struct mlx5_devlink_port *dl_port, 874 u32 controller, u32 sfnum); 875 void mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 876 877 int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 878 void mlx5_esw_offloads_unload_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 879 880 int mlx5_eswitch_load_sf_vport(struct mlx5_eswitch *esw, u16 vport_num, 881 enum mlx5_eswitch_vport_event enabled_events, 882 struct mlx5_devlink_port *dl_port, u32 controller, u32 sfnum); 883 void mlx5_eswitch_unload_sf_vport(struct mlx5_eswitch *esw, u16 vport_num); 884 885 int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs, 886 enum mlx5_eswitch_vport_event enabled_events); 887 void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs); 888 889 int mlx5_esw_offloads_pf_vf_devlink_port_init(struct mlx5_eswitch *esw, 890 struct mlx5_vport *vport); 891 void mlx5_esw_offloads_pf_vf_devlink_port_cleanup(struct mlx5_eswitch *esw, 892 struct mlx5_vport *vport); 893 894 int mlx5_esw_offloads_sf_devlink_port_init(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 895 struct mlx5_devlink_port *dl_port, 896 u32 controller, u32 sfnum); 897 void mlx5_esw_offloads_sf_devlink_port_cleanup(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 898 899 int mlx5_esw_offloads_devlink_port_register(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 900 void mlx5_esw_offloads_devlink_port_unregister(struct mlx5_vport *vport); 901 struct devlink_port *mlx5_esw_offloads_devlink_port(struct mlx5_eswitch *esw, u16 vport_num); 902 903 int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs, u16 *sf_base_id); 904 int mlx5_esw_sf_max_spf_functions(struct mlx5_core_dev *dev, int spf_idx, 905 u16 *max_sfs, u16 *sf_base_id); 906 907 int mlx5_esw_get_num_spfs(struct mlx5_core_dev *dev); 908 int mlx5_esw_spf_get_host_number(struct mlx5_core_dev *dev, int spf_idx, 909 u16 *host_number); 910 u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_dev *dev); 911 u16 mlx5_esw_get_hpf_pf_num(struct mlx5_core_dev *dev); 912 u16 mlx5_esw_sf_controller_to_pfnum(struct mlx5_core_dev *dev, u32 controller); 913 bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev); 914 915 int mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch *esw, 916 struct mlx5_vport *vport); 917 void mlx5_esw_vport_vhca_id_unmap(struct mlx5_eswitch *esw, 918 struct mlx5_vport *vport); 919 int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num); 920 bool mlx5_esw_vport_vhca_id(struct mlx5_eswitch *esw, u16 vportn, u16 *vhca_id); 921 u16 mlx5_esw_vhca_id_to_func_type(struct mlx5_core_dev *dev, u16 vhca_id); 922 923 void mlx5_esw_offloads_rep_remove(struct mlx5_eswitch *esw, 924 const struct mlx5_vport *vport); 925 int mlx5_esw_offloads_rep_add(struct mlx5_eswitch *esw, 926 const struct mlx5_vport *vport); 927 928 /** 929 * struct mlx5_esw_event_info - Indicates eswitch mode changed/changing. 930 * 931 * @new_mode: New mode of eswitch. 932 */ 933 struct mlx5_esw_event_info { 934 u16 new_mode; 935 }; 936 937 int mlx5_esw_event_notifier_register(struct mlx5_core_dev *dev, 938 struct notifier_block *n); 939 void mlx5_esw_event_notifier_unregister(struct mlx5_core_dev *dev, 940 struct notifier_block *n); 941 942 bool mlx5_esw_hold(struct mlx5_core_dev *dev); 943 void mlx5_esw_release(struct mlx5_core_dev *dev); 944 void mlx5_esw_get(struct mlx5_core_dev *dev); 945 void mlx5_esw_put(struct mlx5_core_dev *dev); 946 int mlx5_esw_try_lock(struct mlx5_eswitch *esw); 947 int mlx5_esw_lock(struct mlx5_eswitch *esw); 948 void mlx5_esw_unlock(struct mlx5_eswitch *esw); 949 950 void esw_vport_change_handle_locked(struct mlx5_vport *vport); 951 952 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller); 953 954 int mlx5_eswitch_offloads_vport_lag_add_one(struct mlx5_eswitch *master_esw, 955 struct mlx5_eswitch *slave_esw); 956 void mlx5_eswitch_offloads_vport_lag_del_one(struct mlx5_eswitch *master_esw, 957 struct mlx5_eswitch *slave_esw); 958 int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw, 959 struct mlx5_eswitch *slave_esw, int max_slaves); 960 void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw, 961 struct mlx5_eswitch *slave_esw); 962 int mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw); 963 void mlx5_eswitch_unload_reps(struct mlx5_eswitch *esw); 964 bool mlx5_eswitch_is_peer(struct mlx5_eswitch *esw, 965 struct mlx5_eswitch *peer_esw); 966 967 bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb); 968 void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev); 969 970 int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev); 971 void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev); 972 973 static inline int mlx5_eswitch_num_vfs(struct mlx5_eswitch *esw) 974 { 975 if (mlx5_esw_allowed(esw)) 976 return esw->esw_funcs.num_vfs; 977 978 return 0; 979 } 980 981 static inline struct mlx5_flow_table * 982 mlx5_eswitch_get_slow_fdb(struct mlx5_eswitch *esw) 983 { 984 return esw->fdb_table.offloads.slow_fdb; 985 } 986 987 int mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch *esw, struct mlx5_flow_handle *rule, 988 struct mlx5_esw_flow_attr *esw_attr, int attr_idx); 989 bool mlx5_eswitch_block_ipsec(struct mlx5_core_dev *dev); 990 void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev *dev); 991 bool mlx5_esw_ipsec_vf_offload_supported(struct mlx5_core_dev *dev); 992 int mlx5_esw_ipsec_vf_offload_get(struct mlx5_core_dev *dev, 993 struct mlx5_vport *vport); 994 int mlx5_esw_ipsec_vf_crypto_offload_supported(struct mlx5_core_dev *dev, 995 u16 vport_num); 996 int mlx5_esw_ipsec_vf_crypto_offload_set(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 997 bool enable); 998 int mlx5_esw_ipsec_vf_packet_offload_set(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 999 bool enable); 1000 int mlx5_esw_ipsec_vf_packet_offload_supported(struct mlx5_core_dev *dev, 1001 u16 vport_num); 1002 bool mlx5_esw_host_functions_enabled(const struct mlx5_core_dev *dev); 1003 void mlx5_eswitch_safe_aux_devs_remove(struct mlx5_core_dev *dev); 1004 struct mlx5_flow_group * 1005 mlx5_esw_lag_demux_fg_create(struct mlx5_eswitch *esw, 1006 struct mlx5_flow_table *ft); 1007 struct mlx5_flow_handle * 1008 mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch *esw, u16 vport_num, 1009 struct mlx5_flow_table *lag_ft); 1010 void mlx5_esw_reps_block(struct mlx5_eswitch *esw); 1011 void mlx5_esw_reps_unblock(struct mlx5_eswitch *esw); 1012 #else /* CONFIG_MLX5_ESWITCH */ 1013 /* eswitch API stubs */ 1014 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } 1015 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} 1016 static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; } 1017 static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf) {} 1018 static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {} 1019 static inline void 1020 mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw, 1021 const struct mlx5_devcom_match_attr *attr) {} 1022 static inline void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw) {} 1023 static inline bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw) { return false; } 1024 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } 1025 static inline 1026 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, u16 vport, int link_state) { return 0; } 1027 static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) 1028 { 1029 return ERR_PTR(-EOPNOTSUPP); 1030 } 1031 1032 static inline struct mlx5_esw_pf_info 1033 mlx5_esw_get_host_pf_info(struct mlx5_core_dev *dev, const u32 *out) 1034 { 1035 return (struct mlx5_esw_pf_info) {}; 1036 } 1037 1038 static inline struct mlx5_flow_handle * 1039 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) 1040 { 1041 return ERR_PTR(-EOPNOTSUPP); 1042 } 1043 1044 static inline unsigned int 1045 mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, 1046 u16 vport_num) 1047 { 1048 return vport_num; 1049 } 1050 1051 static inline int 1052 mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw, 1053 struct mlx5_eswitch *slave_esw, int max_slaves) 1054 { 1055 return 0; 1056 } 1057 1058 static inline void 1059 mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw, 1060 struct mlx5_eswitch *slave_esw) {} 1061 1062 static inline int 1063 mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw) 1064 { 1065 return 0; 1066 } 1067 1068 static inline void 1069 mlx5_eswitch_unload_reps(struct mlx5_eswitch *esw) {} 1070 1071 static inline bool 1072 mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb) 1073 { 1074 return true; 1075 } 1076 1077 static inline void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev) 1078 { 1079 } 1080 1081 static inline int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev) { return 0; } 1082 static inline void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev) {} 1083 static inline bool mlx5_eswitch_block_ipsec(struct mlx5_core_dev *dev) 1084 { 1085 return false; 1086 } 1087 1088 static inline void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev *dev) {} 1089 1090 static inline bool 1091 mlx5_esw_host_functions_enabled(const struct mlx5_core_dev *dev) 1092 { 1093 return true; 1094 } 1095 1096 static inline void mlx5_esw_reps_block(struct mlx5_eswitch *esw) {} 1097 static inline void mlx5_esw_reps_unblock(struct mlx5_eswitch *esw) {} 1098 1099 static inline bool 1100 mlx5_esw_vport_vhca_id(struct mlx5_eswitch *esw, u16 vportn, u16 *vhca_id) 1101 { 1102 return false; 1103 } 1104 1105 static inline u16 1106 mlx5_esw_vhca_id_to_func_type(struct mlx5_core_dev *dev, u16 vhca_id) 1107 { 1108 return MLX5_FUNC_TYPE_NONE; 1109 } 1110 1111 static inline void 1112 mlx5_eswitch_safe_aux_devs_remove(struct mlx5_core_dev *dev) {} 1113 static inline struct mlx5_flow_handle * 1114 mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch *esw, u16 vport_num, 1115 struct mlx5_flow_table *lag_ft) 1116 { 1117 return ERR_PTR(-EOPNOTSUPP); 1118 } 1119 1120 #endif /* CONFIG_MLX5_ESWITCH */ 1121 1122 #endif /* __MLX5_ESWITCH_H__ */ 1123