1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/circ_buf.h>
12 #include <linux/module.h>
13 #include <linux/ioport.h>
14 #include <linux/init.h>
15 #include <linux/console.h>
16 #include <linux/sysrq.h>
17 #include <linux/platform_device.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/ktime.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/rational.h>
27 #include <linux/slab.h>
28 #include <linux/of.h>
29 #include <linux/io.h>
30 #include <linux/iopoll.h>
31 #include <linux/dma-mapping.h>
32
33 #include <asm/irq.h>
34 #include <linux/dma/imx-dma.h>
35
36 #include "serial_mctrl_gpio.h"
37
38 /* Register definitions */
39 #define URXD0 0x0 /* Receiver Register */
40 #define URTX0 0x40 /* Transmitter Register */
41 #define UCR1 0x80 /* Control Register 1 */
42 #define UCR2 0x84 /* Control Register 2 */
43 #define UCR3 0x88 /* Control Register 3 */
44 #define UCR4 0x8c /* Control Register 4 */
45 #define UFCR 0x90 /* FIFO Control Register */
46 #define USR1 0x94 /* Status Register 1 */
47 #define USR2 0x98 /* Status Register 2 */
48 #define UESC 0x9c /* Escape Character Register */
49 #define UTIM 0xa0 /* Escape Timer Register */
50 #define UBIR 0xa4 /* BRM Incremental Register */
51 #define UBMR 0xa8 /* BRM Modulator Register */
52 #define UBRC 0xac /* Baud Rate Count Register */
53 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
54 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
55 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
56
57 /* UART Control Register Bit Fields.*/
58 #define URXD_DUMMY_READ (1<<16)
59 #define URXD_CHARRDY (1<<15)
60 #define URXD_ERR (1<<14)
61 #define URXD_OVRRUN (1<<13)
62 #define URXD_FRMERR (1<<12)
63 #define URXD_BRK (1<<11)
64 #define URXD_PRERR (1<<10)
65 #define URXD_RX_DATA (0xFF<<0)
66 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
67 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
68 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
69 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
70 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
71 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
72 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
73 #define UCR1_IREN (1<<7) /* Infrared interface enable */
74 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
75 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
76 #define UCR1_SNDBRK (1<<4) /* Send break */
77 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
78 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
79 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
80 #define UCR1_DOZE (1<<1) /* Doze */
81 #define UCR1_UARTEN (1<<0) /* UART enabled */
82 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
83 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
84 #define UCR2_CTSC (1<<13) /* CTS pin control */
85 #define UCR2_CTS (1<<12) /* Clear to send */
86 #define UCR2_ESCEN (1<<11) /* Escape enable */
87 #define UCR2_PREN (1<<8) /* Parity enable */
88 #define UCR2_PROE (1<<7) /* Parity odd/even */
89 #define UCR2_STPB (1<<6) /* Stop */
90 #define UCR2_WS (1<<5) /* Word size */
91 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
92 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
93 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
94 #define UCR2_RXEN (1<<1) /* Receiver enabled */
95 #define UCR2_SRST (1<<0) /* SW reset */
96 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
97 #define UCR3_PARERREN (1<<12) /* Parity enable */
98 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
99 #define UCR3_DSR (1<<10) /* Data set ready */
100 #define UCR3_DCD (1<<9) /* Data carrier detect */
101 #define UCR3_RI (1<<8) /* Ring indicator */
102 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
103 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
104 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
105 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
106 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
107 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
108 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
109 #define UCR3_BPEN (1<<0) /* Preset registers enable */
110 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
111 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
112 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
113 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
114 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
115 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
116 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
117 #define UCR4_IRSC (1<<5) /* IR special case */
118 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
119 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
120 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
121 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
122 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
123 #define UFCR_RXTL_MASK 0x3F /* Receiver trigger 6 bits wide */
124 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
125 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
126 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
127 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
128 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
129 #define USR1_RTSS (1<<14) /* RTS pin status */
130 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
131 #define USR1_RTSD (1<<12) /* RTS delta */
132 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
133 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
134 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
135 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
136 #define USR1_DTRD (1<<7) /* DTR Delta */
137 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
138 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
139 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
140 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
141 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
142 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
143 #define USR2_IDLE (1<<12) /* Idle condition */
144 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
145 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
146 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
147 #define USR2_WAKE (1<<7) /* Wake */
148 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
149 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
150 #define USR2_TXDC (1<<3) /* Transmitter complete */
151 #define USR2_BRCD (1<<2) /* Break condition */
152 #define USR2_ORE (1<<1) /* Overrun error */
153 #define USR2_RDR (1<<0) /* Recv data ready */
154 #define UTS_FRCPERR (1<<13) /* Force parity error */
155 #define UTS_LOOP (1<<12) /* Loop tx and rx */
156 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
157 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
158 #define UTS_TXFULL (1<<4) /* TxFIFO full */
159 #define UTS_RXFULL (1<<3) /* RxFIFO full */
160 #define UTS_SOFTRST (1<<0) /* Software reset */
161
162 /* We've been assigned a range on the "Low-density serial ports" major */
163 #define SERIAL_IMX_MAJOR 207
164 #define MINOR_START 16
165 #define DEV_NAME "ttymxc"
166
167 /*
168 * This determines how often we check the modem status signals
169 * for any change. They generally aren't connected to an IRQ
170 * so we have to poll them. We also check immediately before
171 * filling the TX fifo incase CTS has been dropped.
172 */
173 #define MCTRL_TIMEOUT (250*HZ/1000)
174
175 #define DRIVER_NAME "IMX-uart"
176
177 #define UART_NR 8
178
179 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
180 enum imx_uart_type {
181 IMX1_UART,
182 IMX21_UART,
183 };
184
185 /* device type dependent stuff */
186 struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189 };
190
191 enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* counter to stop 0xff flood */
214 int idle_counter;
215
216 /* DMA fields */
217 unsigned int dma_is_enabled:1;
218 unsigned int dma_is_rxing:1;
219 unsigned int dma_is_txing:1;
220 struct dma_chan *dma_chan_rx, *dma_chan_tx;
221 struct scatterlist rx_sgl, tx_sgl[2];
222 void *rx_buf;
223 struct circ_buf rx_ring;
224 unsigned int rx_buf_size;
225 unsigned int rx_period_length;
226 unsigned int rx_periods;
227 dma_cookie_t rx_cookie;
228 unsigned int tx_bytes;
229 unsigned int dma_tx_nents;
230 unsigned int saved_reg[10];
231 bool context_saved;
232
233 bool last_putchar_was_newline;
234
235 enum imx_tx_state tx_state;
236 struct hrtimer trigger_start_tx;
237 struct hrtimer trigger_stop_tx;
238 unsigned int rxtl;
239 };
240
241 struct imx_port_ucrs {
242 unsigned int ucr1;
243 unsigned int ucr2;
244 unsigned int ucr3;
245 };
246
247 static const struct imx_uart_data imx_uart_imx1_devdata = {
248 .uts_reg = IMX1_UTS,
249 .devtype = IMX1_UART,
250 };
251
252 static const struct imx_uart_data imx_uart_imx21_devdata = {
253 .uts_reg = IMX21_UTS,
254 .devtype = IMX21_UART,
255 };
256
257 static const struct of_device_id imx_uart_dt_ids[] = {
258 /*
259 * For reasons unknown to me, some UART devices (e.g. imx6ul's) are
260 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
261 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
262 * doesn't make any distinction between these two variants.
263 */
264 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
265 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
266 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
267 { /* sentinel */ }
268 };
269 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
270
to_imx_port(struct uart_port * port)271 static inline struct imx_port *to_imx_port(struct uart_port *port)
272 {
273 return container_of(port, struct imx_port, port);
274 }
275
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)276 static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
277 {
278 writel(val, sport->port.membase + offset);
279 }
280
imx_uart_readl(struct imx_port * sport,u32 offset)281 static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
282 {
283 return readl(sport->port.membase + offset);
284 }
285
imx_uart_uts_reg(struct imx_port * sport)286 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
287 {
288 return sport->devdata->uts_reg;
289 }
290
imx_uart_is_imx1(struct imx_port * sport)291 static inline int imx_uart_is_imx1(struct imx_port *sport)
292 {
293 return sport->devdata->devtype == IMX1_UART;
294 }
295
296 /*
297 * Save and restore functions for UCR1, UCR2 and UCR3 registers
298 */
299 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)300 static void imx_uart_ucrs_save(struct imx_port *sport,
301 struct imx_port_ucrs *ucr)
302 {
303 /* save control registers */
304 ucr->ucr1 = imx_uart_readl(sport, UCR1);
305 ucr->ucr2 = imx_uart_readl(sport, UCR2);
306 ucr->ucr3 = imx_uart_readl(sport, UCR3);
307 }
308
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)309 static void imx_uart_ucrs_restore(struct imx_port *sport,
310 struct imx_port_ucrs *ucr)
311 {
312 /* restore control registers */
313 imx_uart_writel(sport, ucr->ucr1, UCR1);
314 imx_uart_writel(sport, ucr->ucr2, UCR2);
315 imx_uart_writel(sport, ucr->ucr3, UCR3);
316 }
317 #endif
318
319 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)320 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
321 {
322 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
323
324 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
325 }
326
327 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)328 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
329 {
330 *ucr2 &= ~UCR2_CTSC;
331 *ucr2 |= UCR2_CTS;
332
333 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
334 }
335
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)336 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
337 {
338 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
339 }
340
341 /* called with port.lock taken and irqs off */
imx_uart_soft_reset(struct imx_port * sport)342 static void imx_uart_soft_reset(struct imx_port *sport)
343 {
344 int i = 10;
345 u32 ucr2, ubir, ubmr, uts;
346
347 /*
348 * According to the Reference Manual description of the UART SRST bit:
349 *
350 * "Reset the transmit and receive state machines,
351 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
352 * and UTS[6-3]".
353 *
354 * We don't need to restore the old values from USR1, USR2, URXD and
355 * UTXD. UBRC is read only, so only save/restore the other three
356 * registers.
357 */
358 ubir = imx_uart_readl(sport, UBIR);
359 ubmr = imx_uart_readl(sport, UBMR);
360 uts = imx_uart_readl(sport, IMX21_UTS);
361
362 ucr2 = imx_uart_readl(sport, UCR2);
363 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
364
365 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
366 udelay(1);
367
368 /* Restore the registers */
369 imx_uart_writel(sport, ubir, UBIR);
370 imx_uart_writel(sport, ubmr, UBMR);
371 imx_uart_writel(sport, uts, IMX21_UTS);
372
373 sport->idle_counter = 0;
374 }
375
376 /* called with port.lock taken and irqs off */
imx_uart_disable_loopback_rs485(struct imx_port * sport)377 static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
378 {
379 unsigned int uts;
380
381 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
382 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
383 uts &= ~UTS_LOOP;
384 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
385 }
386
387 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)388 static void imx_uart_start_rx(struct uart_port *port)
389 {
390 struct imx_port *sport = to_imx_port(port);
391 unsigned int ucr1, ucr2;
392
393 ucr1 = imx_uart_readl(sport, UCR1);
394 ucr2 = imx_uart_readl(sport, UCR2);
395
396 ucr2 |= UCR2_RXEN;
397
398 if (sport->dma_is_enabled) {
399 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
400 } else {
401 ucr1 |= UCR1_RRDYEN;
402 ucr2 |= UCR2_ATEN;
403 }
404
405 /* Write UCR2 first as it includes RXEN */
406 imx_uart_writel(sport, ucr2, UCR2);
407 imx_uart_writel(sport, ucr1, UCR1);
408 imx_uart_disable_loopback_rs485(sport);
409 }
410
411 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)412 static void imx_uart_stop_tx(struct uart_port *port)
413 {
414 struct imx_port *sport = to_imx_port(port);
415 u32 ucr1, ucr4, usr2;
416
417 if (sport->tx_state == OFF)
418 return;
419
420 /*
421 * We are maybe in the SMP context, so if the DMA TX thread is running
422 * on other cpu, we have to wait for it to finish.
423 */
424 if (sport->dma_is_txing)
425 return;
426
427 ucr1 = imx_uart_readl(sport, UCR1);
428 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
429
430 ucr4 = imx_uart_readl(sport, UCR4);
431 usr2 = imx_uart_readl(sport, USR2);
432 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
433 /* The shifter is still busy, so retry once TC triggers */
434 return;
435 }
436
437 ucr4 &= ~UCR4_TCEN;
438 imx_uart_writel(sport, ucr4, UCR4);
439
440 /* in rs485 mode disable transmitter */
441 if (port->rs485.flags & SER_RS485_ENABLED) {
442 if (sport->tx_state == SEND) {
443 sport->tx_state = WAIT_AFTER_SEND;
444
445 if (port->rs485.delay_rts_after_send > 0) {
446 start_hrtimer_ms(&sport->trigger_stop_tx,
447 port->rs485.delay_rts_after_send);
448 return;
449 }
450
451 /* continue without any delay */
452 }
453
454 if (sport->tx_state == WAIT_AFTER_RTS ||
455 sport->tx_state == WAIT_AFTER_SEND) {
456 u32 ucr2;
457
458 hrtimer_try_to_cancel(&sport->trigger_start_tx);
459
460 ucr2 = imx_uart_readl(sport, UCR2);
461 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
462 imx_uart_rts_active(sport, &ucr2);
463 else
464 imx_uart_rts_inactive(sport, &ucr2);
465 imx_uart_writel(sport, ucr2, UCR2);
466
467 if (!port->rs485_rx_during_tx_gpio)
468 imx_uart_start_rx(port);
469
470 sport->tx_state = OFF;
471 }
472 } else {
473 sport->tx_state = OFF;
474 }
475 }
476
477 /* called with port.lock taken and irqs off */
imx_uart_stop_rx_with_loopback_ctrl(struct uart_port * port,bool loopback)478 static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
479 {
480 struct imx_port *sport = to_imx_port(port);
481 u32 ucr1, ucr2, ucr4, uts;
482
483 ucr1 = imx_uart_readl(sport, UCR1);
484 ucr2 = imx_uart_readl(sport, UCR2);
485 ucr4 = imx_uart_readl(sport, UCR4);
486
487 if (sport->dma_is_enabled) {
488 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
489 } else {
490 ucr1 &= ~UCR1_RRDYEN;
491 ucr2 &= ~UCR2_ATEN;
492 ucr4 &= ~UCR4_OREN;
493 }
494 imx_uart_writel(sport, ucr1, UCR1);
495 imx_uart_writel(sport, ucr4, UCR4);
496
497 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
498 if (port->rs485.flags & SER_RS485_ENABLED &&
499 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
500 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
501 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
502 uts |= UTS_LOOP;
503 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
504 ucr2 |= UCR2_RXEN;
505 } else {
506 ucr2 &= ~UCR2_RXEN;
507 }
508
509 imx_uart_writel(sport, ucr2, UCR2);
510 }
511
512 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)513 static void imx_uart_stop_rx(struct uart_port *port)
514 {
515 /*
516 * Stop RX and enable loopback in order to make sure RS485 bus
517 * is not blocked. Se comment in imx_uart_probe().
518 */
519 imx_uart_stop_rx_with_loopback_ctrl(port, true);
520 }
521
522 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)523 static void imx_uart_enable_ms(struct uart_port *port)
524 {
525 struct imx_port *sport = to_imx_port(port);
526
527 mod_timer(&sport->timer, jiffies);
528
529 mctrl_gpio_enable_ms(sport->gpios);
530 }
531
532 static void imx_uart_dma_tx(struct imx_port *sport);
533
534 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)535 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
536 {
537 struct tty_port *tport = &sport->port.state->port;
538 unsigned char c;
539
540 if (sport->port.x_char) {
541 /* Send next char */
542 imx_uart_writel(sport, sport->port.x_char, URTX0);
543 sport->port.icount.tx++;
544 sport->port.x_char = 0;
545 return;
546 }
547
548 if (kfifo_is_empty(&tport->xmit_fifo) ||
549 uart_tx_stopped(&sport->port)) {
550 imx_uart_stop_tx(&sport->port);
551 return;
552 }
553
554 if (sport->dma_is_enabled) {
555 u32 ucr1;
556 /*
557 * We've just sent a X-char Ensure the TX DMA is enabled
558 * and the TX IRQ is disabled.
559 **/
560 ucr1 = imx_uart_readl(sport, UCR1);
561 ucr1 &= ~UCR1_TRDYEN;
562 if (sport->dma_is_txing) {
563 ucr1 |= UCR1_TXDMAEN;
564 imx_uart_writel(sport, ucr1, UCR1);
565 } else {
566 imx_uart_writel(sport, ucr1, UCR1);
567 imx_uart_dma_tx(sport);
568 }
569
570 return;
571 }
572
573 while (!(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) &&
574 uart_fifo_get(&sport->port, &c))
575 imx_uart_writel(sport, c, URTX0);
576
577 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
578 uart_write_wakeup(&sport->port);
579
580 if (kfifo_is_empty(&tport->xmit_fifo))
581 imx_uart_stop_tx(&sport->port);
582 }
583
imx_uart_dma_tx_callback(void * data)584 static void imx_uart_dma_tx_callback(void *data)
585 {
586 struct imx_port *sport = data;
587 struct tty_port *tport = &sport->port.state->port;
588 struct scatterlist *sgl = &sport->tx_sgl[0];
589 unsigned long flags;
590 u32 ucr1;
591
592 uart_port_lock_irqsave(&sport->port, &flags);
593
594 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
595
596 ucr1 = imx_uart_readl(sport, UCR1);
597 ucr1 &= ~UCR1_TXDMAEN;
598 imx_uart_writel(sport, ucr1, UCR1);
599
600 uart_xmit_advance(&sport->port, sport->tx_bytes);
601
602 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
603
604 sport->dma_is_txing = 0;
605
606 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
607 uart_write_wakeup(&sport->port);
608
609 if (!kfifo_is_empty(&tport->xmit_fifo) &&
610 !uart_tx_stopped(&sport->port))
611 imx_uart_dma_tx(sport);
612 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
613 u32 ucr4 = imx_uart_readl(sport, UCR4);
614 ucr4 |= UCR4_TCEN;
615 imx_uart_writel(sport, ucr4, UCR4);
616 }
617
618 uart_port_unlock_irqrestore(&sport->port, flags);
619 }
620
621 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)622 static void imx_uart_dma_tx(struct imx_port *sport)
623 {
624 struct tty_port *tport = &sport->port.state->port;
625 struct scatterlist *sgl = sport->tx_sgl;
626 struct dma_async_tx_descriptor *desc;
627 struct dma_chan *chan = sport->dma_chan_tx;
628 struct device *dev = sport->port.dev;
629 u32 ucr1, ucr4;
630 int ret;
631
632 if (sport->dma_is_txing)
633 return;
634
635 ucr4 = imx_uart_readl(sport, UCR4);
636 ucr4 &= ~UCR4_TCEN;
637 imx_uart_writel(sport, ucr4, UCR4);
638
639 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl));
640 sport->tx_bytes = kfifo_len(&tport->xmit_fifo);
641 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl,
642 ARRAY_SIZE(sport->tx_sgl), sport->tx_bytes);
643
644 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
645 if (ret == 0) {
646 dev_err(dev, "DMA mapping error for TX.\n");
647 return;
648 }
649 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
650 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
651 if (!desc) {
652 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
653 DMA_TO_DEVICE);
654 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
655 return;
656 }
657 desc->callback = imx_uart_dma_tx_callback;
658 desc->callback_param = sport;
659
660 dev_dbg(dev, "TX: prepare to send %u bytes by DMA.\n", sport->tx_bytes);
661
662 ucr1 = imx_uart_readl(sport, UCR1);
663 ucr1 |= UCR1_TXDMAEN;
664 imx_uart_writel(sport, ucr1, UCR1);
665
666 /* fire it */
667 sport->dma_is_txing = 1;
668 dmaengine_submit(desc);
669 dma_async_issue_pending(chan);
670 return;
671 }
672
673 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)674 static void imx_uart_start_tx(struct uart_port *port)
675 {
676 struct imx_port *sport = to_imx_port(port);
677 struct tty_port *tport = &sport->port.state->port;
678 u32 ucr1;
679
680 if (!sport->port.x_char && kfifo_is_empty(&tport->xmit_fifo))
681 return;
682
683 /*
684 * We cannot simply do nothing here if sport->tx_state == SEND already
685 * because UCR1_TXMPTYEN might already have been cleared in
686 * imx_uart_stop_tx(), but tx_state is still SEND.
687 */
688
689 if (port->rs485.flags & SER_RS485_ENABLED) {
690 if (sport->tx_state == OFF) {
691 u32 ucr2 = imx_uart_readl(sport, UCR2);
692 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
693 imx_uart_rts_active(sport, &ucr2);
694 else
695 imx_uart_rts_inactive(sport, &ucr2);
696 imx_uart_writel(sport, ucr2, UCR2);
697
698 /*
699 * Since we are about to transmit we can not stop RX
700 * with loopback enabled because that will make our
701 * transmitted data being just looped to RX.
702 */
703 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
704 !port->rs485_rx_during_tx_gpio)
705 imx_uart_stop_rx_with_loopback_ctrl(port, false);
706
707 sport->tx_state = WAIT_AFTER_RTS;
708
709 if (port->rs485.delay_rts_before_send > 0) {
710 start_hrtimer_ms(&sport->trigger_start_tx,
711 port->rs485.delay_rts_before_send);
712 return;
713 }
714
715 /* continue without any delay */
716 }
717
718 if (sport->tx_state == WAIT_AFTER_SEND
719 || sport->tx_state == WAIT_AFTER_RTS) {
720
721 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
722
723 /*
724 * Enable transmitter and shifter empty irq only if DMA
725 * is off. In the DMA case this is done in the
726 * tx-callback.
727 */
728 if (!sport->dma_is_enabled) {
729 u32 ucr4 = imx_uart_readl(sport, UCR4);
730 ucr4 |= UCR4_TCEN;
731 imx_uart_writel(sport, ucr4, UCR4);
732 }
733
734 sport->tx_state = SEND;
735 }
736 } else {
737 sport->tx_state = SEND;
738 }
739
740 if (!sport->dma_is_enabled) {
741 ucr1 = imx_uart_readl(sport, UCR1);
742 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
743 }
744
745 if (sport->dma_is_enabled) {
746 if (sport->port.x_char) {
747 /* We have X-char to send, so enable TX IRQ and
748 * disable TX DMA to let TX interrupt to send X-char */
749 ucr1 = imx_uart_readl(sport, UCR1);
750 ucr1 &= ~UCR1_TXDMAEN;
751 ucr1 |= UCR1_TRDYEN;
752 imx_uart_writel(sport, ucr1, UCR1);
753 return;
754 }
755
756 if (!kfifo_is_empty(&tport->xmit_fifo) &&
757 !uart_tx_stopped(port))
758 imx_uart_dma_tx(sport);
759 return;
760 }
761 }
762
__imx_uart_rtsint(int irq,void * dev_id)763 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
764 {
765 struct imx_port *sport = dev_id;
766 u32 usr1;
767
768 imx_uart_writel(sport, USR1_RTSD, USR1);
769 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
770 /*
771 * Update sport->old_status here, so any follow-up calls to
772 * imx_uart_mctrl_check() will be able to recognize that RTS
773 * state changed since last imx_uart_mctrl_check() call.
774 *
775 * In case RTS has been detected as asserted here and later on
776 * deasserted by the time imx_uart_mctrl_check() was called,
777 * imx_uart_mctrl_check() can detect the RTS state change and
778 * trigger uart_handle_cts_change() to unblock the port for
779 * further TX transfers.
780 */
781 if (usr1 & USR1_RTSS)
782 sport->old_status |= TIOCM_CTS;
783 else
784 sport->old_status &= ~TIOCM_CTS;
785 uart_handle_cts_change(&sport->port, usr1);
786 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
787
788 return IRQ_HANDLED;
789 }
790
imx_uart_rtsint(int irq,void * dev_id)791 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
792 {
793 struct imx_port *sport = dev_id;
794 irqreturn_t ret;
795
796 uart_port_lock(&sport->port);
797
798 ret = __imx_uart_rtsint(irq, dev_id);
799
800 uart_port_unlock(&sport->port);
801
802 return ret;
803 }
804
imx_uart_txint(int irq,void * dev_id)805 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
806 {
807 struct imx_port *sport = dev_id;
808
809 uart_port_lock(&sport->port);
810 imx_uart_transmit_buffer(sport);
811 uart_port_unlock(&sport->port);
812 return IRQ_HANDLED;
813 }
814
815 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
816 * This is to be called from Rx ISRs only when some bytes were actually
817 * received.
818 *
819 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
820 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
821 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
822 * that is terminated by any activity on RxD line, or could be stopped by
823 * issuing soft reset to the UART (just stop/start of RX does not help). Note
824 * that what we do here is sending isolated start bit about 2.4 times shorter
825 * than it is to be on UART configured baud rate.
826 *
827 * Called with port.lock taken and irqs off.
828 */
imx_uart_check_flood(struct imx_port * sport,u32 usr2)829 static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
830 {
831 /* To detect hardware 0xff flood we monitor RxD line between RX
832 * interrupts to isolate "receiving" of char(s) with no activity
833 * on RxD line, that'd never happen on actual data transfers.
834 *
835 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
836 * race here if we clear USR2_WAKE when receiving of a char is in
837 * progress, so we might get RX interrupt later with USR2_WAKE bit
838 * cleared. Note though that as we don't try to clear USR2_WAKE when we
839 * detected no activity, this race may hide actual activity only once.
840 *
841 * Yet another case where receive interrupt may occur without RxD
842 * activity is expiration of aging timer, so we consider this as well.
843 *
844 * We use 'idle_counter' to ensure that we got at least so many RX
845 * interrupts without any detected activity on RxD line. 2 cases
846 * described plus 1 to be on the safe side gives us a margin of 3,
847 * below. In practice I was not able to produce a false positive to
848 * induce soft reset at regular data transfers even using 1 as the
849 * margin, so 3 is actually very strong.
850 *
851 * We count interrupts, not chars in 'idle-counter' for simplicity.
852 */
853
854 if (usr2 & USR2_WAKE) {
855 imx_uart_writel(sport, USR2_WAKE, USR2);
856 sport->idle_counter = 0;
857 } else if (++sport->idle_counter > 3) {
858 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
859 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
860 }
861 }
862
863 /* called with port.lock taken and irqs off */
__imx_uart_rxint(int irq,void * dev_id)864 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
865 {
866 struct imx_port *sport = dev_id;
867 struct tty_port *port = &sport->port.state->port;
868 u32 usr2, rx;
869
870 /* If we received something, check for 0xff flood */
871 usr2 = imx_uart_readl(sport, USR2);
872 if (usr2 & USR2_RDR)
873 imx_uart_check_flood(sport, usr2);
874
875 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
876 unsigned int flg = TTY_NORMAL;
877 sport->port.icount.rx++;
878
879 if (unlikely(rx & URXD_ERR)) {
880 if (rx & URXD_BRK) {
881 sport->port.icount.brk++;
882 if (uart_handle_break(&sport->port))
883 continue;
884 }
885 else if (rx & URXD_PRERR)
886 sport->port.icount.parity++;
887 else if (rx & URXD_FRMERR)
888 sport->port.icount.frame++;
889 if (rx & URXD_OVRRUN)
890 sport->port.icount.overrun++;
891
892 if (rx & sport->port.ignore_status_mask)
893 continue;
894
895 rx &= (sport->port.read_status_mask | 0xFF);
896
897 if (rx & URXD_BRK)
898 flg = TTY_BREAK;
899 else if (rx & URXD_PRERR)
900 flg = TTY_PARITY;
901 else if (rx & URXD_FRMERR)
902 flg = TTY_FRAME;
903 if (rx & URXD_OVRRUN)
904 flg = TTY_OVERRUN;
905
906 sport->port.sysrq = 0;
907 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
908 continue;
909 }
910
911 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
912 continue;
913
914 if (tty_insert_flip_char(port, rx, flg) == 0)
915 sport->port.icount.buf_overrun++;
916 }
917
918 tty_flip_buffer_push(port);
919
920 return IRQ_HANDLED;
921 }
922
imx_uart_rxint(int irq,void * dev_id)923 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
924 {
925 struct imx_port *sport = dev_id;
926 irqreturn_t ret;
927
928 uart_port_lock(&sport->port);
929
930 ret = __imx_uart_rxint(irq, dev_id);
931
932 uart_port_unlock(&sport->port);
933
934 return ret;
935 }
936
937 static void imx_uart_clear_rx_errors(struct imx_port *sport);
938
939 /*
940 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
941 */
942 /* called with port.lock taken and irqs off */
imx_uart_get_hwmctrl(struct imx_port * sport)943 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
944 {
945 unsigned int tmp = TIOCM_DSR;
946 unsigned usr1 = imx_uart_readl(sport, USR1);
947 unsigned usr2 = imx_uart_readl(sport, USR2);
948
949 if (usr1 & USR1_RTSS)
950 tmp |= TIOCM_CTS;
951
952 /* in DCE mode DCDIN is always 0 */
953 if (!(usr2 & USR2_DCDIN))
954 tmp |= TIOCM_CAR;
955
956 if (sport->dte_mode)
957 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
958 tmp |= TIOCM_RI;
959
960 return tmp;
961 }
962
963 /*
964 * Handle any change of modem status signal since we were last called.
965 *
966 * Called with port.lock taken and irqs off.
967 */
imx_uart_mctrl_check(struct imx_port * sport)968 static void imx_uart_mctrl_check(struct imx_port *sport)
969 {
970 unsigned int status, changed;
971
972 status = imx_uart_get_hwmctrl(sport);
973 changed = status ^ sport->old_status;
974
975 if (changed == 0)
976 return;
977
978 sport->old_status = status;
979
980 if (changed & TIOCM_RI && status & TIOCM_RI)
981 sport->port.icount.rng++;
982 if (changed & TIOCM_DSR)
983 sport->port.icount.dsr++;
984 if (changed & TIOCM_CAR)
985 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
986 if (changed & TIOCM_CTS)
987 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
988
989 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
990 }
991
imx_uart_int(int irq,void * dev_id)992 static irqreturn_t imx_uart_int(int irq, void *dev_id)
993 {
994 struct imx_port *sport = dev_id;
995 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
996 irqreturn_t ret = IRQ_NONE;
997
998 uart_port_lock(&sport->port);
999
1000 usr1 = imx_uart_readl(sport, USR1);
1001 usr2 = imx_uart_readl(sport, USR2);
1002 ucr1 = imx_uart_readl(sport, UCR1);
1003 ucr2 = imx_uart_readl(sport, UCR2);
1004 ucr3 = imx_uart_readl(sport, UCR3);
1005 ucr4 = imx_uart_readl(sport, UCR4);
1006
1007 /*
1008 * Even if a condition is true that can trigger an irq only handle it if
1009 * the respective irq source is enabled. This prevents some undesired
1010 * actions, for example if a character that sits in the RX FIFO and that
1011 * should be fetched via DMA is tried to be fetched using PIO. Or the
1012 * receiver is currently off and so reading from URXD0 results in an
1013 * exception. So just mask the (raw) status bits for disabled irqs.
1014 */
1015 if ((ucr1 & UCR1_RRDYEN) == 0)
1016 usr1 &= ~USR1_RRDY;
1017 if ((ucr2 & UCR2_ATEN) == 0)
1018 usr1 &= ~USR1_AGTIM;
1019 if ((ucr1 & UCR1_TRDYEN) == 0)
1020 usr1 &= ~USR1_TRDY;
1021 if ((ucr4 & UCR4_TCEN) == 0)
1022 usr2 &= ~USR2_TXDC;
1023 if ((ucr3 & UCR3_DTRDEN) == 0)
1024 usr1 &= ~USR1_DTRD;
1025 if ((ucr1 & UCR1_RTSDEN) == 0)
1026 usr1 &= ~USR1_RTSD;
1027 if ((ucr3 & UCR3_AWAKEN) == 0)
1028 usr1 &= ~USR1_AWAKE;
1029 if ((ucr4 & UCR4_OREN) == 0)
1030 usr2 &= ~USR2_ORE;
1031
1032 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1033 imx_uart_writel(sport, USR1_AGTIM, USR1);
1034
1035 __imx_uart_rxint(irq, dev_id);
1036 ret = IRQ_HANDLED;
1037 }
1038
1039 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1040 imx_uart_transmit_buffer(sport);
1041 ret = IRQ_HANDLED;
1042 }
1043
1044 if (usr1 & USR1_DTRD) {
1045 imx_uart_writel(sport, USR1_DTRD, USR1);
1046
1047 imx_uart_mctrl_check(sport);
1048
1049 ret = IRQ_HANDLED;
1050 }
1051
1052 if (usr1 & USR1_RTSD) {
1053 __imx_uart_rtsint(irq, dev_id);
1054 ret = IRQ_HANDLED;
1055 }
1056
1057 if (usr1 & USR1_AWAKE) {
1058 imx_uart_writel(sport, USR1_AWAKE, USR1);
1059 ret = IRQ_HANDLED;
1060 }
1061
1062 if (usr2 & USR2_ORE) {
1063 sport->port.icount.overrun++;
1064 imx_uart_writel(sport, USR2_ORE, USR2);
1065 ret = IRQ_HANDLED;
1066 }
1067
1068 uart_port_unlock(&sport->port);
1069
1070 return ret;
1071 }
1072
1073 /*
1074 * Return TIOCSER_TEMT when transmitter is not busy.
1075 */
imx_uart_tx_empty(struct uart_port * port)1076 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1077 {
1078 struct imx_port *sport = to_imx_port(port);
1079 unsigned int ret;
1080
1081 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1082
1083 /* If the TX DMA is working, return 0. */
1084 if (sport->dma_is_txing)
1085 ret = 0;
1086
1087 return ret;
1088 }
1089
1090 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1091 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1092 {
1093 struct imx_port *sport = to_imx_port(port);
1094 unsigned int ret = imx_uart_get_hwmctrl(sport);
1095
1096 mctrl_gpio_get(sport->gpios, &ret);
1097
1098 return ret;
1099 }
1100
1101 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1102 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1103 {
1104 struct imx_port *sport = to_imx_port(port);
1105 u32 ucr3, uts;
1106
1107 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1108 u32 ucr2;
1109
1110 /*
1111 * Turn off autoRTS if RTS is lowered and restore autoRTS
1112 * setting if RTS is raised.
1113 */
1114 ucr2 = imx_uart_readl(sport, UCR2);
1115 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1116 if (mctrl & TIOCM_RTS) {
1117 ucr2 |= UCR2_CTS;
1118 /*
1119 * UCR2_IRTS is unset if and only if the port is
1120 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1121 * to get the state to restore to.
1122 */
1123 if (!(ucr2 & UCR2_IRTS))
1124 ucr2 |= UCR2_CTSC;
1125 }
1126 imx_uart_writel(sport, ucr2, UCR2);
1127 }
1128
1129 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1130 if (!(mctrl & TIOCM_DTR))
1131 ucr3 |= UCR3_DSR;
1132 imx_uart_writel(sport, ucr3, UCR3);
1133
1134 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1135 if (mctrl & TIOCM_LOOP)
1136 uts |= UTS_LOOP;
1137 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1138
1139 mctrl_gpio_set(sport->gpios, mctrl);
1140 }
1141
1142 /*
1143 * Interrupts always disabled.
1144 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1145 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1146 {
1147 struct imx_port *sport = to_imx_port(port);
1148 unsigned long flags;
1149 u32 ucr1;
1150
1151 uart_port_lock_irqsave(&sport->port, &flags);
1152
1153 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1154
1155 if (break_state != 0)
1156 ucr1 |= UCR1_SNDBRK;
1157
1158 imx_uart_writel(sport, ucr1, UCR1);
1159
1160 uart_port_unlock_irqrestore(&sport->port, flags);
1161 }
1162
1163 /*
1164 * This is our per-port timeout handler, for checking the
1165 * modem status signals.
1166 */
imx_uart_timeout(struct timer_list * t)1167 static void imx_uart_timeout(struct timer_list *t)
1168 {
1169 struct imx_port *sport = timer_container_of(sport, t, timer);
1170 unsigned long flags;
1171
1172 if (sport->port.state) {
1173 uart_port_lock_irqsave(&sport->port, &flags);
1174 imx_uart_mctrl_check(sport);
1175 uart_port_unlock_irqrestore(&sport->port, flags);
1176
1177 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1178 }
1179 }
1180
1181 /*
1182 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1183 * [1] the RX DMA buffer is full.
1184 * [2] the aging timer expires
1185 *
1186 * Condition [2] is triggered when a character has been sitting in the FIFO
1187 * for at least 8 byte durations.
1188 */
imx_uart_dma_rx_callback(void * data)1189 static void imx_uart_dma_rx_callback(void *data)
1190 {
1191 struct imx_port *sport = data;
1192 struct dma_chan *chan = sport->dma_chan_rx;
1193 struct scatterlist *sgl = &sport->rx_sgl;
1194 struct tty_port *port = &sport->port.state->port;
1195 struct dma_tx_state state;
1196 struct circ_buf *rx_ring = &sport->rx_ring;
1197 enum dma_status status;
1198 unsigned int w_bytes = 0;
1199 unsigned int r_bytes;
1200 unsigned int bd_size;
1201
1202 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1203
1204 if (status == DMA_ERROR) {
1205 uart_port_lock(&sport->port);
1206 imx_uart_clear_rx_errors(sport);
1207 uart_port_unlock(&sport->port);
1208 return;
1209 }
1210
1211 /*
1212 * The state-residue variable represents the empty space
1213 * relative to the entire buffer. Taking this in consideration
1214 * the head is always calculated base on the buffer total
1215 * length - DMA transaction residue. The UART script from the
1216 * SDMA firmware will jump to the next buffer descriptor,
1217 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1218 * Taking this in consideration the tail is always at the
1219 * beginning of the buffer descriptor that contains the head.
1220 */
1221
1222 /* Calculate the head */
1223 rx_ring->head = sg_dma_len(sgl) - state.residue;
1224
1225 /* Calculate the tail. */
1226 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1227 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1228
1229 if (rx_ring->head <= sg_dma_len(sgl) &&
1230 rx_ring->head > rx_ring->tail) {
1231
1232 /* Move data from tail to head */
1233 r_bytes = rx_ring->head - rx_ring->tail;
1234
1235 /* If we received something, check for 0xff flood */
1236 uart_port_lock(&sport->port);
1237 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1238 uart_port_unlock(&sport->port);
1239
1240 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1241
1242 /* CPU claims ownership of RX DMA buffer */
1243 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1244 DMA_FROM_DEVICE);
1245
1246 w_bytes = tty_insert_flip_string(port,
1247 sport->rx_buf + rx_ring->tail, r_bytes);
1248
1249 /* UART retrieves ownership of RX DMA buffer */
1250 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1251 DMA_FROM_DEVICE);
1252
1253 if (w_bytes != r_bytes)
1254 sport->port.icount.buf_overrun++;
1255
1256 sport->port.icount.rx += w_bytes;
1257 }
1258 } else {
1259 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1260 WARN_ON(rx_ring->head <= rx_ring->tail);
1261 }
1262
1263 if (w_bytes) {
1264 tty_flip_buffer_push(port);
1265 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1266 }
1267 }
1268
imx_uart_start_rx_dma(struct imx_port * sport)1269 static int imx_uart_start_rx_dma(struct imx_port *sport)
1270 {
1271 struct scatterlist *sgl = &sport->rx_sgl;
1272 struct dma_chan *chan = sport->dma_chan_rx;
1273 struct device *dev = sport->port.dev;
1274 struct dma_async_tx_descriptor *desc;
1275 int ret;
1276
1277 sport->rx_ring.head = 0;
1278 sport->rx_ring.tail = 0;
1279
1280 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1281 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1282 if (ret == 0) {
1283 dev_err(dev, "DMA mapping error for RX.\n");
1284 return -EINVAL;
1285 }
1286
1287 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1288 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1289 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1290
1291 if (!desc) {
1292 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1293 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1294 return -EINVAL;
1295 }
1296 desc->callback = imx_uart_dma_rx_callback;
1297 desc->callback_param = sport;
1298
1299 dev_dbg(dev, "RX: prepare for the DMA.\n");
1300 sport->dma_is_rxing = 1;
1301 sport->rx_cookie = dmaengine_submit(desc);
1302 dma_async_issue_pending(chan);
1303 return 0;
1304 }
1305
1306 /* called with port.lock taken and irqs off */
imx_uart_clear_rx_errors(struct imx_port * sport)1307 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1308 {
1309 struct tty_port *port = &sport->port.state->port;
1310 u32 usr1, usr2;
1311
1312 usr1 = imx_uart_readl(sport, USR1);
1313 usr2 = imx_uart_readl(sport, USR2);
1314
1315 if (usr2 & USR2_BRCD) {
1316 sport->port.icount.brk++;
1317 imx_uart_writel(sport, USR2_BRCD, USR2);
1318 uart_handle_break(&sport->port);
1319 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1320 sport->port.icount.buf_overrun++;
1321 tty_flip_buffer_push(port);
1322 } else {
1323 if (usr1 & USR1_FRAMERR) {
1324 sport->port.icount.frame++;
1325 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1326 } else if (usr1 & USR1_PARITYERR) {
1327 sport->port.icount.parity++;
1328 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1329 }
1330 }
1331
1332 if (usr2 & USR2_ORE) {
1333 sport->port.icount.overrun++;
1334 imx_uart_writel(sport, USR2_ORE, USR2);
1335 }
1336
1337 sport->idle_counter = 0;
1338
1339 }
1340
1341 #define TXTL_DEFAULT 8
1342 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1343 #define RXTL_CONSOLE_DEFAULT 1
1344 #define TXTL_DMA 8 /* DMA burst setting */
1345 #define RXTL_DMA 9 /* DMA burst setting */
1346
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1347 static void imx_uart_setup_ufcr(struct imx_port *sport,
1348 unsigned char txwl, unsigned char rxwl)
1349 {
1350 unsigned int val;
1351
1352 /* set receiver / transmitter trigger level */
1353 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1354 val |= txwl << UFCR_TXTL_SHF | rxwl;
1355 imx_uart_writel(sport, val, UFCR);
1356 }
1357
imx_uart_dma_exit(struct imx_port * sport)1358 static void imx_uart_dma_exit(struct imx_port *sport)
1359 {
1360 if (sport->dma_chan_rx) {
1361 dmaengine_terminate_sync(sport->dma_chan_rx);
1362 dma_release_channel(sport->dma_chan_rx);
1363 sport->dma_chan_rx = NULL;
1364 sport->rx_cookie = -EINVAL;
1365 kfree(sport->rx_buf);
1366 sport->rx_buf = NULL;
1367 }
1368
1369 if (sport->dma_chan_tx) {
1370 dmaengine_terminate_sync(sport->dma_chan_tx);
1371 dma_release_channel(sport->dma_chan_tx);
1372 sport->dma_chan_tx = NULL;
1373 }
1374 }
1375
imx_uart_dma_init(struct imx_port * sport)1376 static int imx_uart_dma_init(struct imx_port *sport)
1377 {
1378 struct dma_slave_config slave_config = {};
1379 struct device *dev = sport->port.dev;
1380 struct dma_chan *chan;
1381 int ret;
1382
1383 /* Prepare for RX : */
1384 chan = dma_request_chan(dev, "rx");
1385 if (IS_ERR(chan)) {
1386 dev_dbg(dev, "cannot get the DMA channel.\n");
1387 sport->dma_chan_rx = NULL;
1388 ret = PTR_ERR(chan);
1389 goto err;
1390 }
1391 sport->dma_chan_rx = chan;
1392
1393 slave_config.direction = DMA_DEV_TO_MEM;
1394 slave_config.src_addr = sport->port.mapbase + URXD0;
1395 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1396 /* one byte less than the watermark level to enable the aging timer */
1397 slave_config.src_maxburst = RXTL_DMA - 1;
1398 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1399 if (ret) {
1400 dev_err(dev, "error in RX dma configuration.\n");
1401 goto err;
1402 }
1403
1404 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1405 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1406 if (!sport->rx_buf) {
1407 ret = -ENOMEM;
1408 goto err;
1409 }
1410 sport->rx_ring.buf = sport->rx_buf;
1411
1412 /* Prepare for TX : */
1413 chan = dma_request_chan(dev, "tx");
1414 if (IS_ERR(chan)) {
1415 dev_err(dev, "cannot get the TX DMA channel!\n");
1416 sport->dma_chan_tx = NULL;
1417 ret = PTR_ERR(chan);
1418 goto err;
1419 }
1420 sport->dma_chan_tx = chan;
1421
1422 slave_config.direction = DMA_MEM_TO_DEV;
1423 slave_config.dst_addr = sport->port.mapbase + URTX0;
1424 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1425 slave_config.dst_maxburst = TXTL_DMA;
1426 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1427 if (ret) {
1428 dev_err(dev, "error in TX dma configuration.");
1429 goto err;
1430 }
1431
1432 return 0;
1433 err:
1434 imx_uart_dma_exit(sport);
1435 return ret;
1436 }
1437
1438 /* called with port.lock taken and irqs off */
imx_uart_enable_dma(struct imx_port * sport)1439 static void imx_uart_enable_dma(struct imx_port *sport)
1440 {
1441 u32 ucr1;
1442
1443 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1444
1445 /* set UCR1 */
1446 ucr1 = imx_uart_readl(sport, UCR1);
1447 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1448 imx_uart_writel(sport, ucr1, UCR1);
1449
1450 sport->dma_is_enabled = 1;
1451 }
1452
imx_uart_disable_dma(struct imx_port * sport)1453 static void imx_uart_disable_dma(struct imx_port *sport)
1454 {
1455 u32 ucr1;
1456
1457 /* clear UCR1 */
1458 ucr1 = imx_uart_readl(sport, UCR1);
1459 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1460 imx_uart_writel(sport, ucr1, UCR1);
1461
1462 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1463
1464 sport->dma_is_enabled = 0;
1465 }
1466
1467 /* half the RX buffer size */
1468 #define CTSTL 16
1469
imx_uart_startup(struct uart_port * port)1470 static int imx_uart_startup(struct uart_port *port)
1471 {
1472 struct imx_port *sport = to_imx_port(port);
1473 int retval;
1474 unsigned long flags;
1475 int dma_is_inited = 0;
1476 u32 ucr1, ucr2, ucr3, ucr4;
1477
1478 retval = clk_prepare_enable(sport->clk_per);
1479 if (retval)
1480 return retval;
1481 retval = clk_prepare_enable(sport->clk_ipg);
1482 if (retval) {
1483 clk_disable_unprepare(sport->clk_per);
1484 return retval;
1485 }
1486
1487 if (uart_console(&sport->port))
1488 sport->rxtl = RXTL_CONSOLE_DEFAULT;
1489 else
1490 sport->rxtl = RXTL_DEFAULT;
1491
1492 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1493
1494 /* disable the DREN bit (Data Ready interrupt enable) before
1495 * requesting IRQs
1496 */
1497 ucr4 = imx_uart_readl(sport, UCR4);
1498
1499 /* set the trigger level for CTS */
1500 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1501 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1502
1503 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1504
1505 /* Can we enable the DMA support? */
1506 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) {
1507 lockdep_set_subclass(&port->lock, 1);
1508 dma_is_inited = 1;
1509 }
1510
1511 uart_port_lock_irqsave(&sport->port, &flags);
1512
1513 /* Reset fifo's and state machines */
1514 imx_uart_soft_reset(sport);
1515
1516 /*
1517 * Finally, clear and enable interrupts
1518 */
1519 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1520 imx_uart_writel(sport, USR2_ORE, USR2);
1521
1522 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1523 ucr1 |= UCR1_UARTEN;
1524 if (sport->have_rtscts)
1525 ucr1 |= UCR1_RTSDEN;
1526
1527 imx_uart_writel(sport, ucr1, UCR1);
1528
1529 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1530 if (!dma_is_inited)
1531 ucr4 |= UCR4_OREN;
1532 if (sport->inverted_rx)
1533 ucr4 |= UCR4_INVR;
1534 imx_uart_writel(sport, ucr4, UCR4);
1535
1536 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1537 /*
1538 * configure tx polarity before enabling tx
1539 */
1540 if (sport->inverted_tx)
1541 ucr3 |= UCR3_INVT;
1542
1543 if (!imx_uart_is_imx1(sport)) {
1544 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1545
1546 if (sport->dte_mode)
1547 /* disable broken interrupts */
1548 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1549 }
1550 imx_uart_writel(sport, ucr3, UCR3);
1551
1552 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1553 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1554 if (!sport->have_rtscts)
1555 ucr2 |= UCR2_IRTS;
1556 /*
1557 * make sure the edge sensitive RTS-irq is disabled,
1558 * we're using RTSD instead.
1559 */
1560 if (!imx_uart_is_imx1(sport))
1561 ucr2 &= ~UCR2_RTSEN;
1562 imx_uart_writel(sport, ucr2, UCR2);
1563
1564 /*
1565 * Enable modem status interrupts
1566 */
1567 imx_uart_enable_ms(&sport->port);
1568
1569 if (dma_is_inited) {
1570 imx_uart_enable_dma(sport);
1571 imx_uart_start_rx_dma(sport);
1572 } else {
1573 ucr1 = imx_uart_readl(sport, UCR1);
1574 ucr1 |= UCR1_RRDYEN;
1575 imx_uart_writel(sport, ucr1, UCR1);
1576
1577 ucr2 = imx_uart_readl(sport, UCR2);
1578 ucr2 |= UCR2_ATEN;
1579 imx_uart_writel(sport, ucr2, UCR2);
1580 }
1581
1582 imx_uart_disable_loopback_rs485(sport);
1583
1584 uart_port_unlock_irqrestore(&sport->port, flags);
1585
1586 return 0;
1587 }
1588
imx_uart_shutdown(struct uart_port * port)1589 static void imx_uart_shutdown(struct uart_port *port)
1590 {
1591 struct imx_port *sport = to_imx_port(port);
1592 unsigned long flags;
1593 u32 ucr1, ucr2, ucr4, uts;
1594 int loops;
1595
1596 if (sport->dma_is_enabled) {
1597 dmaengine_terminate_sync(sport->dma_chan_tx);
1598 if (sport->dma_is_txing) {
1599 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1600 sport->dma_tx_nents, DMA_TO_DEVICE);
1601 sport->dma_is_txing = 0;
1602 }
1603 dmaengine_terminate_sync(sport->dma_chan_rx);
1604 if (sport->dma_is_rxing) {
1605 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1606 1, DMA_FROM_DEVICE);
1607 sport->dma_is_rxing = 0;
1608 }
1609
1610 uart_port_lock_irqsave(&sport->port, &flags);
1611 imx_uart_stop_tx(port);
1612 imx_uart_stop_rx(port);
1613 imx_uart_disable_dma(sport);
1614 uart_port_unlock_irqrestore(&sport->port, flags);
1615 imx_uart_dma_exit(sport);
1616 }
1617
1618 mctrl_gpio_disable_ms_sync(sport->gpios);
1619
1620 uart_port_lock_irqsave(&sport->port, &flags);
1621 ucr2 = imx_uart_readl(sport, UCR2);
1622 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1623 imx_uart_writel(sport, ucr2, UCR2);
1624 uart_port_unlock_irqrestore(&sport->port, flags);
1625
1626 /*
1627 * Stop our timer.
1628 */
1629 timer_delete_sync(&sport->timer);
1630
1631 /*
1632 * Disable all interrupts, port and break condition.
1633 */
1634
1635 uart_port_lock_irqsave(&sport->port, &flags);
1636
1637 ucr1 = imx_uart_readl(sport, UCR1);
1638 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1639 UCR1_ATDMAEN | UCR1_SNDBRK);
1640 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1641 if (port->rs485.flags & SER_RS485_ENABLED &&
1642 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1643 sport->have_rtscts && !sport->have_rtsgpio) {
1644 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1645 uts |= UTS_LOOP;
1646 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1647 ucr1 |= UCR1_UARTEN;
1648 } else {
1649 ucr1 &= ~UCR1_UARTEN;
1650 }
1651 imx_uart_writel(sport, ucr1, UCR1);
1652
1653 ucr4 = imx_uart_readl(sport, UCR4);
1654 ucr4 &= ~UCR4_TCEN;
1655 imx_uart_writel(sport, ucr4, UCR4);
1656
1657 /*
1658 * We have to ensure the tx state machine ends up in OFF. This
1659 * is especially important for rs485 where we must not leave
1660 * the RTS signal high, blocking the bus indefinitely.
1661 *
1662 * All interrupts are now disabled, so imx_uart_stop_tx() will
1663 * no longer be called from imx_uart_transmit_buffer(). It may
1664 * still be called via the hrtimers, and if those are in play,
1665 * we have to honour the delays.
1666 */
1667 if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND)
1668 imx_uart_stop_tx(port);
1669
1670 /*
1671 * In many cases (rs232 mode, or if tx_state was
1672 * WAIT_AFTER_RTS, or if tx_state was SEND and there is no
1673 * delay_rts_after_send), this will have moved directly to
1674 * OFF. In rs485 mode, tx_state might already have been
1675 * WAIT_AFTER_SEND and the hrtimer thus already started, or
1676 * the above imx_uart_stop_tx() call could have started it. In
1677 * those cases, we have to wait for the hrtimer to fire and
1678 * complete the transition to OFF.
1679 */
1680 loops = port->rs485.flags & SER_RS485_ENABLED ?
1681 port->rs485.delay_rts_after_send : 0;
1682 while (sport->tx_state != OFF && loops--) {
1683 uart_port_unlock_irqrestore(&sport->port, flags);
1684 msleep(1);
1685 uart_port_lock_irqsave(&sport->port, &flags);
1686 }
1687
1688 if (sport->tx_state != OFF) {
1689 dev_warn(sport->port.dev, "unexpected tx_state %d\n",
1690 sport->tx_state);
1691 /*
1692 * This machine may be busted, but ensure the RTS
1693 * signal is inactive in order not to block other
1694 * devices.
1695 */
1696 if (port->rs485.flags & SER_RS485_ENABLED) {
1697 ucr2 = imx_uart_readl(sport, UCR2);
1698 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1699 imx_uart_rts_active(sport, &ucr2);
1700 else
1701 imx_uart_rts_inactive(sport, &ucr2);
1702 imx_uart_writel(sport, ucr2, UCR2);
1703 }
1704 sport->tx_state = OFF;
1705 }
1706
1707 uart_port_unlock_irqrestore(&sport->port, flags);
1708
1709 clk_disable_unprepare(sport->clk_per);
1710 clk_disable_unprepare(sport->clk_ipg);
1711 }
1712
1713 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1714 static void imx_uart_flush_buffer(struct uart_port *port)
1715 {
1716 struct imx_port *sport = to_imx_port(port);
1717 struct scatterlist *sgl = &sport->tx_sgl[0];
1718
1719 if (!sport->dma_chan_tx)
1720 return;
1721
1722 sport->tx_bytes = 0;
1723 dmaengine_terminate_all(sport->dma_chan_tx);
1724 if (sport->dma_is_txing) {
1725 u32 ucr1;
1726
1727 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1728 DMA_TO_DEVICE);
1729 ucr1 = imx_uart_readl(sport, UCR1);
1730 ucr1 &= ~UCR1_TXDMAEN;
1731 imx_uart_writel(sport, ucr1, UCR1);
1732 sport->dma_is_txing = 0;
1733 }
1734
1735 imx_uart_soft_reset(sport);
1736
1737 }
1738
1739 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1740 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1741 const struct ktermios *old)
1742 {
1743 struct imx_port *sport = to_imx_port(port);
1744 unsigned long flags;
1745 u32 ucr2, old_ucr2, ufcr;
1746 unsigned int baud, quot;
1747 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1748 unsigned long div;
1749 unsigned long num, denom, old_ubir, old_ubmr;
1750 uint64_t tdiv64;
1751
1752 /*
1753 * We only support CS7 and CS8.
1754 */
1755 while ((termios->c_cflag & CSIZE) != CS7 &&
1756 (termios->c_cflag & CSIZE) != CS8) {
1757 termios->c_cflag &= ~CSIZE;
1758 termios->c_cflag |= old_csize;
1759 old_csize = CS8;
1760 }
1761
1762 timer_delete_sync(&sport->timer);
1763
1764 /*
1765 * Ask the core to calculate the divisor for us.
1766 */
1767 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1768 quot = uart_get_divisor(port, baud);
1769
1770 uart_port_lock_irqsave(&sport->port, &flags);
1771
1772 /*
1773 * Read current UCR2 and save it for future use, then clear all the bits
1774 * except those we will or may need to preserve.
1775 */
1776 old_ucr2 = imx_uart_readl(sport, UCR2);
1777 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1778
1779 ucr2 |= UCR2_SRST | UCR2_IRTS;
1780 if ((termios->c_cflag & CSIZE) == CS8)
1781 ucr2 |= UCR2_WS;
1782
1783 if (!sport->have_rtscts)
1784 termios->c_cflag &= ~CRTSCTS;
1785
1786 if (port->rs485.flags & SER_RS485_ENABLED) {
1787 /*
1788 * RTS is mandatory for rs485 operation, so keep
1789 * it under manual control and keep transmitter
1790 * disabled.
1791 */
1792 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1793 imx_uart_rts_active(sport, &ucr2);
1794 else
1795 imx_uart_rts_inactive(sport, &ucr2);
1796
1797 } else if (termios->c_cflag & CRTSCTS) {
1798 /*
1799 * Only let receiver control RTS output if we were not requested
1800 * to have RTS inactive (which then should take precedence).
1801 */
1802 if (ucr2 & UCR2_CTS)
1803 ucr2 |= UCR2_CTSC;
1804 }
1805
1806 if (termios->c_cflag & CRTSCTS)
1807 ucr2 &= ~UCR2_IRTS;
1808 if (termios->c_cflag & CSTOPB)
1809 ucr2 |= UCR2_STPB;
1810 if (termios->c_cflag & PARENB) {
1811 ucr2 |= UCR2_PREN;
1812 if (termios->c_cflag & PARODD)
1813 ucr2 |= UCR2_PROE;
1814 }
1815
1816 sport->port.read_status_mask = 0;
1817 if (termios->c_iflag & INPCK)
1818 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1819 if (termios->c_iflag & (BRKINT | PARMRK))
1820 sport->port.read_status_mask |= URXD_BRK;
1821
1822 /*
1823 * Characters to ignore
1824 */
1825 sport->port.ignore_status_mask = 0;
1826 if (termios->c_iflag & IGNPAR)
1827 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1828 if (termios->c_iflag & IGNBRK) {
1829 sport->port.ignore_status_mask |= URXD_BRK;
1830 /*
1831 * If we're ignoring parity and break indicators,
1832 * ignore overruns too (for real raw support).
1833 */
1834 if (termios->c_iflag & IGNPAR)
1835 sport->port.ignore_status_mask |= URXD_OVRRUN;
1836 }
1837
1838 if ((termios->c_cflag & CREAD) == 0)
1839 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1840
1841 /*
1842 * Update the per-port timeout.
1843 */
1844 uart_update_timeout(port, termios->c_cflag, baud);
1845
1846 /* custom-baudrate handling */
1847 div = sport->port.uartclk / (baud * 16);
1848 if (baud == 38400 && quot != div)
1849 baud = sport->port.uartclk / (quot * 16);
1850
1851 div = sport->port.uartclk / (baud * 16);
1852 if (div > 7)
1853 div = 7;
1854 if (!div)
1855 div = 1;
1856
1857 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1858 1 << 16, 1 << 16, &num, &denom);
1859
1860 tdiv64 = sport->port.uartclk;
1861 tdiv64 *= num;
1862 do_div(tdiv64, denom * 16 * div);
1863 tty_termios_encode_baud_rate(termios,
1864 (speed_t)tdiv64, (speed_t)tdiv64);
1865
1866 num -= 1;
1867 denom -= 1;
1868
1869 ufcr = imx_uart_readl(sport, UFCR);
1870 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1871 imx_uart_writel(sport, ufcr, UFCR);
1872
1873 /*
1874 * Two registers below should always be written both and in this
1875 * particular order. One consequence is that we need to check if any of
1876 * them changes and then update both. We do need the check for change
1877 * as even writing the same values seem to "restart"
1878 * transmission/receiving logic in the hardware, that leads to data
1879 * breakage even when rate doesn't in fact change. E.g., user switches
1880 * RTS/CTS handshake and suddenly gets broken bytes.
1881 */
1882 old_ubir = imx_uart_readl(sport, UBIR);
1883 old_ubmr = imx_uart_readl(sport, UBMR);
1884 if (old_ubir != num || old_ubmr != denom) {
1885 imx_uart_writel(sport, num, UBIR);
1886 imx_uart_writel(sport, denom, UBMR);
1887 }
1888
1889 if (!imx_uart_is_imx1(sport))
1890 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1891 IMX21_ONEMS);
1892
1893 imx_uart_writel(sport, ucr2, UCR2);
1894
1895 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1896 imx_uart_enable_ms(&sport->port);
1897
1898 uart_port_unlock_irqrestore(&sport->port, flags);
1899 }
1900
imx_uart_type(struct uart_port * port)1901 static const char *imx_uart_type(struct uart_port *port)
1902 {
1903 return port->type == PORT_IMX ? "IMX" : NULL;
1904 }
1905
1906 /*
1907 * Configure/autoconfigure the port.
1908 */
imx_uart_config_port(struct uart_port * port,int flags)1909 static void imx_uart_config_port(struct uart_port *port, int flags)
1910 {
1911 if (flags & UART_CONFIG_TYPE)
1912 port->type = PORT_IMX;
1913 }
1914
1915 /*
1916 * Verify the new serial_struct (for TIOCSSERIAL).
1917 * The only change we allow are to the flags and type, and
1918 * even then only between PORT_IMX and PORT_UNKNOWN
1919 */
1920 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1921 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1922 {
1923 int ret = 0;
1924
1925 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1926 ret = -EINVAL;
1927 if (port->irq != ser->irq)
1928 ret = -EINVAL;
1929 if (ser->io_type != UPIO_MEM)
1930 ret = -EINVAL;
1931 if (port->uartclk / 16 != ser->baud_base)
1932 ret = -EINVAL;
1933 if (port->mapbase != (unsigned long)ser->iomem_base)
1934 ret = -EINVAL;
1935 if (port->iobase != ser->port)
1936 ret = -EINVAL;
1937 if (ser->hub6 != 0)
1938 ret = -EINVAL;
1939 return ret;
1940 }
1941
1942 #if defined(CONFIG_CONSOLE_POLL)
1943
imx_uart_poll_init(struct uart_port * port)1944 static int imx_uart_poll_init(struct uart_port *port)
1945 {
1946 struct imx_port *sport = to_imx_port(port);
1947 unsigned long flags;
1948 u32 ucr1, ucr2;
1949 int retval;
1950
1951 retval = clk_prepare_enable(sport->clk_ipg);
1952 if (retval)
1953 return retval;
1954 retval = clk_prepare_enable(sport->clk_per);
1955 if (retval)
1956 clk_disable_unprepare(sport->clk_ipg);
1957
1958 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1959
1960 uart_port_lock_irqsave(&sport->port, &flags);
1961
1962 /*
1963 * Be careful about the order of enabling bits here. First enable the
1964 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1965 * This prevents that a character that already sits in the RX fifo is
1966 * triggering an irq but the try to fetch it from there results in an
1967 * exception because UARTEN or RXEN is still off.
1968 */
1969 ucr1 = imx_uart_readl(sport, UCR1);
1970 ucr2 = imx_uart_readl(sport, UCR2);
1971
1972 if (imx_uart_is_imx1(sport))
1973 ucr1 |= IMX1_UCR1_UARTCLKEN;
1974
1975 ucr1 |= UCR1_UARTEN;
1976 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1977
1978 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1979 ucr2 &= ~UCR2_ATEN;
1980
1981 imx_uart_writel(sport, ucr1, UCR1);
1982 imx_uart_writel(sport, ucr2, UCR2);
1983
1984 /* now enable irqs */
1985 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1986 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1987
1988 uart_port_unlock_irqrestore(&sport->port, flags);
1989
1990 return 0;
1991 }
1992
imx_uart_poll_get_char(struct uart_port * port)1993 static int imx_uart_poll_get_char(struct uart_port *port)
1994 {
1995 struct imx_port *sport = to_imx_port(port);
1996 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1997 return NO_POLL_CHAR;
1998
1999 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
2000 }
2001
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)2002 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
2003 {
2004 struct imx_port *sport = to_imx_port(port);
2005 unsigned int status;
2006
2007 /* drain */
2008 do {
2009 status = imx_uart_readl(sport, USR1);
2010 } while (~status & USR1_TRDY);
2011
2012 /* write */
2013 imx_uart_writel(sport, c, URTX0);
2014
2015 /* flush */
2016 do {
2017 status = imx_uart_readl(sport, USR2);
2018 } while (~status & USR2_TXDC);
2019 }
2020 #endif
2021
2022 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485conf)2023 static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
2024 struct serial_rs485 *rs485conf)
2025 {
2026 struct imx_port *sport = to_imx_port(port);
2027 u32 ucr2, ufcr;
2028
2029 if (rs485conf->flags & SER_RS485_ENABLED) {
2030 /* Enable receiver if low-active RTS signal is requested */
2031 if (sport->have_rtscts && !sport->have_rtsgpio &&
2032 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
2033 rs485conf->flags |= SER_RS485_RX_DURING_TX;
2034
2035 /* disable transmitter */
2036 ucr2 = imx_uart_readl(sport, UCR2);
2037 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
2038 imx_uart_rts_active(sport, &ucr2);
2039 else
2040 imx_uart_rts_inactive(sport, &ucr2);
2041 imx_uart_writel(sport, ucr2, UCR2);
2042 }
2043
2044 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
2045 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
2046 rs485conf->flags & SER_RS485_RX_DURING_TX) {
2047 /* If the receiver trigger is 0, set it to a default value */
2048 ufcr = imx_uart_readl(sport, UFCR);
2049 if ((ufcr & UFCR_RXTL_MASK) == 0)
2050 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
2051 imx_uart_start_rx(port);
2052 }
2053
2054 return 0;
2055 }
2056
2057 static const struct uart_ops imx_uart_pops = {
2058 .tx_empty = imx_uart_tx_empty,
2059 .set_mctrl = imx_uart_set_mctrl,
2060 .get_mctrl = imx_uart_get_mctrl,
2061 .stop_tx = imx_uart_stop_tx,
2062 .start_tx = imx_uart_start_tx,
2063 .stop_rx = imx_uart_stop_rx,
2064 .enable_ms = imx_uart_enable_ms,
2065 .break_ctl = imx_uart_break_ctl,
2066 .startup = imx_uart_startup,
2067 .shutdown = imx_uart_shutdown,
2068 .flush_buffer = imx_uart_flush_buffer,
2069 .set_termios = imx_uart_set_termios,
2070 .type = imx_uart_type,
2071 .config_port = imx_uart_config_port,
2072 .verify_port = imx_uart_verify_port,
2073 #if defined(CONFIG_CONSOLE_POLL)
2074 .poll_init = imx_uart_poll_init,
2075 .poll_get_char = imx_uart_poll_get_char,
2076 .poll_put_char = imx_uart_poll_put_char,
2077 #endif
2078 };
2079
2080 static struct imx_port *imx_uart_ports[UART_NR];
2081
2082 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,unsigned char ch)2083 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
2084 {
2085 struct imx_port *sport = to_imx_port(port);
2086
2087 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
2088 barrier();
2089
2090 imx_uart_writel(sport, ch, URTX0);
2091
2092 sport->last_putchar_was_newline = (ch == '\n');
2093 }
2094
imx_uart_console_device_lock(struct console * co,unsigned long * flags)2095 static void imx_uart_console_device_lock(struct console *co, unsigned long *flags)
2096 {
2097 struct uart_port *up = &imx_uart_ports[co->index]->port;
2098
2099 return __uart_port_lock_irqsave(up, flags);
2100 }
2101
imx_uart_console_device_unlock(struct console * co,unsigned long flags)2102 static void imx_uart_console_device_unlock(struct console *co, unsigned long flags)
2103 {
2104 struct uart_port *up = &imx_uart_ports[co->index]->port;
2105
2106 return __uart_port_unlock_irqrestore(up, flags);
2107 }
2108
imx_uart_console_write_atomic(struct console * co,struct nbcon_write_context * wctxt)2109 static void imx_uart_console_write_atomic(struct console *co,
2110 struct nbcon_write_context *wctxt)
2111 {
2112 struct imx_port *sport = imx_uart_ports[co->index];
2113 struct uart_port *port = &sport->port;
2114 struct imx_port_ucrs old_ucr;
2115 unsigned int ucr1, usr2;
2116
2117 if (!nbcon_enter_unsafe(wctxt))
2118 return;
2119
2120 /*
2121 * First, save UCR1/2/3 and then disable interrupts
2122 */
2123 imx_uart_ucrs_save(sport, &old_ucr);
2124 ucr1 = old_ucr.ucr1;
2125
2126 if (imx_uart_is_imx1(sport))
2127 ucr1 |= IMX1_UCR1_UARTCLKEN;
2128 ucr1 |= UCR1_UARTEN;
2129 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2130
2131 imx_uart_writel(sport, ucr1, UCR1);
2132 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2133
2134 if (!sport->last_putchar_was_newline)
2135 uart_console_write(port, "\n", 1, imx_uart_console_putchar);
2136 uart_console_write(port, wctxt->outbuf, wctxt->len,
2137 imx_uart_console_putchar);
2138
2139 /*
2140 * Finally, wait for transmitter to become empty
2141 * and restore UCR1/2/3
2142 */
2143 read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2144 0, USEC_PER_SEC, false, sport, USR2);
2145 imx_uart_ucrs_restore(sport, &old_ucr);
2146
2147 nbcon_exit_unsafe(wctxt);
2148 }
2149
imx_uart_console_write_thread(struct console * co,struct nbcon_write_context * wctxt)2150 static void imx_uart_console_write_thread(struct console *co,
2151 struct nbcon_write_context *wctxt)
2152 {
2153 struct imx_port *sport = imx_uart_ports[co->index];
2154 struct uart_port *port = &sport->port;
2155 struct imx_port_ucrs old_ucr;
2156 unsigned int ucr1, usr2;
2157
2158 if (!nbcon_enter_unsafe(wctxt))
2159 return;
2160
2161 /*
2162 * First, save UCR1/2/3 and then disable interrupts
2163 */
2164 imx_uart_ucrs_save(sport, &old_ucr);
2165 ucr1 = old_ucr.ucr1;
2166
2167 if (imx_uart_is_imx1(sport))
2168 ucr1 |= IMX1_UCR1_UARTCLKEN;
2169 ucr1 |= UCR1_UARTEN;
2170 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2171
2172 imx_uart_writel(sport, ucr1, UCR1);
2173 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2174
2175 if (nbcon_exit_unsafe(wctxt)) {
2176 int len = READ_ONCE(wctxt->len);
2177 int i;
2178
2179 /*
2180 * Write out the message. Toggle unsafe for each byte in order
2181 * to give another (higher priority) context the opportunity
2182 * for a friendly takeover. If such a takeover occurs, this
2183 * context must reacquire ownership in order to perform final
2184 * actions (such as re-enabling the interrupts).
2185 *
2186 * IMPORTANT: wctxt->outbuf and wctxt->len are no longer valid
2187 * after a reacquire so writing the message must be
2188 * aborted.
2189 */
2190 for (i = 0; i < len; i++) {
2191 if (!nbcon_enter_unsafe(wctxt))
2192 break;
2193
2194 uart_console_write(port, wctxt->outbuf + i, 1,
2195 imx_uart_console_putchar);
2196
2197 if (!nbcon_exit_unsafe(wctxt))
2198 break;
2199 }
2200 }
2201
2202 while (!nbcon_enter_unsafe(wctxt))
2203 nbcon_reacquire_nobuf(wctxt);
2204
2205 /*
2206 * Finally, wait for transmitter to become empty
2207 * and restore UCR1/2/3
2208 */
2209 read_poll_timeout(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2210 0, USEC_PER_SEC, false, sport, USR2);
2211 imx_uart_ucrs_restore(sport, &old_ucr);
2212
2213 nbcon_exit_unsafe(wctxt);
2214 }
2215
2216 /*
2217 * If the port was already initialised (eg, by a boot loader),
2218 * try to determine the current setup.
2219 */
2220 static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2221 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2222 int *parity, int *bits)
2223 {
2224
2225 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2226 /* ok, the port was enabled */
2227 unsigned int ucr2, ubir, ubmr, uartclk;
2228 unsigned int baud_raw;
2229 unsigned int ucfr_rfdiv;
2230
2231 ucr2 = imx_uart_readl(sport, UCR2);
2232
2233 *parity = 'n';
2234 if (ucr2 & UCR2_PREN) {
2235 if (ucr2 & UCR2_PROE)
2236 *parity = 'o';
2237 else
2238 *parity = 'e';
2239 }
2240
2241 if (ucr2 & UCR2_WS)
2242 *bits = 8;
2243 else
2244 *bits = 7;
2245
2246 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2247 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2248
2249 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2250 if (ucfr_rfdiv == 6)
2251 ucfr_rfdiv = 7;
2252 else
2253 ucfr_rfdiv = 6 - ucfr_rfdiv;
2254
2255 uartclk = clk_get_rate(sport->clk_per);
2256 uartclk /= ucfr_rfdiv;
2257
2258 { /*
2259 * The next code provides exact computation of
2260 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2261 * without need of float support or long long division,
2262 * which would be required to prevent 32bit arithmetic overflow
2263 */
2264 unsigned int mul = ubir + 1;
2265 unsigned int div = 16 * (ubmr + 1);
2266 unsigned int rem = uartclk % div;
2267
2268 baud_raw = (uartclk / div) * mul;
2269 baud_raw += (rem * mul + div / 2) / div;
2270 *baud = (baud_raw + 50) / 100 * 100;
2271 }
2272
2273 if (*baud != baud_raw)
2274 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2275 baud_raw, *baud);
2276 }
2277 }
2278
2279 static int
imx_uart_console_setup(struct console * co,char * options)2280 imx_uart_console_setup(struct console *co, char *options)
2281 {
2282 struct imx_port *sport;
2283 int baud = 9600;
2284 int bits = 8;
2285 int parity = 'n';
2286 int flow = 'n';
2287 int retval;
2288
2289 /*
2290 * Check whether an invalid uart number has been specified, and
2291 * if so, search for the first available port that does have
2292 * console support.
2293 */
2294 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2295 co->index = 0;
2296 sport = imx_uart_ports[co->index];
2297 if (sport == NULL)
2298 return -ENODEV;
2299
2300 /* For setting the registers, we only need to enable the ipg clock. */
2301 retval = clk_prepare_enable(sport->clk_ipg);
2302 if (retval)
2303 goto error_console;
2304
2305 sport->last_putchar_was_newline = true;
2306
2307 if (options)
2308 uart_parse_options(options, &baud, &parity, &bits, &flow);
2309 else
2310 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2311
2312 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
2313
2314 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2315
2316 if (retval) {
2317 clk_disable_unprepare(sport->clk_ipg);
2318 goto error_console;
2319 }
2320
2321 retval = clk_prepare_enable(sport->clk_per);
2322 if (retval)
2323 clk_disable_unprepare(sport->clk_ipg);
2324
2325 error_console:
2326 return retval;
2327 }
2328
2329 static int
imx_uart_console_exit(struct console * co)2330 imx_uart_console_exit(struct console *co)
2331 {
2332 struct imx_port *sport = imx_uart_ports[co->index];
2333
2334 clk_disable_unprepare(sport->clk_per);
2335 clk_disable_unprepare(sport->clk_ipg);
2336
2337 return 0;
2338 }
2339
2340 static struct uart_driver imx_uart_uart_driver;
2341 static struct console imx_uart_console = {
2342 .name = DEV_NAME,
2343 .write_atomic = imx_uart_console_write_atomic,
2344 .write_thread = imx_uart_console_write_thread,
2345 .device_lock = imx_uart_console_device_lock,
2346 .device_unlock = imx_uart_console_device_unlock,
2347 .flags = CON_PRINTBUFFER | CON_NBCON,
2348 .device = uart_console_device,
2349 .setup = imx_uart_console_setup,
2350 .exit = imx_uart_console_exit,
2351 .index = -1,
2352 .data = &imx_uart_uart_driver,
2353 };
2354
2355 #define IMX_CONSOLE &imx_uart_console
2356
2357 #else
2358 #define IMX_CONSOLE NULL
2359 #endif
2360
2361 static struct uart_driver imx_uart_uart_driver = {
2362 .owner = THIS_MODULE,
2363 .driver_name = DRIVER_NAME,
2364 .dev_name = DEV_NAME,
2365 .major = SERIAL_IMX_MAJOR,
2366 .minor = MINOR_START,
2367 .nr = ARRAY_SIZE(imx_uart_ports),
2368 .cons = IMX_CONSOLE,
2369 };
2370
imx_trigger_start_tx(struct hrtimer * t)2371 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2372 {
2373 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2374 unsigned long flags;
2375
2376 uart_port_lock_irqsave(&sport->port, &flags);
2377 if (sport->tx_state == WAIT_AFTER_RTS)
2378 imx_uart_start_tx(&sport->port);
2379 uart_port_unlock_irqrestore(&sport->port, flags);
2380
2381 return HRTIMER_NORESTART;
2382 }
2383
imx_trigger_stop_tx(struct hrtimer * t)2384 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2385 {
2386 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2387 unsigned long flags;
2388
2389 uart_port_lock_irqsave(&sport->port, &flags);
2390 if (sport->tx_state == WAIT_AFTER_SEND)
2391 imx_uart_stop_tx(&sport->port);
2392 uart_port_unlock_irqrestore(&sport->port, flags);
2393
2394 return HRTIMER_NORESTART;
2395 }
2396
2397 static const struct serial_rs485 imx_rs485_supported = {
2398 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2399 SER_RS485_RX_DURING_TX,
2400 .delay_rts_before_send = 1,
2401 .delay_rts_after_send = 1,
2402 };
2403
2404 /* Default RX DMA buffer configuration */
2405 #define RX_DMA_PERIODS 16
2406 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2407
imx_uart_probe(struct platform_device * pdev)2408 static int imx_uart_probe(struct platform_device *pdev)
2409 {
2410 struct device_node *np = pdev->dev.of_node;
2411 struct imx_port *sport;
2412 void __iomem *base;
2413 u32 dma_buf_conf[2];
2414 int ret = 0;
2415 u32 ucr1, ucr2, uts;
2416 struct resource *res;
2417 int txirq, rxirq, rtsirq;
2418
2419 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2420 if (!sport)
2421 return -ENOMEM;
2422
2423 sport->devdata = of_device_get_match_data(&pdev->dev);
2424
2425 ret = of_alias_get_id(np, "serial");
2426 if (ret < 0) {
2427 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2428 return ret;
2429 }
2430 sport->port.line = ret;
2431
2432 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2433 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2434
2435 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2436
2437 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2438
2439 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2440
2441 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2442
2443 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2444 sport->rx_period_length = dma_buf_conf[0];
2445 sport->rx_periods = dma_buf_conf[1];
2446 } else {
2447 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2448 sport->rx_periods = RX_DMA_PERIODS;
2449 }
2450
2451 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2452 dev_err(&pdev->dev, "serial%d out of range\n",
2453 sport->port.line);
2454 return -EINVAL;
2455 }
2456
2457 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2458 if (IS_ERR(base))
2459 return PTR_ERR(base);
2460
2461 rxirq = platform_get_irq(pdev, 0);
2462 if (rxirq < 0)
2463 return rxirq;
2464 txirq = platform_get_irq_optional(pdev, 1);
2465 rtsirq = platform_get_irq_optional(pdev, 2);
2466
2467 sport->port.dev = &pdev->dev;
2468 sport->port.mapbase = res->start;
2469 sport->port.membase = base;
2470 sport->port.type = PORT_IMX;
2471 sport->port.iotype = UPIO_MEM;
2472 sport->port.irq = rxirq;
2473 sport->port.fifosize = 32;
2474 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2475 sport->port.ops = &imx_uart_pops;
2476 sport->port.rs485_config = imx_uart_rs485_config;
2477 /* RTS is required to control the RS485 transmitter */
2478 if (sport->have_rtscts || sport->have_rtsgpio)
2479 sport->port.rs485_supported = imx_rs485_supported;
2480 sport->port.flags = UPF_BOOT_AUTOCONF;
2481 timer_setup(&sport->timer, imx_uart_timeout, 0);
2482
2483 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2484 if (IS_ERR(sport->gpios))
2485 return PTR_ERR(sport->gpios);
2486
2487 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2488 if (IS_ERR(sport->clk_ipg)) {
2489 ret = PTR_ERR(sport->clk_ipg);
2490 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2491 return ret;
2492 }
2493
2494 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2495 if (IS_ERR(sport->clk_per)) {
2496 ret = PTR_ERR(sport->clk_per);
2497 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2498 return ret;
2499 }
2500
2501 sport->port.uartclk = clk_get_rate(sport->clk_per);
2502
2503 /* For register access, we only need to enable the ipg clock. */
2504 ret = clk_prepare_enable(sport->clk_ipg);
2505 if (ret) {
2506 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2507 return ret;
2508 }
2509
2510 ret = uart_get_rs485_mode(&sport->port);
2511 if (ret)
2512 goto err_clk;
2513
2514 /*
2515 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2516 * signal cannot be set low during transmission in case the
2517 * receiver is off (limitation of the i.MX UART IP).
2518 */
2519 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2520 sport->have_rtscts && !sport->have_rtsgpio &&
2521 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2522 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2523 dev_err(&pdev->dev,
2524 "low-active RTS not possible when receiver is off, enabling receiver\n");
2525
2526 /* Disable interrupts before requesting them */
2527 ucr1 = imx_uart_readl(sport, UCR1);
2528 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2529 imx_uart_writel(sport, ucr1, UCR1);
2530
2531 /* Disable Ageing Timer interrupt */
2532 ucr2 = imx_uart_readl(sport, UCR2);
2533 ucr2 &= ~UCR2_ATEN;
2534 imx_uart_writel(sport, ucr2, UCR2);
2535
2536 /*
2537 * In case RS485 is enabled without GPIO RTS control, the UART IP
2538 * is used to control CTS signal. Keep both the UART and Receiver
2539 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2540 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2541 * data from being fed into the RX FIFO, enable loopback mode in
2542 * UTS register, which disconnects the RX path from external RXD
2543 * pin and connects it to the Transceiver, which is disabled, so
2544 * no data can be fed to the RX FIFO that way.
2545 */
2546 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2547 sport->have_rtscts && !sport->have_rtsgpio) {
2548 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2549 uts |= UTS_LOOP;
2550 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2551
2552 ucr1 = imx_uart_readl(sport, UCR1);
2553 ucr1 |= UCR1_UARTEN;
2554 imx_uart_writel(sport, ucr1, UCR1);
2555
2556 ucr2 = imx_uart_readl(sport, UCR2);
2557 ucr2 |= UCR2_RXEN;
2558 imx_uart_writel(sport, ucr2, UCR2);
2559 }
2560
2561 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2562 /*
2563 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2564 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2565 * and DCD (when they are outputs) or enables the respective
2566 * irqs. So set this bit early, i.e. before requesting irqs.
2567 */
2568 u32 ufcr = imx_uart_readl(sport, UFCR);
2569 if (!(ufcr & UFCR_DCEDTE))
2570 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2571
2572 /*
2573 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2574 * enabled later because they cannot be cleared
2575 * (confirmed on i.MX25) which makes them unusable.
2576 */
2577 imx_uart_writel(sport,
2578 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2579 UCR3);
2580
2581 } else {
2582 u32 ucr3 = UCR3_DSR;
2583 u32 ufcr = imx_uart_readl(sport, UFCR);
2584 if (ufcr & UFCR_DCEDTE)
2585 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2586
2587 if (!imx_uart_is_imx1(sport))
2588 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2589 imx_uart_writel(sport, ucr3, UCR3);
2590 }
2591
2592 hrtimer_setup(&sport->trigger_start_tx, imx_trigger_start_tx, CLOCK_MONOTONIC,
2593 HRTIMER_MODE_REL);
2594 hrtimer_setup(&sport->trigger_stop_tx, imx_trigger_stop_tx, CLOCK_MONOTONIC,
2595 HRTIMER_MODE_REL);
2596
2597 /*
2598 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2599 * chips only have one interrupt.
2600 */
2601 if (txirq > 0) {
2602 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2603 dev_name(&pdev->dev), sport);
2604 if (ret) {
2605 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2606 ret);
2607 goto err_clk;
2608 }
2609
2610 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2611 dev_name(&pdev->dev), sport);
2612 if (ret) {
2613 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2614 ret);
2615 goto err_clk;
2616 }
2617
2618 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2619 dev_name(&pdev->dev), sport);
2620 if (ret) {
2621 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2622 ret);
2623 goto err_clk;
2624 }
2625 } else {
2626 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2627 dev_name(&pdev->dev), sport);
2628 if (ret) {
2629 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2630 goto err_clk;
2631 }
2632 }
2633
2634 imx_uart_ports[sport->port.line] = sport;
2635
2636 platform_set_drvdata(pdev, sport);
2637
2638 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2639
2640 err_clk:
2641 clk_disable_unprepare(sport->clk_ipg);
2642
2643 return ret;
2644 }
2645
imx_uart_remove(struct platform_device * pdev)2646 static void imx_uart_remove(struct platform_device *pdev)
2647 {
2648 struct imx_port *sport = platform_get_drvdata(pdev);
2649
2650 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2651 }
2652
imx_uart_restore_context(struct imx_port * sport)2653 static void imx_uart_restore_context(struct imx_port *sport)
2654 {
2655 unsigned long flags;
2656
2657 uart_port_lock_irqsave(&sport->port, &flags);
2658 if (!sport->context_saved) {
2659 uart_port_unlock_irqrestore(&sport->port, flags);
2660 return;
2661 }
2662
2663 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2664 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2665 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2666 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2667 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2668 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2669 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2670 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2671 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2672 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2673 sport->context_saved = false;
2674 uart_port_unlock_irqrestore(&sport->port, flags);
2675 }
2676
imx_uart_save_context(struct imx_port * sport)2677 static void imx_uart_save_context(struct imx_port *sport)
2678 {
2679 unsigned long flags;
2680
2681 /* Save necessary regs */
2682 uart_port_lock_irqsave(&sport->port, &flags);
2683 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2684 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2685 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2686 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2687 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2688 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2689 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2690 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2691 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2692 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2693 sport->context_saved = true;
2694 uart_port_unlock_irqrestore(&sport->port, flags);
2695 }
2696
2697 /* called with irq off */
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2698 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2699 {
2700 u32 ucr3;
2701
2702 uart_port_lock_irq(&sport->port);
2703
2704 ucr3 = imx_uart_readl(sport, UCR3);
2705 if (on) {
2706 imx_uart_writel(sport, USR1_AWAKE, USR1);
2707 ucr3 |= UCR3_AWAKEN;
2708 } else {
2709 ucr3 &= ~UCR3_AWAKEN;
2710 }
2711 imx_uart_writel(sport, ucr3, UCR3);
2712
2713 if (sport->have_rtscts) {
2714 u32 ucr1 = imx_uart_readl(sport, UCR1);
2715 if (on) {
2716 imx_uart_writel(sport, USR1_RTSD, USR1);
2717 ucr1 |= UCR1_RTSDEN;
2718 } else {
2719 ucr1 &= ~UCR1_RTSDEN;
2720 }
2721 imx_uart_writel(sport, ucr1, UCR1);
2722 }
2723
2724 uart_port_unlock_irq(&sport->port);
2725 }
2726
imx_uart_suspend_noirq(struct device * dev)2727 static int imx_uart_suspend_noirq(struct device *dev)
2728 {
2729 struct imx_port *sport = dev_get_drvdata(dev);
2730
2731 imx_uart_save_context(sport);
2732
2733 clk_disable(sport->clk_ipg);
2734
2735 pinctrl_pm_select_sleep_state(dev);
2736
2737 return 0;
2738 }
2739
imx_uart_resume_noirq(struct device * dev)2740 static int imx_uart_resume_noirq(struct device *dev)
2741 {
2742 struct imx_port *sport = dev_get_drvdata(dev);
2743 int ret;
2744
2745 pinctrl_pm_select_default_state(dev);
2746
2747 ret = clk_enable(sport->clk_ipg);
2748 if (ret)
2749 return ret;
2750
2751 imx_uart_restore_context(sport);
2752
2753 return 0;
2754 }
2755
imx_uart_suspend(struct device * dev)2756 static int imx_uart_suspend(struct device *dev)
2757 {
2758 struct imx_port *sport = dev_get_drvdata(dev);
2759 int ret;
2760
2761 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2762 disable_irq(sport->port.irq);
2763
2764 ret = clk_prepare_enable(sport->clk_ipg);
2765 if (ret)
2766 return ret;
2767
2768 /* enable wakeup from i.MX UART */
2769 imx_uart_enable_wakeup(sport, true);
2770
2771 return 0;
2772 }
2773
imx_uart_resume(struct device * dev)2774 static int imx_uart_resume(struct device *dev)
2775 {
2776 struct imx_port *sport = dev_get_drvdata(dev);
2777
2778 /* disable wakeup from i.MX UART */
2779 imx_uart_enable_wakeup(sport, false);
2780
2781 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2782 enable_irq(sport->port.irq);
2783
2784 clk_disable_unprepare(sport->clk_ipg);
2785
2786 return 0;
2787 }
2788
imx_uart_freeze(struct device * dev)2789 static int imx_uart_freeze(struct device *dev)
2790 {
2791 struct imx_port *sport = dev_get_drvdata(dev);
2792
2793 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2794
2795 return clk_prepare_enable(sport->clk_ipg);
2796 }
2797
imx_uart_thaw(struct device * dev)2798 static int imx_uart_thaw(struct device *dev)
2799 {
2800 struct imx_port *sport = dev_get_drvdata(dev);
2801
2802 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2803
2804 clk_disable_unprepare(sport->clk_ipg);
2805
2806 return 0;
2807 }
2808
2809 static const struct dev_pm_ops imx_uart_pm_ops = {
2810 .suspend_noirq = imx_uart_suspend_noirq,
2811 .resume_noirq = imx_uart_resume_noirq,
2812 .freeze_noirq = imx_uart_suspend_noirq,
2813 .thaw_noirq = imx_uart_resume_noirq,
2814 .restore_noirq = imx_uart_resume_noirq,
2815 .suspend = imx_uart_suspend,
2816 .resume = imx_uart_resume,
2817 .freeze = imx_uart_freeze,
2818 .thaw = imx_uart_thaw,
2819 .restore = imx_uart_thaw,
2820 };
2821
2822 static struct platform_driver imx_uart_platform_driver = {
2823 .probe = imx_uart_probe,
2824 .remove = imx_uart_remove,
2825
2826 .driver = {
2827 .name = "imx-uart",
2828 .of_match_table = imx_uart_dt_ids,
2829 .pm = &imx_uart_pm_ops,
2830 },
2831 };
2832
imx_uart_init(void)2833 static int __init imx_uart_init(void)
2834 {
2835 int ret = uart_register_driver(&imx_uart_uart_driver);
2836
2837 if (ret)
2838 return ret;
2839
2840 ret = platform_driver_register(&imx_uart_platform_driver);
2841 if (ret != 0)
2842 uart_unregister_driver(&imx_uart_uart_driver);
2843
2844 return ret;
2845 }
2846
imx_uart_exit(void)2847 static void __exit imx_uart_exit(void)
2848 {
2849 platform_driver_unregister(&imx_uart_platform_driver);
2850 uart_unregister_driver(&imx_uart_uart_driver);
2851 }
2852
2853 module_init(imx_uart_init);
2854 module_exit(imx_uart_exit);
2855
2856 MODULE_AUTHOR("Sascha Hauer");
2857 MODULE_DESCRIPTION("IMX generic serial port driver");
2858 MODULE_LICENSE("GPL");
2859 MODULE_ALIAS("platform:imx-uart");
2860