1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright 2020 NXP
4 //
5 // Author: Daniel Baluta <daniel.baluta@nxp.com>
6 //
7 // Hardware interface for audio DSP on i.MX8M
8
9 #include <linux/bits.h>
10 #include <linux/firmware.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/of_platform.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/regmap.h>
16
17 #include <linux/module.h>
18 #include <sound/sof.h>
19 #include <sound/sof/xtensa.h>
20 #include <linux/firmware/imx/dsp.h>
21
22 #include "../ops.h"
23 #include "../sof-of-dev.h"
24 #include "imx-common.h"
25
26 #define MBOX_OFFSET 0x800000
27 #define MBOX_SIZE 0x1000
28
29 /* DAP registers */
30 #define IMX8M_DAP_DEBUG 0x28800000
31 #define IMX8M_DAP_DEBUG_SIZE (64 * 1024)
32 #define IMX8M_DAP_PWRCTL (0x4000 + 0x3020)
33 #define IMX8M_PWRCTL_CORERESET BIT(16)
34
35 /* DSP audio mix registers */
36 #define AudioDSP_REG0 0x100
37 #define AudioDSP_REG1 0x104
38 #define AudioDSP_REG2 0x108
39 #define AudioDSP_REG3 0x10c
40
41 #define AudioDSP_REG2_RUNSTALL BIT(5)
42
43 struct imx8m_priv {
44 struct device *dev;
45 struct snd_sof_dev *sdev;
46
47 /* DSP IPC handler */
48 struct imx_dsp_ipc *dsp_ipc;
49 struct platform_device *ipc_dev;
50
51 struct clk_bulk_data *clks;
52 int clk_num;
53
54 void __iomem *dap;
55 struct regmap *regmap;
56 };
57
imx8m_get_mailbox_offset(struct snd_sof_dev * sdev)58 static int imx8m_get_mailbox_offset(struct snd_sof_dev *sdev)
59 {
60 return MBOX_OFFSET;
61 }
62
imx8m_get_window_offset(struct snd_sof_dev * sdev,u32 id)63 static int imx8m_get_window_offset(struct snd_sof_dev *sdev, u32 id)
64 {
65 return MBOX_OFFSET;
66 }
67
imx8m_dsp_handle_reply(struct imx_dsp_ipc * ipc)68 static void imx8m_dsp_handle_reply(struct imx_dsp_ipc *ipc)
69 {
70 struct imx8m_priv *priv = imx_dsp_get_data(ipc);
71 unsigned long flags;
72
73 spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
74 snd_sof_ipc_process_reply(priv->sdev, 0);
75 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
76 }
77
imx8m_dsp_handle_request(struct imx_dsp_ipc * ipc)78 static void imx8m_dsp_handle_request(struct imx_dsp_ipc *ipc)
79 {
80 struct imx8m_priv *priv = imx_dsp_get_data(ipc);
81 u32 p; /* Panic code */
82
83 /* Read the message from the debug box. */
84 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
85
86 /* Check to see if the message is a panic code (0x0dead***) */
87 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
88 snd_sof_dsp_panic(priv->sdev, p, true);
89 else
90 snd_sof_ipc_msgs_rx(priv->sdev);
91 }
92
93 static struct imx_dsp_ops imx8m_dsp_ops = {
94 .handle_reply = imx8m_dsp_handle_reply,
95 .handle_request = imx8m_dsp_handle_request,
96 };
97
imx8m_send_msg(struct snd_sof_dev * sdev,struct snd_sof_ipc_msg * msg)98 static int imx8m_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
99 {
100 struct imx8m_priv *priv = sdev->pdata->hw_pdata;
101
102 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
103 msg->msg_size);
104 imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
105
106 return 0;
107 }
108
109 /*
110 * DSP control.
111 */
imx8m_run(struct snd_sof_dev * sdev)112 static int imx8m_run(struct snd_sof_dev *sdev)
113 {
114 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;
115
116 regmap_update_bits(priv->regmap, AudioDSP_REG2, AudioDSP_REG2_RUNSTALL, 0);
117
118 return 0;
119 }
120
imx8m_reset(struct snd_sof_dev * sdev)121 static int imx8m_reset(struct snd_sof_dev *sdev)
122 {
123 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;
124 u32 pwrctl;
125
126 /* put DSP into reset and stall */
127 pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL);
128 pwrctl |= IMX8M_PWRCTL_CORERESET;
129 writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL);
130
131 /* keep reset asserted for 10 cycles */
132 usleep_range(1, 2);
133
134 regmap_update_bits(priv->regmap, AudioDSP_REG2,
135 AudioDSP_REG2_RUNSTALL, AudioDSP_REG2_RUNSTALL);
136
137 /* take the DSP out of reset and keep stalled for FW loading */
138 pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL);
139 pwrctl &= ~IMX8M_PWRCTL_CORERESET;
140 writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL);
141
142 return 0;
143 }
144
imx8m_probe(struct snd_sof_dev * sdev)145 static int imx8m_probe(struct snd_sof_dev *sdev)
146 {
147 struct platform_device *pdev = to_platform_device(sdev->dev);
148 struct device_node *np = pdev->dev.of_node;
149 struct device_node *res_node;
150 struct resource *mmio;
151 struct imx8m_priv *priv;
152 struct resource res;
153 u32 base, size;
154 int ret = 0;
155
156 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
157 if (!priv)
158 return -ENOMEM;
159
160 sdev->num_cores = 1;
161 sdev->pdata->hw_pdata = priv;
162 priv->dev = sdev->dev;
163 priv->sdev = sdev;
164
165 priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
166 PLATFORM_DEVID_NONE,
167 pdev, sizeof(*pdev));
168 if (IS_ERR(priv->ipc_dev))
169 return PTR_ERR(priv->ipc_dev);
170
171 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
172 if (!priv->dsp_ipc) {
173 /* DSP IPC driver not probed yet, try later */
174 ret = -EPROBE_DEFER;
175 dev_err(sdev->dev, "Failed to get drvdata\n");
176 goto exit_pdev_unregister;
177 }
178
179 imx_dsp_set_data(priv->dsp_ipc, priv);
180 priv->dsp_ipc->ops = &imx8m_dsp_ops;
181
182 /* DSP base */
183 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
184 if (mmio) {
185 base = mmio->start;
186 size = resource_size(mmio);
187 } else {
188 dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
189 ret = -EINVAL;
190 goto exit_pdev_unregister;
191 }
192
193 priv->dap = devm_ioremap(sdev->dev, IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE);
194 if (!priv->dap) {
195 dev_err(sdev->dev, "error: failed to map DAP debug memory area");
196 ret = -ENODEV;
197 goto exit_pdev_unregister;
198 }
199
200 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
201 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
202 dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
203 base, size);
204 ret = -ENODEV;
205 goto exit_pdev_unregister;
206 }
207 sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
208
209 res_node = of_parse_phandle(np, "memory-region", 0);
210 if (!res_node) {
211 dev_err(&pdev->dev, "failed to get memory region node\n");
212 ret = -ENODEV;
213 goto exit_pdev_unregister;
214 }
215
216 ret = of_address_to_resource(res_node, 0, &res);
217 of_node_put(res_node);
218 if (ret) {
219 dev_err(&pdev->dev, "failed to get reserved region address\n");
220 goto exit_pdev_unregister;
221 }
222
223 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
224 resource_size(&res));
225 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
226 dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
227 base, size);
228 ret = -ENOMEM;
229 goto exit_pdev_unregister;
230 }
231 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
232
233 /* set default mailbox offset for FW ready message */
234 sdev->dsp_box.offset = MBOX_OFFSET;
235
236 priv->regmap = syscon_regmap_lookup_by_phandle(np, "fsl,dsp-ctrl");
237 if (IS_ERR(priv->regmap)) {
238 dev_err(sdev->dev, "cannot find dsp-ctrl registers");
239 ret = PTR_ERR(priv->regmap);
240 goto exit_pdev_unregister;
241 }
242
243 ret = devm_clk_bulk_get_all(sdev->dev, &priv->clks);
244 if (ret < 0) {
245 dev_err(sdev->dev, "failed to fetch clocks: %d\n", ret);
246 goto exit_pdev_unregister;
247 }
248 priv->clk_num = ret;
249
250 ret = clk_bulk_prepare_enable(priv->clk_num, priv->clks);
251 if (ret < 0) {
252 dev_err(sdev->dev, "failed to enable clocks: %d\n", ret);
253 goto exit_pdev_unregister;
254 }
255
256 return 0;
257
258 exit_pdev_unregister:
259 platform_device_unregister(priv->ipc_dev);
260 return ret;
261 }
262
imx8m_remove(struct snd_sof_dev * sdev)263 static void imx8m_remove(struct snd_sof_dev *sdev)
264 {
265 struct imx8m_priv *priv = sdev->pdata->hw_pdata;
266
267 clk_bulk_disable_unprepare(priv->clk_num, priv->clks);
268 platform_device_unregister(priv->ipc_dev);
269 }
270
271 /* on i.MX8 there is 1 to 1 match between type and BAR idx */
imx8m_get_bar_index(struct snd_sof_dev * sdev,u32 type)272 static int imx8m_get_bar_index(struct snd_sof_dev *sdev, u32 type)
273 {
274 /* Only IRAM and SRAM bars are valid */
275 switch (type) {
276 case SOF_FW_BLK_TYPE_IRAM:
277 case SOF_FW_BLK_TYPE_SRAM:
278 return type;
279 default:
280 return -EINVAL;
281 }
282 }
283
284 static struct snd_soc_dai_driver imx8m_dai[] = {
285 {
286 .name = "sai1",
287 .playback = {
288 .channels_min = 1,
289 .channels_max = 32,
290 },
291 .capture = {
292 .channels_min = 1,
293 .channels_max = 32,
294 },
295 },
296 {
297 .name = "sai2",
298 .playback = {
299 .channels_min = 1,
300 .channels_max = 32,
301 },
302 .capture = {
303 .channels_min = 1,
304 .channels_max = 32,
305 },
306 },
307 {
308 .name = "sai3",
309 .playback = {
310 .channels_min = 1,
311 .channels_max = 32,
312 },
313 .capture = {
314 .channels_min = 1,
315 .channels_max = 32,
316 },
317 },
318 {
319 .name = "sai5",
320 .playback = {
321 .channels_min = 1,
322 .channels_max = 32,
323 },
324 .capture = {
325 .channels_min = 1,
326 .channels_max = 32,
327 },
328 },
329 {
330 .name = "sai6",
331 .playback = {
332 .channels_min = 1,
333 .channels_max = 32,
334 },
335 .capture = {
336 .channels_min = 1,
337 .channels_max = 32,
338 },
339 },
340 {
341 .name = "sai7",
342 .playback = {
343 .channels_min = 1,
344 .channels_max = 32,
345 },
346 .capture = {
347 .channels_min = 1,
348 .channels_max = 32,
349 },
350 },
351 {
352 .name = "micfil",
353 .capture = {
354 .channels_min = 1,
355 .channels_max = 8,
356 },
357 },
358 };
359
imx8m_dsp_set_power_state(struct snd_sof_dev * sdev,const struct sof_dsp_power_state * target_state)360 static int imx8m_dsp_set_power_state(struct snd_sof_dev *sdev,
361 const struct sof_dsp_power_state *target_state)
362 {
363 sdev->dsp_power_state = *target_state;
364
365 return 0;
366 }
367
imx8m_resume(struct snd_sof_dev * sdev)368 static int imx8m_resume(struct snd_sof_dev *sdev)
369 {
370 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;
371 int ret;
372 int i;
373
374 ret = clk_bulk_prepare_enable(priv->clk_num, priv->clks);
375 if (ret < 0) {
376 dev_err(sdev->dev, "failed to enable clocks: %d\n", ret);
377 return ret;
378 }
379
380 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
381 imx_dsp_request_channel(priv->dsp_ipc, i);
382
383 return 0;
384 }
385
imx8m_suspend(struct snd_sof_dev * sdev)386 static void imx8m_suspend(struct snd_sof_dev *sdev)
387 {
388 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;
389 int i;
390
391 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
392 imx_dsp_free_channel(priv->dsp_ipc, i);
393
394 clk_bulk_disable_unprepare(priv->clk_num, priv->clks);
395 }
396
imx8m_dsp_runtime_resume(struct snd_sof_dev * sdev)397 static int imx8m_dsp_runtime_resume(struct snd_sof_dev *sdev)
398 {
399 int ret;
400 const struct sof_dsp_power_state target_dsp_state = {
401 .state = SOF_DSP_PM_D0,
402 };
403
404 ret = imx8m_resume(sdev);
405 if (ret < 0)
406 return ret;
407
408 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
409 }
410
imx8m_dsp_runtime_suspend(struct snd_sof_dev * sdev)411 static int imx8m_dsp_runtime_suspend(struct snd_sof_dev *sdev)
412 {
413 const struct sof_dsp_power_state target_dsp_state = {
414 .state = SOF_DSP_PM_D3,
415 };
416
417 imx8m_suspend(sdev);
418
419 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
420 }
421
imx8m_dsp_resume(struct snd_sof_dev * sdev)422 static int imx8m_dsp_resume(struct snd_sof_dev *sdev)
423 {
424 int ret;
425 const struct sof_dsp_power_state target_dsp_state = {
426 .state = SOF_DSP_PM_D0,
427 };
428
429 ret = imx8m_resume(sdev);
430 if (ret < 0)
431 return ret;
432
433 if (pm_runtime_suspended(sdev->dev)) {
434 pm_runtime_disable(sdev->dev);
435 pm_runtime_set_active(sdev->dev);
436 pm_runtime_mark_last_busy(sdev->dev);
437 pm_runtime_enable(sdev->dev);
438 pm_runtime_idle(sdev->dev);
439 }
440
441 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
442 }
443
imx8m_dsp_suspend(struct snd_sof_dev * sdev,unsigned int target_state)444 static int imx8m_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state)
445 {
446 const struct sof_dsp_power_state target_dsp_state = {
447 .state = target_state,
448 };
449
450 if (!pm_runtime_suspended(sdev->dev))
451 imx8m_suspend(sdev);
452
453 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
454 }
455
456 /* i.MX8 ops */
457 static const struct snd_sof_dsp_ops sof_imx8m_ops = {
458 /* probe and remove */
459 .probe = imx8m_probe,
460 .remove = imx8m_remove,
461 /* DSP core boot */
462 .run = imx8m_run,
463 .reset = imx8m_reset,
464
465 /* Block IO */
466 .block_read = sof_block_read,
467 .block_write = sof_block_write,
468
469 /* Mailbox IO */
470 .mailbox_read = sof_mailbox_read,
471 .mailbox_write = sof_mailbox_write,
472
473 /* ipc */
474 .send_msg = imx8m_send_msg,
475 .get_mailbox_offset = imx8m_get_mailbox_offset,
476 .get_window_offset = imx8m_get_window_offset,
477
478 .ipc_msg_data = sof_ipc_msg_data,
479 .set_stream_data_offset = sof_set_stream_data_offset,
480
481 .get_bar_index = imx8m_get_bar_index,
482
483 /* firmware loading */
484 .load_firmware = snd_sof_load_firmware_memcpy,
485
486 /* Debug information */
487 .dbg_dump = imx8_dump,
488 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
489
490 /* stream callbacks */
491 .pcm_open = sof_stream_pcm_open,
492 .pcm_close = sof_stream_pcm_close,
493 /* Firmware ops */
494 .dsp_arch_ops = &sof_xtensa_arch_ops,
495
496 /* DAI drivers */
497 .drv = imx8m_dai,
498 .num_drv = ARRAY_SIZE(imx8m_dai),
499
500 .suspend = imx8m_dsp_suspend,
501 .resume = imx8m_dsp_resume,
502
503 .runtime_suspend = imx8m_dsp_runtime_suspend,
504 .runtime_resume = imx8m_dsp_runtime_resume,
505
506 .set_power_state = imx8m_dsp_set_power_state,
507
508 .hw_info = SNDRV_PCM_INFO_MMAP |
509 SNDRV_PCM_INFO_MMAP_VALID |
510 SNDRV_PCM_INFO_INTERLEAVED |
511 SNDRV_PCM_INFO_PAUSE |
512 SNDRV_PCM_INFO_BATCH |
513 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
514 };
515
516 static struct snd_sof_of_mach sof_imx8mp_machs[] = {
517 {
518 .compatible = "fsl,imx8mp-evk-revb4",
519 .sof_tplg_filename = "sof-imx8mp-wm8962.tplg",
520 .drv_name = "asoc-audio-graph-card2",
521 },
522 {
523 .compatible = "fsl,imx8mp-evk",
524 .sof_tplg_filename = "sof-imx8mp-wm8960.tplg",
525 .drv_name = "asoc-audio-graph-card2",
526 },
527 {}
528 };
529
530 static struct sof_dev_desc sof_of_imx8mp_desc = {
531 .of_machines = sof_imx8mp_machs,
532 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
533 .ipc_default = SOF_IPC_TYPE_3,
534 .default_fw_path = {
535 [SOF_IPC_TYPE_3] = "imx/sof",
536 },
537 .default_tplg_path = {
538 [SOF_IPC_TYPE_3] = "imx/sof-tplg",
539 },
540 .default_fw_filename = {
541 [SOF_IPC_TYPE_3] = "sof-imx8m.ri",
542 },
543 .nocodec_tplg_filename = "sof-imx8-nocodec.tplg",
544 .ops = &sof_imx8m_ops,
545 };
546
547 static const struct of_device_id sof_of_imx8m_ids[] = {
548 { .compatible = "fsl,imx8mp-dsp", .data = &sof_of_imx8mp_desc},
549 { }
550 };
551 MODULE_DEVICE_TABLE(of, sof_of_imx8m_ids);
552
553 /* DT driver definition */
554 static struct platform_driver snd_sof_of_imx8m_driver = {
555 .probe = sof_of_probe,
556 .remove = sof_of_remove,
557 .driver = {
558 .name = "sof-audio-of-imx8m",
559 .pm = &sof_of_pm,
560 .of_match_table = sof_of_imx8m_ids,
561 },
562 };
563 module_platform_driver(snd_sof_of_imx8m_driver);
564
565 MODULE_LICENSE("Dual BSD/GPL");
566 MODULE_DESCRIPTION("SOF support for IMX8M platforms");
567 MODULE_IMPORT_NS("SND_SOC_SOF_XTENSA");
568