1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (C) 2016 Freescale Semiconductor, Inc.
4 // Copyright (C) 2017 NXP
5 //
6 // Author: Dong Aisheng <aisheng.dong@nxp.com>
7
8 #include <linux/err.h>
9 #include <linux/init.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/pinctrl/pinctrl.h>
13
14 #include "pinctrl-imx.h"
15
16 enum imx7ulp_pads {
17 IMX7ULP_PAD_PTC0 = 0,
18 IMX7ULP_PAD_PTC1,
19 IMX7ULP_PAD_PTC2,
20 IMX7ULP_PAD_PTC3,
21 IMX7ULP_PAD_PTC4,
22 IMX7ULP_PAD_PTC5,
23 IMX7ULP_PAD_PTC6,
24 IMX7ULP_PAD_PTC7,
25 IMX7ULP_PAD_PTC8,
26 IMX7ULP_PAD_PTC9,
27 IMX7ULP_PAD_PTC10,
28 IMX7ULP_PAD_PTC11,
29 IMX7ULP_PAD_PTC12,
30 IMX7ULP_PAD_PTC13,
31 IMX7ULP_PAD_PTC14,
32 IMX7ULP_PAD_PTC15,
33 IMX7ULP_PAD_PTC16,
34 IMX7ULP_PAD_PTC17,
35 IMX7ULP_PAD_PTC18,
36 IMX7ULP_PAD_PTC19,
37 IMX7ULP_PAD_RESERVE0,
38 IMX7ULP_PAD_RESERVE1,
39 IMX7ULP_PAD_RESERVE2,
40 IMX7ULP_PAD_RESERVE3,
41 IMX7ULP_PAD_RESERVE4,
42 IMX7ULP_PAD_RESERVE5,
43 IMX7ULP_PAD_RESERVE6,
44 IMX7ULP_PAD_RESERVE7,
45 IMX7ULP_PAD_RESERVE8,
46 IMX7ULP_PAD_RESERVE9,
47 IMX7ULP_PAD_RESERVE10,
48 IMX7ULP_PAD_RESERVE11,
49 IMX7ULP_PAD_PTD0,
50 IMX7ULP_PAD_PTD1,
51 IMX7ULP_PAD_PTD2,
52 IMX7ULP_PAD_PTD3,
53 IMX7ULP_PAD_PTD4,
54 IMX7ULP_PAD_PTD5,
55 IMX7ULP_PAD_PTD6,
56 IMX7ULP_PAD_PTD7,
57 IMX7ULP_PAD_PTD8,
58 IMX7ULP_PAD_PTD9,
59 IMX7ULP_PAD_PTD10,
60 IMX7ULP_PAD_PTD11,
61 IMX7ULP_PAD_RESERVE12,
62 IMX7ULP_PAD_RESERVE13,
63 IMX7ULP_PAD_RESERVE14,
64 IMX7ULP_PAD_RESERVE15,
65 IMX7ULP_PAD_RESERVE16,
66 IMX7ULP_PAD_RESERVE17,
67 IMX7ULP_PAD_RESERVE18,
68 IMX7ULP_PAD_RESERVE19,
69 IMX7ULP_PAD_RESERVE20,
70 IMX7ULP_PAD_RESERVE21,
71 IMX7ULP_PAD_RESERVE22,
72 IMX7ULP_PAD_RESERVE23,
73 IMX7ULP_PAD_RESERVE24,
74 IMX7ULP_PAD_RESERVE25,
75 IMX7ULP_PAD_RESERVE26,
76 IMX7ULP_PAD_RESERVE27,
77 IMX7ULP_PAD_RESERVE28,
78 IMX7ULP_PAD_RESERVE29,
79 IMX7ULP_PAD_RESERVE30,
80 IMX7ULP_PAD_RESERVE31,
81 IMX7ULP_PAD_PTE0,
82 IMX7ULP_PAD_PTE1,
83 IMX7ULP_PAD_PTE2,
84 IMX7ULP_PAD_PTE3,
85 IMX7ULP_PAD_PTE4,
86 IMX7ULP_PAD_PTE5,
87 IMX7ULP_PAD_PTE6,
88 IMX7ULP_PAD_PTE7,
89 IMX7ULP_PAD_PTE8,
90 IMX7ULP_PAD_PTE9,
91 IMX7ULP_PAD_PTE10,
92 IMX7ULP_PAD_PTE11,
93 IMX7ULP_PAD_PTE12,
94 IMX7ULP_PAD_PTE13,
95 IMX7ULP_PAD_PTE14,
96 IMX7ULP_PAD_PTE15,
97 IMX7ULP_PAD_RESERVE32,
98 IMX7ULP_PAD_RESERVE33,
99 IMX7ULP_PAD_RESERVE34,
100 IMX7ULP_PAD_RESERVE35,
101 IMX7ULP_PAD_RESERVE36,
102 IMX7ULP_PAD_RESERVE37,
103 IMX7ULP_PAD_RESERVE38,
104 IMX7ULP_PAD_RESERVE39,
105 IMX7ULP_PAD_RESERVE40,
106 IMX7ULP_PAD_RESERVE41,
107 IMX7ULP_PAD_RESERVE42,
108 IMX7ULP_PAD_RESERVE43,
109 IMX7ULP_PAD_RESERVE44,
110 IMX7ULP_PAD_RESERVE45,
111 IMX7ULP_PAD_RESERVE46,
112 IMX7ULP_PAD_RESERVE47,
113 IMX7ULP_PAD_PTF0,
114 IMX7ULP_PAD_PTF1,
115 IMX7ULP_PAD_PTF2,
116 IMX7ULP_PAD_PTF3,
117 IMX7ULP_PAD_PTF4,
118 IMX7ULP_PAD_PTF5,
119 IMX7ULP_PAD_PTF6,
120 IMX7ULP_PAD_PTF7,
121 IMX7ULP_PAD_PTF8,
122 IMX7ULP_PAD_PTF9,
123 IMX7ULP_PAD_PTF10,
124 IMX7ULP_PAD_PTF11,
125 IMX7ULP_PAD_PTF12,
126 IMX7ULP_PAD_PTF13,
127 IMX7ULP_PAD_PTF14,
128 IMX7ULP_PAD_PTF15,
129 IMX7ULP_PAD_PTF16,
130 IMX7ULP_PAD_PTF17,
131 IMX7ULP_PAD_PTF18,
132 IMX7ULP_PAD_PTF19,
133 };
134
135 /* Pad names for the pinmux subsystem */
136 static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
137 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC0),
138 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC1),
139 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC2),
140 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC3),
141 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC4),
142 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC5),
143 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC6),
144 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC7),
145 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC8),
146 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC9),
147 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC10),
148 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC11),
149 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC12),
150 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC13),
151 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC14),
152 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC15),
153 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC16),
154 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC17),
155 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC18),
156 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC19),
157 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE0),
158 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE1),
159 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE2),
160 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE3),
161 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE4),
162 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE5),
163 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE6),
164 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE7),
165 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE8),
166 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE9),
167 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE10),
168 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE11),
169 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD0),
170 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD1),
171 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD2),
172 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD3),
173 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD4),
174 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD5),
175 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD6),
176 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD7),
177 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD8),
178 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD9),
179 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD10),
180 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD11),
181 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE12),
182 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE13),
183 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE14),
184 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE15),
185 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE16),
186 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE17),
187 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE18),
188 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE19),
189 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE20),
190 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE21),
191 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE22),
192 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE23),
193 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE24),
194 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE25),
195 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE26),
196 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE27),
197 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE28),
198 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE29),
199 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE30),
200 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE31),
201 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE0),
202 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE1),
203 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE2),
204 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE3),
205 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE4),
206 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE5),
207 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE6),
208 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE7),
209 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE8),
210 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE9),
211 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE10),
212 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE11),
213 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE12),
214 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE13),
215 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE14),
216 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE15),
217 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE32),
218 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE33),
219 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE34),
220 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE35),
221 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE36),
222 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE37),
223 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE38),
224 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE39),
225 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE40),
226 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE41),
227 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE42),
228 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE43),
229 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE44),
230 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE45),
231 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE46),
232 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE47),
233 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF0),
234 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF1),
235 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF2),
236 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF3),
237 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF4),
238 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF5),
239 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF6),
240 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF7),
241 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF8),
242 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF9),
243 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF10),
244 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF11),
245 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF12),
246 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF13),
247 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF14),
248 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF15),
249 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF16),
250 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF17),
251 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF18),
252 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19),
253 };
254
255 #define BM_OBE_ENABLED BIT(17)
256 #define BM_IBE_ENABLED BIT(16)
257 #define BM_MUX_MODE 0xf00
258 #define BP_MUX_MODE 8
259
imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset,bool input)260 static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
261 struct pinctrl_gpio_range *range,
262 unsigned offset, bool input)
263 {
264 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
265 const struct imx_pin_reg *pin_reg;
266 u32 reg;
267
268 pin_reg = &ipctl->pin_regs[offset];
269 if (pin_reg->mux_reg == -1)
270 return -EINVAL;
271
272 reg = readl(ipctl->base + pin_reg->mux_reg);
273 if (input)
274 reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
275 else
276 reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
277 writel(reg, ipctl->base + pin_reg->mux_reg);
278
279 return 0;
280 }
281
282 static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
283 .pins = imx7ulp_pinctrl_pads,
284 .npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
285 .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
286 .gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
287 .mux_mask = BM_MUX_MODE,
288 .mux_shift = BP_MUX_MODE,
289 };
290
291 static const struct of_device_id imx7ulp_pinctrl_of_match[] = {
292 { .compatible = "fsl,imx7ulp-iomuxc1", },
293 { /* sentinel */ }
294 };
295
imx7ulp_pinctrl_probe(struct platform_device * pdev)296 static int imx7ulp_pinctrl_probe(struct platform_device *pdev)
297 {
298 return imx_pinctrl_probe(pdev, &imx7ulp_pinctrl_info);
299 }
300
301 static struct platform_driver imx7ulp_pinctrl_driver = {
302 .driver = {
303 .name = "imx7ulp-pinctrl",
304 .of_match_table = imx7ulp_pinctrl_of_match,
305 .suppress_bind_attrs = true,
306 },
307 .probe = imx7ulp_pinctrl_probe,
308 };
309
imx7ulp_pinctrl_init(void)310 static int __init imx7ulp_pinctrl_init(void)
311 {
312 return platform_driver_register(&imx7ulp_pinctrl_driver);
313 }
314 arch_initcall(imx7ulp_pinctrl_init);
315