1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include "clk-gate.h" 7 #include "clk-mtk.h" 8 9 #include <dt-bindings/clock/mt8195-clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/platform_device.h> 12 13 static const struct mtk_gate_regs img_cg_regs = { 14 .set_ofs = 0x4, 15 .clr_ofs = 0x8, 16 .sta_ofs = 0x0, 17 }; 18 19 #define GATE_IMG(_id, _name, _parent, _shift) \ 20 GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 21 22 static const struct mtk_gate img_clks[] = { 23 GATE_IMG(CLK_IMG_LARB9, "img_larb9", "top_img", 0), 24 GATE_IMG(CLK_IMG_TRAW0, "img_traw0", "top_img", 1), 25 GATE_IMG(CLK_IMG_TRAW1, "img_traw1", "top_img", 2), 26 GATE_IMG(CLK_IMG_TRAW2, "img_traw2", "top_img", 3), 27 GATE_IMG(CLK_IMG_TRAW3, "img_traw3", "top_img", 4), 28 GATE_IMG(CLK_IMG_DIP0, "img_dip0", "top_img", 8), 29 GATE_IMG(CLK_IMG_WPE0, "img_wpe0", "top_img", 9), 30 GATE_IMG(CLK_IMG_IPE, "img_ipe", "top_img", 10), 31 GATE_IMG(CLK_IMG_DIP1, "img_dip1", "top_img", 11), 32 GATE_IMG(CLK_IMG_WPE1, "img_wpe1", "top_img", 12), 33 GATE_IMG(CLK_IMG_GALS, "img_gals", "top_img", 31), 34 }; 35 36 static const struct mtk_gate img1_dip_top_clks[] = { 37 GATE_IMG(CLK_IMG1_DIP_TOP_LARB10, "img1_dip_top_larb10", "top_img", 0), 38 GATE_IMG(CLK_IMG1_DIP_TOP_DIP_TOP, "img1_dip_top_dip_top", "top_img", 1), 39 }; 40 41 static const struct mtk_gate img1_dip_nr_clks[] = { 42 GATE_IMG(CLK_IMG1_DIP_NR_RESERVE, "img1_dip_nr_reserve", "top_img", 0), 43 GATE_IMG(CLK_IMG1_DIP_NR_DIP_NR, "img1_dip_nr_dip_nr", "top_img", 1), 44 }; 45 46 static const struct mtk_gate img1_wpe_clks[] = { 47 GATE_IMG(CLK_IMG1_WPE_LARB11, "img1_wpe_larb11", "top_img", 0), 48 GATE_IMG(CLK_IMG1_WPE_WPE, "img1_wpe_wpe", "top_img", 1), 49 }; 50 51 static const struct mtk_clk_desc img_desc = { 52 .clks = img_clks, 53 .num_clks = ARRAY_SIZE(img_clks), 54 }; 55 56 static const struct mtk_clk_desc img1_dip_top_desc = { 57 .clks = img1_dip_top_clks, 58 .num_clks = ARRAY_SIZE(img1_dip_top_clks), 59 }; 60 61 static const struct mtk_clk_desc img1_dip_nr_desc = { 62 .clks = img1_dip_nr_clks, 63 .num_clks = ARRAY_SIZE(img1_dip_nr_clks), 64 }; 65 66 static const struct mtk_clk_desc img1_wpe_desc = { 67 .clks = img1_wpe_clks, 68 .num_clks = ARRAY_SIZE(img1_wpe_clks), 69 }; 70 71 static const struct of_device_id of_match_clk_mt8195_img[] = { 72 { 73 .compatible = "mediatek,mt8195-imgsys", 74 .data = &img_desc, 75 }, { 76 .compatible = "mediatek,mt8195-imgsys1_dip_top", 77 .data = &img1_dip_top_desc, 78 }, { 79 .compatible = "mediatek,mt8195-imgsys1_dip_nr", 80 .data = &img1_dip_nr_desc, 81 }, { 82 .compatible = "mediatek,mt8195-imgsys1_wpe", 83 .data = &img1_wpe_desc, 84 }, { 85 /* sentinel */ 86 } 87 }; 88 MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_img); 89 90 static struct platform_driver clk_mt8195_img_drv = { 91 .probe = mtk_clk_simple_probe, 92 .remove = mtk_clk_simple_remove, 93 .driver = { 94 .name = "clk-mt8195-img", 95 .of_match_table = of_match_clk_mt8195_img, 96 }, 97 }; 98 module_platform_driver(clk_mt8195_img_drv); 99 100 MODULE_DESCRIPTION("MediaTek MT8195 imgsys clocks driver"); 101 MODULE_LICENSE("GPL"); 102