1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel.vetter@ffwll.ch> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "i915_reg.h" 30 #include "intel_de.h" 31 #include "intel_display_irq.h" 32 #include "intel_display_trace.h" 33 #include "intel_display_types.h" 34 #include "intel_fbc.h" 35 #include "intel_fifo_underrun.h" 36 #include "intel_pch_display.h" 37 38 /** 39 * DOC: fifo underrun handling 40 * 41 * The i915 driver checks for display fifo underruns using the interrupt signals 42 * provided by the hardware. This is enabled by default and fairly useful to 43 * debug display issues, especially watermark settings. 44 * 45 * If an underrun is detected this is logged into dmesg. To avoid flooding logs 46 * and occupying the cpu underrun interrupts are disabled after the first 47 * occurrence until the next modeset on a given pipe. 48 * 49 * Note that underrun detection on gmch platforms is a bit more ugly since there 50 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe 51 * interrupt register). Also on some other platforms underrun interrupts are 52 * shared, which means that if we detect an underrun we need to disable underrun 53 * reporting on all pipes. 54 * 55 * The code also supports underrun detection on the PCH transcoder. 56 */ 57 58 static bool ivb_can_enable_err_int(struct intel_display *display) 59 { 60 struct drm_i915_private *dev_priv = to_i915(display->drm); 61 struct intel_crtc *crtc; 62 enum pipe pipe; 63 64 lockdep_assert_held(&dev_priv->irq_lock); 65 66 for_each_pipe(display, pipe) { 67 crtc = intel_crtc_for_pipe(display, pipe); 68 69 if (crtc->cpu_fifo_underrun_disabled) 70 return false; 71 } 72 73 return true; 74 } 75 76 static bool cpt_can_enable_serr_int(struct intel_display *display) 77 { 78 struct drm_i915_private *dev_priv = to_i915(display->drm); 79 enum pipe pipe; 80 struct intel_crtc *crtc; 81 82 lockdep_assert_held(&dev_priv->irq_lock); 83 84 for_each_pipe(display, pipe) { 85 crtc = intel_crtc_for_pipe(display, pipe); 86 87 if (crtc->pch_fifo_underrun_disabled) 88 return false; 89 } 90 91 return true; 92 } 93 94 static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) 95 { 96 struct intel_display *display = to_intel_display(crtc); 97 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 98 i915_reg_t reg = PIPESTAT(display, crtc->pipe); 99 u32 enable_mask; 100 101 lockdep_assert_held(&dev_priv->irq_lock); 102 103 if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) 104 return; 105 106 enable_mask = i915_pipestat_enable_mask(display, crtc->pipe); 107 intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); 108 intel_de_posting_read(display, reg); 109 110 trace_intel_cpu_fifo_underrun(display, crtc->pipe); 111 drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); 112 } 113 114 static void i9xx_set_fifo_underrun_reporting(struct intel_display *display, 115 enum pipe pipe, 116 bool enable, bool old) 117 { 118 struct drm_i915_private *dev_priv = to_i915(display->drm); 119 i915_reg_t reg = PIPESTAT(display, pipe); 120 121 lockdep_assert_held(&dev_priv->irq_lock); 122 123 if (enable) { 124 u32 enable_mask = i915_pipestat_enable_mask(display, pipe); 125 126 intel_de_write(display, reg, 127 enable_mask | PIPE_FIFO_UNDERRUN_STATUS); 128 intel_de_posting_read(display, reg); 129 } else { 130 if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) 131 drm_err(display->drm, "pipe %c underrun\n", 132 pipe_name(pipe)); 133 } 134 } 135 136 static void ilk_set_fifo_underrun_reporting(struct intel_display *display, 137 enum pipe pipe, bool enable) 138 { 139 struct drm_i915_private *dev_priv = to_i915(display->drm); 140 u32 bit = (pipe == PIPE_A) ? 141 DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN; 142 143 if (enable) 144 ilk_enable_display_irq(dev_priv, bit); 145 else 146 ilk_disable_display_irq(dev_priv, bit); 147 } 148 149 static void ivb_check_fifo_underruns(struct intel_crtc *crtc) 150 { 151 struct intel_display *display = to_intel_display(crtc); 152 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 153 enum pipe pipe = crtc->pipe; 154 u32 err_int = intel_de_read(display, GEN7_ERR_INT); 155 156 lockdep_assert_held(&dev_priv->irq_lock); 157 158 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) 159 return; 160 161 intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 162 intel_de_posting_read(display, GEN7_ERR_INT); 163 164 trace_intel_cpu_fifo_underrun(display, pipe); 165 drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe)); 166 } 167 168 static void ivb_set_fifo_underrun_reporting(struct intel_display *display, 169 enum pipe pipe, bool enable, 170 bool old) 171 { 172 struct drm_i915_private *dev_priv = to_i915(display->drm); 173 if (enable) { 174 intel_de_write(display, GEN7_ERR_INT, 175 ERR_INT_FIFO_UNDERRUN(pipe)); 176 177 if (!ivb_can_enable_err_int(display)) 178 return; 179 180 ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB); 181 } else { 182 ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB); 183 184 if (old && 185 intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { 186 drm_err(display->drm, 187 "uncleared fifo underrun on pipe %c\n", 188 pipe_name(pipe)); 189 } 190 } 191 } 192 193 static void bdw_set_fifo_underrun_reporting(struct intel_display *display, 194 enum pipe pipe, bool enable) 195 { 196 struct drm_i915_private *dev_priv = to_i915(display->drm); 197 198 if (enable) 199 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); 200 else 201 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); 202 } 203 204 static void ibx_set_fifo_underrun_reporting(struct intel_display *display, 205 enum pipe pch_transcoder, 206 bool enable) 207 { 208 struct drm_i915_private *dev_priv = to_i915(display->drm); 209 u32 bit = (pch_transcoder == PIPE_A) ? 210 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; 211 212 if (enable) 213 ibx_enable_display_interrupt(dev_priv, bit); 214 else 215 ibx_disable_display_interrupt(dev_priv, bit); 216 } 217 218 static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) 219 { 220 struct intel_display *display = to_intel_display(crtc); 221 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 222 enum pipe pch_transcoder = crtc->pipe; 223 u32 serr_int = intel_de_read(display, SERR_INT); 224 225 lockdep_assert_held(&dev_priv->irq_lock); 226 227 if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) 228 return; 229 230 intel_de_write(display, SERR_INT, 231 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 232 intel_de_posting_read(display, SERR_INT); 233 234 trace_intel_pch_fifo_underrun(display, pch_transcoder); 235 drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n", 236 pipe_name(pch_transcoder)); 237 } 238 239 static void cpt_set_fifo_underrun_reporting(struct intel_display *display, 240 enum pipe pch_transcoder, 241 bool enable, bool old) 242 { 243 struct drm_i915_private *dev_priv = to_i915(display->drm); 244 245 if (enable) { 246 intel_de_write(display, SERR_INT, 247 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 248 249 if (!cpt_can_enable_serr_int(display)) 250 return; 251 252 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); 253 } else { 254 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); 255 256 if (old && intel_de_read(display, SERR_INT) & 257 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { 258 drm_err(display->drm, 259 "uncleared pch fifo underrun on pch transcoder %c\n", 260 pipe_name(pch_transcoder)); 261 } 262 } 263 } 264 265 static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, 266 enum pipe pipe, bool enable) 267 { 268 struct drm_i915_private *dev_priv = to_i915(display->drm); 269 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 270 bool old; 271 272 lockdep_assert_held(&dev_priv->irq_lock); 273 274 old = !crtc->cpu_fifo_underrun_disabled; 275 crtc->cpu_fifo_underrun_disabled = !enable; 276 277 if (HAS_GMCH(display)) 278 i9xx_set_fifo_underrun_reporting(display, pipe, enable, old); 279 else if (display->platform.ironlake || display->platform.sandybridge) 280 ilk_set_fifo_underrun_reporting(display, pipe, enable); 281 else if (DISPLAY_VER(display) == 7) 282 ivb_set_fifo_underrun_reporting(display, pipe, enable, old); 283 else if (DISPLAY_VER(display) >= 8) 284 bdw_set_fifo_underrun_reporting(display, pipe, enable); 285 286 return old; 287 } 288 289 /** 290 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrun reporting state 291 * @display: display device instance 292 * @pipe: (CPU) pipe to set state for 293 * @enable: whether underruns should be reported or not 294 * 295 * This function sets the fifo underrun state for @pipe. It is used in the 296 * modeset code to avoid false positives since on many platforms underruns are 297 * expected when disabling or enabling the pipe. 298 * 299 * Notice that on some platforms disabling underrun reports for one pipe 300 * disables for all due to shared interrupts. Actual reporting is still per-pipe 301 * though. 302 * 303 * Returns the previous state of underrun reporting. 304 */ 305 bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, 306 enum pipe pipe, bool enable) 307 { 308 struct drm_i915_private *dev_priv = to_i915(display->drm); 309 unsigned long flags; 310 bool ret; 311 312 spin_lock_irqsave(&dev_priv->irq_lock, flags); 313 ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable); 314 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 315 316 return ret; 317 } 318 319 /** 320 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state 321 * @display: display device instance 322 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 323 * @enable: whether underruns should be reported or not 324 * 325 * This function makes us disable or enable PCH fifo underruns for a specific 326 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO 327 * underrun reporting for one transcoder may also disable all the other PCH 328 * error interruts for the other transcoders, due to the fact that there's just 329 * one interrupt mask/enable bit for all the transcoders. 330 * 331 * Returns the previous state of underrun reporting. 332 */ 333 bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, 334 enum pipe pch_transcoder, 335 bool enable) 336 { 337 struct drm_i915_private *dev_priv = to_i915(display->drm); 338 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pch_transcoder); 339 unsigned long flags; 340 bool old; 341 342 /* 343 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT 344 * has only one pch transcoder A that all pipes can use. To avoid racy 345 * pch transcoder -> pipe lookups from interrupt code simply store the 346 * underrun statistics in crtc A. Since we never expose this anywhere 347 * nor use it outside of the fifo underrun code here using the "wrong" 348 * crtc on LPT won't cause issues. 349 */ 350 351 spin_lock_irqsave(&dev_priv->irq_lock, flags); 352 353 old = !crtc->pch_fifo_underrun_disabled; 354 crtc->pch_fifo_underrun_disabled = !enable; 355 356 if (HAS_PCH_IBX(dev_priv)) 357 ibx_set_fifo_underrun_reporting(display, 358 pch_transcoder, 359 enable); 360 else 361 cpt_set_fifo_underrun_reporting(display, 362 pch_transcoder, 363 enable, old); 364 365 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 366 return old; 367 } 368 369 /** 370 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt 371 * @display: display device instance 372 * @pipe: (CPU) pipe to set state for 373 * 374 * This handles a CPU fifo underrun interrupt, generating an underrun warning 375 * into dmesg if underrun reporting is enabled and then disables the underrun 376 * interrupt to avoid an irq storm. 377 */ 378 void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display, 379 enum pipe pipe) 380 { 381 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 382 383 /* We may be called too early in init, thanks BIOS! */ 384 if (crtc == NULL) 385 return; 386 387 /* GMCH can't disable fifo underruns, filter them. */ 388 if (HAS_GMCH(display) && 389 crtc->cpu_fifo_underrun_disabled) 390 return; 391 392 if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) { 393 trace_intel_cpu_fifo_underrun(display, pipe); 394 395 drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); 396 } 397 398 intel_fbc_handle_fifo_underrun_irq(display); 399 } 400 401 /** 402 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt 403 * @display: display device instance 404 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 405 * 406 * This handles a PCH fifo underrun interrupt, generating an underrun warning 407 * into dmesg if underrun reporting is enabled and then disables the underrun 408 * interrupt to avoid an irq storm. 409 */ 410 void intel_pch_fifo_underrun_irq_handler(struct intel_display *display, 411 enum pipe pch_transcoder) 412 { 413 if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, 414 false)) { 415 trace_intel_pch_fifo_underrun(display, pch_transcoder); 416 drm_err(display->drm, "PCH transcoder %c FIFO underrun\n", 417 pipe_name(pch_transcoder)); 418 } 419 } 420 421 /** 422 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately 423 * @display: display device instance 424 * 425 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared 426 * error interrupt may have been disabled, and so CPU fifo underruns won't 427 * necessarily raise an interrupt, and on GMCH platforms where underruns never 428 * raise an interrupt. 429 */ 430 void intel_check_cpu_fifo_underruns(struct intel_display *display) 431 { 432 struct drm_i915_private *dev_priv = to_i915(display->drm); 433 struct intel_crtc *crtc; 434 435 spin_lock_irq(&dev_priv->irq_lock); 436 437 for_each_intel_crtc(display->drm, crtc) { 438 if (crtc->cpu_fifo_underrun_disabled) 439 continue; 440 441 if (HAS_GMCH(display)) 442 i9xx_check_fifo_underruns(crtc); 443 else if (DISPLAY_VER(display) == 7) 444 ivb_check_fifo_underruns(crtc); 445 } 446 447 spin_unlock_irq(&dev_priv->irq_lock); 448 } 449 450 /** 451 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately 452 * @display: display device instance 453 * 454 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared 455 * error interrupt may have been disabled, and so PCH fifo underruns won't 456 * necessarily raise an interrupt. 457 */ 458 void intel_check_pch_fifo_underruns(struct intel_display *display) 459 { 460 struct drm_i915_private *dev_priv = to_i915(display->drm); 461 struct intel_crtc *crtc; 462 463 spin_lock_irq(&dev_priv->irq_lock); 464 465 for_each_intel_crtc(display->drm, crtc) { 466 if (crtc->pch_fifo_underrun_disabled) 467 continue; 468 469 if (HAS_PCH_CPT(dev_priv)) 470 cpt_check_pch_fifo_underruns(crtc); 471 } 472 473 spin_unlock_irq(&dev_priv->irq_lock); 474 } 475 476 void intel_init_fifo_underrun_reporting(struct intel_display *display, 477 struct intel_crtc *crtc, 478 bool enable) 479 { 480 struct drm_i915_private *i915 = to_i915(display->drm); 481 482 crtc->cpu_fifo_underrun_disabled = !enable; 483 484 /* 485 * We track the PCH trancoder underrun reporting state 486 * within the crtc. With crtc for pipe A housing the underrun 487 * reporting state for PCH transcoder A, crtc for pipe B housing 488 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 489 * and marking underrun reporting as disabled for the non-existing 490 * PCH transcoders B and C would prevent enabling the south 491 * error interrupt (see cpt_can_enable_serr_int()). 492 */ 493 if (intel_has_pch_trancoder(i915, crtc->pipe)) 494 crtc->pch_fifo_underrun_disabled = !enable; 495 } 496