1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * DRM driver for Ilitek ILI9486 panels
4 *
5 * Copyright 2020 Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>
6 */
7
8 #include <linux/backlight.h>
9 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/module.h>
12 #include <linux/property.h>
13 #include <linux/spi/spi.h>
14
15 #include <video/mipi_display.h>
16
17 #include <drm/clients/drm_client_setup.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_drv.h>
20 #include <drm/drm_fbdev_dma.h>
21 #include <drm/drm_gem_atomic_helper.h>
22 #include <drm/drm_gem_dma_helper.h>
23 #include <drm/drm_managed.h>
24 #include <drm/drm_mipi_dbi.h>
25 #include <drm/drm_modeset_helper.h>
26
27 #define ILI9486_ITFCTR1 0xb0
28 #define ILI9486_PWCTRL1 0xc2
29 #define ILI9486_VMCTRL1 0xc5
30 #define ILI9486_PGAMCTRL 0xe0
31 #define ILI9486_NGAMCTRL 0xe1
32 #define ILI9486_DGAMCTRL 0xe2
33 #define ILI9486_MADCTL_BGR BIT(3)
34 #define ILI9486_MADCTL_MV BIT(5)
35 #define ILI9486_MADCTL_MX BIT(6)
36 #define ILI9486_MADCTL_MY BIT(7)
37
38 /*
39 * The PiScreen/waveshare rpi-lcd-35 has a SPI to 16-bit parallel bus converter
40 * in front of the display controller. This means that 8-bit values have to be
41 * transferred as 16-bit.
42 */
waveshare_command(struct mipi_dbi * mipi,u8 * cmd,u8 * par,size_t num)43 static int waveshare_command(struct mipi_dbi *mipi, u8 *cmd, u8 *par,
44 size_t num)
45 {
46 struct spi_device *spi = mipi->spi;
47 unsigned int bpw = 8;
48 void *data = par;
49 u32 speed_hz;
50 int i, ret;
51 __be16 *buf;
52
53 buf = kmalloc(32 * sizeof(u16), GFP_KERNEL);
54 if (!buf)
55 return -ENOMEM;
56
57 /*
58 * The displays are Raspberry Pi HATs and connected to the 8-bit only
59 * SPI controller, so 16-bit command and parameters need byte swapping
60 * before being transferred as 8-bit on the big endian SPI bus.
61 */
62 buf[0] = cpu_to_be16(*cmd);
63 spi_bus_lock(spi->controller);
64 gpiod_set_value_cansleep(mipi->dc, 0);
65 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 2);
66 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, buf, 2);
67 spi_bus_unlock(spi->controller);
68 if (ret || !num)
69 goto free;
70
71 /* 8-bit configuration data, not 16-bit pixel data */
72 if (num <= 32) {
73 for (i = 0; i < num; i++)
74 buf[i] = cpu_to_be16(par[i]);
75 num *= 2;
76 data = buf;
77 }
78
79 /*
80 * Check whether pixel data bytes needs to be swapped or not
81 */
82 if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !mipi->swap_bytes)
83 bpw = 16;
84
85 spi_bus_lock(spi->controller);
86 gpiod_set_value_cansleep(mipi->dc, 1);
87 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
88 ret = mipi_dbi_spi_transfer(spi, speed_hz, bpw, data, num);
89 spi_bus_unlock(spi->controller);
90 free:
91 kfree(buf);
92
93 return ret;
94 }
95
waveshare_enable(struct drm_simple_display_pipe * pipe,struct drm_crtc_state * crtc_state,struct drm_plane_state * plane_state)96 static void waveshare_enable(struct drm_simple_display_pipe *pipe,
97 struct drm_crtc_state *crtc_state,
98 struct drm_plane_state *plane_state)
99 {
100 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
101 struct mipi_dbi *dbi = &dbidev->dbi;
102 u8 addr_mode;
103 int ret, idx;
104
105 if (!drm_dev_enter(pipe->crtc.dev, &idx))
106 return;
107
108 DRM_DEBUG_KMS("\n");
109
110 ret = mipi_dbi_poweron_conditional_reset(dbidev);
111 if (ret < 0)
112 goto out_exit;
113 if (ret == 1)
114 goto out_enable;
115
116 mipi_dbi_command(dbi, ILI9486_ITFCTR1);
117 mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
118 msleep(250);
119
120 mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 0x55);
121
122 mipi_dbi_command(dbi, ILI9486_PWCTRL1, 0x44);
123
124 mipi_dbi_command(dbi, ILI9486_VMCTRL1, 0x00, 0x00, 0x00, 0x00);
125
126 mipi_dbi_command(dbi, ILI9486_PGAMCTRL,
127 0x0F, 0x1F, 0x1C, 0x0C, 0x0F, 0x08, 0x48, 0x98,
128 0x37, 0x0A, 0x13, 0x04, 0x11, 0x0D, 0x0);
129 mipi_dbi_command(dbi, ILI9486_NGAMCTRL,
130 0x0F, 0x32, 0x2E, 0x0B, 0x0D, 0x05, 0x47, 0x75,
131 0x37, 0x06, 0x10, 0x03, 0x24, 0x20, 0x00);
132 mipi_dbi_command(dbi, ILI9486_DGAMCTRL,
133 0x0F, 0x32, 0x2E, 0x0B, 0x0D, 0x05, 0x47, 0x75,
134 0x37, 0x06, 0x10, 0x03, 0x24, 0x20, 0x00);
135
136 mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
137 msleep(100);
138
139 out_enable:
140 switch (dbidev->rotation) {
141 case 90:
142 addr_mode = ILI9486_MADCTL_MY;
143 break;
144 case 180:
145 addr_mode = ILI9486_MADCTL_MV;
146 break;
147 case 270:
148 addr_mode = ILI9486_MADCTL_MX;
149 break;
150 default:
151 addr_mode = ILI9486_MADCTL_MV | ILI9486_MADCTL_MY |
152 ILI9486_MADCTL_MX;
153 break;
154 }
155 addr_mode |= ILI9486_MADCTL_BGR;
156 mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
157 mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
158 out_exit:
159 drm_dev_exit(idx);
160 }
161
162 static const struct drm_simple_display_pipe_funcs waveshare_pipe_funcs = {
163 DRM_MIPI_DBI_SIMPLE_DISPLAY_PIPE_FUNCS(waveshare_enable),
164 };
165
166 static const struct drm_display_mode waveshare_mode = {
167 DRM_SIMPLE_MODE(480, 320, 73, 49),
168 };
169
170 DEFINE_DRM_GEM_DMA_FOPS(ili9486_fops);
171
172 static const struct drm_driver ili9486_driver = {
173 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
174 .fops = &ili9486_fops,
175 DRM_GEM_DMA_DRIVER_OPS_VMAP,
176 DRM_FBDEV_DMA_DRIVER_OPS,
177 .debugfs_init = mipi_dbi_debugfs_init,
178 .name = "ili9486",
179 .desc = "Ilitek ILI9486",
180 .major = 1,
181 .minor = 0,
182 };
183
184 static const struct of_device_id ili9486_of_match[] = {
185 { .compatible = "waveshare,rpi-lcd-35" },
186 { .compatible = "ozzmaker,piscreen" },
187 {},
188 };
189 MODULE_DEVICE_TABLE(of, ili9486_of_match);
190
191 static const struct spi_device_id ili9486_id[] = {
192 { "ili9486", 0 },
193 { "rpi-lcd-35", 0 },
194 { "piscreen", 0 },
195 { }
196 };
197 MODULE_DEVICE_TABLE(spi, ili9486_id);
198
ili9486_probe(struct spi_device * spi)199 static int ili9486_probe(struct spi_device *spi)
200 {
201 struct device *dev = &spi->dev;
202 struct mipi_dbi_dev *dbidev;
203 struct drm_device *drm;
204 struct mipi_dbi *dbi;
205 struct gpio_desc *dc;
206 u32 rotation = 0;
207 int ret;
208
209 dbidev = devm_drm_dev_alloc(dev, &ili9486_driver,
210 struct mipi_dbi_dev, drm);
211 if (IS_ERR(dbidev))
212 return PTR_ERR(dbidev);
213
214 dbi = &dbidev->dbi;
215 drm = &dbidev->drm;
216
217 dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
218 if (IS_ERR(dbi->reset))
219 return dev_err_probe(dev, PTR_ERR(dbi->reset), "Failed to get GPIO 'reset'\n");
220
221 dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
222 if (IS_ERR(dc))
223 return dev_err_probe(dev, PTR_ERR(dc), "Failed to get GPIO 'dc'\n");
224
225 dbidev->backlight = devm_of_find_backlight(dev);
226 if (IS_ERR(dbidev->backlight))
227 return PTR_ERR(dbidev->backlight);
228
229 device_property_read_u32(dev, "rotation", &rotation);
230
231 ret = mipi_dbi_spi_init(spi, dbi, dc);
232 if (ret)
233 return ret;
234
235 dbi->command = waveshare_command;
236 dbi->read_commands = NULL;
237
238 ret = mipi_dbi_dev_init(dbidev, &waveshare_pipe_funcs,
239 &waveshare_mode, rotation);
240 if (ret)
241 return ret;
242
243 drm_mode_config_reset(drm);
244
245 ret = drm_dev_register(drm, 0);
246 if (ret)
247 return ret;
248
249 spi_set_drvdata(spi, drm);
250
251 drm_client_setup(drm, NULL);
252
253 return 0;
254 }
255
ili9486_remove(struct spi_device * spi)256 static void ili9486_remove(struct spi_device *spi)
257 {
258 struct drm_device *drm = spi_get_drvdata(spi);
259
260 drm_dev_unplug(drm);
261 drm_atomic_helper_shutdown(drm);
262 }
263
ili9486_shutdown(struct spi_device * spi)264 static void ili9486_shutdown(struct spi_device *spi)
265 {
266 drm_atomic_helper_shutdown(spi_get_drvdata(spi));
267 }
268
269 static struct spi_driver ili9486_spi_driver = {
270 .driver = {
271 .name = "ili9486",
272 .of_match_table = ili9486_of_match,
273 },
274 .id_table = ili9486_id,
275 .probe = ili9486_probe,
276 .remove = ili9486_remove,
277 .shutdown = ili9486_shutdown,
278 };
279 module_spi_driver(ili9486_spi_driver);
280
281 MODULE_DESCRIPTION("Ilitek ILI9486 DRM driver");
282 MODULE_AUTHOR("Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>");
283 MODULE_LICENSE("GPL");
284