1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018 Intel Corporation */
3
4 #include <linux/pci.h>
5 #include <linux/delay.h>
6
7 #include "igc_mac.h"
8 #include "igc_hw.h"
9
10 /**
11 * igc_disable_pcie_master - Disables PCI-express master access
12 * @hw: pointer to the HW structure
13 *
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
16 * the master requests to be disabled.
17 *
18 * Disables PCI-Express master access and verifies there are no pending
19 * requests.
20 */
igc_disable_pcie_master(struct igc_hw * hw)21 s32 igc_disable_pcie_master(struct igc_hw *hw)
22 {
23 s32 timeout = MASTER_DISABLE_TIMEOUT;
24 s32 ret_val = 0;
25 u32 ctrl;
26
27 ctrl = rd32(IGC_CTRL);
28 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
29 wr32(IGC_CTRL, ctrl);
30
31 while (timeout) {
32 if (!(rd32(IGC_STATUS) &
33 IGC_STATUS_GIO_MASTER_ENABLE))
34 break;
35 usleep_range(2000, 3000);
36 timeout--;
37 }
38
39 if (!timeout) {
40 hw_dbg("Master requests are pending.\n");
41 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING;
42 goto out;
43 }
44
45 out:
46 return ret_val;
47 }
48
49 /**
50 * igc_init_rx_addrs - Initialize receive addresses
51 * @hw: pointer to the HW structure
52 * @rar_count: receive address registers
53 *
54 * Setup the receive address registers by setting the base receive address
55 * register to the devices MAC address and clearing all the other receive
56 * address registers to 0.
57 */
igc_init_rx_addrs(struct igc_hw * hw,u16 rar_count)58 void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count)
59 {
60 u8 mac_addr[ETH_ALEN] = {0};
61 u32 i;
62
63 /* Setup the receive address */
64 hw_dbg("Programming MAC Address into RAR[0]\n");
65
66 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
67
68 /* Zero out the other (rar_entry_count - 1) receive addresses */
69 hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
70 for (i = 1; i < rar_count; i++)
71 hw->mac.ops.rar_set(hw, mac_addr, i);
72 }
73
74 /**
75 * igc_set_fc_watermarks - Set flow control high/low watermarks
76 * @hw: pointer to the HW structure
77 *
78 * Sets the flow control high/low threshold (watermark) registers. If
79 * flow control XON frame transmission is enabled, then set XON frame
80 * transmission as well.
81 */
igc_set_fc_watermarks(struct igc_hw * hw)82 static s32 igc_set_fc_watermarks(struct igc_hw *hw)
83 {
84 u32 fcrtl = 0, fcrth = 0;
85
86 /* Set the flow control receive threshold registers. Normally,
87 * these registers will be set to a default threshold that may be
88 * adjusted later by the driver's runtime code. However, if the
89 * ability to transmit pause frames is not enabled, then these
90 * registers will be set to 0.
91 */
92 if (hw->fc.current_mode & igc_fc_tx_pause) {
93 /* We need to set up the Receive Threshold high and low water
94 * marks as well as (optionally) enabling the transmission of
95 * XON frames.
96 */
97 fcrtl = hw->fc.low_water;
98 if (hw->fc.send_xon)
99 fcrtl |= IGC_FCRTL_XONE;
100
101 fcrth = hw->fc.high_water;
102 }
103 wr32(IGC_FCRTL, fcrtl);
104 wr32(IGC_FCRTH, fcrth);
105
106 return 0;
107 }
108
109 /**
110 * igc_setup_link - Setup flow control and link settings
111 * @hw: pointer to the HW structure
112 *
113 * Determines which flow control settings to use, then configures flow
114 * control. Calls the appropriate media-specific link configuration
115 * function. Assuming the adapter has a valid link partner, a valid link
116 * should be established. Assumes the hardware has previously been reset
117 * and the transmitter and receiver are not enabled.
118 */
igc_setup_link(struct igc_hw * hw)119 s32 igc_setup_link(struct igc_hw *hw)
120 {
121 s32 ret_val = 0;
122
123 /* In the case of the phy reset being blocked, we already have a link.
124 * We do not need to set it up again.
125 */
126 if (igc_check_reset_block(hw))
127 goto out;
128
129 /* If requested flow control is set to default, set flow control
130 * to both 'rx' and 'tx' pause frames.
131 */
132 if (hw->fc.requested_mode == igc_fc_default)
133 hw->fc.requested_mode = igc_fc_full;
134
135 /* We want to save off the original Flow Control configuration just
136 * in case we get disconnected and then reconnected into a different
137 * hub or switch with different Flow Control capabilities.
138 */
139 hw->fc.current_mode = hw->fc.requested_mode;
140
141 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
142
143 /* Call the necessary media_type subroutine to configure the link. */
144 ret_val = hw->mac.ops.setup_physical_interface(hw);
145 if (ret_val)
146 goto out;
147
148 /* Initialize the flow control address, type, and PAUSE timer
149 * registers to their default values. This is done even if flow
150 * control is disabled, because it does not hurt anything to
151 * initialize these registers.
152 */
153 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
154 wr32(IGC_FCT, FLOW_CONTROL_TYPE);
155 wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
156 wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
157
158 wr32(IGC_FCTTV, hw->fc.pause_time);
159
160 ret_val = igc_set_fc_watermarks(hw);
161
162 out:
163 return ret_val;
164 }
165
166 /**
167 * igc_force_mac_fc - Force the MAC's flow control settings
168 * @hw: pointer to the HW structure
169 *
170 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
171 * device control register to reflect the adapter settings. TFCE and RFCE
172 * need to be explicitly set by software when a copper PHY is used because
173 * autonegotiation is managed by the PHY rather than the MAC. Software must
174 * also configure these bits when link is forced on a fiber connection.
175 */
igc_force_mac_fc(struct igc_hw * hw)176 s32 igc_force_mac_fc(struct igc_hw *hw)
177 {
178 s32 ret_val = 0;
179 u32 ctrl;
180
181 ctrl = rd32(IGC_CTRL);
182
183 /* Because we didn't get link via the internal auto-negotiation
184 * mechanism (we either forced link or we got link via PHY
185 * auto-neg), we have to manually enable/disable transmit an
186 * receive flow control.
187 *
188 * The "Case" statement below enables/disable flow control
189 * according to the "hw->fc.current_mode" parameter.
190 *
191 * The possible values of the "fc" parameter are:
192 * 0: Flow control is completely disabled
193 * 1: Rx flow control is enabled (we can receive pause
194 * frames but not send pause frames).
195 * 2: Tx flow control is enabled (we can send pause frames
196 * but we do not receive pause frames).
197 * 3: Both Rx and TX flow control (symmetric) is enabled.
198 * other: No other values should be possible at this point.
199 */
200 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
201
202 switch (hw->fc.current_mode) {
203 case igc_fc_none:
204 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
205 break;
206 case igc_fc_rx_pause:
207 ctrl &= (~IGC_CTRL_TFCE);
208 ctrl |= IGC_CTRL_RFCE;
209 break;
210 case igc_fc_tx_pause:
211 ctrl &= (~IGC_CTRL_RFCE);
212 ctrl |= IGC_CTRL_TFCE;
213 break;
214 case igc_fc_full:
215 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
216 break;
217 default:
218 hw_dbg("Flow control param set incorrectly\n");
219 ret_val = -IGC_ERR_CONFIG;
220 goto out;
221 }
222
223 wr32(IGC_CTRL, ctrl);
224
225 out:
226 return ret_val;
227 }
228
229 /**
230 * igc_clear_hw_cntrs_base - Clear base hardware counters
231 * @hw: pointer to the HW structure
232 *
233 * Clears the base hardware counters by reading the counter registers.
234 */
igc_clear_hw_cntrs_base(struct igc_hw * hw)235 void igc_clear_hw_cntrs_base(struct igc_hw *hw)
236 {
237 rd32(IGC_CRCERRS);
238 rd32(IGC_MPC);
239 rd32(IGC_SCC);
240 rd32(IGC_ECOL);
241 rd32(IGC_MCC);
242 rd32(IGC_LATECOL);
243 rd32(IGC_COLC);
244 rd32(IGC_RERC);
245 rd32(IGC_DC);
246 rd32(IGC_RLEC);
247 rd32(IGC_XONRXC);
248 rd32(IGC_XONTXC);
249 rd32(IGC_XOFFRXC);
250 rd32(IGC_XOFFTXC);
251 rd32(IGC_FCRUC);
252 rd32(IGC_GPRC);
253 rd32(IGC_BPRC);
254 rd32(IGC_MPRC);
255 rd32(IGC_GPTC);
256 rd32(IGC_GORCL);
257 rd32(IGC_GORCH);
258 rd32(IGC_GOTCL);
259 rd32(IGC_GOTCH);
260 rd32(IGC_RNBC);
261 rd32(IGC_RUC);
262 rd32(IGC_RFC);
263 rd32(IGC_ROC);
264 rd32(IGC_RJC);
265 rd32(IGC_TORL);
266 rd32(IGC_TORH);
267 rd32(IGC_TOTL);
268 rd32(IGC_TOTH);
269 rd32(IGC_TPR);
270 rd32(IGC_TPT);
271 rd32(IGC_MPTC);
272 rd32(IGC_BPTC);
273
274 rd32(IGC_PRC64);
275 rd32(IGC_PRC127);
276 rd32(IGC_PRC255);
277 rd32(IGC_PRC511);
278 rd32(IGC_PRC1023);
279 rd32(IGC_PRC1522);
280 rd32(IGC_PTC64);
281 rd32(IGC_PTC127);
282 rd32(IGC_PTC255);
283 rd32(IGC_PTC511);
284 rd32(IGC_PTC1023);
285 rd32(IGC_PTC1522);
286
287 rd32(IGC_ALGNERRC);
288 rd32(IGC_RXERRC);
289 rd32(IGC_TNCRS);
290 rd32(IGC_HTDPMC);
291 rd32(IGC_TSCTC);
292
293 rd32(IGC_MGTPRC);
294 rd32(IGC_MGTPDC);
295 rd32(IGC_MGTPTC);
296
297 rd32(IGC_IAC);
298
299 rd32(IGC_RPTHC);
300 rd32(IGC_TLPIC);
301 rd32(IGC_RLPIC);
302 rd32(IGC_HGPTC);
303 rd32(IGC_RXDMTC);
304 rd32(IGC_HGORCL);
305 rd32(IGC_HGORCH);
306 rd32(IGC_HGOTCL);
307 rd32(IGC_HGOTCH);
308 rd32(IGC_LENERRS);
309 }
310
311 /**
312 * igc_rar_set - Set receive address register
313 * @hw: pointer to the HW structure
314 * @addr: pointer to the receive address
315 * @index: receive address array register
316 *
317 * Sets the receive address array register at index to the address passed
318 * in by addr.
319 */
igc_rar_set(struct igc_hw * hw,u8 * addr,u32 index)320 void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index)
321 {
322 u32 rar_low, rar_high;
323
324 /* HW expects these in little endian so we reverse the byte order
325 * from network order (big endian) to little endian
326 */
327 rar_low = ((u32)addr[0] |
328 ((u32)addr[1] << 8) |
329 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
330
331 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
332
333 /* If MAC address zero, no need to set the AV bit */
334 if (rar_low || rar_high)
335 rar_high |= IGC_RAH_AV;
336
337 /* Some bridges will combine consecutive 32-bit writes into
338 * a single burst write, which will malfunction on some parts.
339 * The flushes avoid this.
340 */
341 wr32(IGC_RAL(index), rar_low);
342 wrfl();
343 wr32(IGC_RAH(index), rar_high);
344 wrfl();
345 }
346
347 /**
348 * igc_check_for_copper_link - Check for link (Copper)
349 * @hw: pointer to the HW structure
350 *
351 * Checks to see of the link status of the hardware has changed. If a
352 * change in link status has been detected, then we read the PHY registers
353 * to get the current speed/duplex if link exists.
354 */
igc_check_for_copper_link(struct igc_hw * hw)355 s32 igc_check_for_copper_link(struct igc_hw *hw)
356 {
357 struct igc_mac_info *mac = &hw->mac;
358 bool link = false;
359 s32 ret_val;
360
361 /* We only want to go out to the PHY registers to see if Auto-Neg
362 * has completed and/or if our link status has changed. The
363 * get_link_status flag is set upon receiving a Link Status
364 * Change or Rx Sequence Error interrupt.
365 */
366 if (!mac->get_link_status) {
367 ret_val = 0;
368 goto out;
369 }
370
371 /* First we want to see if the MII Status Register reports
372 * link. If so, then we want to get the current speed/duplex
373 * of the PHY.
374 */
375 ret_val = igc_phy_has_link(hw, 1, 0, &link);
376 if (ret_val)
377 goto out;
378
379 if (!link)
380 goto out; /* No link detected */
381
382 mac->get_link_status = false;
383
384 /* Check if there was DownShift, must be checked
385 * immediately after link-up
386 */
387 igc_check_downshift(hw);
388
389 /* Auto-Neg is enabled. Auto Speed Detection takes care
390 * of MAC speed/duplex configuration. So we only need to
391 * configure Collision Distance in the MAC.
392 */
393 igc_config_collision_dist(hw);
394
395 /* Configure Flow Control now that Auto-Neg has completed.
396 * First, we need to restore the desired flow control
397 * settings because we may have had to re-autoneg with a
398 * different link partner.
399 */
400 ret_val = igc_config_fc_after_link_up(hw);
401 if (ret_val)
402 hw_dbg("Error configuring flow control\n");
403
404 out:
405 /* Now that we are aware of our link settings, we can set the LTR
406 * thresholds.
407 */
408 ret_val = igc_set_ltr_i225(hw, link);
409
410 return ret_val;
411 }
412
413 /**
414 * igc_config_collision_dist - Configure collision distance
415 * @hw: pointer to the HW structure
416 *
417 * Configures the collision distance to the default value and is used
418 * during link setup. Currently no func pointer exists and all
419 * implementations are handled in the generic version of this function.
420 */
igc_config_collision_dist(struct igc_hw * hw)421 void igc_config_collision_dist(struct igc_hw *hw)
422 {
423 u32 tctl;
424
425 tctl = rd32(IGC_TCTL);
426
427 tctl &= ~IGC_TCTL_COLD;
428 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
429
430 wr32(IGC_TCTL, tctl);
431 wrfl();
432 }
433
434 /**
435 * igc_config_fc_after_link_up - Configures flow control after link
436 * @hw: pointer to the HW structure
437 *
438 * Checks the status of auto-negotiation after link up to ensure that the
439 * speed and duplex were not forced. If the link needed to be forced, then
440 * flow control needs to be forced also. If auto-negotiation is enabled
441 * then we configure flow control based on our link partner.
442 */
igc_config_fc_after_link_up(struct igc_hw * hw)443 s32 igc_config_fc_after_link_up(struct igc_hw *hw)
444 {
445 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
446 u16 speed, duplex;
447 s32 ret_val = 0;
448
449 /* Without autoneg, flow control capability is not exchanged with the
450 * link partner. IEEE 802.3 prohibits flow control in half-duplex mode.
451 */
452 if (!hw->mac.autoneg_enabled) {
453 if (hw->mac.forced_speed_duplex == IGC_FORCED_10H ||
454 hw->mac.forced_speed_duplex == IGC_FORCED_100H)
455 hw->fc.current_mode = igc_fc_none;
456
457 goto force_fc;
458 }
459
460 /* In auto-neg, we need to check and see if Auto-Neg has completed,
461 * and if so, how the PHY and link partner has flow control
462 * configured.
463 */
464
465 /* Read the MII Status Register and check to see if AutoNeg
466 * has completed. We read this twice because this reg has
467 * some "sticky" (latched) bits.
468 */
469 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
470 &mii_status_reg);
471 if (ret_val)
472 return ret_val;
473 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
474 &mii_status_reg);
475 if (ret_val)
476 return ret_val;
477
478 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
479 hw_dbg("Copper PHY and Auto Neg has not completed.\n");
480 return ret_val;
481 }
482
483 /* The AutoNeg process has completed, so we now need to
484 * read both the Auto Negotiation Advertisement
485 * Register (Address 4) and the Auto_Negotiation Base
486 * Page Ability Register (Address 5) to determine how
487 * flow control was negotiated.
488 */
489 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
490 &mii_nway_adv_reg);
491 if (ret_val)
492 return ret_val;
493 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
494 &mii_nway_lp_ability_reg);
495 if (ret_val)
496 return ret_val;
497 /* Two bits in the Auto Negotiation Advertisement Register
498 * (Address 4) and two bits in the Auto Negotiation Base
499 * Page Ability Register (Address 5) determine flow control
500 * for both the PHY and the link partner. The following
501 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
502 * 1999, describes these PAUSE resolution bits and how flow
503 * control is determined based upon these settings.
504 * NOTE: DC = Don't Care
505 *
506 * LOCAL DEVICE | LINK PARTNER
507 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
508 *-------|---------|-------|---------|--------------------
509 * 0 | 0 | DC | DC | igc_fc_none
510 * 0 | 1 | 0 | DC | igc_fc_none
511 * 0 | 1 | 1 | 0 | igc_fc_none
512 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
513 * 1 | 0 | 0 | DC | igc_fc_none
514 * 1 | DC | 1 | DC | igc_fc_full
515 * 1 | 1 | 0 | 0 | igc_fc_none
516 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
517 *
518 * Are both PAUSE bits set to 1? If so, this implies
519 * Symmetric Flow Control is enabled at both ends. The
520 * ASM_DIR bits are irrelevant per the spec.
521 *
522 * For Symmetric Flow Control:
523 *
524 * LOCAL DEVICE | LINK PARTNER
525 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
526 *-------|---------|-------|---------|--------------------
527 * 1 | DC | 1 | DC | IGC_fc_full
528 *
529 */
530 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
531 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
532 /* Now we need to check if the user selected RX ONLY
533 * of pause frames. In this case, we had to advertise
534 * FULL flow control because we could not advertise RX
535 * ONLY. Hence, we must now check to see if we need to
536 * turn OFF the TRANSMISSION of PAUSE frames.
537 */
538 if (hw->fc.requested_mode == igc_fc_full) {
539 hw->fc.current_mode = igc_fc_full;
540 hw_dbg("Flow Control = FULL.\n");
541 } else {
542 hw->fc.current_mode = igc_fc_rx_pause;
543 hw_dbg("Flow Control = RX PAUSE frames only.\n");
544 }
545 }
546
547 /* For receiving PAUSE frames ONLY.
548 *
549 * LOCAL DEVICE | LINK PARTNER
550 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
551 *-------|---------|-------|---------|--------------------
552 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
553 */
554 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
555 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
556 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
557 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
558 hw->fc.current_mode = igc_fc_tx_pause;
559 hw_dbg("Flow Control = TX PAUSE frames only.\n");
560 }
561 /* For transmitting PAUSE frames ONLY.
562 *
563 * LOCAL DEVICE | LINK PARTNER
564 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
565 *-------|---------|-------|---------|--------------------
566 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
567 */
568 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
569 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
570 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
571 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
572 hw->fc.current_mode = igc_fc_rx_pause;
573 hw_dbg("Flow Control = RX PAUSE frames only.\n");
574 }
575 /* Per the IEEE spec, at this point flow control should be
576 * disabled. However, we want to consider that we could
577 * be connected to a legacy switch that doesn't advertise
578 * desired flow control, but can be forced on the link
579 * partner. So if we advertised no flow control, that is
580 * what we will resolve to. If we advertised some kind of
581 * receive capability (Rx Pause Only or Full Flow Control)
582 * and the link partner advertised none, we will configure
583 * ourselves to enable Rx Flow Control only. We can do
584 * this safely for two reasons: If the link partner really
585 * didn't want flow control enabled, and we enable Rx, no
586 * harm done since we won't be receiving any PAUSE frames
587 * anyway. If the intent on the link partner was to have
588 * flow control enabled, then by us enabling RX only, we
589 * can at least receive pause frames and process them.
590 * This is a good idea because in most cases, since we are
591 * predominantly a server NIC, more times than not we will
592 * be asked to delay transmission of packets than asking
593 * our link partner to pause transmission of frames.
594 */
595 else if ((hw->fc.requested_mode == igc_fc_none) ||
596 (hw->fc.requested_mode == igc_fc_tx_pause) ||
597 (hw->fc.strict_ieee)) {
598 hw->fc.current_mode = igc_fc_none;
599 hw_dbg("Flow Control = NONE.\n");
600 } else {
601 hw->fc.current_mode = igc_fc_rx_pause;
602 hw_dbg("Flow Control = RX PAUSE frames only.\n");
603 }
604
605 /* Now we need to do one last check... If we auto-
606 * negotiated to HALF DUPLEX, flow control should not be
607 * enabled per IEEE 802.3 spec.
608 */
609 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
610 if (ret_val) {
611 hw_dbg("Error getting link speed and duplex\n");
612 return ret_val;
613 }
614
615 if (duplex == HALF_DUPLEX)
616 hw->fc.current_mode = igc_fc_none;
617
618 /* Now we call a subroutine to actually force the MAC
619 * controller to use the correct flow control settings.
620 */
621 force_fc:
622 ret_val = igc_force_mac_fc(hw);
623 if (ret_val) {
624 hw_dbg("Error forcing flow control settings\n");
625 return ret_val;
626 }
627
628 return ret_val;
629 }
630
631 /**
632 * igc_get_auto_rd_done - Check for auto read completion
633 * @hw: pointer to the HW structure
634 *
635 * Check EEPROM for Auto Read done bit.
636 */
igc_get_auto_rd_done(struct igc_hw * hw)637 s32 igc_get_auto_rd_done(struct igc_hw *hw)
638 {
639 s32 ret_val = 0;
640 s32 i = 0;
641
642 while (i < AUTO_READ_DONE_TIMEOUT) {
643 if (rd32(IGC_EECD) & IGC_EECD_AUTO_RD)
644 break;
645 usleep_range(1000, 2000);
646 i++;
647 }
648
649 if (i == AUTO_READ_DONE_TIMEOUT) {
650 hw_dbg("Auto read by HW from NVM has not completed.\n");
651 ret_val = -IGC_ERR_RESET;
652 goto out;
653 }
654
655 out:
656 return ret_val;
657 }
658
659 /**
660 * igc_get_speed_and_duplex_copper - Retrieve current speed/duplex
661 * @hw: pointer to the HW structure
662 * @speed: stores the current speed
663 * @duplex: stores the current duplex
664 *
665 * Read the status register for the current speed/duplex and store the current
666 * speed and duplex for copper connections.
667 */
igc_get_speed_and_duplex_copper(struct igc_hw * hw,u16 * speed,u16 * duplex)668 s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed,
669 u16 *duplex)
670 {
671 u32 status;
672
673 status = rd32(IGC_STATUS);
674 if (status & IGC_STATUS_SPEED_1000) {
675 /* For I225, STATUS will indicate 1G speed in both 1 Gbps
676 * and 2.5 Gbps link modes. An additional bit is used
677 * to differentiate between 1 Gbps and 2.5 Gbps.
678 */
679 if (hw->mac.type == igc_i225 &&
680 (status & IGC_STATUS_SPEED_2500)) {
681 *speed = SPEED_2500;
682 hw_dbg("2500 Mbs, ");
683 } else {
684 *speed = SPEED_1000;
685 hw_dbg("1000 Mbs, ");
686 }
687 } else if (status & IGC_STATUS_SPEED_100) {
688 *speed = SPEED_100;
689 hw_dbg("100 Mbs, ");
690 } else {
691 *speed = SPEED_10;
692 hw_dbg("10 Mbs, ");
693 }
694
695 if (status & IGC_STATUS_FD) {
696 *duplex = FULL_DUPLEX;
697 hw_dbg("Full Duplex\n");
698 } else {
699 *duplex = HALF_DUPLEX;
700 hw_dbg("Half Duplex\n");
701 }
702
703 return 0;
704 }
705
706 /**
707 * igc_put_hw_semaphore - Release hardware semaphore
708 * @hw: pointer to the HW structure
709 *
710 * Release hardware semaphore used to access the PHY or NVM
711 */
igc_put_hw_semaphore(struct igc_hw * hw)712 void igc_put_hw_semaphore(struct igc_hw *hw)
713 {
714 u32 swsm;
715
716 swsm = rd32(IGC_SWSM);
717
718 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
719
720 wr32(IGC_SWSM, swsm);
721 }
722
723 /**
724 * igc_enable_mng_pass_thru - Enable processing of ARP's
725 * @hw: pointer to the HW structure
726 *
727 * Verifies the hardware needs to leave interface enabled so that frames can
728 * be directed to and from the management interface.
729 */
igc_enable_mng_pass_thru(struct igc_hw * hw)730 bool igc_enable_mng_pass_thru(struct igc_hw *hw)
731 {
732 bool ret_val = false;
733 u32 fwsm, factps;
734 u32 manc;
735
736 if (!hw->mac.asf_firmware_present)
737 goto out;
738
739 manc = rd32(IGC_MANC);
740
741 if (!(manc & IGC_MANC_RCV_TCO_EN))
742 goto out;
743
744 if (hw->mac.arc_subsystem_valid) {
745 fwsm = rd32(IGC_FWSM);
746 factps = rd32(IGC_FACTPS);
747
748 if (!(factps & IGC_FACTPS_MNGCG) &&
749 ((fwsm & IGC_FWSM_MODE_MASK) ==
750 (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT))) {
751 ret_val = true;
752 goto out;
753 }
754 } else {
755 if ((manc & IGC_MANC_SMBUS_EN) &&
756 !(manc & IGC_MANC_ASF_EN)) {
757 ret_val = true;
758 goto out;
759 }
760 }
761
762 out:
763 return ret_val;
764 }
765
766 /**
767 * igc_hash_mc_addr - Generate a multicast hash value
768 * @hw: pointer to the HW structure
769 * @mc_addr: pointer to a multicast address
770 *
771 * Generates a multicast address hash value which is used to determine
772 * the multicast filter table array address and new table value. See
773 * igc_mta_set()
774 **/
igc_hash_mc_addr(struct igc_hw * hw,u8 * mc_addr)775 static u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr)
776 {
777 u32 hash_value, hash_mask;
778 u8 bit_shift = 0;
779
780 /* Register count multiplied by bits per register */
781 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
782
783 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
784 * where 0xFF would still fall within the hash mask.
785 */
786 while (hash_mask >> bit_shift != 0xFF)
787 bit_shift++;
788
789 /* The portion of the address that is used for the hash table
790 * is determined by the mc_filter_type setting.
791 * The algorithm is such that there is a total of 8 bits of shifting.
792 * The bit_shift for a mc_filter_type of 0 represents the number of
793 * left-shifts where the MSB of mc_addr[5] would still fall within
794 * the hash_mask. Case 0 does this exactly. Since there are a total
795 * of 8 bits of shifting, then mc_addr[4] will shift right the
796 * remaining number of bits. Thus 8 - bit_shift. The rest of the
797 * cases are a variation of this algorithm...essentially raising the
798 * number of bits to shift mc_addr[5] left, while still keeping the
799 * 8-bit shifting total.
800 *
801 * For example, given the following Destination MAC Address and an
802 * MTA register count of 128 (thus a 4096-bit vector and 0xFFF mask),
803 * we can see that the bit_shift for case 0 is 4. These are the hash
804 * values resulting from each mc_filter_type...
805 * [0] [1] [2] [3] [4] [5]
806 * 01 AA 00 12 34 56
807 * LSB MSB
808 *
809 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
810 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
811 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
812 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
813 */
814 switch (hw->mac.mc_filter_type) {
815 default:
816 case 0:
817 break;
818 case 1:
819 bit_shift += 1;
820 break;
821 case 2:
822 bit_shift += 2;
823 break;
824 case 3:
825 bit_shift += 4;
826 break;
827 }
828
829 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
830 (((u16)mc_addr[5]) << bit_shift)));
831
832 return hash_value;
833 }
834
835 /**
836 * igc_update_mc_addr_list - Update Multicast addresses
837 * @hw: pointer to the HW structure
838 * @mc_addr_list: array of multicast addresses to program
839 * @mc_addr_count: number of multicast addresses to program
840 *
841 * Updates entire Multicast Table Array.
842 * The caller must have a packed mc_addr_list of multicast addresses.
843 **/
igc_update_mc_addr_list(struct igc_hw * hw,u8 * mc_addr_list,u32 mc_addr_count)844 void igc_update_mc_addr_list(struct igc_hw *hw,
845 u8 *mc_addr_list, u32 mc_addr_count)
846 {
847 u32 hash_value, hash_bit, hash_reg;
848 int i;
849
850 /* clear mta_shadow */
851 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
852
853 /* update mta_shadow from mc_addr_list */
854 for (i = 0; (u32)i < mc_addr_count; i++) {
855 hash_value = igc_hash_mc_addr(hw, mc_addr_list);
856
857 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
858 hash_bit = hash_value & 0x1F;
859
860 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
861 mc_addr_list += ETH_ALEN;
862 }
863
864 /* replace the entire MTA table */
865 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
866 array_wr32(IGC_MTA, i, hw->mac.mta_shadow[i]);
867 wrfl();
868 }
869