1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 Intel Corporation */
3
4 #include "igc.h"
5
6 #include <linux/module.h>
7 #include <linux/device.h>
8 #include <linux/pci.h>
9 #include <linux/ptp_classify.h>
10 #include <linux/clocksource.h>
11 #include <linux/ktime.h>
12 #include <linux/delay.h>
13 #include <linux/iopoll.h>
14 #include <net/xdp_sock_drv.h>
15
16 #define INCVALUE_MASK 0x7fffffff
17 #define ISGN 0x80000000
18
19 #define IGC_PTP_TX_TIMEOUT (HZ * 15)
20
21 #define IGC_PTM_STAT_SLEEP 2
22 #define IGC_PTM_STAT_TIMEOUT 100
23
24 /* SYSTIM read access for I225 */
igc_ptp_read(struct igc_adapter * adapter,struct timespec64 * ts)25 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts)
26 {
27 struct igc_hw *hw = &adapter->hw;
28 u32 sec, nsec;
29
30 /* The timestamp is latched when SYSTIML is read. */
31 nsec = rd32(IGC_SYSTIML);
32 sec = rd32(IGC_SYSTIMH);
33
34 ts->tv_sec = sec;
35 ts->tv_nsec = nsec;
36 }
37
igc_ptp_write_i225(struct igc_adapter * adapter,const struct timespec64 * ts)38 static void igc_ptp_write_i225(struct igc_adapter *adapter,
39 const struct timespec64 *ts)
40 {
41 struct igc_hw *hw = &adapter->hw;
42
43 wr32(IGC_SYSTIML, ts->tv_nsec);
44 wr32(IGC_SYSTIMH, ts->tv_sec);
45 }
46
igc_ptp_adjfine_i225(struct ptp_clock_info * ptp,long scaled_ppm)47 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)
48 {
49 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
50 ptp_caps);
51 struct igc_hw *hw = &igc->hw;
52 int neg_adj = 0;
53 u64 rate;
54 u32 inca;
55
56 if (scaled_ppm < 0) {
57 neg_adj = 1;
58 scaled_ppm = -scaled_ppm;
59 }
60 rate = scaled_ppm;
61 rate <<= 14;
62 rate = div_u64(rate, 78125);
63
64 inca = rate & INCVALUE_MASK;
65 if (neg_adj)
66 inca |= ISGN;
67
68 wr32(IGC_TIMINCA, inca);
69
70 return 0;
71 }
72
igc_ptp_adjtime_i225(struct ptp_clock_info * ptp,s64 delta)73 static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta)
74 {
75 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
76 ptp_caps);
77 struct timespec64 now, then = ns_to_timespec64(delta);
78 unsigned long flags;
79
80 spin_lock_irqsave(&igc->tmreg_lock, flags);
81
82 igc_ptp_read(igc, &now);
83 now = timespec64_add(now, then);
84 igc_ptp_write_i225(igc, (const struct timespec64 *)&now);
85
86 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
87
88 return 0;
89 }
90
igc_ptp_gettimex64_i225(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)91 static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp,
92 struct timespec64 *ts,
93 struct ptp_system_timestamp *sts)
94 {
95 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
96 ptp_caps);
97 struct igc_hw *hw = &igc->hw;
98 unsigned long flags;
99
100 spin_lock_irqsave(&igc->tmreg_lock, flags);
101
102 ptp_read_system_prets(sts);
103 ts->tv_nsec = rd32(IGC_SYSTIML);
104 ts->tv_sec = rd32(IGC_SYSTIMH);
105 ptp_read_system_postts(sts);
106
107 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
108
109 return 0;
110 }
111
igc_ptp_settime_i225(struct ptp_clock_info * ptp,const struct timespec64 * ts)112 static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
113 const struct timespec64 *ts)
114 {
115 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
116 ptp_caps);
117 unsigned long flags;
118
119 spin_lock_irqsave(&igc->tmreg_lock, flags);
120
121 igc_ptp_write_i225(igc, ts);
122
123 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
124
125 return 0;
126 }
127
igc_pin_direction(int pin,int input,u32 * ctrl,u32 * ctrl_ext)128 static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
129 {
130 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
131 static const u32 mask[IGC_N_SDP] = {
132 IGC_CTRL_SDP0_DIR,
133 IGC_CTRL_SDP1_DIR,
134 IGC_CTRL_EXT_SDP2_DIR,
135 IGC_CTRL_EXT_SDP3_DIR,
136 };
137
138 if (input)
139 *ptr &= ~mask[pin];
140 else
141 *ptr |= mask[pin];
142 }
143
igc_pin_perout(struct igc_adapter * igc,int chan,int pin,int freq)144 static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq)
145 {
146 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
147 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
148 };
149 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
150 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
151 };
152 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
153 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
154 };
155 static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = {
156 IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0,
157 IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0,
158 };
159 static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = {
160 IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1,
161 IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1,
162 };
163 static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = {
164 IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0,
165 IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0,
166 };
167 static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = {
168 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
169 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
170 };
171 static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = {
172 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
173 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
174 };
175 struct igc_hw *hw = &igc->hw;
176 u32 ctrl, ctrl_ext, tssdp = 0;
177
178 ctrl = rd32(IGC_CTRL);
179 ctrl_ext = rd32(IGC_CTRL_EXT);
180 tssdp = rd32(IGC_TSSDP);
181
182 igc_pin_direction(pin, 0, &ctrl, &ctrl_ext);
183
184 /* Make sure this pin is not enabled as an input. */
185 if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin])
186 tssdp &= ~IGC_AUX0_TS_SDP_EN;
187
188 if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin])
189 tssdp &= ~IGC_AUX1_TS_SDP_EN;
190
191 tssdp &= ~igc_ts_sdp_sel_clr[pin];
192 if (freq) {
193 if (chan == 1)
194 tssdp |= igc_ts_sdp_sel_fc1[pin];
195 else
196 tssdp |= igc_ts_sdp_sel_fc0[pin];
197 } else {
198 if (chan == 1)
199 tssdp |= igc_ts_sdp_sel_tt1[pin];
200 else
201 tssdp |= igc_ts_sdp_sel_tt0[pin];
202 }
203 tssdp |= igc_ts_sdp_en[pin];
204
205 wr32(IGC_TSSDP, tssdp);
206 wr32(IGC_CTRL, ctrl);
207 wr32(IGC_CTRL_EXT, ctrl_ext);
208 }
209
igc_pin_extts(struct igc_adapter * igc,int chan,int pin)210 static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin)
211 {
212 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
213 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
214 };
215 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
216 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
217 };
218 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
219 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
220 };
221 struct igc_hw *hw = &igc->hw;
222 u32 ctrl, ctrl_ext, tssdp = 0;
223
224 ctrl = rd32(IGC_CTRL);
225 ctrl_ext = rd32(IGC_CTRL_EXT);
226 tssdp = rd32(IGC_TSSDP);
227
228 igc_pin_direction(pin, 1, &ctrl, &ctrl_ext);
229
230 /* Make sure this pin is not enabled as an output. */
231 tssdp &= ~igc_ts_sdp_en[pin];
232
233 if (chan == 1) {
234 tssdp &= ~IGC_AUX1_SEL_SDP3;
235 tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN;
236 } else {
237 tssdp &= ~IGC_AUX0_SEL_SDP3;
238 tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN;
239 }
240
241 wr32(IGC_TSSDP, tssdp);
242 wr32(IGC_CTRL, ctrl);
243 wr32(IGC_CTRL_EXT, ctrl_ext);
244 }
245
igc_ptp_feature_enable_i225(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)246 static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
247 struct ptp_clock_request *rq, int on)
248 {
249 struct igc_adapter *igc =
250 container_of(ptp, struct igc_adapter, ptp_caps);
251 struct igc_hw *hw = &igc->hw;
252 unsigned long flags;
253 struct timespec64 ts;
254 int use_freq = 0, pin = -1;
255 u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
256 s64 ns;
257
258 switch (rq->type) {
259 case PTP_CLK_REQ_EXTTS:
260 /* Reject requests failing to enable both edges. */
261 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
262 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
263 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
264 return -EOPNOTSUPP;
265
266 if (on) {
267 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_EXTTS,
268 rq->extts.index);
269 if (pin < 0)
270 return -EBUSY;
271 }
272 if (rq->extts.index == 1) {
273 tsauxc_mask = IGC_TSAUXC_EN_TS1;
274 tsim_mask = IGC_TSICR_AUTT1;
275 } else {
276 tsauxc_mask = IGC_TSAUXC_EN_TS0;
277 tsim_mask = IGC_TSICR_AUTT0;
278 }
279 spin_lock_irqsave(&igc->tmreg_lock, flags);
280 tsauxc = rd32(IGC_TSAUXC);
281 tsim = rd32(IGC_TSIM);
282 if (on) {
283 igc_pin_extts(igc, rq->extts.index, pin);
284 tsauxc |= tsauxc_mask;
285 tsim |= tsim_mask;
286 } else {
287 tsauxc &= ~tsauxc_mask;
288 tsim &= ~tsim_mask;
289 }
290 wr32(IGC_TSAUXC, tsauxc);
291 wr32(IGC_TSIM, tsim);
292 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
293 return 0;
294
295 case PTP_CLK_REQ_PEROUT:
296 if (on) {
297 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_PEROUT,
298 rq->perout.index);
299 if (pin < 0)
300 return -EBUSY;
301 }
302 ts.tv_sec = rq->perout.period.sec;
303 ts.tv_nsec = rq->perout.period.nsec;
304 ns = timespec64_to_ns(&ts);
305 ns = ns >> 1;
306 if (on && (ns <= 70000000LL || ns == 125000000LL ||
307 ns == 250000000LL || ns == 500000000LL)) {
308 if (ns < 8LL)
309 return -EINVAL;
310 use_freq = 1;
311 }
312 ts = ns_to_timespec64(ns);
313 if (rq->perout.index == 1) {
314 if (use_freq) {
315 tsauxc_mask = IGC_TSAUXC_EN_CLK1 | IGC_TSAUXC_ST1;
316 tsim_mask = 0;
317 } else {
318 tsauxc_mask = IGC_TSAUXC_EN_TT1;
319 tsim_mask = IGC_TSICR_TT1;
320 }
321 trgttiml = IGC_TRGTTIML1;
322 trgttimh = IGC_TRGTTIMH1;
323 freqout = IGC_FREQOUT1;
324 } else {
325 if (use_freq) {
326 tsauxc_mask = IGC_TSAUXC_EN_CLK0 | IGC_TSAUXC_ST0;
327 tsim_mask = 0;
328 } else {
329 tsauxc_mask = IGC_TSAUXC_EN_TT0;
330 tsim_mask = IGC_TSICR_TT0;
331 }
332 trgttiml = IGC_TRGTTIML0;
333 trgttimh = IGC_TRGTTIMH0;
334 freqout = IGC_FREQOUT0;
335 }
336 spin_lock_irqsave(&igc->tmreg_lock, flags);
337 tsauxc = rd32(IGC_TSAUXC);
338 tsim = rd32(IGC_TSIM);
339 if (rq->perout.index == 1) {
340 tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1 |
341 IGC_TSAUXC_ST1);
342 tsim &= ~IGC_TSICR_TT1;
343 } else {
344 tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0 |
345 IGC_TSAUXC_ST0);
346 tsim &= ~IGC_TSICR_TT0;
347 }
348 if (on) {
349 struct timespec64 safe_start;
350 int i = rq->perout.index;
351
352 igc_pin_perout(igc, i, pin, use_freq);
353 igc_ptp_read(igc, &safe_start);
354
355 /* PPS output start time is triggered by Target time(TT)
356 * register. Programming any past time value into TT
357 * register will cause PPS to never start. Need to make
358 * sure we program the TT register a time ahead in
359 * future. There isn't a stringent need to fire PPS out
360 * right away. Adding +2 seconds should take care of
361 * corner cases. Let's say if the SYSTIML is close to
362 * wrap up and the timer keeps ticking as we program the
363 * register, adding +2seconds is safe bet.
364 */
365 safe_start.tv_sec += 2;
366
367 if (rq->perout.start.sec < safe_start.tv_sec)
368 igc->perout[i].start.tv_sec = safe_start.tv_sec;
369 else
370 igc->perout[i].start.tv_sec = rq->perout.start.sec;
371 igc->perout[i].start.tv_nsec = rq->perout.start.nsec;
372 igc->perout[i].period.tv_sec = ts.tv_sec;
373 igc->perout[i].period.tv_nsec = ts.tv_nsec;
374 wr32(trgttimh, (u32)igc->perout[i].start.tv_sec);
375 /* For now, always select timer 0 as source. */
376 wr32(trgttiml, (u32)(igc->perout[i].start.tv_nsec |
377 IGC_TT_IO_TIMER_SEL_SYSTIM0));
378 if (use_freq)
379 wr32(freqout, ns);
380 tsauxc |= tsauxc_mask;
381 tsim |= tsim_mask;
382 }
383 wr32(IGC_TSAUXC, tsauxc);
384 wr32(IGC_TSIM, tsim);
385 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
386 return 0;
387
388 case PTP_CLK_REQ_PPS:
389 spin_lock_irqsave(&igc->tmreg_lock, flags);
390 tsim = rd32(IGC_TSIM);
391 if (on)
392 tsim |= IGC_TSICR_SYS_WRAP;
393 else
394 tsim &= ~IGC_TSICR_SYS_WRAP;
395 igc->pps_sys_wrap_on = on;
396 wr32(IGC_TSIM, tsim);
397 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
398 return 0;
399
400 default:
401 break;
402 }
403
404 return -EOPNOTSUPP;
405 }
406
igc_ptp_verify_pin(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)407 static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
408 enum ptp_pin_function func, unsigned int chan)
409 {
410 switch (func) {
411 case PTP_PF_NONE:
412 case PTP_PF_EXTTS:
413 case PTP_PF_PEROUT:
414 break;
415 case PTP_PF_PHYSYNC:
416 return -1;
417 }
418 return 0;
419 }
420
421 /**
422 * igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
423 * @adapter: board private structure
424 * @hwtstamps: timestamp structure to update
425 * @systim: unsigned 64bit system time value
426 *
427 * We need to convert the system time value stored in the RX/TXSTMP registers
428 * into a hwtstamp which can be used by the upper level timestamping functions.
429 *
430 * Returns 0 on success.
431 **/
igc_ptp_systim_to_hwtstamp(struct igc_adapter * adapter,struct skb_shared_hwtstamps * hwtstamps,u64 systim)432 static int igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,
433 struct skb_shared_hwtstamps *hwtstamps,
434 u64 systim)
435 {
436 switch (adapter->hw.mac.type) {
437 case igc_i225:
438 memset(hwtstamps, 0, sizeof(*hwtstamps));
439 /* Upper 32 bits contain s, lower 32 bits contain ns. */
440 hwtstamps->hwtstamp = ktime_set(systim >> 32,
441 systim & 0xFFFFFFFF);
442 break;
443 default:
444 return -EINVAL;
445 }
446 return 0;
447 }
448
449 /**
450 * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer
451 * @adapter: Pointer to adapter the packet buffer belongs to
452 * @buf: Pointer to start of timestamp in HW format (2 32-bit words)
453 *
454 * This function retrieves and converts the timestamp stored at @buf
455 * to ktime_t, adjusting for hardware latencies.
456 *
457 * Returns timestamp value.
458 */
igc_ptp_rx_pktstamp(struct igc_adapter * adapter,__le32 * buf)459 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf)
460 {
461 ktime_t timestamp;
462 u32 secs, nsecs;
463 int adjust;
464
465 nsecs = le32_to_cpu(buf[0]);
466 secs = le32_to_cpu(buf[1]);
467
468 timestamp = ktime_set(secs, nsecs);
469
470 /* Adjust timestamp for the RX latency based on link speed */
471 switch (adapter->link_speed) {
472 case SPEED_10:
473 adjust = IGC_I225_RX_LATENCY_10;
474 break;
475 case SPEED_100:
476 adjust = IGC_I225_RX_LATENCY_100;
477 break;
478 case SPEED_1000:
479 adjust = IGC_I225_RX_LATENCY_1000;
480 break;
481 case SPEED_2500:
482 adjust = IGC_I225_RX_LATENCY_2500;
483 break;
484 default:
485 adjust = 0;
486 netdev_warn_once(adapter->netdev, "Imprecise timestamp\n");
487 break;
488 }
489
490 return ktime_sub_ns(timestamp, adjust);
491 }
492
igc_ptp_disable_rx_timestamp(struct igc_adapter * adapter)493 static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter)
494 {
495 struct igc_hw *hw = &adapter->hw;
496 u32 val;
497 int i;
498
499 wr32(IGC_TSYNCRXCTL, 0);
500
501 for (i = 0; i < adapter->num_rx_queues; i++) {
502 val = rd32(IGC_SRRCTL(i));
503 val &= ~IGC_SRRCTL_TIMESTAMP;
504 wr32(IGC_SRRCTL(i), val);
505 }
506
507 val = rd32(IGC_RXPBS);
508 val &= ~IGC_RXPBS_CFG_TS_EN;
509 wr32(IGC_RXPBS, val);
510 }
511
igc_ptp_enable_rx_timestamp(struct igc_adapter * adapter)512 static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter)
513 {
514 struct igc_hw *hw = &adapter->hw;
515 u32 val;
516 int i;
517
518 val = rd32(IGC_RXPBS);
519 val |= IGC_RXPBS_CFG_TS_EN;
520 wr32(IGC_RXPBS, val);
521
522 for (i = 0; i < adapter->num_rx_queues; i++) {
523 val = rd32(IGC_SRRCTL(i));
524 /* Enable retrieving timestamps from timer 0, the
525 * "adjustable clock" and timer 1 the "free running
526 * clock".
527 */
528 val |= IGC_SRRCTL_TIMER1SEL(1) | IGC_SRRCTL_TIMER0SEL(0) |
529 IGC_SRRCTL_TIMESTAMP;
530 wr32(IGC_SRRCTL(i), val);
531 }
532
533 val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL |
534 IGC_TSYNCRXCTL_RXSYNSIG;
535 wr32(IGC_TSYNCRXCTL, val);
536 }
537
igc_ptp_free_tx_buffer(struct igc_adapter * adapter,struct igc_tx_timestamp_request * tstamp)538 static void igc_ptp_free_tx_buffer(struct igc_adapter *adapter,
539 struct igc_tx_timestamp_request *tstamp)
540 {
541 if (tstamp->buffer_type == IGC_TX_BUFFER_TYPE_XSK) {
542 /* Release the transmit completion */
543 tstamp->xsk_tx_buffer->xsk_pending_ts = false;
544
545 /* Note: tstamp->skb and tstamp->xsk_tx_buffer are in union.
546 * By setting tstamp->xsk_tx_buffer to NULL, tstamp->skb will
547 * become NULL as well.
548 */
549 tstamp->xsk_tx_buffer = NULL;
550 tstamp->buffer_type = 0;
551
552 /* Trigger txrx interrupt for transmit completion */
553 igc_xsk_wakeup(adapter->netdev, tstamp->xsk_queue_index, 0);
554
555 return;
556 }
557
558 dev_kfree_skb_any(tstamp->skb);
559 tstamp->skb = NULL;
560 }
561
igc_ptp_clear_tx_tstamp(struct igc_adapter * adapter)562 static void igc_ptp_clear_tx_tstamp(struct igc_adapter *adapter)
563 {
564 unsigned long flags;
565 int i;
566
567 spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
568
569 for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
570 struct igc_tx_timestamp_request *tstamp = &adapter->tx_tstamp[i];
571
572 if (tstamp->skb)
573 igc_ptp_free_tx_buffer(adapter, tstamp);
574 }
575
576 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);
577 }
578
igc_ptp_disable_tx_timestamp(struct igc_adapter * adapter)579 static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter)
580 {
581 struct igc_hw *hw = &adapter->hw;
582 int i;
583
584 /* Clear the flags first to avoid new packets to be enqueued
585 * for TX timestamping.
586 */
587 for (i = 0; i < adapter->num_tx_queues; i++) {
588 struct igc_ring *tx_ring = adapter->tx_ring[i];
589
590 clear_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags);
591 }
592
593 /* Now we can clean the pending TX timestamp requests. */
594 igc_ptp_clear_tx_tstamp(adapter);
595
596 wr32(IGC_TSYNCTXCTL, 0);
597 }
598
igc_ptp_enable_tx_timestamp(struct igc_adapter * adapter)599 static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter)
600 {
601 struct igc_hw *hw = &adapter->hw;
602 int i;
603
604 wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG);
605
606 /* Read TXSTMP registers to discard any timestamp previously stored. */
607 rd32(IGC_TXSTMPL);
608 rd32(IGC_TXSTMPH);
609
610 /* The hardware is ready to accept TX timestamp requests,
611 * notify the transmit path.
612 */
613 for (i = 0; i < adapter->num_tx_queues; i++) {
614 struct igc_ring *tx_ring = adapter->tx_ring[i];
615
616 set_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags);
617 }
618
619 }
620
621 /**
622 * igc_ptp_set_timestamp_mode - setup hardware for timestamping
623 * @adapter: networking device structure
624 * @config: hwtstamp configuration
625 *
626 * Return: 0 in case of success, negative errno code otherwise.
627 */
igc_ptp_set_timestamp_mode(struct igc_adapter * adapter,struct kernel_hwtstamp_config * config)628 static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
629 struct kernel_hwtstamp_config *config)
630 {
631 switch (config->tx_type) {
632 case HWTSTAMP_TX_OFF:
633 igc_ptp_disable_tx_timestamp(adapter);
634 break;
635 case HWTSTAMP_TX_ON:
636 igc_ptp_enable_tx_timestamp(adapter);
637 break;
638 default:
639 return -ERANGE;
640 }
641
642 switch (config->rx_filter) {
643 case HWTSTAMP_FILTER_NONE:
644 igc_ptp_disable_rx_timestamp(adapter);
645 break;
646 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
647 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
648 case HWTSTAMP_FILTER_PTP_V2_EVENT:
649 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
650 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
651 case HWTSTAMP_FILTER_PTP_V2_SYNC:
652 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
653 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
654 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
655 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
656 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
657 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
658 case HWTSTAMP_FILTER_NTP_ALL:
659 case HWTSTAMP_FILTER_ALL:
660 igc_ptp_enable_rx_timestamp(adapter);
661 config->rx_filter = HWTSTAMP_FILTER_ALL;
662 break;
663 default:
664 return -ERANGE;
665 }
666
667 return 0;
668 }
669
670 /* Requires adapter->ptp_tx_lock held by caller. */
igc_ptp_tx_timeout(struct igc_adapter * adapter,struct igc_tx_timestamp_request * tstamp)671 static void igc_ptp_tx_timeout(struct igc_adapter *adapter,
672 struct igc_tx_timestamp_request *tstamp)
673 {
674 if (tstamp->skb)
675 igc_ptp_free_tx_buffer(adapter, tstamp);
676
677 adapter->tx_hwtstamp_timeouts++;
678
679 netdev_warn(adapter->netdev, "Tx timestamp timeout\n");
680 }
681
igc_ptp_tx_hang(struct igc_adapter * adapter)682 void igc_ptp_tx_hang(struct igc_adapter *adapter)
683 {
684 struct igc_tx_timestamp_request *tstamp;
685 struct igc_hw *hw = &adapter->hw;
686 unsigned long flags;
687 bool found = false;
688 int i;
689
690 spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
691
692 for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
693 tstamp = &adapter->tx_tstamp[i];
694
695 if (!tstamp->skb)
696 continue;
697
698 if (time_is_after_jiffies(tstamp->start + IGC_PTP_TX_TIMEOUT))
699 continue;
700
701 igc_ptp_tx_timeout(adapter, tstamp);
702 found = true;
703 }
704
705 if (found) {
706 /* Reading the high register of the first set of timestamp registers
707 * clears all the equivalent bits in the TSYNCTXCTL register.
708 */
709 rd32(IGC_TXSTMPH_0);
710 }
711
712 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);
713 }
714
igc_ptp_tx_reg_to_stamp(struct igc_adapter * adapter,struct igc_tx_timestamp_request * tstamp,u64 regval)715 static void igc_ptp_tx_reg_to_stamp(struct igc_adapter *adapter,
716 struct igc_tx_timestamp_request *tstamp, u64 regval)
717 {
718 struct skb_shared_hwtstamps shhwtstamps;
719 struct sk_buff *skb;
720 int adjust = 0;
721
722 skb = tstamp->skb;
723 if (!skb)
724 return;
725
726 if (igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval))
727 return;
728
729 switch (adapter->link_speed) {
730 case SPEED_10:
731 adjust = IGC_I225_TX_LATENCY_10;
732 break;
733 case SPEED_100:
734 adjust = IGC_I225_TX_LATENCY_100;
735 break;
736 case SPEED_1000:
737 adjust = IGC_I225_TX_LATENCY_1000;
738 break;
739 case SPEED_2500:
740 adjust = IGC_I225_TX_LATENCY_2500;
741 break;
742 }
743
744 shhwtstamps.hwtstamp =
745 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
746
747 /* Copy the tx hardware timestamp into xdp metadata or skb */
748 if (tstamp->buffer_type == IGC_TX_BUFFER_TYPE_XSK) {
749 struct xsk_buff_pool *xsk_pool;
750
751 xsk_pool = adapter->tx_ring[tstamp->xsk_queue_index]->xsk_pool;
752 if (xsk_pool && xp_tx_metadata_enabled(xsk_pool)) {
753 xsk_tx_metadata_complete(&tstamp->xsk_meta,
754 &igc_xsk_tx_metadata_ops,
755 &shhwtstamps.hwtstamp);
756 }
757 } else {
758 skb_tstamp_tx(skb, &shhwtstamps);
759 }
760
761 igc_ptp_free_tx_buffer(adapter, tstamp);
762 }
763
764 /**
765 * igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp
766 * @adapter: Board private structure
767 *
768 * Check against the ready mask for which of the timestamp register
769 * sets are ready to be retrieved, then retrieve that and notify the
770 * rest of the stack.
771 *
772 * Context: Expects adapter->ptp_tx_lock to be held by caller.
773 */
igc_ptp_tx_hwtstamp(struct igc_adapter * adapter)774 static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter)
775 {
776 struct igc_hw *hw = &adapter->hw;
777 u64 regval;
778 u32 mask;
779 int i;
780
781 mask = rd32(IGC_TSYNCTXCTL) & IGC_TSYNCTXCTL_TXTT_ANY;
782 if (mask & IGC_TSYNCTXCTL_TXTT_0) {
783 regval = rd32(IGC_TXSTMPL);
784 regval |= (u64)rd32(IGC_TXSTMPH) << 32;
785 } else {
786 /* There's a bug in the hardware that could cause
787 * missing interrupts for TX timestamping. The issue
788 * is that for new interrupts to be triggered, the
789 * IGC_TXSTMPH_0 register must be read.
790 *
791 * To avoid discarding a valid timestamp that just
792 * happened at the "wrong" time, we need to confirm
793 * that there was no timestamp captured, we do that by
794 * assuming that no two timestamps in sequence have
795 * the same nanosecond value.
796 *
797 * So, we read the "low" register, read the "high"
798 * register (to latch a new timestamp) and read the
799 * "low" register again, if "old" and "new" versions
800 * of the "low" register are different, a valid
801 * timestamp was captured, we can read the "high"
802 * register again.
803 */
804 u32 txstmpl_old, txstmpl_new;
805
806 txstmpl_old = rd32(IGC_TXSTMPL);
807 rd32(IGC_TXSTMPH);
808 txstmpl_new = rd32(IGC_TXSTMPL);
809
810 if (txstmpl_old == txstmpl_new)
811 goto done;
812
813 regval = txstmpl_new;
814 regval |= (u64)rd32(IGC_TXSTMPH) << 32;
815 }
816
817 igc_ptp_tx_reg_to_stamp(adapter, &adapter->tx_tstamp[0], regval);
818
819 done:
820 /* Now that the problematic first register was handled, we can
821 * use retrieve the timestamps from the other registers
822 * (starting from '1') with less complications.
823 */
824 for (i = 1; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
825 struct igc_tx_timestamp_request *tstamp = &adapter->tx_tstamp[i];
826
827 if (!(tstamp->mask & mask))
828 continue;
829
830 regval = rd32(tstamp->regl);
831 regval |= (u64)rd32(tstamp->regh) << 32;
832
833 igc_ptp_tx_reg_to_stamp(adapter, tstamp, regval);
834 }
835 }
836
837 /**
838 * igc_ptp_tx_tstamp_event
839 * @adapter: board private structure
840 *
841 * Called when a TX timestamp interrupt happens to retrieve the
842 * timestamp and send it up to the socket.
843 */
igc_ptp_tx_tstamp_event(struct igc_adapter * adapter)844 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter)
845 {
846 unsigned long flags;
847
848 spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
849
850 igc_ptp_tx_hwtstamp(adapter);
851
852 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);
853 }
854
855 /**
856 * igc_ptp_hwtstamp_set - set hardware time stamping config
857 * @netdev: network interface device structure
858 * @config: timestamping configuration structure
859 * @extack: netlink extended ack structure for error reporting
860 *
861 **/
igc_ptp_hwtstamp_set(struct net_device * netdev,struct kernel_hwtstamp_config * config,struct netlink_ext_ack * extack)862 int igc_ptp_hwtstamp_set(struct net_device *netdev,
863 struct kernel_hwtstamp_config *config,
864 struct netlink_ext_ack *extack)
865 {
866 struct igc_adapter *adapter = netdev_priv(netdev);
867 int err;
868
869 err = igc_ptp_set_timestamp_mode(adapter, config);
870 if (err)
871 return err;
872
873 /* save these settings for future reference */
874 adapter->tstamp_config = *config;
875
876 return 0;
877 }
878
879 /**
880 * igc_ptp_hwtstamp_get - get hardware time stamping config
881 * @netdev: network interface device structure
882 * @config: timestamping configuration structure
883 *
884 * Get the hwtstamp_config settings to return to the user. Rather than attempt
885 * to deconstruct the settings from the registers, just return a shadow copy
886 * of the last known settings.
887 **/
igc_ptp_hwtstamp_get(struct net_device * netdev,struct kernel_hwtstamp_config * config)888 int igc_ptp_hwtstamp_get(struct net_device *netdev,
889 struct kernel_hwtstamp_config *config)
890 {
891 struct igc_adapter *adapter = netdev_priv(netdev);
892
893 *config = adapter->tstamp_config;
894
895 return 0;
896 }
897
898 /* The two conditions below must be met for cross timestamping via
899 * PCIe PTM:
900 *
901 * 1. We have an way to convert the timestamps in the PTM messages
902 * to something related to the system clocks (right now, only
903 * X86 systems with support for the Always Running Timer allow that);
904 *
905 * 2. We have PTM enabled in the path from the device to the PCIe root port.
906 */
igc_is_crosststamp_supported(struct igc_adapter * adapter)907 static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)
908 {
909 if (!IS_ENABLED(CONFIG_X86_TSC))
910 return false;
911
912 /* FIXME: it was noticed that enabling support for PCIe PTM in
913 * some i225-V models could cause lockups when bringing the
914 * interface up/down. There should be no downsides to
915 * disabling crosstimestamping support for i225-V, as it
916 * doesn't have any PTP support. That way we gain some time
917 * while root causing the issue.
918 */
919 if (adapter->pdev->device == IGC_DEV_ID_I225_V)
920 return false;
921
922 return pcie_ptm_enabled(adapter->pdev);
923 }
924
igc_device_tstamp_to_system(u64 tstamp)925 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp)
926 {
927 #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML)
928 return (struct system_counterval_t) {
929 .cs_id = CSID_X86_ART,
930 .cycles = tstamp,
931 .use_nsecs = true,
932 };
933 #else
934 return (struct system_counterval_t) { };
935 #endif
936 }
937
igc_ptm_log_error(struct igc_adapter * adapter,u32 ptm_stat)938 static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat)
939 {
940 struct net_device *netdev = adapter->netdev;
941
942 switch (ptm_stat) {
943 case IGC_PTM_STAT_RET_ERR:
944 netdev_err(netdev, "PTM Error: Root port timeout\n");
945 break;
946 case IGC_PTM_STAT_BAD_PTM_RES:
947 netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n");
948 break;
949 case IGC_PTM_STAT_T4M1_OVFL:
950 netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n");
951 break;
952 case IGC_PTM_STAT_ADJUST_1ST:
953 netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n");
954 break;
955 case IGC_PTM_STAT_ADJUST_CYC:
956 netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n");
957 break;
958 default:
959 netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat);
960 break;
961 }
962 }
963
964 /* The PTM lock: adapter->ptm_lock must be held when calling igc_ptm_trigger() */
igc_ptm_trigger(struct igc_hw * hw)965 static void igc_ptm_trigger(struct igc_hw *hw)
966 {
967 u32 ctrl;
968
969 /* To "manually" start the PTM cycle we need to set the
970 * trigger (TRIG) bit
971 */
972 ctrl = rd32(IGC_PTM_CTRL);
973 ctrl |= IGC_PTM_CTRL_TRIG;
974 wr32(IGC_PTM_CTRL, ctrl);
975 /* Perform flush after write to CTRL register otherwise
976 * transaction may not start
977 */
978 wrfl();
979 }
980
981 /* The PTM lock: adapter->ptm_lock must be held when calling igc_ptm_reset() */
igc_ptm_reset(struct igc_hw * hw)982 static void igc_ptm_reset(struct igc_hw *hw)
983 {
984 u32 ctrl;
985
986 ctrl = rd32(IGC_PTM_CTRL);
987 ctrl &= ~IGC_PTM_CTRL_TRIG;
988 wr32(IGC_PTM_CTRL, ctrl);
989 /* Write to clear all status */
990 wr32(IGC_PTM_STAT, IGC_PTM_STAT_ALL);
991 }
992
igc_phc_get_syncdevicetime(ktime_t * device,struct system_counterval_t * system,void * ctx)993 static int igc_phc_get_syncdevicetime(ktime_t *device,
994 struct system_counterval_t *system,
995 void *ctx)
996 {
997 struct igc_adapter *adapter = ctx;
998 struct igc_hw *hw = &adapter->hw;
999 u32 stat, t2_curr_h, t2_curr_l;
1000 int err, count = 100;
1001 ktime_t t1, t2_curr;
1002
1003 /* Doing this in a loop because in the event of a
1004 * badly timed (ha!) system clock adjustment, we may
1005 * get PTM errors from the PCI root, but these errors
1006 * are transitory. Repeating the process returns valid
1007 * data eventually.
1008 */
1009 do {
1010 /* Get a snapshot of system clocks to use as historic value. */
1011 ktime_get_snapshot(&adapter->snapshot);
1012
1013 igc_ptm_trigger(hw);
1014
1015 err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat,
1016 stat, IGC_PTM_STAT_SLEEP,
1017 IGC_PTM_STAT_TIMEOUT);
1018 igc_ptm_reset(hw);
1019
1020 if (err < 0) {
1021 netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n");
1022 return err;
1023 }
1024
1025 if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID)
1026 break;
1027
1028 igc_ptm_log_error(adapter, stat);
1029 } while (--count);
1030
1031 if (!count) {
1032 netdev_err(adapter->netdev, "Exceeded number of tries for PTM cycle\n");
1033 return -ETIMEDOUT;
1034 }
1035
1036 t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L));
1037
1038 t2_curr_l = rd32(IGC_PTM_CURR_T2_L);
1039 t2_curr_h = rd32(IGC_PTM_CURR_T2_H);
1040
1041 /* FIXME: When the register that tells the endianness of the
1042 * PTM registers are implemented, check them here and add the
1043 * appropriate conversion.
1044 */
1045 t2_curr_h = swab32(t2_curr_h);
1046
1047 t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l);
1048
1049 *device = t1;
1050 *system = igc_device_tstamp_to_system(t2_curr);
1051
1052 return 0;
1053 }
1054
igc_ptp_getcrosststamp(struct ptp_clock_info * ptp,struct system_device_crosststamp * cts)1055 static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp,
1056 struct system_device_crosststamp *cts)
1057 {
1058 struct igc_adapter *adapter = container_of(ptp, struct igc_adapter,
1059 ptp_caps);
1060 int ret;
1061
1062 /* This blocks until any in progress PTM transactions complete */
1063 mutex_lock(&adapter->ptm_lock);
1064
1065 ret = get_device_system_crosststamp(igc_phc_get_syncdevicetime,
1066 adapter, &adapter->snapshot, cts);
1067 mutex_unlock(&adapter->ptm_lock);
1068
1069 return ret;
1070 }
1071
igc_ptp_getcyclesx64(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)1072 static int igc_ptp_getcyclesx64(struct ptp_clock_info *ptp,
1073 struct timespec64 *ts,
1074 struct ptp_system_timestamp *sts)
1075 {
1076 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, ptp_caps);
1077 struct igc_hw *hw = &igc->hw;
1078 unsigned long flags;
1079
1080 spin_lock_irqsave(&igc->free_timer_lock, flags);
1081
1082 ptp_read_system_prets(sts);
1083 ts->tv_nsec = rd32(IGC_SYSTIML_1);
1084 ts->tv_sec = rd32(IGC_SYSTIMH_1);
1085 ptp_read_system_postts(sts);
1086
1087 spin_unlock_irqrestore(&igc->free_timer_lock, flags);
1088
1089 return 0;
1090 }
1091
1092 /**
1093 * igc_ptp_init - Initialize PTP functionality
1094 * @adapter: Board private structure
1095 *
1096 * This function is called at device probe to initialize the PTP
1097 * functionality.
1098 */
igc_ptp_init(struct igc_adapter * adapter)1099 void igc_ptp_init(struct igc_adapter *adapter)
1100 {
1101 struct net_device *netdev = adapter->netdev;
1102 struct igc_tx_timestamp_request *tstamp;
1103 struct igc_hw *hw = &adapter->hw;
1104 int i;
1105
1106 tstamp = &adapter->tx_tstamp[0];
1107 tstamp->mask = IGC_TSYNCTXCTL_TXTT_0;
1108 tstamp->regl = IGC_TXSTMPL_0;
1109 tstamp->regh = IGC_TXSTMPH_0;
1110 tstamp->flags = 0;
1111
1112 tstamp = &adapter->tx_tstamp[1];
1113 tstamp->mask = IGC_TSYNCTXCTL_TXTT_1;
1114 tstamp->regl = IGC_TXSTMPL_1;
1115 tstamp->regh = IGC_TXSTMPH_1;
1116 tstamp->flags = IGC_TX_FLAGS_TSTAMP_1;
1117
1118 tstamp = &adapter->tx_tstamp[2];
1119 tstamp->mask = IGC_TSYNCTXCTL_TXTT_2;
1120 tstamp->regl = IGC_TXSTMPL_2;
1121 tstamp->regh = IGC_TXSTMPH_2;
1122 tstamp->flags = IGC_TX_FLAGS_TSTAMP_2;
1123
1124 tstamp = &adapter->tx_tstamp[3];
1125 tstamp->mask = IGC_TSYNCTXCTL_TXTT_3;
1126 tstamp->regl = IGC_TXSTMPL_3;
1127 tstamp->regh = IGC_TXSTMPH_3;
1128 tstamp->flags = IGC_TX_FLAGS_TSTAMP_3;
1129
1130 switch (hw->mac.type) {
1131 case igc_i225:
1132 for (i = 0; i < IGC_N_SDP; i++) {
1133 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1134
1135 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1136 ppd->index = i;
1137 ppd->func = PTP_PF_NONE;
1138 }
1139 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1140 adapter->ptp_caps.owner = THIS_MODULE;
1141 adapter->ptp_caps.max_adj = 62499999;
1142 adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225;
1143 adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225;
1144 adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225;
1145 adapter->ptp_caps.getcyclesx64 = igc_ptp_getcyclesx64;
1146 adapter->ptp_caps.settime64 = igc_ptp_settime_i225;
1147 adapter->ptp_caps.enable = igc_ptp_feature_enable_i225;
1148 adapter->ptp_caps.pps = 1;
1149 adapter->ptp_caps.pin_config = adapter->sdp_config;
1150 adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS;
1151 adapter->ptp_caps.n_per_out = IGC_N_PEROUT;
1152 adapter->ptp_caps.supported_extts_flags = PTP_RISING_EDGE |
1153 PTP_FALLING_EDGE |
1154 PTP_STRICT_FLAGS;
1155 adapter->ptp_caps.n_pins = IGC_N_SDP;
1156 adapter->ptp_caps.verify = igc_ptp_verify_pin;
1157
1158 if (!igc_is_crosststamp_supported(adapter))
1159 break;
1160
1161 adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp;
1162 break;
1163 default:
1164 adapter->ptp_clock = NULL;
1165 return;
1166 }
1167
1168 spin_lock_init(&adapter->ptp_tx_lock);
1169 spin_lock_init(&adapter->free_timer_lock);
1170 spin_lock_init(&adapter->tmreg_lock);
1171 mutex_init(&adapter->ptm_lock);
1172
1173 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1174 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1175
1176 adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real());
1177 adapter->ptp_reset_start = ktime_get();
1178
1179 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1180 &adapter->pdev->dev);
1181 if (IS_ERR(adapter->ptp_clock)) {
1182 adapter->ptp_clock = NULL;
1183 netdev_err(netdev, "ptp_clock_register failed\n");
1184 mutex_destroy(&adapter->ptm_lock);
1185 } else if (adapter->ptp_clock) {
1186 netdev_info(netdev, "PHC added\n");
1187 adapter->ptp_flags |= IGC_PTP_ENABLED;
1188 }
1189 }
1190
igc_ptp_time_save(struct igc_adapter * adapter)1191 static void igc_ptp_time_save(struct igc_adapter *adapter)
1192 {
1193 igc_ptp_read(adapter, &adapter->prev_ptp_time);
1194 adapter->ptp_reset_start = ktime_get();
1195 }
1196
igc_ptp_time_restore(struct igc_adapter * adapter)1197 static void igc_ptp_time_restore(struct igc_adapter *adapter)
1198 {
1199 struct timespec64 ts = adapter->prev_ptp_time;
1200 ktime_t delta;
1201
1202 delta = ktime_sub(ktime_get(), adapter->ptp_reset_start);
1203
1204 timespec64_add_ns(&ts, ktime_to_ns(delta));
1205
1206 igc_ptp_write_i225(adapter, &ts);
1207 }
1208
igc_ptm_stop(struct igc_adapter * adapter)1209 static void igc_ptm_stop(struct igc_adapter *adapter)
1210 {
1211 struct igc_hw *hw = &adapter->hw;
1212 u32 ctrl;
1213
1214 mutex_lock(&adapter->ptm_lock);
1215 ctrl = rd32(IGC_PTM_CTRL);
1216 ctrl &= ~IGC_PTM_CTRL_EN;
1217
1218 wr32(IGC_PTM_CTRL, ctrl);
1219 mutex_unlock(&adapter->ptm_lock);
1220 }
1221
1222 /**
1223 * igc_ptp_suspend - Disable PTP work items and prepare for suspend
1224 * @adapter: Board private structure
1225 *
1226 * This function stops the overflow check work and PTP Tx timestamp work, and
1227 * will prepare the device for OS suspend.
1228 */
igc_ptp_suspend(struct igc_adapter * adapter)1229 void igc_ptp_suspend(struct igc_adapter *adapter)
1230 {
1231 if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1232 return;
1233
1234 igc_ptp_clear_tx_tstamp(adapter);
1235
1236 if (pci_device_is_present(adapter->pdev)) {
1237 igc_ptp_time_save(adapter);
1238 igc_ptm_stop(adapter);
1239 }
1240 }
1241
1242 /**
1243 * igc_ptp_stop - Disable PTP device and stop the overflow check.
1244 * @adapter: Board private structure.
1245 *
1246 * This function stops the PTP support and cancels the delayed work.
1247 **/
igc_ptp_stop(struct igc_adapter * adapter)1248 void igc_ptp_stop(struct igc_adapter *adapter)
1249 {
1250 if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1251 return;
1252
1253 igc_ptp_suspend(adapter);
1254
1255 adapter->ptp_flags &= ~IGC_PTP_ENABLED;
1256 if (adapter->ptp_clock) {
1257 ptp_clock_unregister(adapter->ptp_clock);
1258 netdev_info(adapter->netdev, "PHC removed\n");
1259 adapter->ptp_flags &= ~IGC_PTP_ENABLED;
1260 }
1261 mutex_destroy(&adapter->ptm_lock);
1262 }
1263
1264 /**
1265 * igc_ptp_reset - Re-enable the adapter for PTP following a reset.
1266 * @adapter: Board private structure.
1267 *
1268 * This function handles the reset work required to re-enable the PTP device.
1269 **/
igc_ptp_reset(struct igc_adapter * adapter)1270 void igc_ptp_reset(struct igc_adapter *adapter)
1271 {
1272 struct igc_hw *hw = &adapter->hw;
1273 u32 cycle_ctrl, ctrl, stat;
1274 unsigned long flags;
1275 u32 timadj;
1276
1277 if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1278 return;
1279
1280 /* reset the tstamp_config */
1281 igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1282
1283 mutex_lock(&adapter->ptm_lock);
1284
1285 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1286
1287 switch (adapter->hw.mac.type) {
1288 case igc_i225:
1289 timadj = rd32(IGC_TIMADJ);
1290 timadj |= IGC_TIMADJ_ADJUST_METH;
1291 wr32(IGC_TIMADJ, timadj);
1292
1293 wr32(IGC_TSAUXC, 0x0);
1294 wr32(IGC_TSSDP, 0x0);
1295 wr32(IGC_TSIM,
1296 IGC_TSICR_INTERRUPTS |
1297 (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0));
1298 wr32(IGC_IMS, IGC_IMS_TS);
1299
1300 if (!igc_is_crosststamp_supported(adapter))
1301 break;
1302
1303 wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT);
1304 wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT);
1305
1306 cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT);
1307
1308 wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl);
1309
1310 ctrl = IGC_PTM_CTRL_EN |
1311 IGC_PTM_CTRL_START_NOW |
1312 IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) |
1313 IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT);
1314
1315 wr32(IGC_PTM_CTRL, ctrl);
1316
1317 /* Force the first cycle to run. */
1318 igc_ptm_trigger(hw);
1319
1320 if (readx_poll_timeout_atomic(rd32, IGC_PTM_STAT, stat,
1321 stat, IGC_PTM_STAT_SLEEP,
1322 IGC_PTM_STAT_TIMEOUT))
1323 netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n");
1324
1325 igc_ptm_reset(hw);
1326 break;
1327 default:
1328 /* No work to do. */
1329 goto out;
1330 }
1331
1332 /* Re-initialize the timer. */
1333 if (hw->mac.type == igc_i225) {
1334 igc_ptp_time_restore(adapter);
1335 } else {
1336 timecounter_init(&adapter->tc, &adapter->cc,
1337 ktime_to_ns(ktime_get_real()));
1338 }
1339 out:
1340 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1341
1342 mutex_unlock(&adapter->ptm_lock);
1343
1344 wrfl();
1345 }
1346