1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel E3-1200
4 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com>
5 *
6 * Support for the E3-1200 processor family. Heavily based on previous
7 * Intel EDAC drivers.
8 *
9 * Since the DRAM controller is on the cpu chip, we can use its PCI device
10 * id to identify these processors.
11 *
12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
13 *
14 * 0108: Xeon E3-1200 Processor Family DRAM Controller
15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
22 * 590f: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
23 * 5918: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
24 * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
25 * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
26 * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
27 *
28 * Based on Intel specification:
29 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
30 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
31 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf
32 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf
33 * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
34 * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html
35 *
36 * According to the above datasheet (p.16):
37 * "
38 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
39 * requests that cross a DW boundary.
40 * "
41 *
42 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into
43 * 2 readl() calls. This restriction may be lifted in subsequent chip releases,
44 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
45 */
46
47 #include <linux/bitfield.h>
48 #include <linux/module.h>
49 #include <linux/init.h>
50 #include <linux/pci.h>
51 #include <linux/pci_ids.h>
52 #include <linux/edac.h>
53
54 #include <linux/io-64-nonatomic-lo-hi.h>
55 #include <asm/mce.h>
56 #include <asm/msr.h>
57 #include "edac_module.h"
58
59 #define EDAC_MOD_STR "ie31200_edac"
60
61 #define ie31200_printk(level, fmt, arg...) \
62 edac_printk(level, "ie31200", fmt, ##arg)
63
64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
65 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
66 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
71 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
72 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918
73 #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
74 #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x590f
75 #define PCI_DEVICE_ID_INTEL_IE31200_HB_12 0x5918
76
77 /* Coffee Lake-S */
78 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
79 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f
80 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18
81 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f
82 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30
83 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31
84 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32
85 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33
86 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2
87 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6
88 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca
89
90 /* Raptor Lake-S */
91 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1 0xa703 /* 8P+8E, e.g. i7-13700 */
92 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2 0x4640 /* 6P+8E, e.g. i5-13500, i5-13600, i5-14500 */
93 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3 0x4630 /* 4P+0E, e.g. i3-13100E */
94 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_4 0xa700 /* 8P+16E, e.g. i9-13900, i9-14900 */
95 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_5 0xa740 /* 8P+12E, e.g. i7-14700 */
96 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_6 0xa704 /* 6P+8E, e.g. i5-14600 */
97
98 /* Raptor Lake-HX */
99 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_HX_1 0xa702 /* 8P+16E, e.g. i9-13950HX */
100
101 /* Alder Lake-S */
102 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_1 0x4660
103 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_2 0x4668 /* 8P+4E, e.g. i7-12700K */
104 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_3 0x4648 /* 6P+4E, e.g. i5-12600K */
105
106 /* Bartlett Lake-S */
107 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_1 0x4639
108 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_2 0x463c
109 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_3 0x4642
110 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_4 0x4643
111 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_5 0xa731
112 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_6 0xa732
113 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_7 0xa733
114 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_8 0xa741
115 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_9 0xa744
116 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_10 0xa745
117
118 #define IE31200_RANKS_PER_CHANNEL 8
119 #define IE31200_DIMMS_PER_CHANNEL 2
120 #define IE31200_CHANNELS 2
121 #define IE31200_IMC_NUM 2
122
123 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
124 #define IE31200_MCHBAR_LOW 0x48
125 #define IE31200_MCHBAR_HIGH 0x4c
126
127 /*
128 * Error Status Register (16b)
129 *
130 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
131 * 0 Single-bit DRAM ECC Error Flag (DSERR)
132 */
133 #define IE31200_ERRSTS 0xc8
134 #define IE31200_ERRSTS_UE BIT(1)
135 #define IE31200_ERRSTS_CE BIT(0)
136 #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE)
137
138 #define IE31200_CAPID0 0xe4
139 #define IE31200_CAPID0_PDCD BIT(4)
140 #define IE31200_CAPID0_DDPCD BIT(6)
141 #define IE31200_CAPID0_ECC BIT(1)
142
143 static int nr_channels;
144 static struct pci_dev *mci_pdev;
145 static int ie31200_registered = 1;
146
147 struct res_config {
148 enum mem_type mtype;
149 bool cmci;
150 int imc_num;
151 /* Host MMIO configuration register */
152 u64 reg_mchbar_mask;
153 u64 reg_mchbar_window_size;
154 /* ECC error log register */
155 u64 reg_eccerrlog_offset[IE31200_CHANNELS];
156 u64 reg_eccerrlog_ce_mask;
157 u64 reg_eccerrlog_ce_ovfl_mask;
158 u64 reg_eccerrlog_ue_mask;
159 u64 reg_eccerrlog_ue_ovfl_mask;
160 u64 reg_eccerrlog_rank_mask;
161 u64 reg_eccerrlog_syndrome_mask;
162 /* MSR to clear ECC error log register */
163 u32 msr_clear_eccerrlog_offset;
164 /* DIMM characteristics register */
165 u64 reg_mad_dimm_size_granularity;
166 u64 reg_mad_dimm_offset[IE31200_CHANNELS];
167 u32 reg_mad_dimm_size_mask[IE31200_DIMMS_PER_CHANNEL];
168 u32 reg_mad_dimm_rank_mask[IE31200_DIMMS_PER_CHANNEL];
169 u32 reg_mad_dimm_width_mask[IE31200_DIMMS_PER_CHANNEL];
170 };
171
172 struct ie31200_priv {
173 void __iomem *window;
174 void __iomem *c0errlog;
175 void __iomem *c1errlog;
176 struct res_config *cfg;
177 struct mem_ctl_info *mci;
178 struct pci_dev *pdev;
179 struct device dev;
180 };
181
182 static struct ie31200_pvt {
183 struct ie31200_priv *priv[IE31200_IMC_NUM];
184 } ie31200_pvt;
185
186 enum ie31200_chips {
187 IE31200 = 0,
188 IE31200_1 = 1,
189 };
190
191 struct ie31200_dev_info {
192 const char *ctl_name;
193 };
194
195 struct ie31200_error_info {
196 u16 errsts;
197 u16 errsts2;
198 u64 eccerrlog[IE31200_CHANNELS];
199 u64 erraddr;
200 };
201
202 static const struct ie31200_dev_info ie31200_devs[] = {
203 [IE31200] = {
204 .ctl_name = "IE31200"
205 },
206 [IE31200_1] = {
207 .ctl_name = "IE31200_1"
208 },
209 };
210
211 struct dimm_data {
212 u64 size; /* in bytes */
213 u8 ranks;
214 enum dev_type dtype;
215 };
216
how_many_channels(struct pci_dev * pdev)217 static int how_many_channels(struct pci_dev *pdev)
218 {
219 int n_channels;
220 unsigned char capid0_2b; /* 2nd byte of CAPID0 */
221
222 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b);
223
224 /* check PDCD: Dual Channel Disable */
225 if (capid0_2b & IE31200_CAPID0_PDCD) {
226 edac_dbg(0, "In single channel mode\n");
227 n_channels = 1;
228 } else {
229 edac_dbg(0, "In dual channel mode\n");
230 n_channels = 2;
231 }
232
233 /* check DDPCD - check if both channels are filled */
234 if (capid0_2b & IE31200_CAPID0_DDPCD)
235 edac_dbg(0, "2 DIMMS per channel disabled\n");
236 else
237 edac_dbg(0, "2 DIMMS per channel enabled\n");
238
239 return n_channels;
240 }
241
ecc_capable(struct pci_dev * pdev)242 static bool ecc_capable(struct pci_dev *pdev)
243 {
244 unsigned char capid0_4b; /* 4th byte of CAPID0 */
245
246 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);
247 if (capid0_4b & IE31200_CAPID0_ECC)
248 return false;
249 return true;
250 }
251
252 #define mci_to_pci_dev(mci) (((struct ie31200_priv *)(mci)->pvt_info)->pdev)
253
ie31200_clear_error_info(struct mem_ctl_info * mci)254 static void ie31200_clear_error_info(struct mem_ctl_info *mci)
255 {
256 struct ie31200_priv *priv = mci->pvt_info;
257 struct res_config *cfg = priv->cfg;
258
259 /*
260 * The PCI ERRSTS register is deprecated. Write the MSR to clear
261 * the ECC error log registers in all memory controllers.
262 */
263 if (cfg->msr_clear_eccerrlog_offset) {
264 if (wrmsr_safe(cfg->msr_clear_eccerrlog_offset,
265 cfg->reg_eccerrlog_ce_mask |
266 cfg->reg_eccerrlog_ce_ovfl_mask |
267 cfg->reg_eccerrlog_ue_mask |
268 cfg->reg_eccerrlog_ue_ovfl_mask, 0) < 0)
269 ie31200_printk(KERN_ERR, "Failed to wrmsr.\n");
270
271 return;
272 }
273
274 /*
275 * Clear any error bits.
276 * (Yes, we really clear bits by writing 1 to them.)
277 */
278 pci_write_bits16(mci_to_pci_dev(mci), IE31200_ERRSTS,
279 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS);
280 }
281
ie31200_get_and_clear_error_info(struct mem_ctl_info * mci,struct ie31200_error_info * info)282 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
283 struct ie31200_error_info *info)
284 {
285 struct pci_dev *pdev = mci_to_pci_dev(mci);
286 struct ie31200_priv *priv = mci->pvt_info;
287
288 /*
289 * The PCI ERRSTS register is deprecated, directly read the
290 * MMIO-mapped ECC error log registers.
291 */
292 if (priv->cfg->msr_clear_eccerrlog_offset) {
293 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
294 if (nr_channels == 2)
295 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog);
296
297 ie31200_clear_error_info(mci);
298 return;
299 }
300
301 /*
302 * This is a mess because there is no atomic way to read all the
303 * registers at once and the registers can transition from CE being
304 * overwritten by UE.
305 */
306 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);
307 if (!(info->errsts & IE31200_ERRSTS_BITS))
308 return;
309
310 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
311 if (nr_channels == 2)
312 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog);
313
314 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
315
316 /*
317 * If the error is the same for both reads then the first set
318 * of reads is valid. If there is a change then there is a CE
319 * with no info and the second set of reads is valid and
320 * should be UE info.
321 */
322 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
323 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
324 if (nr_channels == 2)
325 info->eccerrlog[1] =
326 lo_hi_readq(priv->c1errlog);
327 }
328
329 ie31200_clear_error_info(mci);
330 }
331
ie31200_process_error_info(struct mem_ctl_info * mci,struct ie31200_error_info * info)332 static void ie31200_process_error_info(struct mem_ctl_info *mci,
333 struct ie31200_error_info *info)
334 {
335 struct ie31200_priv *priv = mci->pvt_info;
336 struct res_config *cfg = priv->cfg;
337 int channel;
338 u64 log;
339
340 if (!cfg->msr_clear_eccerrlog_offset) {
341 if (!(info->errsts & IE31200_ERRSTS_BITS))
342 return;
343
344 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
345 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
346 -1, -1, -1, "UE overwrote CE", "");
347 info->errsts = info->errsts2;
348 }
349 }
350
351 for (channel = 0; channel < nr_channels; channel++) {
352 log = info->eccerrlog[channel];
353 if (log & cfg->reg_eccerrlog_ue_mask) {
354 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
355 info->erraddr >> PAGE_SHIFT, 0, 0,
356 field_get(cfg->reg_eccerrlog_rank_mask, log),
357 channel, -1,
358 "ie31200 UE", "");
359 } else if (log & cfg->reg_eccerrlog_ce_mask) {
360 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
361 info->erraddr >> PAGE_SHIFT, 0,
362 field_get(cfg->reg_eccerrlog_syndrome_mask, log),
363 field_get(cfg->reg_eccerrlog_rank_mask, log),
364 channel, -1,
365 "ie31200 CE", "");
366 }
367 }
368 }
369
__ie31200_check(struct mem_ctl_info * mci,struct mce * mce)370 static void __ie31200_check(struct mem_ctl_info *mci, struct mce *mce)
371 {
372 struct ie31200_error_info info;
373
374 info.erraddr = mce ? mce->addr : 0;
375 ie31200_get_and_clear_error_info(mci, &info);
376 ie31200_process_error_info(mci, &info);
377 }
378
ie31200_check(struct mem_ctl_info * mci)379 static void ie31200_check(struct mem_ctl_info *mci)
380 {
381 __ie31200_check(mci, NULL);
382 }
383
ie31200_map_mchbar(struct pci_dev * pdev,struct res_config * cfg,int mc)384 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev, struct res_config *cfg, int mc)
385 {
386 union {
387 u64 mchbar;
388 struct {
389 u32 mchbar_low;
390 u32 mchbar_high;
391 };
392 } u;
393 void __iomem *window;
394
395 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low);
396 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high);
397 u.mchbar &= cfg->reg_mchbar_mask;
398 u.mchbar += cfg->reg_mchbar_window_size * mc;
399
400 if (u.mchbar != (resource_size_t)u.mchbar) {
401 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",
402 (unsigned long long)u.mchbar);
403 return NULL;
404 }
405
406 window = ioremap(u.mchbar, cfg->reg_mchbar_window_size);
407 if (!window)
408 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
409 (unsigned long long)u.mchbar);
410
411 return window;
412 }
413
populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int dimm,struct res_config * cfg)414 static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int dimm,
415 struct res_config *cfg)
416 {
417 dd->size = field_get(cfg->reg_mad_dimm_size_mask[dimm], addr_decode) * cfg->reg_mad_dimm_size_granularity;
418 dd->ranks = field_get(cfg->reg_mad_dimm_rank_mask[dimm], addr_decode) + 1;
419 dd->dtype = field_get(cfg->reg_mad_dimm_width_mask[dimm], addr_decode) + DEV_X8;
420 }
421
ie31200_get_dimm_config(struct mem_ctl_info * mci,void __iomem * window,struct res_config * cfg,int mc)422 static void ie31200_get_dimm_config(struct mem_ctl_info *mci, void __iomem *window,
423 struct res_config *cfg, int mc)
424 {
425 struct dimm_data dimm_info;
426 struct dimm_info *dimm;
427 unsigned long nr_pages;
428 u32 addr_decode;
429 int i, j, k;
430
431 for (i = 0; i < IE31200_CHANNELS; i++) {
432 addr_decode = readl(window + cfg->reg_mad_dimm_offset[i]);
433 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
434
435 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
436 populate_dimm_info(&dimm_info, addr_decode, j, cfg);
437 edac_dbg(0, "mc: %d, channel: %d, dimm: %d, size: %lld MiB, ranks: %d, DRAM chip type: %d\n",
438 mc, i, j, dimm_info.size >> 20,
439 dimm_info.ranks,
440 dimm_info.dtype);
441
442 nr_pages = MiB_TO_PAGES(dimm_info.size >> 20);
443 if (nr_pages == 0)
444 continue;
445
446 nr_pages = nr_pages / dimm_info.ranks;
447 for (k = 0; k < dimm_info.ranks; k++) {
448 dimm = edac_get_dimm(mci, (j * dimm_info.ranks) + k, i, 0);
449 dimm->nr_pages = nr_pages;
450 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
451 dimm->grain = 8; /* just a guess */
452 dimm->mtype = cfg->mtype;
453 dimm->dtype = dimm_info.dtype;
454 dimm->edac_mode = EDAC_UNKNOWN;
455 }
456 }
457 }
458 }
459
ie31200_register_mci(struct pci_dev * pdev,struct res_config * cfg,int mc)460 static int ie31200_register_mci(struct pci_dev *pdev, struct res_config *cfg, int mc)
461 {
462 struct edac_mc_layer layers[2];
463 struct ie31200_priv *priv;
464 struct mem_ctl_info *mci;
465 void __iomem *window;
466 int ret;
467
468 nr_channels = how_many_channels(pdev);
469 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
470 layers[0].size = IE31200_RANKS_PER_CHANNEL;
471 layers[0].is_virt_csrow = true;
472 layers[1].type = EDAC_MC_LAYER_CHANNEL;
473 layers[1].size = nr_channels;
474 layers[1].is_virt_csrow = false;
475 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers,
476 sizeof(struct ie31200_priv));
477 if (!mci)
478 return -ENOMEM;
479
480 window = ie31200_map_mchbar(pdev, cfg, mc);
481 if (!window) {
482 ret = -ENODEV;
483 goto fail_free;
484 }
485
486 edac_dbg(3, "MC: init mci\n");
487 mci->mtype_cap = BIT(cfg->mtype);
488 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
489 mci->edac_cap = EDAC_FLAG_SECDED;
490 mci->mod_name = EDAC_MOD_STR;
491 mci->ctl_name = ie31200_devs[mc].ctl_name;
492 mci->dev_name = pci_name(pdev);
493 mci->edac_check = cfg->cmci ? NULL : ie31200_check;
494 mci->ctl_page_to_phys = NULL;
495 priv = mci->pvt_info;
496 priv->window = window;
497 priv->c0errlog = window + cfg->reg_eccerrlog_offset[0];
498 priv->c1errlog = window + cfg->reg_eccerrlog_offset[1];
499 priv->cfg = cfg;
500 priv->mci = mci;
501 priv->pdev = pdev;
502 device_initialize(&priv->dev);
503 /*
504 * The EDAC core uses mci->pdev (pointer to the structure device)
505 * as the memory controller ID. The SoCs attach one or more memory
506 * controllers to a single pci_dev (a single pci_dev->dev can
507 * correspond to multiple memory controllers).
508 *
509 * To make mci->pdev unique, assign pci_dev->dev to mci->pdev
510 * for the first memory controller and assign a unique priv->dev
511 * to mci->pdev for each additional memory controller.
512 */
513 mci->pdev = mc ? &priv->dev : &pdev->dev;
514
515 ie31200_get_dimm_config(mci, window, cfg, mc);
516 ie31200_clear_error_info(mci);
517
518 if (edac_mc_add_mc(mci)) {
519 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
520 ret = -ENODEV;
521 goto fail_unmap;
522 }
523
524 ie31200_pvt.priv[mc] = priv;
525 return 0;
526 fail_unmap:
527 put_device(&priv->dev);
528 iounmap(window);
529 fail_free:
530 edac_mc_free(mci);
531 return ret;
532 }
533
mce_check(struct mce * mce)534 static void mce_check(struct mce *mce)
535 {
536 struct ie31200_priv *priv;
537 int i;
538
539 for (i = 0; i < IE31200_IMC_NUM; i++) {
540 priv = ie31200_pvt.priv[i];
541 if (!priv)
542 continue;
543
544 __ie31200_check(priv->mci, mce);
545 }
546 }
547
mce_handler(struct notifier_block * nb,unsigned long val,void * data)548 static int mce_handler(struct notifier_block *nb, unsigned long val, void *data)
549 {
550 struct mce *mce = (struct mce *)data;
551 char *type;
552
553 if (mce->kflags & MCE_HANDLED_CEC)
554 return NOTIFY_DONE;
555
556 /*
557 * Ignore unless this is a memory related error.
558 * Don't check MCI_STATUS_ADDRV since it's not set on some CPUs.
559 */
560 if ((mce->status & 0xefff) >> 7 != 1)
561 return NOTIFY_DONE;
562
563 type = mce->mcgstatus & MCG_STATUS_MCIP ? "Exception" : "Event";
564
565 edac_dbg(0, "CPU %d: Machine Check %s: 0x%llx Bank %d: 0x%llx\n",
566 mce->extcpu, type, mce->mcgstatus,
567 mce->bank, mce->status);
568 edac_dbg(0, "TSC 0x%llx\n", mce->tsc);
569 edac_dbg(0, "ADDR 0x%llx\n", mce->addr);
570 edac_dbg(0, "MISC 0x%llx\n", mce->misc);
571 edac_dbg(0, "PROCESSOR %u:0x%x TIME %llu SOCKET %u APIC 0x%x\n",
572 mce->cpuvendor, mce->cpuid, mce->time,
573 mce->socketid, mce->apicid);
574
575 mce_check(mce);
576 mce->kflags |= MCE_HANDLED_EDAC;
577
578 return NOTIFY_DONE;
579 }
580
581 static struct notifier_block ie31200_mce_dec = {
582 .notifier_call = mce_handler,
583 .priority = MCE_PRIO_EDAC,
584 };
585
ie31200_unregister_mcis(void)586 static void ie31200_unregister_mcis(void)
587 {
588 struct ie31200_priv *priv;
589 struct mem_ctl_info *mci;
590 int i;
591
592 for (i = 0; i < IE31200_IMC_NUM; i++) {
593 priv = ie31200_pvt.priv[i];
594 if (!priv)
595 continue;
596
597 mci = priv->mci;
598 edac_mc_del_mc(mci->pdev);
599 iounmap(priv->window);
600 put_device(&priv->dev);
601 edac_mc_free(mci);
602 }
603 }
604
ie31200_probe1(struct pci_dev * pdev,struct res_config * cfg)605 static int ie31200_probe1(struct pci_dev *pdev, struct res_config *cfg)
606 {
607 int i, ret;
608
609 edac_dbg(0, "MC:\n");
610
611 if (!ecc_capable(pdev)) {
612 ie31200_printk(KERN_INFO, "No ECC support\n");
613 return -ENODEV;
614 }
615
616 for (i = 0; i < cfg->imc_num; i++) {
617 ret = ie31200_register_mci(pdev, cfg, i);
618 if (ret)
619 goto fail_register;
620 }
621
622 if (cfg->cmci) {
623 mce_register_decode_chain(&ie31200_mce_dec);
624 edac_op_state = EDAC_OPSTATE_INT;
625 } else {
626 edac_op_state = EDAC_OPSTATE_POLL;
627 }
628
629 /* get this far and it's successful. */
630 edac_dbg(3, "MC: success\n");
631 return 0;
632
633 fail_register:
634 ie31200_unregister_mcis();
635 return ret;
636 }
637
ie31200_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)638 static int ie31200_init_one(struct pci_dev *pdev,
639 const struct pci_device_id *ent)
640 {
641 int rc;
642
643 edac_dbg(0, "MC:\n");
644 if (pci_enable_device(pdev) < 0)
645 return -EIO;
646 rc = ie31200_probe1(pdev, (struct res_config *)ent->driver_data);
647 if (rc == 0 && !mci_pdev)
648 mci_pdev = pci_dev_get(pdev);
649
650 return rc;
651 }
652
ie31200_remove_one(struct pci_dev * pdev)653 static void ie31200_remove_one(struct pci_dev *pdev)
654 {
655 struct ie31200_priv *priv = ie31200_pvt.priv[0];
656
657 edac_dbg(0, "\n");
658 pci_dev_put(mci_pdev);
659 mci_pdev = NULL;
660 if (priv->cfg->cmci)
661 mce_unregister_decode_chain(&ie31200_mce_dec);
662 ie31200_unregister_mcis();
663 }
664
665 static struct res_config snb_cfg = {
666 .mtype = MEM_DDR3,
667 .imc_num = 1,
668 .reg_mchbar_mask = GENMASK_ULL(38, 15),
669 .reg_mchbar_window_size = BIT_ULL(15),
670 .reg_eccerrlog_offset[0] = 0x40c8,
671 .reg_eccerrlog_offset[1] = 0x44c8,
672 .reg_eccerrlog_ce_mask = BIT_ULL(0),
673 .reg_eccerrlog_ue_mask = BIT_ULL(1),
674 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27),
675 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16),
676 .reg_mad_dimm_size_granularity = BIT_ULL(28),
677 .reg_mad_dimm_offset[0] = 0x5004,
678 .reg_mad_dimm_offset[1] = 0x5008,
679 .reg_mad_dimm_size_mask[0] = GENMASK(7, 0),
680 .reg_mad_dimm_size_mask[1] = GENMASK(15, 8),
681 .reg_mad_dimm_rank_mask[0] = BIT(17),
682 .reg_mad_dimm_rank_mask[1] = BIT(18),
683 .reg_mad_dimm_width_mask[0] = BIT(19),
684 .reg_mad_dimm_width_mask[1] = BIT(20),
685 };
686
687 static struct res_config skl_cfg = {
688 .mtype = MEM_DDR4,
689 .imc_num = 1,
690 .reg_mchbar_mask = GENMASK_ULL(38, 15),
691 .reg_mchbar_window_size = BIT_ULL(15),
692 .reg_eccerrlog_offset[0] = 0x4048,
693 .reg_eccerrlog_offset[1] = 0x4448,
694 .reg_eccerrlog_ce_mask = BIT_ULL(0),
695 .reg_eccerrlog_ue_mask = BIT_ULL(1),
696 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27),
697 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16),
698 .reg_mad_dimm_size_granularity = BIT_ULL(30),
699 .reg_mad_dimm_offset[0] = 0x500c,
700 .reg_mad_dimm_offset[1] = 0x5010,
701 .reg_mad_dimm_size_mask[0] = GENMASK(5, 0),
702 .reg_mad_dimm_size_mask[1] = GENMASK(21, 16),
703 .reg_mad_dimm_rank_mask[0] = BIT(10),
704 .reg_mad_dimm_rank_mask[1] = BIT(26),
705 .reg_mad_dimm_width_mask[0] = GENMASK(9, 8),
706 .reg_mad_dimm_width_mask[1] = GENMASK(25, 24),
707 };
708
709 struct res_config rpl_s_cfg = {
710 .mtype = MEM_DDR5,
711 .cmci = true,
712 .imc_num = 2,
713 .reg_mchbar_mask = GENMASK_ULL(41, 17),
714 .reg_mchbar_window_size = BIT_ULL(16),
715 .reg_eccerrlog_offset[0] = 0xe048,
716 .reg_eccerrlog_offset[1] = 0xe848,
717 .reg_eccerrlog_ce_mask = BIT_ULL(0),
718 .reg_eccerrlog_ce_ovfl_mask = BIT_ULL(1),
719 .reg_eccerrlog_ue_mask = BIT_ULL(2),
720 .reg_eccerrlog_ue_ovfl_mask = BIT_ULL(3),
721 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27),
722 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16),
723 .msr_clear_eccerrlog_offset = 0x791,
724 .reg_mad_dimm_offset[0] = 0xd80c,
725 .reg_mad_dimm_offset[1] = 0xd810,
726 .reg_mad_dimm_size_granularity = BIT_ULL(29),
727 .reg_mad_dimm_size_mask[0] = GENMASK(6, 0),
728 .reg_mad_dimm_size_mask[1] = GENMASK(22, 16),
729 .reg_mad_dimm_rank_mask[0] = GENMASK(10, 9),
730 .reg_mad_dimm_rank_mask[1] = GENMASK(27, 26),
731 .reg_mad_dimm_width_mask[0] = GENMASK(8, 7),
732 .reg_mad_dimm_width_mask[1] = GENMASK(25, 24),
733 };
734
735 static const struct pci_device_id ie31200_pci_tbl[] = {
736 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_1), (kernel_ulong_t)&snb_cfg },
737 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_2), (kernel_ulong_t)&snb_cfg },
738 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_3), (kernel_ulong_t)&snb_cfg },
739 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_4), (kernel_ulong_t)&snb_cfg },
740 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_5), (kernel_ulong_t)&snb_cfg },
741 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_6), (kernel_ulong_t)&snb_cfg },
742 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_7), (kernel_ulong_t)&snb_cfg },
743 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_8), (kernel_ulong_t)&skl_cfg },
744 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_9), (kernel_ulong_t)&skl_cfg },
745 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_10), (kernel_ulong_t)&skl_cfg },
746 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_11), (kernel_ulong_t)&skl_cfg },
747 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_12), (kernel_ulong_t)&skl_cfg },
748 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1), (kernel_ulong_t)&skl_cfg },
749 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2), (kernel_ulong_t)&skl_cfg },
750 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3), (kernel_ulong_t)&skl_cfg },
751 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4), (kernel_ulong_t)&skl_cfg },
752 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5), (kernel_ulong_t)&skl_cfg },
753 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6), (kernel_ulong_t)&skl_cfg },
754 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7), (kernel_ulong_t)&skl_cfg },
755 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8), (kernel_ulong_t)&skl_cfg },
756 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9), (kernel_ulong_t)&skl_cfg },
757 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10), (kernel_ulong_t)&skl_cfg },
758 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1), (kernel_ulong_t)&rpl_s_cfg},
759 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2), (kernel_ulong_t)&rpl_s_cfg},
760 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3), (kernel_ulong_t)&rpl_s_cfg},
761 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_4), (kernel_ulong_t)&rpl_s_cfg},
762 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_5), (kernel_ulong_t)&rpl_s_cfg},
763 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_6), (kernel_ulong_t)&rpl_s_cfg},
764 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_HX_1), (kernel_ulong_t)&rpl_s_cfg},
765 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_ADL_S_1), (kernel_ulong_t)&rpl_s_cfg},
766 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_ADL_S_2), (kernel_ulong_t)&rpl_s_cfg},
767 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_ADL_S_3), (kernel_ulong_t)&rpl_s_cfg},
768 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_1), (kernel_ulong_t)&rpl_s_cfg},
769 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_2), (kernel_ulong_t)&rpl_s_cfg},
770 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_3), (kernel_ulong_t)&rpl_s_cfg},
771 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_4), (kernel_ulong_t)&rpl_s_cfg},
772 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_5), (kernel_ulong_t)&rpl_s_cfg},
773 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_6), (kernel_ulong_t)&rpl_s_cfg},
774 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_7), (kernel_ulong_t)&rpl_s_cfg},
775 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_8), (kernel_ulong_t)&rpl_s_cfg},
776 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_9), (kernel_ulong_t)&rpl_s_cfg},
777 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_10), (kernel_ulong_t)&rpl_s_cfg},
778 { 0, } /* 0 terminated list. */
779 };
780 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
781
782 static struct pci_driver ie31200_driver = {
783 .name = EDAC_MOD_STR,
784 .probe = ie31200_init_one,
785 .remove = ie31200_remove_one,
786 .id_table = ie31200_pci_tbl,
787 };
788
ie31200_init(void)789 static int __init ie31200_init(void)
790 {
791 int pci_rc, i;
792
793 edac_dbg(3, "MC:\n");
794
795 pci_rc = pci_register_driver(&ie31200_driver);
796 if (pci_rc < 0)
797 return pci_rc;
798
799 if (!mci_pdev) {
800 ie31200_registered = 0;
801 for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) {
802 mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor,
803 ie31200_pci_tbl[i].device,
804 NULL);
805 if (mci_pdev)
806 break;
807 }
808
809 if (!mci_pdev) {
810 edac_dbg(0, "ie31200 pci_get_device fail\n");
811 pci_rc = -ENODEV;
812 goto fail0;
813 }
814
815 pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]);
816 if (pci_rc < 0) {
817 edac_dbg(0, "ie31200 init fail\n");
818 pci_rc = -ENODEV;
819 goto fail1;
820 }
821 }
822
823 return 0;
824 fail1:
825 pci_dev_put(mci_pdev);
826 fail0:
827 pci_unregister_driver(&ie31200_driver);
828
829 return pci_rc;
830 }
831
ie31200_exit(void)832 static void __exit ie31200_exit(void)
833 {
834 edac_dbg(3, "MC:\n");
835 pci_unregister_driver(&ie31200_driver);
836 if (!ie31200_registered)
837 ie31200_remove_one(mci_pdev);
838 }
839
840 module_init(ie31200_init);
841 module_exit(ie31200_exit);
842
843 MODULE_LICENSE("GPL");
844 MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>");
845 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers");
846