1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2023 Intel Corporation */
3
4 #include "idpf.h"
5 #include "idpf_lan_pf_regs.h"
6 #include "idpf_virtchnl.h"
7 #include "idpf_ptp.h"
8
9 #define IDPF_PF_ITR_IDX_SPACING 0x4
10
11 /**
12 * idpf_ctlq_reg_init - initialize default mailbox registers
13 * @adapter: adapter structure
14 * @cq: pointer to the array of create control queues
15 */
idpf_ctlq_reg_init(struct idpf_adapter * adapter,struct idpf_ctlq_create_info * cq)16 static void idpf_ctlq_reg_init(struct idpf_adapter *adapter,
17 struct idpf_ctlq_create_info *cq)
18 {
19 resource_size_t mbx_start = adapter->dev_ops.static_reg_info[0].start;
20 int i;
21
22 for (i = 0; i < IDPF_NUM_DFLT_MBX_Q; i++) {
23 struct idpf_ctlq_create_info *ccq = cq + i;
24
25 switch (ccq->type) {
26 case IDPF_CTLQ_TYPE_MAILBOX_TX:
27 /* set head and tail registers in our local struct */
28 ccq->reg.head = PF_FW_ATQH - mbx_start;
29 ccq->reg.tail = PF_FW_ATQT - mbx_start;
30 ccq->reg.len = PF_FW_ATQLEN - mbx_start;
31 ccq->reg.bah = PF_FW_ATQBAH - mbx_start;
32 ccq->reg.bal = PF_FW_ATQBAL - mbx_start;
33 ccq->reg.len_mask = PF_FW_ATQLEN_ATQLEN_M;
34 ccq->reg.len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M;
35 ccq->reg.head_mask = PF_FW_ATQH_ATQH_M;
36 break;
37 case IDPF_CTLQ_TYPE_MAILBOX_RX:
38 /* set head and tail registers in our local struct */
39 ccq->reg.head = PF_FW_ARQH - mbx_start;
40 ccq->reg.tail = PF_FW_ARQT - mbx_start;
41 ccq->reg.len = PF_FW_ARQLEN - mbx_start;
42 ccq->reg.bah = PF_FW_ARQBAH - mbx_start;
43 ccq->reg.bal = PF_FW_ARQBAL - mbx_start;
44 ccq->reg.len_mask = PF_FW_ARQLEN_ARQLEN_M;
45 ccq->reg.len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M;
46 ccq->reg.head_mask = PF_FW_ARQH_ARQH_M;
47 break;
48 default:
49 break;
50 }
51 }
52 }
53
54 /**
55 * idpf_mb_intr_reg_init - Initialize mailbox interrupt register
56 * @adapter: adapter structure
57 */
idpf_mb_intr_reg_init(struct idpf_adapter * adapter)58 static void idpf_mb_intr_reg_init(struct idpf_adapter *adapter)
59 {
60 struct idpf_intr_reg *intr = &adapter->mb_vector.intr_reg;
61 u32 dyn_ctl = le32_to_cpu(adapter->caps.mailbox_dyn_ctl);
62
63 intr->dyn_ctl = idpf_get_reg_addr(adapter, dyn_ctl);
64 intr->dyn_ctl_intena_m = PF_GLINT_DYN_CTL_INTENA_M;
65 intr->dyn_ctl_itridx_m = PF_GLINT_DYN_CTL_ITR_INDX_M;
66 intr->icr_ena = idpf_get_reg_addr(adapter, PF_INT_DIR_OICR_ENA);
67 intr->icr_ena_ctlq_m = PF_INT_DIR_OICR_ENA_M;
68 }
69
70 /**
71 * idpf_intr_reg_init - Initialize interrupt registers
72 * @vport: virtual port structure
73 */
idpf_intr_reg_init(struct idpf_vport * vport)74 static int idpf_intr_reg_init(struct idpf_vport *vport)
75 {
76 struct idpf_adapter *adapter = vport->adapter;
77 int num_vecs = vport->num_q_vectors;
78 struct idpf_vec_regs *reg_vals;
79 int num_regs, i, err = 0;
80 u32 rx_itr, tx_itr;
81 u16 total_vecs;
82
83 total_vecs = idpf_get_reserved_vecs(vport->adapter);
84 reg_vals = kcalloc(total_vecs, sizeof(struct idpf_vec_regs),
85 GFP_KERNEL);
86 if (!reg_vals)
87 return -ENOMEM;
88
89 num_regs = idpf_get_reg_intr_vecs(vport, reg_vals);
90 if (num_regs < num_vecs) {
91 err = -EINVAL;
92 goto free_reg_vals;
93 }
94
95 for (i = 0; i < num_vecs; i++) {
96 struct idpf_q_vector *q_vector = &vport->q_vectors[i];
97 u16 vec_id = vport->q_vector_idxs[i] - IDPF_MBX_Q_VEC;
98 struct idpf_intr_reg *intr = &q_vector->intr_reg;
99 u32 spacing;
100
101 intr->dyn_ctl = idpf_get_reg_addr(adapter,
102 reg_vals[vec_id].dyn_ctl_reg);
103 intr->dyn_ctl_intena_m = PF_GLINT_DYN_CTL_INTENA_M;
104 intr->dyn_ctl_intena_msk_m = PF_GLINT_DYN_CTL_INTENA_MSK_M;
105 intr->dyn_ctl_itridx_s = PF_GLINT_DYN_CTL_ITR_INDX_S;
106 intr->dyn_ctl_intrvl_s = PF_GLINT_DYN_CTL_INTERVAL_S;
107 intr->dyn_ctl_wb_on_itr_m = PF_GLINT_DYN_CTL_WB_ON_ITR_M;
108 intr->dyn_ctl_swint_trig_m = PF_GLINT_DYN_CTL_SWINT_TRIG_M;
109 intr->dyn_ctl_sw_itridx_ena_m =
110 PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_M;
111
112 spacing = IDPF_ITR_IDX_SPACING(reg_vals[vec_id].itrn_index_spacing,
113 IDPF_PF_ITR_IDX_SPACING);
114 rx_itr = PF_GLINT_ITR_ADDR(VIRTCHNL2_ITR_IDX_0,
115 reg_vals[vec_id].itrn_reg,
116 spacing);
117 tx_itr = PF_GLINT_ITR_ADDR(VIRTCHNL2_ITR_IDX_1,
118 reg_vals[vec_id].itrn_reg,
119 spacing);
120 intr->rx_itr = idpf_get_reg_addr(adapter, rx_itr);
121 intr->tx_itr = idpf_get_reg_addr(adapter, tx_itr);
122 }
123
124 free_reg_vals:
125 kfree(reg_vals);
126
127 return err;
128 }
129
130 /**
131 * idpf_reset_reg_init - Initialize reset registers
132 * @adapter: Driver specific private structure
133 */
idpf_reset_reg_init(struct idpf_adapter * adapter)134 static void idpf_reset_reg_init(struct idpf_adapter *adapter)
135 {
136 adapter->reset_reg.rstat = idpf_get_rstat_reg_addr(adapter, PFGEN_RSTAT);
137 adapter->reset_reg.rstat_m = PFGEN_RSTAT_PFR_STATE_M;
138 }
139
140 /**
141 * idpf_trigger_reset - trigger reset
142 * @adapter: Driver specific private structure
143 * @trig_cause: Reason to trigger a reset
144 */
idpf_trigger_reset(struct idpf_adapter * adapter,enum idpf_flags __always_unused trig_cause)145 static void idpf_trigger_reset(struct idpf_adapter *adapter,
146 enum idpf_flags __always_unused trig_cause)
147 {
148 u32 reset_reg;
149
150 reset_reg = readl(idpf_get_rstat_reg_addr(adapter, PFGEN_CTRL));
151 writel(reset_reg | PFGEN_CTRL_PFSWR,
152 idpf_get_rstat_reg_addr(adapter, PFGEN_CTRL));
153 }
154
155 /**
156 * idpf_ptp_reg_init - Initialize required registers
157 * @adapter: Driver specific private structure
158 *
159 * Set the bits required for enabling shtime and cmd execution
160 */
idpf_ptp_reg_init(const struct idpf_adapter * adapter)161 static void idpf_ptp_reg_init(const struct idpf_adapter *adapter)
162 {
163 adapter->ptp->cmd.shtime_enable_mask = PF_GLTSYN_CMD_SYNC_SHTIME_EN_M;
164 adapter->ptp->cmd.exec_cmd_mask = PF_GLTSYN_CMD_SYNC_EXEC_CMD_M;
165 }
166
167 /**
168 * idpf_idc_register - register for IDC callbacks
169 * @adapter: Driver specific private structure
170 *
171 * Return: 0 on success or error code on failure.
172 */
idpf_idc_register(struct idpf_adapter * adapter)173 static int idpf_idc_register(struct idpf_adapter *adapter)
174 {
175 return idpf_idc_init_aux_core_dev(adapter, IIDC_FUNCTION_TYPE_PF);
176 }
177
178 /**
179 * idpf_reg_ops_init - Initialize register API function pointers
180 * @adapter: Driver specific private structure
181 */
idpf_reg_ops_init(struct idpf_adapter * adapter)182 static void idpf_reg_ops_init(struct idpf_adapter *adapter)
183 {
184 adapter->dev_ops.reg_ops.ctlq_reg_init = idpf_ctlq_reg_init;
185 adapter->dev_ops.reg_ops.intr_reg_init = idpf_intr_reg_init;
186 adapter->dev_ops.reg_ops.mb_intr_reg_init = idpf_mb_intr_reg_init;
187 adapter->dev_ops.reg_ops.reset_reg_init = idpf_reset_reg_init;
188 adapter->dev_ops.reg_ops.trigger_reset = idpf_trigger_reset;
189 adapter->dev_ops.reg_ops.ptp_reg_init = idpf_ptp_reg_init;
190 }
191
192 /**
193 * idpf_dev_ops_init - Initialize device API function pointers
194 * @adapter: Driver specific private structure
195 */
idpf_dev_ops_init(struct idpf_adapter * adapter)196 void idpf_dev_ops_init(struct idpf_adapter *adapter)
197 {
198 idpf_reg_ops_init(adapter);
199
200 adapter->dev_ops.idc_init = idpf_idc_register;
201
202 resource_set_range(&adapter->dev_ops.static_reg_info[0],
203 PF_FW_BASE, IDPF_PF_MBX_REGION_SZ);
204 resource_set_range(&adapter->dev_ops.static_reg_info[1],
205 PFGEN_RTRIG, IDPF_PF_RSTAT_REGION_SZ);
206 }
207