1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/error-injection.h> 26 27 #include <drm/drm_color_mgmt.h> 28 #include <drm/drm_drv.h> 29 #include <drm/intel/pci_config.h> 30 #include <drm/intel/pciids.h> 31 32 #include "display/intel_display_driver.h" 33 #include "gt/intel_gt_regs.h" 34 #include "gt/intel_sa_media.h" 35 #include "gem/i915_gem_object_types.h" 36 37 #include "i915_driver.h" 38 #include "i915_drv.h" 39 #include "i915_pci.h" 40 #include "i915_reg.h" 41 42 __diag_push(); 43 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for device info"); 44 45 #define PLATFORM(x) .platform = (x) 46 #define GEN(x) \ 47 .__runtime.graphics.ip.ver = (x), \ 48 .__runtime.media.ip.ver = (x) 49 50 #define LEGACY_CACHELEVEL \ 51 .cachelevel_to_pat = { \ 52 [I915_CACHE_NONE] = 0, \ 53 [I915_CACHE_LLC] = 1, \ 54 [I915_CACHE_L3_LLC] = 2, \ 55 [I915_CACHE_WT] = 3, \ 56 } 57 58 #define TGL_CACHELEVEL \ 59 .cachelevel_to_pat = { \ 60 [I915_CACHE_NONE] = 3, \ 61 [I915_CACHE_LLC] = 0, \ 62 [I915_CACHE_L3_LLC] = 0, \ 63 [I915_CACHE_WT] = 2, \ 64 } 65 66 #define MTL_CACHELEVEL \ 67 .cachelevel_to_pat = { \ 68 [I915_CACHE_NONE] = 2, \ 69 [I915_CACHE_LLC] = 3, \ 70 [I915_CACHE_L3_LLC] = 3, \ 71 [I915_CACHE_WT] = 1, \ 72 } 73 74 /* Keep in gen based order, and chronological order within a gen */ 75 76 #define GEN_DEFAULT_PAGE_SIZES \ 77 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K 78 79 #define GEN_DEFAULT_REGIONS \ 80 .memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_STOLEN_SMEM) 81 82 #define I830_FEATURES \ 83 GEN(2), \ 84 .is_mobile = 1, \ 85 .gpu_reset_clobbers_display = true, \ 86 .has_3d_pipeline = 1, \ 87 .hws_needs_physical = 1, \ 88 .unfenced_needs_alignment = 1, \ 89 .platform_engine_mask = BIT(RCS0), \ 90 .has_snoop = true, \ 91 .has_coherent_ggtt = false, \ 92 .dma_mask_size = 32, \ 93 .max_pat_index = 3, \ 94 GEN_DEFAULT_PAGE_SIZES, \ 95 GEN_DEFAULT_REGIONS, \ 96 LEGACY_CACHELEVEL 97 98 #define I845_FEATURES \ 99 GEN(2), \ 100 .has_3d_pipeline = 1, \ 101 .gpu_reset_clobbers_display = true, \ 102 .hws_needs_physical = 1, \ 103 .unfenced_needs_alignment = 1, \ 104 .platform_engine_mask = BIT(RCS0), \ 105 .has_snoop = true, \ 106 .has_coherent_ggtt = false, \ 107 .dma_mask_size = 32, \ 108 .max_pat_index = 3, \ 109 GEN_DEFAULT_PAGE_SIZES, \ 110 GEN_DEFAULT_REGIONS, \ 111 LEGACY_CACHELEVEL 112 113 static const struct intel_device_info i830_info = { 114 I830_FEATURES, 115 PLATFORM(INTEL_I830), 116 }; 117 118 static const struct intel_device_info i845g_info = { 119 I845_FEATURES, 120 PLATFORM(INTEL_I845G), 121 }; 122 123 static const struct intel_device_info i85x_info = { 124 I830_FEATURES, 125 PLATFORM(INTEL_I85X), 126 }; 127 128 static const struct intel_device_info i865g_info = { 129 I845_FEATURES, 130 PLATFORM(INTEL_I865G), 131 }; 132 133 #define GEN3_FEATURES \ 134 GEN(3), \ 135 .gpu_reset_clobbers_display = true, \ 136 .platform_engine_mask = BIT(RCS0), \ 137 .has_3d_pipeline = 1, \ 138 .has_snoop = true, \ 139 .has_coherent_ggtt = true, \ 140 .dma_mask_size = 32, \ 141 .max_pat_index = 3, \ 142 GEN_DEFAULT_PAGE_SIZES, \ 143 GEN_DEFAULT_REGIONS, \ 144 LEGACY_CACHELEVEL 145 146 static const struct intel_device_info i915g_info = { 147 GEN3_FEATURES, 148 PLATFORM(INTEL_I915G), 149 .has_coherent_ggtt = false, 150 .hws_needs_physical = 1, 151 .unfenced_needs_alignment = 1, 152 }; 153 154 static const struct intel_device_info i915gm_info = { 155 GEN3_FEATURES, 156 PLATFORM(INTEL_I915GM), 157 .is_mobile = 1, 158 .hws_needs_physical = 1, 159 .unfenced_needs_alignment = 1, 160 }; 161 162 static const struct intel_device_info i945g_info = { 163 GEN3_FEATURES, 164 PLATFORM(INTEL_I945G), 165 .hws_needs_physical = 1, 166 .unfenced_needs_alignment = 1, 167 }; 168 169 static const struct intel_device_info i945gm_info = { 170 GEN3_FEATURES, 171 PLATFORM(INTEL_I945GM), 172 .is_mobile = 1, 173 .hws_needs_physical = 1, 174 .unfenced_needs_alignment = 1, 175 }; 176 177 static const struct intel_device_info g33_info = { 178 GEN3_FEATURES, 179 PLATFORM(INTEL_G33), 180 .dma_mask_size = 36, 181 }; 182 183 static const struct intel_device_info pnv_g_info = { 184 GEN3_FEATURES, 185 PLATFORM(INTEL_PINEVIEW), 186 .dma_mask_size = 36, 187 }; 188 189 static const struct intel_device_info pnv_m_info = { 190 GEN3_FEATURES, 191 PLATFORM(INTEL_PINEVIEW), 192 .is_mobile = 1, 193 .dma_mask_size = 36, 194 }; 195 196 #define GEN4_FEATURES \ 197 GEN(4), \ 198 .gpu_reset_clobbers_display = true, \ 199 .platform_engine_mask = BIT(RCS0), \ 200 .has_3d_pipeline = 1, \ 201 .has_snoop = true, \ 202 .has_coherent_ggtt = true, \ 203 .dma_mask_size = 36, \ 204 .max_pat_index = 3, \ 205 GEN_DEFAULT_PAGE_SIZES, \ 206 GEN_DEFAULT_REGIONS, \ 207 LEGACY_CACHELEVEL 208 209 static const struct intel_device_info i965g_info = { 210 GEN4_FEATURES, 211 PLATFORM(INTEL_I965G), 212 .hws_needs_physical = 1, 213 .has_snoop = false, 214 }; 215 216 static const struct intel_device_info i965gm_info = { 217 GEN4_FEATURES, 218 PLATFORM(INTEL_I965GM), 219 .is_mobile = 1, 220 .hws_needs_physical = 1, 221 .has_snoop = false, 222 }; 223 224 static const struct intel_device_info g45_info = { 225 GEN4_FEATURES, 226 PLATFORM(INTEL_G45), 227 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 228 .gpu_reset_clobbers_display = false, 229 }; 230 231 static const struct intel_device_info gm45_info = { 232 GEN4_FEATURES, 233 PLATFORM(INTEL_GM45), 234 .is_mobile = 1, 235 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 236 .gpu_reset_clobbers_display = false, 237 }; 238 239 #define GEN5_FEATURES \ 240 GEN(5), \ 241 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 242 .has_3d_pipeline = 1, \ 243 .has_snoop = true, \ 244 .has_coherent_ggtt = true, \ 245 /* ilk does support rc6, but we do not implement [power] contexts */ \ 246 .has_rc6 = 0, \ 247 .dma_mask_size = 36, \ 248 .max_pat_index = 3, \ 249 GEN_DEFAULT_PAGE_SIZES, \ 250 GEN_DEFAULT_REGIONS, \ 251 LEGACY_CACHELEVEL 252 253 static const struct intel_device_info ilk_d_info = { 254 GEN5_FEATURES, 255 PLATFORM(INTEL_IRONLAKE), 256 }; 257 258 static const struct intel_device_info ilk_m_info = { 259 GEN5_FEATURES, 260 PLATFORM(INTEL_IRONLAKE), 261 .is_mobile = 1, 262 .has_rps = true, 263 }; 264 265 #define GEN6_FEATURES \ 266 GEN(6), \ 267 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 268 .has_3d_pipeline = 1, \ 269 .has_coherent_ggtt = true, \ 270 .has_llc = 1, \ 271 .has_rc6 = 1, \ 272 /* snb does support rc6p, but enabling it causes various issues */ \ 273 .has_rc6p = 0, \ 274 .has_rps = true, \ 275 .dma_mask_size = 40, \ 276 .max_pat_index = 3, \ 277 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 278 .__runtime.ppgtt_size = 31, \ 279 GEN_DEFAULT_PAGE_SIZES, \ 280 GEN_DEFAULT_REGIONS, \ 281 LEGACY_CACHELEVEL 282 283 #define SNB_D_PLATFORM \ 284 GEN6_FEATURES, \ 285 PLATFORM(INTEL_SANDYBRIDGE) 286 287 static const struct intel_device_info snb_d_gt1_info = { 288 SNB_D_PLATFORM, 289 .gt = 1, 290 }; 291 292 static const struct intel_device_info snb_d_gt2_info = { 293 SNB_D_PLATFORM, 294 .gt = 2, 295 }; 296 297 #define SNB_M_PLATFORM \ 298 GEN6_FEATURES, \ 299 PLATFORM(INTEL_SANDYBRIDGE), \ 300 .is_mobile = 1 301 302 303 static const struct intel_device_info snb_m_gt1_info = { 304 SNB_M_PLATFORM, 305 .gt = 1, 306 }; 307 308 static const struct intel_device_info snb_m_gt2_info = { 309 SNB_M_PLATFORM, 310 .gt = 2, 311 }; 312 313 #define GEN7_FEATURES \ 314 GEN(7), \ 315 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 316 .has_3d_pipeline = 1, \ 317 .has_coherent_ggtt = true, \ 318 .has_llc = 1, \ 319 .has_rc6 = 1, \ 320 .has_rc6p = 1, \ 321 .has_reset_engine = true, \ 322 .has_rps = true, \ 323 .dma_mask_size = 40, \ 324 .max_pat_index = 3, \ 325 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 326 .__runtime.ppgtt_size = 31, \ 327 GEN_DEFAULT_PAGE_SIZES, \ 328 GEN_DEFAULT_REGIONS, \ 329 LEGACY_CACHELEVEL 330 331 #define IVB_D_PLATFORM \ 332 GEN7_FEATURES, \ 333 PLATFORM(INTEL_IVYBRIDGE), \ 334 .has_l3_dpf = 1 335 336 static const struct intel_device_info ivb_d_gt1_info = { 337 IVB_D_PLATFORM, 338 .gt = 1, 339 }; 340 341 static const struct intel_device_info ivb_d_gt2_info = { 342 IVB_D_PLATFORM, 343 .gt = 2, 344 }; 345 346 #define IVB_M_PLATFORM \ 347 GEN7_FEATURES, \ 348 PLATFORM(INTEL_IVYBRIDGE), \ 349 .is_mobile = 1, \ 350 .has_l3_dpf = 1 351 352 static const struct intel_device_info ivb_m_gt1_info = { 353 IVB_M_PLATFORM, 354 .gt = 1, 355 }; 356 357 static const struct intel_device_info ivb_m_gt2_info = { 358 IVB_M_PLATFORM, 359 .gt = 2, 360 }; 361 362 static const struct intel_device_info ivb_q_info = { 363 GEN7_FEATURES, 364 PLATFORM(INTEL_IVYBRIDGE), 365 .gt = 2, 366 .has_l3_dpf = 1, 367 }; 368 369 static const struct intel_device_info vlv_info = { 370 PLATFORM(INTEL_VALLEYVIEW), 371 GEN(7), 372 .has_runtime_pm = 1, 373 .has_rc6 = 1, 374 .has_reset_engine = true, 375 .has_rps = true, 376 .dma_mask_size = 40, 377 .max_pat_index = 3, 378 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, 379 .__runtime.ppgtt_size = 31, 380 .has_snoop = true, 381 .has_coherent_ggtt = false, 382 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 383 GEN_DEFAULT_PAGE_SIZES, 384 GEN_DEFAULT_REGIONS, 385 LEGACY_CACHELEVEL, 386 }; 387 388 #define G75_FEATURES \ 389 GEN7_FEATURES, \ 390 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 391 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 392 .has_runtime_pm = 1 393 394 #define HSW_PLATFORM \ 395 G75_FEATURES, \ 396 PLATFORM(INTEL_HASWELL), \ 397 .has_l3_dpf = 1 398 399 static const struct intel_device_info hsw_gt1_info = { 400 HSW_PLATFORM, 401 .gt = 1, 402 }; 403 404 static const struct intel_device_info hsw_gt2_info = { 405 HSW_PLATFORM, 406 .gt = 2, 407 }; 408 409 static const struct intel_device_info hsw_gt3_info = { 410 HSW_PLATFORM, 411 .gt = 3, 412 }; 413 414 #define GEN8_FEATURES \ 415 G75_FEATURES, \ 416 GEN(8), \ 417 .has_logical_ring_contexts = 1, \ 418 .dma_mask_size = 39, \ 419 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 420 .__runtime.ppgtt_size = 48, \ 421 .has_64bit_reloc = 1 422 423 #define BDW_PLATFORM \ 424 GEN8_FEATURES, \ 425 PLATFORM(INTEL_BROADWELL) 426 427 static const struct intel_device_info bdw_gt1_info = { 428 BDW_PLATFORM, 429 .gt = 1, 430 }; 431 432 static const struct intel_device_info bdw_gt2_info = { 433 BDW_PLATFORM, 434 .gt = 2, 435 }; 436 437 static const struct intel_device_info bdw_rsvd_info = { 438 BDW_PLATFORM, 439 .gt = 3, 440 /* According to the device ID those devices are GT3, they were 441 * previously treated as not GT3, keep it like that. 442 */ 443 }; 444 445 static const struct intel_device_info bdw_gt3_info = { 446 BDW_PLATFORM, 447 .gt = 3, 448 .platform_engine_mask = 449 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 450 }; 451 452 static const struct intel_device_info chv_info = { 453 PLATFORM(INTEL_CHERRYVIEW), 454 GEN(8), 455 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 456 .has_64bit_reloc = 1, 457 .has_runtime_pm = 1, 458 .has_rc6 = 1, 459 .has_rps = true, 460 .has_logical_ring_contexts = 1, 461 .dma_mask_size = 39, 462 .max_pat_index = 3, 463 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, 464 .__runtime.ppgtt_size = 32, 465 .has_reset_engine = 1, 466 .has_snoop = true, 467 .has_coherent_ggtt = false, 468 GEN_DEFAULT_PAGE_SIZES, 469 GEN_DEFAULT_REGIONS, 470 LEGACY_CACHELEVEL, 471 }; 472 473 #define GEN9_DEFAULT_PAGE_SIZES \ 474 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 475 I915_GTT_PAGE_SIZE_64K 476 477 #define GEN9_FEATURES \ 478 GEN8_FEATURES, \ 479 GEN(9), \ 480 GEN9_DEFAULT_PAGE_SIZES, \ 481 .has_gt_uc = 1 482 483 #define SKL_PLATFORM \ 484 GEN9_FEATURES, \ 485 PLATFORM(INTEL_SKYLAKE) 486 487 static const struct intel_device_info skl_gt1_info = { 488 SKL_PLATFORM, 489 .gt = 1, 490 }; 491 492 static const struct intel_device_info skl_gt2_info = { 493 SKL_PLATFORM, 494 .gt = 2, 495 }; 496 497 #define SKL_GT3_PLUS_PLATFORM \ 498 SKL_PLATFORM, \ 499 .platform_engine_mask = \ 500 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 501 502 503 static const struct intel_device_info skl_gt3_info = { 504 SKL_GT3_PLUS_PLATFORM, 505 .gt = 3, 506 }; 507 508 static const struct intel_device_info skl_gt4_info = { 509 SKL_GT3_PLUS_PLATFORM, 510 .gt = 4, 511 }; 512 513 #define GEN9_LP_FEATURES \ 514 GEN(9), \ 515 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 516 .has_3d_pipeline = 1, \ 517 .has_64bit_reloc = 1, \ 518 .has_runtime_pm = 1, \ 519 .has_rc6 = 1, \ 520 .has_rps = true, \ 521 .has_logical_ring_contexts = 1, \ 522 .has_gt_uc = 1, \ 523 .dma_mask_size = 39, \ 524 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 525 .__runtime.ppgtt_size = 48, \ 526 .has_reset_engine = 1, \ 527 .has_snoop = true, \ 528 .has_coherent_ggtt = false, \ 529 .max_pat_index = 3, \ 530 GEN9_DEFAULT_PAGE_SIZES, \ 531 GEN_DEFAULT_REGIONS, \ 532 LEGACY_CACHELEVEL 533 534 static const struct intel_device_info bxt_info = { 535 GEN9_LP_FEATURES, 536 PLATFORM(INTEL_BROXTON), 537 }; 538 539 static const struct intel_device_info glk_info = { 540 GEN9_LP_FEATURES, 541 PLATFORM(INTEL_GEMINILAKE), 542 }; 543 544 #define KBL_PLATFORM \ 545 GEN9_FEATURES, \ 546 PLATFORM(INTEL_KABYLAKE) 547 548 static const struct intel_device_info kbl_gt1_info = { 549 KBL_PLATFORM, 550 .gt = 1, 551 }; 552 553 static const struct intel_device_info kbl_gt2_info = { 554 KBL_PLATFORM, 555 .gt = 2, 556 }; 557 558 static const struct intel_device_info kbl_gt3_info = { 559 KBL_PLATFORM, 560 .gt = 3, 561 .platform_engine_mask = 562 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 563 }; 564 565 #define CFL_PLATFORM \ 566 GEN9_FEATURES, \ 567 PLATFORM(INTEL_COFFEELAKE) 568 569 static const struct intel_device_info cfl_gt1_info = { 570 CFL_PLATFORM, 571 .gt = 1, 572 }; 573 574 static const struct intel_device_info cfl_gt2_info = { 575 CFL_PLATFORM, 576 .gt = 2, 577 }; 578 579 static const struct intel_device_info cfl_gt3_info = { 580 CFL_PLATFORM, 581 .gt = 3, 582 .platform_engine_mask = 583 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 584 }; 585 586 #define CML_PLATFORM \ 587 GEN9_FEATURES, \ 588 PLATFORM(INTEL_COMETLAKE) 589 590 static const struct intel_device_info cml_gt1_info = { 591 CML_PLATFORM, 592 .gt = 1, 593 }; 594 595 static const struct intel_device_info cml_gt2_info = { 596 CML_PLATFORM, 597 .gt = 2, 598 }; 599 600 #define GEN11_DEFAULT_PAGE_SIZES \ 601 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 602 I915_GTT_PAGE_SIZE_64K | \ 603 I915_GTT_PAGE_SIZE_2M 604 605 #define GEN11_FEATURES \ 606 GEN9_FEATURES, \ 607 GEN11_DEFAULT_PAGE_SIZES, \ 608 GEN(11), \ 609 .has_coherent_ggtt = false, \ 610 .has_logical_ring_elsq = 1 611 612 static const struct intel_device_info icl_info = { 613 GEN11_FEATURES, 614 PLATFORM(INTEL_ICELAKE), 615 .platform_engine_mask = 616 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 617 }; 618 619 static const struct intel_device_info ehl_info = { 620 GEN11_FEATURES, 621 PLATFORM(INTEL_ELKHARTLAKE), 622 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 623 .__runtime.ppgtt_size = 36, 624 }; 625 626 static const struct intel_device_info jsl_info = { 627 GEN11_FEATURES, 628 PLATFORM(INTEL_JASPERLAKE), 629 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 630 .__runtime.ppgtt_size = 36, 631 }; 632 633 #define GEN12_FEATURES \ 634 GEN11_FEATURES, \ 635 GEN(12), \ 636 TGL_CACHELEVEL, \ 637 .has_global_mocs = 1, \ 638 .has_pxp = 1, \ 639 .max_pat_index = 3 640 641 static const struct intel_device_info tgl_info = { 642 GEN12_FEATURES, 643 PLATFORM(INTEL_TIGERLAKE), 644 .platform_engine_mask = 645 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 646 }; 647 648 static const struct intel_device_info rkl_info = { 649 GEN12_FEATURES, 650 PLATFORM(INTEL_ROCKETLAKE), 651 .platform_engine_mask = 652 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 653 }; 654 655 #define DGFX_FEATURES \ 656 .memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_LMEM_0) | BIT(INTEL_REGION_STOLEN_LMEM), \ 657 .has_llc = 0, \ 658 .has_pxp = 0, \ 659 .has_snoop = 1, \ 660 .is_dgfx = 1, \ 661 .has_heci_gscfi = 1 662 663 static const struct intel_device_info dg1_info = { 664 GEN12_FEATURES, 665 DGFX_FEATURES, 666 .__runtime.graphics.ip.rel = 10, 667 PLATFORM(INTEL_DG1), 668 .platform_engine_mask = 669 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 670 BIT(VCS0) | BIT(VCS2), 671 /* Wa_16011227922 */ 672 .__runtime.ppgtt_size = 47, 673 }; 674 675 static const struct intel_device_info adl_s_info = { 676 GEN12_FEATURES, 677 PLATFORM(INTEL_ALDERLAKE_S), 678 .platform_engine_mask = 679 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 680 .dma_mask_size = 39, 681 }; 682 683 static const struct intel_device_info adl_p_info = { 684 GEN12_FEATURES, 685 PLATFORM(INTEL_ALDERLAKE_P), 686 .platform_engine_mask = 687 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 688 .__runtime.ppgtt_size = 48, 689 .dma_mask_size = 39, 690 }; 691 692 #undef GEN 693 694 #define XE_HP_PAGE_SIZES \ 695 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 696 I915_GTT_PAGE_SIZE_64K | \ 697 I915_GTT_PAGE_SIZE_2M 698 699 #define XE_HP_FEATURES \ 700 XE_HP_PAGE_SIZES, \ 701 TGL_CACHELEVEL, \ 702 .dma_mask_size = 46, \ 703 .has_3d_pipeline = 1, \ 704 .has_64bit_reloc = 1, \ 705 .has_flat_ccs = 1, \ 706 .has_global_mocs = 1, \ 707 .has_gt_uc = 1, \ 708 .has_llc = 1, \ 709 .has_logical_ring_contexts = 1, \ 710 .has_logical_ring_elsq = 1, \ 711 .has_mslice_steering = 1, \ 712 .has_oa_bpc_reporting = 1, \ 713 .has_oa_slice_contrib_limits = 1, \ 714 .has_oam = 1, \ 715 .has_rc6 = 1, \ 716 .has_reset_engine = 1, \ 717 .has_rps = 1, \ 718 .has_runtime_pm = 1, \ 719 .max_pat_index = 3, \ 720 .__runtime.ppgtt_size = 48, \ 721 .__runtime.ppgtt_type = INTEL_PPGTT_FULL 722 723 #define DG2_FEATURES \ 724 XE_HP_FEATURES, \ 725 DGFX_FEATURES, \ 726 .__runtime.graphics.ip.ver = 12, \ 727 .__runtime.graphics.ip.rel = 55, \ 728 .__runtime.media.ip.ver = 12, \ 729 .__runtime.media.ip.rel = 55, \ 730 PLATFORM(INTEL_DG2), \ 731 .has_64k_pages = 1, \ 732 .has_guc_deprivilege = 1, \ 733 .has_heci_pxp = 1, \ 734 .has_media_ratio_mode = 1, \ 735 .platform_engine_mask = \ 736 BIT(RCS0) | BIT(BCS0) | \ 737 BIT(VECS0) | BIT(VECS1) | \ 738 BIT(VCS0) | BIT(VCS2) | \ 739 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3) 740 741 static const struct intel_device_info dg2_info = { 742 DG2_FEATURES, 743 }; 744 745 static const struct intel_device_info ats_m_info = { 746 DG2_FEATURES, 747 .require_force_probe = 1, 748 .tuning_thread_rr_after_dep = 1, 749 }; 750 751 static const struct intel_gt_definition xelpmp_extra_gt[] = { 752 { 753 .type = GT_MEDIA, 754 .name = "Standalone Media GT", 755 .gsi_offset = MTL_MEDIA_GSI_BASE, 756 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0), 757 }, 758 {} 759 }; 760 761 static const struct intel_device_info mtl_info = { 762 XE_HP_FEATURES, 763 /* 764 * Real graphics IP version will be obtained from hardware GMD_ID 765 * register. Value provided here is just for sanity checking. 766 */ 767 .__runtime.graphics.ip.ver = 12, 768 .__runtime.graphics.ip.rel = 70, 769 .__runtime.media.ip.ver = 13, 770 PLATFORM(INTEL_METEORLAKE), 771 .extra_gt_list = xelpmp_extra_gt, 772 .has_flat_ccs = 0, 773 .has_gmd_id = 1, 774 .has_guc_deprivilege = 1, 775 .has_guc_tlb_invalidation = 1, 776 .has_llc = 0, 777 .has_mslice_steering = 0, 778 .has_snoop = 1, 779 .max_pat_index = 4, 780 .has_pxp = 1, 781 .memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_STOLEN_LMEM), 782 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), 783 MTL_CACHELEVEL, 784 }; 785 786 #undef PLATFORM 787 788 __diag_pop(); 789 790 /* 791 * Make sure any device matches here are from most specific to most 792 * general. For example, since the Quanta match is based on the subsystem 793 * and subvendor IDs, we need it to come before the more general IVB 794 * PCI ID matches, otherwise we'll use the wrong info struct above. 795 */ 796 static const struct pci_device_id pciidlist[] = { 797 INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_info), 798 INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845g_info), 799 INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_info), 800 INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_info), 801 INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_info), 802 INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_info), 803 INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_info), 804 INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_info), 805 INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_info), 806 INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_info), 807 INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_info), 808 INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_info), 809 INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_info), 810 INTEL_PNV_G_IDS(INTEL_VGA_DEVICE, &pnv_g_info), 811 INTEL_PNV_M_IDS(INTEL_VGA_DEVICE, &pnv_m_info), 812 INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_info), 813 INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_info), 814 INTEL_SNB_D_GT1_IDS(INTEL_VGA_DEVICE, &snb_d_gt1_info), 815 INTEL_SNB_D_GT2_IDS(INTEL_VGA_DEVICE, &snb_d_gt2_info), 816 INTEL_SNB_M_GT1_IDS(INTEL_VGA_DEVICE, &snb_m_gt1_info), 817 INTEL_SNB_M_GT2_IDS(INTEL_VGA_DEVICE, &snb_m_gt2_info), 818 INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, &ivb_q_info), /* must be first IVB */ 819 INTEL_IVB_M_GT1_IDS(INTEL_VGA_DEVICE, &ivb_m_gt1_info), 820 INTEL_IVB_M_GT2_IDS(INTEL_VGA_DEVICE, &ivb_m_gt2_info), 821 INTEL_IVB_D_GT1_IDS(INTEL_VGA_DEVICE, &ivb_d_gt1_info), 822 INTEL_IVB_D_GT2_IDS(INTEL_VGA_DEVICE, &ivb_d_gt2_info), 823 INTEL_HSW_GT1_IDS(INTEL_VGA_DEVICE, &hsw_gt1_info), 824 INTEL_HSW_GT2_IDS(INTEL_VGA_DEVICE, &hsw_gt2_info), 825 INTEL_HSW_GT3_IDS(INTEL_VGA_DEVICE, &hsw_gt3_info), 826 INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_info), 827 INTEL_BDW_GT1_IDS(INTEL_VGA_DEVICE, &bdw_gt1_info), 828 INTEL_BDW_GT2_IDS(INTEL_VGA_DEVICE, &bdw_gt2_info), 829 INTEL_BDW_GT3_IDS(INTEL_VGA_DEVICE, &bdw_gt3_info), 830 INTEL_BDW_RSVD_IDS(INTEL_VGA_DEVICE, &bdw_rsvd_info), 831 INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_info), 832 INTEL_SKL_GT1_IDS(INTEL_VGA_DEVICE, &skl_gt1_info), 833 INTEL_SKL_GT2_IDS(INTEL_VGA_DEVICE, &skl_gt2_info), 834 INTEL_SKL_GT3_IDS(INTEL_VGA_DEVICE, &skl_gt3_info), 835 INTEL_SKL_GT4_IDS(INTEL_VGA_DEVICE, &skl_gt4_info), 836 INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_info), 837 INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_info), 838 INTEL_KBL_GT1_IDS(INTEL_VGA_DEVICE, &kbl_gt1_info), 839 INTEL_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info), 840 INTEL_KBL_GT3_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info), 841 INTEL_KBL_GT4_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info), 842 INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info), 843 INTEL_CFL_S_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info), 844 INTEL_CFL_S_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), 845 INTEL_CFL_H_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info), 846 INTEL_CFL_H_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), 847 INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), 848 INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info), 849 INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info), 850 INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), 851 INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), 852 INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info), 853 INTEL_CML_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info), 854 INTEL_CML_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info), 855 INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info), 856 INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info), 857 INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_info), 858 INTEL_EHL_IDS(INTEL_VGA_DEVICE, &ehl_info), 859 INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_info), 860 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_info), 861 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_info), 862 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_info), 863 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_info), 864 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_p_info), 865 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_info), 866 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_info), 867 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_info), 868 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_info), 869 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_info), 870 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_info), 871 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_info), 872 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_info), 873 {} 874 }; 875 MODULE_DEVICE_TABLE(pci, pciidlist); 876 877 static void i915_pci_remove(struct pci_dev *pdev) 878 { 879 struct drm_i915_private *i915; 880 881 i915 = pdev_to_i915(pdev); 882 if (!i915) /* driver load aborted, nothing to cleanup */ 883 return; 884 885 i915_driver_remove(i915); 886 pci_set_drvdata(pdev, NULL); 887 } 888 889 /* is device_id present in comma separated list of ids */ 890 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 891 { 892 char *s, *p, *tok; 893 bool ret; 894 895 if (!devices || !*devices) 896 return false; 897 898 /* match everything */ 899 if (negative && strcmp(devices, "!*") == 0) 900 return true; 901 if (!negative && strcmp(devices, "*") == 0) 902 return true; 903 904 s = kstrdup(devices, GFP_KERNEL); 905 if (!s) 906 return false; 907 908 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 909 u16 val; 910 911 if (negative && tok[0] == '!') 912 tok++; 913 else if ((negative && tok[0] != '!') || 914 (!negative && tok[0] == '!')) 915 continue; 916 917 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 918 ret = true; 919 break; 920 } 921 } 922 923 kfree(s); 924 925 return ret; 926 } 927 928 static bool id_forced(u16 device_id) 929 { 930 return device_id_in_list(device_id, i915_modparams.force_probe, false); 931 } 932 933 static bool id_blocked(u16 device_id) 934 { 935 return device_id_in_list(device_id, i915_modparams.force_probe, true); 936 } 937 938 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar) 939 { 940 if (!pci_resource_flags(pdev, bar)) 941 return false; 942 943 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 944 return false; 945 946 if (!pci_resource_len(pdev, bar)) 947 return false; 948 949 return true; 950 } 951 952 static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info) 953 { 954 return i915_pci_resource_valid(pdev, intel_mmio_bar(intel_info->__runtime.graphics.ip.ver)); 955 } 956 957 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 958 { 959 struct intel_device_info *intel_info = 960 (struct intel_device_info *) ent->driver_data; 961 int err; 962 963 if (!intel_info) 964 return -ENODEV; 965 966 if (intel_info->require_force_probe && !id_forced(pdev->device)) { 967 dev_info(&pdev->dev, 968 "Your graphics device %04x is not properly supported by i915 in this\n" 969 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 970 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 971 "or (recommended) check for kernel updates.\n", 972 pdev->device, pdev->device, pdev->device); 973 return -ENODEV; 974 } 975 976 if (id_blocked(pdev->device)) { 977 dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n", 978 pdev->device); 979 return -ENODEV; 980 } 981 982 if (intel_info->require_force_probe) { 983 dev_info(&pdev->dev, "Force probing unsupported Device ID %04x, tainting kernel\n", 984 pdev->device); 985 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 986 } 987 988 /* Only bind to function 0 of the device. Early generations 989 * used function 1 as a placeholder for multi-head. This causes 990 * us confusion instead, especially on the systems where both 991 * functions have the same PCI-ID! 992 */ 993 if (PCI_FUNC(pdev->devfn)) 994 return -ENODEV; 995 996 if (!intel_mmio_bar_valid(pdev, intel_info)) 997 return -ENXIO; 998 999 /* Detect if we need to wait for other drivers early on */ 1000 if (intel_display_driver_probe_defer(pdev)) 1001 return -EPROBE_DEFER; 1002 1003 err = i915_driver_probe(pdev, ent); 1004 if (err) 1005 return err; 1006 1007 err = i915_live_selftests(pdev); 1008 if (err) { 1009 i915_pci_remove(pdev); 1010 return err > 0 ? -ENOTTY : err; 1011 } 1012 1013 err = i915_perf_selftests(pdev); 1014 if (err) { 1015 i915_pci_remove(pdev); 1016 return err > 0 ? -ENOTTY : err; 1017 } 1018 1019 return 0; 1020 } 1021 ALLOW_ERROR_INJECTION(i915_pci_probe, ERRNO); 1022 1023 static void i915_pci_shutdown(struct pci_dev *pdev) 1024 { 1025 struct drm_i915_private *i915 = pdev_to_i915(pdev); 1026 1027 i915_driver_shutdown(i915); 1028 } 1029 1030 static struct pci_driver i915_pci_driver = { 1031 .name = DRIVER_NAME, 1032 .id_table = pciidlist, 1033 .probe = i915_pci_probe, 1034 .remove = i915_pci_remove, 1035 .shutdown = i915_pci_shutdown, 1036 .driver.pm = &i915_pm_ops, 1037 }; 1038 1039 int i915_pci_register_driver(void) 1040 { 1041 return pci_register_driver(&i915_pci_driver); 1042 } 1043 1044 void i915_pci_unregister_driver(void) 1045 { 1046 pci_unregister_driver(&i915_pci_driver); 1047 } 1048