1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Intel Corporation. */
3
4 #include <linux/vmalloc.h>
5
6 #include "ice_common.h"
7
8 /**
9 * ice_aq_read_nvm
10 * @hw: pointer to the HW struct
11 * @module_typeid: module pointer location in words from the NVM beginning
12 * @offset: byte offset from the module beginning
13 * @length: length of the section to be read (in bytes from the offset)
14 * @data: command buffer (size [bytes] = length)
15 * @last_command: tells if this is the last command in a series
16 * @read_shadow_ram: tell if this is a shadow RAM read
17 * @cd: pointer to command details structure or NULL
18 *
19 * Read the NVM using the admin queue commands (0x0701)
20 */
ice_aq_read_nvm(struct ice_hw * hw,u16 module_typeid,u32 offset,u16 length,void * data,bool last_command,bool read_shadow_ram,struct ice_sq_cd * cd)21 int ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
22 u16 length, void *data, bool last_command,
23 bool read_shadow_ram, struct ice_sq_cd *cd)
24 {
25 struct libie_aq_desc desc;
26 struct ice_aqc_nvm *cmd;
27
28 cmd = libie_aq_raw(&desc);
29
30 if (offset > ICE_AQC_NVM_MAX_OFFSET)
31 return -EINVAL;
32
33 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
34
35 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
36 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
37
38 /* If this is the last command in a series, set the proper flag. */
39 if (last_command)
40 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
41 cmd->module_typeid = cpu_to_le16(module_typeid);
42 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
43 cmd->offset_high = (offset >> 16) & 0xFF;
44 cmd->length = cpu_to_le16(length);
45
46 return ice_aq_send_cmd(hw, &desc, data, length, cd);
47 }
48
49 /**
50 * ice_read_flat_nvm - Read portion of NVM by flat offset
51 * @hw: pointer to the HW struct
52 * @offset: offset from beginning of NVM
53 * @length: (in) number of bytes to read; (out) number of bytes actually read
54 * @data: buffer to return data in (sized to fit the specified length)
55 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
56 * @read_aq_err: if non-NULL, receives the AQ error status of the failing read
57 *
58 * Reads a portion of the NVM, as a flat memory space. This function correctly
59 * breaks read requests across Shadow RAM sectors and ensures that no single
60 * read request exceeds the maximum 4KB read for a single AdminQ command.
61 *
62 * FW caps the read lock at a maximum of 3000ms, so a read spanning multiple
63 * 4KB sectors cannot be done under a single lock without FW reclaiming it
64 * mid-read. The NVM lock is therefore acquired and released around each AQ
65 * read, so this function must be called without the lock held.
66 *
67 * Since ice_release_nvm() issues an AQ command that overwrites
68 * hw->adminq.sq_last_status, callers that need the failing read's AQ error
69 * must use @read_aq_err rather than inspecting sq_last_status afterwards.
70 *
71 * Returns a status code on failure. Note that the data pointer may be
72 * partially updated if some reads succeed before a failure.
73 */
74 int
ice_read_flat_nvm(struct ice_hw * hw,u32 offset,u32 * length,u8 * data,bool read_shadow_ram,enum libie_aq_err * read_aq_err)75 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
76 bool read_shadow_ram, enum libie_aq_err *read_aq_err)
77 {
78 u32 inlen = *length;
79 u32 bytes_read = 0;
80 bool last_cmd;
81 int status;
82
83 *length = 0;
84
85 /* Verify the length of the read if this is for the Shadow RAM */
86 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
87 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested offset is beyond Shadow RAM limit\n");
88 return -EINVAL;
89 }
90
91 do {
92 u32 read_size, sector_offset;
93
94 /* ice_aq_read_nvm cannot read more than 4KB at a time.
95 * Additionally, a read from the Shadow RAM may not cross over
96 * a sector boundary. Conveniently, the sector size is also
97 * 4KB.
98 */
99 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
100 read_size = min_t(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
101 inlen - bytes_read);
102
103 last_cmd = !(bytes_read + read_size < inlen);
104
105 status = ice_acquire_nvm(hw, ICE_RES_READ);
106 if (status) {
107 ice_debug(hw, ICE_DBG_NVM, "Failed to acquire NVM lock, err %d aq_err %s\n",
108 status, libie_aq_str(hw->adminq.sq_last_status));
109 break;
110 }
111
112 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
113 offset, read_size,
114 data + bytes_read, last_cmd,
115 read_shadow_ram, NULL);
116 if (status) {
117 /* Capture the read's AQ error before ice_release_nvm()
118 * issues its own AQ command and overwrites
119 * sq_last_status.
120 */
121 if (read_aq_err)
122 *read_aq_err = hw->adminq.sq_last_status;
123
124 ice_release_nvm(hw);
125 break;
126 }
127
128 ice_release_nvm(hw);
129
130 bytes_read += read_size;
131 offset += read_size;
132 } while (!last_cmd);
133
134 *length = bytes_read;
135 return status;
136 }
137
138 /**
139 * ice_aq_update_nvm
140 * @hw: pointer to the HW struct
141 * @module_typeid: module pointer location in words from the NVM beginning
142 * @offset: byte offset from the module beginning
143 * @length: length of the section to be written (in bytes from the offset)
144 * @data: command buffer (size [bytes] = length)
145 * @last_command: tells if this is the last command in a series
146 * @command_flags: command parameters
147 * @cd: pointer to command details structure or NULL
148 *
149 * Update the NVM using the admin queue commands (0x0703)
150 */
151 int
ice_aq_update_nvm(struct ice_hw * hw,u16 module_typeid,u32 offset,u16 length,void * data,bool last_command,u8 command_flags,struct ice_sq_cd * cd)152 ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
153 u16 length, void *data, bool last_command, u8 command_flags,
154 struct ice_sq_cd *cd)
155 {
156 struct libie_aq_desc desc;
157 struct ice_aqc_nvm *cmd;
158
159 cmd = libie_aq_raw(&desc);
160
161 /* In offset the highest byte must be zeroed. */
162 if (offset & 0xFF000000)
163 return -EINVAL;
164
165 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write);
166
167 cmd->cmd_flags |= command_flags;
168
169 /* If this is the last command in a series, set the proper flag. */
170 if (last_command)
171 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
172 cmd->module_typeid = cpu_to_le16(module_typeid);
173 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
174 cmd->offset_high = (offset >> 16) & 0xFF;
175 cmd->length = cpu_to_le16(length);
176
177 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
178
179 return ice_aq_send_cmd(hw, &desc, data, length, cd);
180 }
181
182 /**
183 * ice_aq_erase_nvm
184 * @hw: pointer to the HW struct
185 * @module_typeid: module pointer location in words from the NVM beginning
186 * @cd: pointer to command details structure or NULL
187 *
188 * Erase the NVM sector using the admin queue commands (0x0702)
189 */
ice_aq_erase_nvm(struct ice_hw * hw,u16 module_typeid,struct ice_sq_cd * cd)190 int ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd)
191 {
192 struct libie_aq_desc desc;
193 struct ice_aqc_nvm *cmd;
194
195 cmd = libie_aq_raw(&desc);
196
197 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_erase);
198
199 cmd->module_typeid = cpu_to_le16(module_typeid);
200 cmd->length = cpu_to_le16(ICE_AQC_NVM_ERASE_LEN);
201 cmd->offset_low = 0;
202 cmd->offset_high = 0;
203
204 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
205 }
206
207 /**
208 * ice_read_sr_word - Reads Shadow RAM word
209 * @hw: pointer to the HW structure
210 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
211 * @data: word read from the Shadow RAM
212 *
213 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
214 *
215 * The NVM lock is acquired and released internally by ice_read_flat_nvm()
216 * around the FW read, so this function must be called without the lock held.
217 *
218 * Return: zero on success, or a negative error code on failure.
219 */
ice_read_sr_word(struct ice_hw * hw,u16 offset,u16 * data)220 int ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
221 {
222 u32 bytes = sizeof(u16);
223 __le16 data_local;
224 int status;
225
226 /* Note that ice_read_flat_nvm takes into account the 4Kb AdminQ and
227 * Shadow RAM sector restrictions necessary when reading from the NVM.
228 */
229 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
230 (__force u8 *)&data_local, true, NULL);
231 if (status)
232 return status;
233
234 *data = le16_to_cpu(data_local);
235 return 0;
236 }
237
238 /**
239 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
240 * @hw: pointer to the HW structure
241 * @access: NVM access type (read or write)
242 *
243 * This function will request NVM ownership.
244 */
ice_acquire_nvm(struct ice_hw * hw,enum ice_aq_res_access_type access)245 int ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
246 {
247 if (hw->flash.blank_nvm_mode)
248 return 0;
249
250 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
251 }
252
253 /**
254 * ice_release_nvm - Generic request for releasing the NVM ownership
255 * @hw: pointer to the HW structure
256 *
257 * This function will release NVM ownership.
258 */
ice_release_nvm(struct ice_hw * hw)259 void ice_release_nvm(struct ice_hw *hw)
260 {
261 if (hw->flash.blank_nvm_mode)
262 return;
263
264 ice_release_res(hw, ICE_NVM_RES_ID);
265 }
266
267 /**
268 * ice_get_flash_bank_offset - Get offset into requested flash bank
269 * @hw: pointer to the HW structure
270 * @bank: whether to read from the active or inactive flash bank
271 * @module: the module to read from
272 *
273 * Based on the module, lookup the module offset from the beginning of the
274 * flash.
275 *
276 * Returns the flash offset. Note that a value of zero is invalid and must be
277 * treated as an error.
278 */
ice_get_flash_bank_offset(struct ice_hw * hw,enum ice_bank_select bank,u16 module)279 static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
280 {
281 struct ice_bank_info *banks = &hw->flash.banks;
282 enum ice_flash_bank active_bank;
283 bool second_bank_active;
284 u32 offset, size;
285
286 switch (module) {
287 case ICE_SR_1ST_NVM_BANK_PTR:
288 offset = banks->nvm_ptr;
289 size = banks->nvm_size;
290 active_bank = banks->nvm_bank;
291 break;
292 case ICE_SR_1ST_OROM_BANK_PTR:
293 offset = banks->orom_ptr;
294 size = banks->orom_size;
295 active_bank = banks->orom_bank;
296 break;
297 case ICE_SR_NETLIST_BANK_PTR:
298 offset = banks->netlist_ptr;
299 size = banks->netlist_size;
300 active_bank = banks->netlist_bank;
301 break;
302 default:
303 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
304 return 0;
305 }
306
307 switch (active_bank) {
308 case ICE_1ST_FLASH_BANK:
309 second_bank_active = false;
310 break;
311 case ICE_2ND_FLASH_BANK:
312 second_bank_active = true;
313 break;
314 default:
315 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
316 active_bank);
317 return 0;
318 }
319
320 /* The second flash bank is stored immediately following the first
321 * bank. Based on whether the 1st or 2nd bank is active, and whether
322 * we want the active or inactive bank, calculate the desired offset.
323 */
324 switch (bank) {
325 case ICE_ACTIVE_FLASH_BANK:
326 return offset + (second_bank_active ? size : 0);
327 case ICE_INACTIVE_FLASH_BANK:
328 return offset + (second_bank_active ? 0 : size);
329 }
330
331 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
332 return 0;
333 }
334
335 /**
336 * ice_read_flash_module - Read a word from one of the main NVM modules
337 * @hw: pointer to the HW structure
338 * @bank: which bank of the module to read
339 * @module: the module to read
340 * @offset: the offset into the module in bytes
341 * @data: storage for the word read from the flash
342 * @length: bytes of data to read
343 *
344 * Read data from the specified flash module. The bank parameter indicates
345 * whether or not to read from the active bank or the inactive bank of that
346 * module.
347 *
348 * The word will be read using flat NVM access, and relies on the
349 * hw->flash.banks data being setup by ice_determine_active_flash_banks()
350 * during initialization.
351 */
352 static int
ice_read_flash_module(struct ice_hw * hw,enum ice_bank_select bank,u16 module,u32 offset,u8 * data,u32 length)353 ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
354 u32 offset, u8 *data, u32 length)
355 {
356 int status;
357 u32 start;
358
359 start = ice_get_flash_bank_offset(hw, bank, module);
360 if (!start) {
361 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
362 module);
363 return -EINVAL;
364 }
365
366 status = ice_read_flat_nvm(hw, start + offset, &length, data, false,
367 NULL);
368
369 return status;
370 }
371
372 /**
373 * ice_read_nvm_module - Read from the active main NVM module
374 * @hw: pointer to the HW structure
375 * @bank: whether to read from active or inactive NVM module
376 * @offset: offset into the NVM module to read, in words
377 * @data: storage for returned word value
378 *
379 * Read the specified word from the active NVM module. This includes the CSS
380 * header at the start of the NVM module.
381 */
382 static int
ice_read_nvm_module(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data)383 ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
384 {
385 __le16 data_local;
386 int status;
387
388 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16),
389 (__force u8 *)&data_local, sizeof(u16));
390 if (!status)
391 *data = le16_to_cpu(data_local);
392
393 return status;
394 }
395
396 /**
397 * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank
398 * @hw: pointer to the HW structure
399 * @bank: whether to read from the active or inactive NVM module
400 * @offset: offset into the Shadow RAM copy to read, in words
401 * @data: storage for returned word value
402 *
403 * Read the specified word from the copy of the Shadow RAM found in the
404 * specified NVM module.
405 *
406 * Note that the Shadow RAM copy is always located after the CSS header, and
407 * is aligned to 64-byte (32-word) offsets.
408 */
409 static int
ice_read_nvm_sr_copy(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data)410 ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
411 {
412 u32 sr_copy;
413
414 switch (bank) {
415 case ICE_ACTIVE_FLASH_BANK:
416 sr_copy = roundup(hw->flash.banks.active_css_hdr_len, 32);
417 break;
418 case ICE_INACTIVE_FLASH_BANK:
419 sr_copy = roundup(hw->flash.banks.inactive_css_hdr_len, 32);
420 break;
421 }
422
423 return ice_read_nvm_module(hw, bank, sr_copy + offset, data);
424 }
425
426 /**
427 * ice_read_netlist_module - Read data from the netlist module area
428 * @hw: pointer to the HW structure
429 * @bank: whether to read from the active or inactive module
430 * @offset: offset into the netlist to read from
431 * @data: storage for returned word value
432 *
433 * Read a word from the specified netlist bank.
434 */
435 static int
ice_read_netlist_module(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data)436 ice_read_netlist_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
437 {
438 __le16 data_local;
439 int status;
440
441 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR, offset * sizeof(u16),
442 (__force u8 *)&data_local, sizeof(u16));
443 if (!status)
444 *data = le16_to_cpu(data_local);
445
446 return status;
447 }
448
449 /**
450 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
451 * @hw: pointer to hardware structure
452 * @module_tlv: pointer to module TLV to return
453 * @module_tlv_len: pointer to module TLV length to return
454 * @module_type: module type requested
455 *
456 * Finds the requested sub module TLV type from the Preserved Field
457 * Area (PFA) and returns the TLV pointer and length. The caller can
458 * use these to read the variable length TLV value.
459 */
460 int
ice_get_pfa_module_tlv(struct ice_hw * hw,u16 * module_tlv,u16 * module_tlv_len,u16 module_type)461 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
462 u16 module_type)
463 {
464 u16 pfa_len, pfa_ptr, next_tlv, max_tlv;
465 int status;
466
467 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
468 if (status) {
469 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
470 return status;
471 }
472 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
473 if (status) {
474 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
475 return status;
476 }
477
478 /* The Preserved Fields Area contains a sequence of Type-Length-Value
479 * structures which define its contents. The PFA length includes all
480 * of the TLVs, plus the initial length word itself, *and* one final
481 * word at the end after all of the TLVs.
482 */
483 if (check_add_overflow(pfa_ptr, pfa_len - 1, &max_tlv)) {
484 dev_warn(ice_hw_to_dev(hw), "PFA starts at offset %u. PFA length of %u caused 16-bit arithmetic overflow.\n",
485 pfa_ptr, pfa_len);
486 return -EINVAL;
487 }
488
489 /* Starting with first TLV after PFA length, iterate through the list
490 * of TLVs to find the requested one.
491 */
492 next_tlv = pfa_ptr + 1;
493 while (next_tlv < max_tlv) {
494 u16 tlv_sub_module_type;
495 u16 tlv_len;
496
497 /* Read TLV type */
498 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
499 if (status) {
500 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
501 break;
502 }
503 /* Read TLV length */
504 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
505 if (status) {
506 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
507 break;
508 }
509 if (tlv_sub_module_type == module_type) {
510 if (tlv_len) {
511 *module_tlv = next_tlv;
512 *module_tlv_len = tlv_len;
513 return 0;
514 }
515 return -EINVAL;
516 }
517
518 if (check_add_overflow(next_tlv, 2, &next_tlv) ||
519 check_add_overflow(next_tlv, tlv_len, &next_tlv)) {
520 dev_warn(ice_hw_to_dev(hw), "TLV of type %u and length 0x%04x caused 16-bit arithmetic overflow. The PFA starts at 0x%04x and has length of 0x%04x\n",
521 tlv_sub_module_type, tlv_len, pfa_ptr, pfa_len);
522 return -EINVAL;
523 }
524 }
525 /* Module does not exist */
526 return -ENOENT;
527 }
528
529 /**
530 * ice_read_pba_string - Reads part number string from NVM
531 * @hw: pointer to hardware structure
532 * @pba_num: stores the part number string from the NVM
533 * @pba_num_size: part number string buffer length
534 *
535 * Reads the part number string from the NVM.
536 */
ice_read_pba_string(struct ice_hw * hw,u8 * pba_num,u32 pba_num_size)537 int ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
538 {
539 u16 pba_tlv, pba_tlv_len;
540 u16 pba_word, pba_size;
541 int status;
542 u16 i;
543
544 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
545 ICE_SR_PBA_BLOCK_PTR);
546 if (status) {
547 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
548 return status;
549 }
550
551 /* pba_size is the next word */
552 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
553 if (status) {
554 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
555 return status;
556 }
557
558 if (pba_tlv_len < pba_size) {
559 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
560 return -EINVAL;
561 }
562
563 /* Subtract one to get PBA word count (PBA Size word is included in
564 * total size)
565 */
566 pba_size--;
567 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
568 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
569 return -EINVAL;
570 }
571
572 for (i = 0; i < pba_size; i++) {
573 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
574 if (status) {
575 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
576 return status;
577 }
578
579 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
580 pba_num[(i * 2) + 1] = pba_word & 0xFF;
581 }
582 pba_num[(pba_size * 2)] = '\0';
583
584 return status;
585 }
586
587 /**
588 * ice_get_nvm_ver_info - Read NVM version information
589 * @hw: pointer to the HW struct
590 * @bank: whether to read from the active or inactive flash bank
591 * @nvm: pointer to NVM info structure
592 *
593 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling
594 * in the NVM info structure.
595 */
596 static int
ice_get_nvm_ver_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_nvm_info * nvm)597 ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm)
598 {
599 u16 eetrack_lo, eetrack_hi, ver;
600 int status;
601
602 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver);
603 if (status) {
604 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
605 return status;
606 }
607
608 nvm->major = FIELD_GET(ICE_NVM_VER_HI_MASK, ver);
609 nvm->minor = FIELD_GET(ICE_NVM_VER_LO_MASK, ver);
610
611 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
612 if (status) {
613 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
614 return status;
615 }
616 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
617 if (status) {
618 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
619 return status;
620 }
621
622 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
623
624 return 0;
625 }
626
627 /**
628 * ice_get_inactive_nvm_ver - Read Option ROM version from the inactive bank
629 * @hw: pointer to the HW structure
630 * @nvm: storage for Option ROM version information
631 *
632 * Reads the NVM EETRACK ID, Map version, and security revision of the
633 * inactive NVM bank. Used to access version data for a pending update that
634 * has not yet been activated.
635 */
ice_get_inactive_nvm_ver(struct ice_hw * hw,struct ice_nvm_info * nvm)636 int ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm)
637 {
638 return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm);
639 }
640
641 /**
642 * ice_get_orom_civd_data - Get the combo version information from Option ROM
643 * @hw: pointer to the HW struct
644 * @bank: whether to read from the active or inactive flash module
645 * @civd: storage for the Option ROM CIVD data.
646 *
647 * Searches through the Option ROM flash contents to locate the CIVD data for
648 * the image.
649 */
650 static int
ice_get_orom_civd_data(struct ice_hw * hw,enum ice_bank_select bank,struct ice_orom_civd_info * civd)651 ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank,
652 struct ice_orom_civd_info *civd)
653 {
654 u8 *orom_data;
655 int status;
656 u32 offset;
657
658 /* The CIVD section is located in the Option ROM aligned to 512 bytes.
659 * The first 4 bytes must contain the ASCII characters "$CIV".
660 * A simple modulo 256 sum of all of the bytes of the structure must
661 * equal 0.
662 *
663 * The exact location is unknown and varies between images but is
664 * usually somewhere in the middle of the bank. We need to scan the
665 * Option ROM bank to locate it.
666 *
667 * It's significantly faster to read the entire Option ROM up front
668 * using the maximum page size, than to read each possible location
669 * with a separate firmware command.
670 */
671 orom_data = vzalloc(hw->flash.banks.orom_size);
672 if (!orom_data)
673 return -ENOMEM;
674
675 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, 0,
676 orom_data, hw->flash.banks.orom_size);
677 if (status) {
678 vfree(orom_data);
679 ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM data\n");
680 return status;
681 }
682
683 /* Scan the memory buffer to locate the CIVD data section */
684 for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) {
685 struct ice_orom_civd_info *tmp;
686 u8 sum = 0, i;
687
688 tmp = (struct ice_orom_civd_info *)&orom_data[offset];
689
690 /* Skip forward until we find a matching signature */
691 if (memcmp("$CIV", tmp->signature, sizeof(tmp->signature)) != 0)
692 continue;
693
694 ice_debug(hw, ICE_DBG_NVM, "Found CIVD section at offset %u\n",
695 offset);
696
697 /* Verify that the simple checksum is zero */
698 for (i = 0; i < sizeof(*tmp); i++)
699 sum += ((u8 *)tmp)[i];
700
701 if (sum) {
702 ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n",
703 sum);
704 goto err_invalid_checksum;
705 }
706
707 *civd = *tmp;
708 vfree(orom_data);
709 return 0;
710 }
711
712 ice_debug(hw, ICE_DBG_NVM, "Unable to locate CIVD data within the Option ROM\n");
713
714 err_invalid_checksum:
715 vfree(orom_data);
716 return -EIO;
717 }
718
719 /**
720 * ice_get_orom_ver_info - Read Option ROM version information
721 * @hw: pointer to the HW struct
722 * @bank: whether to read from the active or inactive flash module
723 * @orom: pointer to Option ROM info structure
724 *
725 * Read Option ROM version and security revision from the Option ROM flash
726 * section.
727 */
728 static int
ice_get_orom_ver_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_orom_info * orom)729 ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom)
730 {
731 struct ice_orom_civd_info civd;
732 u32 combo_ver;
733 int status;
734
735 status = ice_get_orom_civd_data(hw, bank, &civd);
736 if (status) {
737 ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n");
738 return status;
739 }
740
741 combo_ver = le32_to_cpu(civd.combo_ver);
742
743 orom->major = FIELD_GET(ICE_OROM_VER_MASK, combo_ver);
744 orom->patch = FIELD_GET(ICE_OROM_VER_PATCH_MASK, combo_ver);
745 orom->build = FIELD_GET(ICE_OROM_VER_BUILD_MASK, combo_ver);
746
747 return 0;
748 }
749
750 /**
751 * ice_get_inactive_orom_ver - Read Option ROM version from the inactive bank
752 * @hw: pointer to the HW structure
753 * @orom: storage for Option ROM version information
754 *
755 * Reads the Option ROM version and security revision data for the inactive
756 * section of flash. Used to access version data for a pending update that has
757 * not yet been activated.
758 */
ice_get_inactive_orom_ver(struct ice_hw * hw,struct ice_orom_info * orom)759 int ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom)
760 {
761 return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom);
762 }
763
764 /**
765 * ice_get_netlist_info
766 * @hw: pointer to the HW struct
767 * @bank: whether to read from the active or inactive flash bank
768 * @netlist: pointer to netlist version info structure
769 *
770 * Get the netlist version information from the requested bank. Reads the Link
771 * Topology section to find the Netlist ID block and extract the relevant
772 * information into the netlist version structure.
773 */
774 static int
ice_get_netlist_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_netlist_info * netlist)775 ice_get_netlist_info(struct ice_hw *hw, enum ice_bank_select bank,
776 struct ice_netlist_info *netlist)
777 {
778 u16 module_id, length, node_count, i;
779 u16 *id_blk;
780 int status;
781
782 status = ice_read_netlist_module(hw, bank, ICE_NETLIST_TYPE_OFFSET, &module_id);
783 if (status)
784 return status;
785
786 if (module_id != ICE_NETLIST_LINK_TOPO_MOD_ID) {
787 ice_debug(hw, ICE_DBG_NVM, "Expected netlist module_id ID of 0x%04x, but got 0x%04x\n",
788 ICE_NETLIST_LINK_TOPO_MOD_ID, module_id);
789 return -EIO;
790 }
791
792 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_MODULE_LEN, &length);
793 if (status)
794 return status;
795
796 /* sanity check that we have at least enough words to store the netlist ID block */
797 if (length < ICE_NETLIST_ID_BLK_SIZE) {
798 ice_debug(hw, ICE_DBG_NVM, "Netlist Link Topology module too small. Expected at least %u words, but got %u words.\n",
799 ICE_NETLIST_ID_BLK_SIZE, length);
800 return -EIO;
801 }
802
803 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_NODE_COUNT, &node_count);
804 if (status)
805 return status;
806 node_count &= ICE_LINK_TOPO_NODE_COUNT_M;
807
808 id_blk = kcalloc(ICE_NETLIST_ID_BLK_SIZE, sizeof(*id_blk), GFP_KERNEL);
809 if (!id_blk)
810 return -ENOMEM;
811
812 /* Read out the entire Netlist ID Block at once. */
813 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR,
814 ICE_NETLIST_ID_BLK_OFFSET(node_count) * sizeof(u16),
815 (u8 *)id_blk, ICE_NETLIST_ID_BLK_SIZE * sizeof(u16));
816 if (status)
817 goto exit_error;
818
819 for (i = 0; i < ICE_NETLIST_ID_BLK_SIZE; i++)
820 id_blk[i] = le16_to_cpu(((__force __le16 *)id_blk)[i]);
821
822 netlist->major = id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16 |
823 id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_LOW];
824 netlist->minor = id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16 |
825 id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_LOW];
826 netlist->type = id_blk[ICE_NETLIST_ID_BLK_TYPE_HIGH] << 16 |
827 id_blk[ICE_NETLIST_ID_BLK_TYPE_LOW];
828 netlist->rev = id_blk[ICE_NETLIST_ID_BLK_REV_HIGH] << 16 |
829 id_blk[ICE_NETLIST_ID_BLK_REV_LOW];
830 netlist->cust_ver = id_blk[ICE_NETLIST_ID_BLK_CUST_VER];
831 /* Read the left most 4 bytes of SHA */
832 netlist->hash = id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(15)] << 16 |
833 id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(14)];
834
835 exit_error:
836 kfree(id_blk);
837
838 return status;
839 }
840
841 /**
842 * ice_get_inactive_netlist_ver
843 * @hw: pointer to the HW struct
844 * @netlist: pointer to netlist version info structure
845 *
846 * Read the netlist version data from the inactive netlist bank. Used to
847 * extract version data of a pending flash update in order to display the
848 * version data.
849 */
ice_get_inactive_netlist_ver(struct ice_hw * hw,struct ice_netlist_info * netlist)850 int ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist)
851 {
852 return ice_get_netlist_info(hw, ICE_INACTIVE_FLASH_BANK, netlist);
853 }
854
855 /**
856 * ice_discover_flash_size - Discover the available flash size.
857 * @hw: pointer to the HW struct
858 *
859 * The device flash could be up to 16MB in size. However, it is possible that
860 * the actual size is smaller. Use bisection to determine the accessible size
861 * of flash memory.
862 */
ice_discover_flash_size(struct ice_hw * hw)863 static int ice_discover_flash_size(struct ice_hw *hw)
864 {
865 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
866 int status = 0;
867
868 while ((max_size - min_size) > 1) {
869 enum libie_aq_err read_aq_err = LIBIE_AQ_RC_OK;
870 u32 offset = (max_size + min_size) / 2;
871 u32 len = 1;
872 u8 data;
873
874 status = ice_read_flat_nvm(hw, offset, &len, &data, false,
875 &read_aq_err);
876 if (status == -EIO &&
877 read_aq_err == LIBIE_AQ_RC_EINVAL) {
878 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
879 __func__, offset);
880 status = 0;
881 max_size = offset;
882 } else if (!status) {
883 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
884 __func__, offset);
885 min_size = offset;
886 } else {
887 /* an unexpected error occurred */
888 return status;
889 }
890 }
891
892 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
893
894 hw->flash.flash_size = max_size;
895
896 return status;
897 }
898
899 /**
900 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
901 * @hw: pointer to the HW structure
902 * @offset: the word offset of the Shadow RAM word to read
903 * @pointer: pointer value read from Shadow RAM
904 *
905 * Read the given Shadow RAM word, and convert it to a pointer value specified
906 * in bytes. This function assumes the specified offset is a valid pointer
907 * word.
908 *
909 * Each pointer word specifies whether it is stored in word size or 4KB
910 * sector size by using the highest bit. The reported pointer value will be in
911 * bytes, intended for flat NVM reads.
912 */
ice_read_sr_pointer(struct ice_hw * hw,u16 offset,u32 * pointer)913 static int ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
914 {
915 int status;
916 u16 value;
917
918 status = ice_read_sr_word(hw, offset, &value);
919 if (status)
920 return status;
921
922 /* Determine if the pointer is in 4KB or word units */
923 if (value & ICE_SR_NVM_PTR_4KB_UNITS)
924 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
925 else
926 *pointer = value * 2;
927
928 return 0;
929 }
930
931 /**
932 * ice_read_sr_area_size - Read an area size from a Shadow RAM word
933 * @hw: pointer to the HW structure
934 * @offset: the word offset of the Shadow RAM to read
935 * @size: size value read from the Shadow RAM
936 *
937 * Read the given Shadow RAM word, and convert it to an area size value
938 * specified in bytes. This function assumes the specified offset is a valid
939 * area size word.
940 *
941 * Each area size word is specified in 4KB sector units. This function reports
942 * the size in bytes, intended for flat NVM reads.
943 */
ice_read_sr_area_size(struct ice_hw * hw,u16 offset,u32 * size)944 static int ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
945 {
946 int status;
947 u16 value;
948
949 status = ice_read_sr_word(hw, offset, &value);
950 if (status)
951 return status;
952
953 /* Area sizes are always specified in 4KB units */
954 *size = value * 4 * 1024;
955
956 return 0;
957 }
958
959 /**
960 * ice_determine_active_flash_banks - Discover active bank for each module
961 * @hw: pointer to the HW struct
962 *
963 * Read the Shadow RAM control word and determine which banks are active for
964 * the NVM, OROM, and Netlist modules. Also read and calculate the associated
965 * pointer and size. These values are then cached into the ice_flash_info
966 * structure for later use in order to calculate the correct offset to read
967 * from the active module.
968 */
ice_determine_active_flash_banks(struct ice_hw * hw)969 static int ice_determine_active_flash_banks(struct ice_hw *hw)
970 {
971 struct ice_bank_info *banks = &hw->flash.banks;
972 u16 ctrl_word;
973 int status;
974
975 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
976 if (status) {
977 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
978 return status;
979 }
980
981 /* Check that the control word indicates validity */
982 if (FIELD_GET(ICE_SR_CTRL_WORD_1_M, ctrl_word) !=
983 ICE_SR_CTRL_WORD_VALID) {
984 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
985 return -EIO;
986 }
987
988 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
989 banks->nvm_bank = ICE_1ST_FLASH_BANK;
990 else
991 banks->nvm_bank = ICE_2ND_FLASH_BANK;
992
993 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
994 banks->orom_bank = ICE_1ST_FLASH_BANK;
995 else
996 banks->orom_bank = ICE_2ND_FLASH_BANK;
997
998 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
999 banks->netlist_bank = ICE_1ST_FLASH_BANK;
1000 else
1001 banks->netlist_bank = ICE_2ND_FLASH_BANK;
1002
1003 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
1004 if (status) {
1005 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
1006 return status;
1007 }
1008
1009 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
1010 if (status) {
1011 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
1012 return status;
1013 }
1014
1015 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
1016 if (status) {
1017 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
1018 return status;
1019 }
1020
1021 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
1022 if (status) {
1023 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
1024 return status;
1025 }
1026
1027 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
1028 if (status) {
1029 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
1030 return status;
1031 }
1032
1033 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
1034 if (status) {
1035 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
1036 return status;
1037 }
1038
1039 return 0;
1040 }
1041
1042 /**
1043 * ice_get_nvm_css_hdr_len - Read the CSS header length from the NVM CSS header
1044 * @hw: pointer to the HW struct
1045 * @bank: whether to read from the active or inactive flash bank
1046 * @hdr_len: storage for header length in words
1047 *
1048 * Read the CSS header length from the NVM CSS header and add the Authentication
1049 * header size, and then convert to words.
1050 *
1051 * Return: zero on success, or a negative error code on failure.
1052 */
1053 static int
ice_get_nvm_css_hdr_len(struct ice_hw * hw,enum ice_bank_select bank,u32 * hdr_len)1054 ice_get_nvm_css_hdr_len(struct ice_hw *hw, enum ice_bank_select bank,
1055 u32 *hdr_len)
1056 {
1057 u16 hdr_len_l, hdr_len_h;
1058 u32 hdr_len_dword;
1059 int status;
1060
1061 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_L,
1062 &hdr_len_l);
1063 if (status)
1064 return status;
1065
1066 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_H,
1067 &hdr_len_h);
1068 if (status)
1069 return status;
1070
1071 /* CSS header length is in DWORD, so convert to words and add
1072 * authentication header size
1073 */
1074 hdr_len_dword = hdr_len_h << 16 | hdr_len_l;
1075 *hdr_len = (hdr_len_dword * 2) + ICE_NVM_AUTH_HEADER_LEN;
1076
1077 return 0;
1078 }
1079
1080 /**
1081 * ice_determine_css_hdr_len - Discover CSS header length for the device
1082 * @hw: pointer to the HW struct
1083 *
1084 * Determine the size of the CSS header at the start of the NVM module. This
1085 * is useful for locating the Shadow RAM copy in the NVM, as the Shadow RAM is
1086 * always located just after the CSS header.
1087 *
1088 * Return: zero on success, or a negative error code on failure.
1089 */
ice_determine_css_hdr_len(struct ice_hw * hw)1090 static int ice_determine_css_hdr_len(struct ice_hw *hw)
1091 {
1092 struct ice_bank_info *banks = &hw->flash.banks;
1093 int status;
1094
1095 status = ice_get_nvm_css_hdr_len(hw, ICE_ACTIVE_FLASH_BANK,
1096 &banks->active_css_hdr_len);
1097 if (status)
1098 return status;
1099
1100 status = ice_get_nvm_css_hdr_len(hw, ICE_INACTIVE_FLASH_BANK,
1101 &banks->inactive_css_hdr_len);
1102 if (status)
1103 return status;
1104
1105 return 0;
1106 }
1107
1108 /**
1109 * ice_init_nvm - initializes NVM setting
1110 * @hw: pointer to the HW struct
1111 *
1112 * This function reads and populates NVM settings such as Shadow RAM size,
1113 * max_timeout, and blank_nvm_mode
1114 */
ice_init_nvm(struct ice_hw * hw)1115 int ice_init_nvm(struct ice_hw *hw)
1116 {
1117 struct ice_flash_info *flash = &hw->flash;
1118 u32 fla, gens_stat;
1119 u8 sr_size;
1120 int status;
1121
1122 /* The SR size is stored regardless of the NVM programming mode
1123 * as the blank mode may be used in the factory line.
1124 */
1125 gens_stat = rd32(hw, GLNVM_GENS);
1126 sr_size = FIELD_GET(GLNVM_GENS_SR_SIZE_M, gens_stat);
1127
1128 /* Switching to words (sr_size contains power of 2) */
1129 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
1130
1131 /* Check if we are in the normal or blank NVM programming mode */
1132 fla = rd32(hw, GLNVM_FLA);
1133 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
1134 flash->blank_nvm_mode = false;
1135 } else {
1136 /* Blank programming mode */
1137 flash->blank_nvm_mode = true;
1138 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
1139 return -EIO;
1140 }
1141
1142 status = ice_discover_flash_size(hw);
1143 if (status) {
1144 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
1145 return status;
1146 }
1147
1148 status = ice_determine_active_flash_banks(hw);
1149 if (status) {
1150 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
1151 return status;
1152 }
1153
1154 status = ice_determine_css_hdr_len(hw);
1155 if (status) {
1156 ice_debug(hw, ICE_DBG_NVM, "Failed to determine Shadow RAM copy offsets.\n");
1157 return status;
1158 }
1159
1160 status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm);
1161 if (status) {
1162 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
1163 return status;
1164 }
1165
1166 status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom);
1167 if (status)
1168 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
1169
1170 /* read the netlist version information */
1171 status = ice_get_netlist_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->netlist);
1172 if (status)
1173 ice_debug(hw, ICE_DBG_INIT, "Failed to read netlist info.\n");
1174
1175 return 0;
1176 }
1177
1178 /**
1179 * ice_nvm_validate_checksum
1180 * @hw: pointer to the HW struct
1181 *
1182 * Verify NVM PFA checksum validity (0x0706)
1183 */
ice_nvm_validate_checksum(struct ice_hw * hw)1184 int ice_nvm_validate_checksum(struct ice_hw *hw)
1185 {
1186 struct ice_aqc_nvm_checksum *cmd;
1187 struct libie_aq_desc desc;
1188 int status;
1189
1190 status = ice_acquire_nvm(hw, ICE_RES_READ);
1191 if (status)
1192 return status;
1193
1194 cmd = libie_aq_raw(&desc);
1195
1196 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1197 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
1198
1199 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1200 ice_release_nvm(hw);
1201
1202 if (!status)
1203 if (le16_to_cpu(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
1204 status = -EIO;
1205
1206 return status;
1207 }
1208
1209 /**
1210 * ice_nvm_write_activate
1211 * @hw: pointer to the HW struct
1212 * @cmd_flags: flags for write activate command
1213 * @response_flags: response indicators from firmware
1214 *
1215 * Update the control word with the required banks' validity bits
1216 * and dumps the Shadow RAM to flash (0x0707)
1217 *
1218 * cmd_flags controls which banks to activate, the preservation level to use
1219 * when activating the NVM bank, and whether an EMP reset is required for
1220 * activation.
1221 *
1222 * Note that the 16bit cmd_flags value is split between two separate 1 byte
1223 * flag values in the descriptor.
1224 *
1225 * On successful return of the firmware command, the response_flags variable
1226 * is updated with the flags reported by firmware indicating certain status,
1227 * such as whether EMP reset is enabled.
1228 */
ice_nvm_write_activate(struct ice_hw * hw,u16 cmd_flags,u8 * response_flags)1229 int ice_nvm_write_activate(struct ice_hw *hw, u16 cmd_flags, u8 *response_flags)
1230 {
1231 struct libie_aq_desc desc;
1232 struct ice_aqc_nvm *cmd;
1233 int err;
1234
1235 cmd = libie_aq_raw(&desc);
1236 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write_activate);
1237
1238 cmd->cmd_flags = (u8)(cmd_flags & 0xFF);
1239 cmd->offset_high = (u8)((cmd_flags >> 8) & 0xFF);
1240
1241 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1242 if (!err && response_flags)
1243 *response_flags = cmd->cmd_flags;
1244
1245 return err;
1246 }
1247
1248 /**
1249 * ice_aq_nvm_update_empr
1250 * @hw: pointer to the HW struct
1251 *
1252 * Update empr (0x0709). This command allows SW to
1253 * request an EMPR to activate new FW.
1254 */
ice_aq_nvm_update_empr(struct ice_hw * hw)1255 int ice_aq_nvm_update_empr(struct ice_hw *hw)
1256 {
1257 struct libie_aq_desc desc;
1258
1259 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_update_empr);
1260
1261 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1262 }
1263
1264 /* ice_nvm_set_pkg_data
1265 * @hw: pointer to the HW struct
1266 * @del_pkg_data_flag: If is set then the current pkg_data store by FW
1267 * is deleted.
1268 * If bit is set to 1, then buffer should be size 0.
1269 * @data: pointer to buffer
1270 * @length: length of the buffer
1271 * @cd: pointer to command details structure or NULL
1272 *
1273 * Set package data (0x070A). This command is equivalent to the reception
1274 * of a PLDM FW Update GetPackageData cmd. This command should be sent
1275 * as part of the NVM update as the first cmd in the flow.
1276 */
1277
1278 int
ice_nvm_set_pkg_data(struct ice_hw * hw,bool del_pkg_data_flag,u8 * data,u16 length,struct ice_sq_cd * cd)1279 ice_nvm_set_pkg_data(struct ice_hw *hw, bool del_pkg_data_flag, u8 *data,
1280 u16 length, struct ice_sq_cd *cd)
1281 {
1282 struct ice_aqc_nvm_pkg_data *cmd;
1283 struct libie_aq_desc desc;
1284
1285 if (length != 0 && !data)
1286 return -EINVAL;
1287
1288 cmd = libie_aq_raw(&desc);
1289
1290 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_pkg_data);
1291 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
1292
1293 if (del_pkg_data_flag)
1294 cmd->cmd_flags |= ICE_AQC_NVM_PKG_DELETE;
1295
1296 return ice_aq_send_cmd(hw, &desc, data, length, cd);
1297 }
1298
1299 /* ice_nvm_pass_component_tbl
1300 * @hw: pointer to the HW struct
1301 * @data: pointer to buffer
1302 * @length: length of the buffer
1303 * @transfer_flag: parameter for determining stage of the update
1304 * @comp_response: a pointer to the response from the 0x070B AQC.
1305 * @comp_response_code: a pointer to the response code from the 0x070B AQC.
1306 * @cd: pointer to command details structure or NULL
1307 *
1308 * Pass component table (0x070B). This command is equivalent to the reception
1309 * of a PLDM FW Update PassComponentTable cmd. This command should be sent once
1310 * per component. It can be only sent after Set Package Data cmd and before
1311 * actual update. FW will assume these commands are going to be sent until
1312 * the TransferFlag is set to End or StartAndEnd.
1313 */
1314
1315 int
ice_nvm_pass_component_tbl(struct ice_hw * hw,u8 * data,u16 length,u8 transfer_flag,u8 * comp_response,u8 * comp_response_code,struct ice_sq_cd * cd)1316 ice_nvm_pass_component_tbl(struct ice_hw *hw, u8 *data, u16 length,
1317 u8 transfer_flag, u8 *comp_response,
1318 u8 *comp_response_code, struct ice_sq_cd *cd)
1319 {
1320 struct ice_aqc_nvm_pass_comp_tbl *cmd;
1321 struct libie_aq_desc desc;
1322 int status;
1323
1324 if (!data || !comp_response || !comp_response_code)
1325 return -EINVAL;
1326
1327 cmd = libie_aq_raw(&desc);
1328
1329 ice_fill_dflt_direct_cmd_desc(&desc,
1330 ice_aqc_opc_nvm_pass_component_tbl);
1331 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
1332
1333 cmd->transfer_flag = transfer_flag;
1334 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
1335
1336 if (!status) {
1337 *comp_response = cmd->component_response;
1338 *comp_response_code = cmd->component_response_code;
1339 }
1340 return status;
1341 }
1342