1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192 } 193 194 /** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200 bool ice_is_generic_mac(struct ice_hw *hw) 201 { 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204 } 205 206 /** 207 * ice_clear_pf_cfg - Clear PF configuration 208 * @hw: pointer to the hardware structure 209 * 210 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 211 * configuration, flow director filters, etc.). 212 */ 213 int ice_clear_pf_cfg(struct ice_hw *hw) 214 { 215 struct libie_aq_desc desc; 216 217 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 218 219 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 220 } 221 222 /** 223 * ice_aq_manage_mac_read - manage MAC address read command 224 * @hw: pointer to the HW struct 225 * @buf: a virtual buffer to hold the manage MAC read response 226 * @buf_size: Size of the virtual buffer 227 * @cd: pointer to command details structure or NULL 228 * 229 * This function is used to return per PF station MAC address (0x0107). 230 * NOTE: Upon successful completion of this command, MAC address information 231 * is returned in user specified buffer. Please interpret user specified 232 * buffer as "manage_mac_read" response. 233 * Response such as various MAC addresses are stored in HW struct (port.mac) 234 * ice_discover_dev_caps is expected to be called before this function is 235 * called. 236 */ 237 static int 238 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 239 struct ice_sq_cd *cd) 240 { 241 struct ice_aqc_manage_mac_read_resp *resp; 242 struct ice_aqc_manage_mac_read *cmd; 243 struct libie_aq_desc desc; 244 int status; 245 u16 flags; 246 u8 i; 247 248 cmd = libie_aq_raw(&desc); 249 250 if (buf_size < sizeof(*resp)) 251 return -EINVAL; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 254 255 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 256 if (status) 257 return status; 258 259 resp = buf; 260 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 261 262 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 263 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 264 return -EIO; 265 } 266 267 /* A single port can report up to two (LAN and WoL) addresses */ 268 for (i = 0; i < cmd->num_addr; i++) 269 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 270 ether_addr_copy(hw->port_info->mac.lan_addr, 271 resp[i].mac_addr); 272 ether_addr_copy(hw->port_info->mac.perm_addr, 273 resp[i].mac_addr); 274 break; 275 } 276 277 return 0; 278 } 279 280 /** 281 * ice_aq_get_phy_caps - returns PHY capabilities 282 * @pi: port information structure 283 * @qual_mods: report qualified modules 284 * @report_mode: report mode capabilities 285 * @pcaps: structure for PHY capabilities to be filled 286 * @cd: pointer to command details structure or NULL 287 * 288 * Returns the various PHY capabilities supported on the Port (0x0600) 289 */ 290 int 291 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 292 struct ice_aqc_get_phy_caps_data *pcaps, 293 struct ice_sq_cd *cd) 294 { 295 struct ice_aqc_get_phy_caps *cmd; 296 u16 pcaps_size = sizeof(*pcaps); 297 struct libie_aq_desc desc; 298 const char *prefix; 299 struct ice_hw *hw; 300 int status; 301 302 cmd = libie_aq_raw(&desc); 303 304 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 305 return -EINVAL; 306 hw = pi->hw; 307 308 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 309 !ice_fw_supports_report_dflt_cfg(hw)) 310 return -EINVAL; 311 312 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 313 314 if (qual_mods) 315 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 316 317 cmd->param0 |= cpu_to_le16(report_mode); 318 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 319 320 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 321 322 switch (report_mode) { 323 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 324 prefix = "phy_caps_media"; 325 break; 326 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 327 prefix = "phy_caps_no_media"; 328 break; 329 case ICE_AQC_REPORT_ACTIVE_CFG: 330 prefix = "phy_caps_active"; 331 break; 332 case ICE_AQC_REPORT_DFLT_CFG: 333 prefix = "phy_caps_default"; 334 break; 335 default: 336 prefix = "phy_caps_invalid"; 337 } 338 339 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 340 le64_to_cpu(pcaps->phy_type_high), prefix); 341 342 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 343 prefix, report_mode); 344 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 345 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 346 pcaps->low_power_ctrl_an); 347 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 348 pcaps->eee_cap); 349 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 350 pcaps->eeer_value); 351 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 352 pcaps->link_fec_options); 353 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 354 prefix, pcaps->module_compliance_enforcement); 355 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 356 prefix, pcaps->extended_compliance_code); 357 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 358 pcaps->module_type[0]); 359 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 360 pcaps->module_type[1]); 361 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 362 pcaps->module_type[2]); 363 364 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 365 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 366 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 367 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 368 sizeof(pi->phy.link_info.module_type)); 369 } 370 371 return status; 372 } 373 374 /** 375 * ice_aq_get_link_topo_handle - get link topology node return status 376 * @pi: port information structure 377 * @node_type: requested node type 378 * @cd: pointer to command details structure or NULL 379 * 380 * Get link topology node return status for specified node type (0x06E0) 381 * 382 * Node type cage can be used to determine if cage is present. If AQC 383 * returns error (ENOENT), then no cage present. If no cage present, then 384 * connection type is backplane or BASE-T. 385 */ 386 static int 387 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 388 struct ice_sq_cd *cd) 389 { 390 struct ice_aqc_get_link_topo *cmd; 391 struct libie_aq_desc desc; 392 393 cmd = libie_aq_raw(&desc); 394 395 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 396 397 cmd->addr.topo_params.node_type_ctx = 398 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 399 ICE_AQC_LINK_TOPO_NODE_CTX_S); 400 401 /* set node type */ 402 cmd->addr.topo_params.node_type_ctx |= 403 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 404 405 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 406 } 407 408 /** 409 * ice_aq_get_netlist_node 410 * @hw: pointer to the hw struct 411 * @cmd: get_link_topo AQ structure 412 * @node_part_number: output node part number if node found 413 * @node_handle: output node handle parameter if node found 414 * 415 * Get netlist node handle. 416 */ 417 int 418 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 419 u8 *node_part_number, u16 *node_handle) 420 { 421 struct ice_aqc_get_link_topo *resp; 422 struct libie_aq_desc desc; 423 424 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 425 resp = libie_aq_raw(&desc); 426 *resp = *cmd; 427 428 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 429 return -EINTR; 430 431 if (node_handle) 432 *node_handle = le16_to_cpu(resp->addr.handle); 433 if (node_part_number) 434 *node_part_number = resp->node_part_num; 435 436 return 0; 437 } 438 439 /** 440 * ice_find_netlist_node 441 * @hw: pointer to the hw struct 442 * @node_type: type of netlist node to look for 443 * @ctx: context of the search 444 * @node_part_number: node part number to look for 445 * @node_handle: output parameter if node found - optional 446 * 447 * Scan the netlist for a node handle of the given node type and part number. 448 * 449 * If node_handle is non-NULL it will be modified on function exit. It is only 450 * valid if the function returns zero, and should be ignored on any non-zero 451 * return value. 452 * 453 * Return: 454 * * 0 if the node is found, 455 * * -ENOENT if no handle was found, 456 * * negative error code on failure to access the AQ. 457 */ 458 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 459 u8 node_part_number, u16 *node_handle) 460 { 461 u8 idx; 462 463 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 464 struct ice_aqc_get_link_topo cmd = {}; 465 u8 rec_node_part_number; 466 int status; 467 468 cmd.addr.topo_params.node_type_ctx = 469 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 470 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 471 cmd.addr.topo_params.index = idx; 472 473 status = ice_aq_get_netlist_node(hw, &cmd, 474 &rec_node_part_number, 475 node_handle); 476 if (status) 477 return status; 478 479 if (rec_node_part_number == node_part_number) 480 return 0; 481 } 482 483 return -ENOENT; 484 } 485 486 /** 487 * ice_is_media_cage_present 488 * @pi: port information structure 489 * 490 * Returns true if media cage is present, else false. If no cage, then 491 * media type is backplane or BASE-T. 492 */ 493 static bool ice_is_media_cage_present(struct ice_port_info *pi) 494 { 495 /* Node type cage can be used to determine if cage is present. If AQC 496 * returns error (ENOENT), then no cage present. If no cage present then 497 * connection type is backplane or BASE-T. 498 */ 499 return !ice_aq_get_link_topo_handle(pi, 500 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 501 NULL); 502 } 503 504 /** 505 * ice_get_media_type - Gets media type 506 * @pi: port information structure 507 */ 508 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 509 { 510 struct ice_link_status *hw_link_info; 511 512 if (!pi) 513 return ICE_MEDIA_UNKNOWN; 514 515 hw_link_info = &pi->phy.link_info; 516 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 517 /* If more than one media type is selected, report unknown */ 518 return ICE_MEDIA_UNKNOWN; 519 520 if (hw_link_info->phy_type_low) { 521 /* 1G SGMII is a special case where some DA cable PHYs 522 * may show this as an option when it really shouldn't 523 * be since SGMII is meant to be between a MAC and a PHY 524 * in a backplane. Try to detect this case and handle it 525 */ 526 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 527 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 528 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 529 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 530 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 531 return ICE_MEDIA_DA; 532 533 switch (hw_link_info->phy_type_low) { 534 case ICE_PHY_TYPE_LOW_1000BASE_SX: 535 case ICE_PHY_TYPE_LOW_1000BASE_LX: 536 case ICE_PHY_TYPE_LOW_10GBASE_SR: 537 case ICE_PHY_TYPE_LOW_10GBASE_LR: 538 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 539 case ICE_PHY_TYPE_LOW_25GBASE_SR: 540 case ICE_PHY_TYPE_LOW_25GBASE_LR: 541 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 542 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 543 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 544 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 545 case ICE_PHY_TYPE_LOW_50GBASE_SR: 546 case ICE_PHY_TYPE_LOW_50GBASE_FR: 547 case ICE_PHY_TYPE_LOW_50GBASE_LR: 548 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 549 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 550 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 551 case ICE_PHY_TYPE_LOW_100GBASE_DR: 552 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 553 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 554 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 555 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 556 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 557 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 558 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 559 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 560 return ICE_MEDIA_FIBER; 561 case ICE_PHY_TYPE_LOW_100BASE_TX: 562 case ICE_PHY_TYPE_LOW_1000BASE_T: 563 case ICE_PHY_TYPE_LOW_2500BASE_T: 564 case ICE_PHY_TYPE_LOW_5GBASE_T: 565 case ICE_PHY_TYPE_LOW_10GBASE_T: 566 case ICE_PHY_TYPE_LOW_25GBASE_T: 567 return ICE_MEDIA_BASET; 568 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 569 case ICE_PHY_TYPE_LOW_25GBASE_CR: 570 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 571 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 572 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 573 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 574 case ICE_PHY_TYPE_LOW_50GBASE_CP: 575 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 576 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 577 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 578 return ICE_MEDIA_DA; 579 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 580 case ICE_PHY_TYPE_LOW_40G_XLAUI: 581 case ICE_PHY_TYPE_LOW_50G_LAUI2: 582 case ICE_PHY_TYPE_LOW_50G_AUI2: 583 case ICE_PHY_TYPE_LOW_50G_AUI1: 584 case ICE_PHY_TYPE_LOW_100G_AUI4: 585 case ICE_PHY_TYPE_LOW_100G_CAUI4: 586 if (ice_is_media_cage_present(pi)) 587 return ICE_MEDIA_DA; 588 fallthrough; 589 case ICE_PHY_TYPE_LOW_1000BASE_KX: 590 case ICE_PHY_TYPE_LOW_2500BASE_KX: 591 case ICE_PHY_TYPE_LOW_2500BASE_X: 592 case ICE_PHY_TYPE_LOW_5GBASE_KR: 593 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 594 case ICE_PHY_TYPE_LOW_25GBASE_KR: 595 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 596 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 597 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 598 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 599 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 600 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 601 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 602 return ICE_MEDIA_BACKPLANE; 603 } 604 } else { 605 switch (hw_link_info->phy_type_high) { 606 case ICE_PHY_TYPE_HIGH_100G_AUI2: 607 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 608 if (ice_is_media_cage_present(pi)) 609 return ICE_MEDIA_DA; 610 fallthrough; 611 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 612 return ICE_MEDIA_BACKPLANE; 613 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 614 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 615 return ICE_MEDIA_FIBER; 616 } 617 } 618 return ICE_MEDIA_UNKNOWN; 619 } 620 621 /** 622 * ice_get_link_status_datalen 623 * @hw: pointer to the HW struct 624 * 625 * Returns datalength for the Get Link Status AQ command, which is bigger for 626 * newer adapter families handled by ice driver. 627 */ 628 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 629 { 630 switch (hw->mac_type) { 631 case ICE_MAC_E830: 632 return ICE_AQC_LS_DATA_SIZE_V2; 633 case ICE_MAC_E810: 634 default: 635 return ICE_AQC_LS_DATA_SIZE_V1; 636 } 637 } 638 639 /** 640 * ice_aq_get_link_info 641 * @pi: port information structure 642 * @ena_lse: enable/disable LinkStatusEvent reporting 643 * @link: pointer to link status structure - optional 644 * @cd: pointer to command details structure or NULL 645 * 646 * Get Link Status (0x607). Returns the link status of the adapter. 647 */ 648 int 649 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 650 struct ice_link_status *link, struct ice_sq_cd *cd) 651 { 652 struct ice_aqc_get_link_status_data link_data = { 0 }; 653 struct ice_aqc_get_link_status *resp; 654 struct ice_link_status *li_old, *li; 655 enum ice_media_type *hw_media_type; 656 struct ice_fc_info *hw_fc_info; 657 struct libie_aq_desc desc; 658 bool tx_pause, rx_pause; 659 struct ice_hw *hw; 660 u16 cmd_flags; 661 int status; 662 663 if (!pi) 664 return -EINVAL; 665 hw = pi->hw; 666 li_old = &pi->phy.link_info_old; 667 hw_media_type = &pi->phy.media_type; 668 li = &pi->phy.link_info; 669 hw_fc_info = &pi->fc; 670 671 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 672 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 673 resp = libie_aq_raw(&desc); 674 resp->cmd_flags = cpu_to_le16(cmd_flags); 675 resp->lport_num = pi->lport; 676 677 status = ice_aq_send_cmd(hw, &desc, &link_data, 678 ice_get_link_status_datalen(hw), cd); 679 if (status) 680 return status; 681 682 /* save off old link status information */ 683 *li_old = *li; 684 685 /* update current link status information */ 686 li->link_speed = le16_to_cpu(link_data.link_speed); 687 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 688 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 689 *hw_media_type = ice_get_media_type(pi); 690 li->link_info = link_data.link_info; 691 li->link_cfg_err = link_data.link_cfg_err; 692 li->an_info = link_data.an_info; 693 li->ext_info = link_data.ext_info; 694 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 695 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 696 li->topo_media_conflict = link_data.topo_media_conflict; 697 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 698 ICE_AQ_CFG_PACING_TYPE_M); 699 700 /* update fc info */ 701 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 702 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 703 if (tx_pause && rx_pause) 704 hw_fc_info->current_mode = ICE_FC_FULL; 705 else if (tx_pause) 706 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 707 else if (rx_pause) 708 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 709 else 710 hw_fc_info->current_mode = ICE_FC_NONE; 711 712 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 713 714 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 715 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 716 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 717 (unsigned long long)li->phy_type_low); 718 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 719 (unsigned long long)li->phy_type_high); 720 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 721 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 722 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 723 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 724 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 725 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 726 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 727 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 728 li->max_frame_size); 729 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 730 731 /* save link status information */ 732 if (link) 733 *link = *li; 734 735 /* flag cleared so calling functions don't call AQ again */ 736 pi->phy.get_link_info = false; 737 738 return 0; 739 } 740 741 /** 742 * ice_fill_tx_timer_and_fc_thresh 743 * @hw: pointer to the HW struct 744 * @cmd: pointer to MAC cfg structure 745 * 746 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 747 * descriptor 748 */ 749 static void 750 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 751 struct ice_aqc_set_mac_cfg *cmd) 752 { 753 u32 val, fc_thres_m; 754 755 /* We read back the transmit timer and FC threshold value of 756 * LFC. Thus, we will use index = 757 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 758 * 759 * Also, because we are operating on transmit timer and FC 760 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 761 */ 762 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 763 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 764 765 if (hw->mac_type == ICE_MAC_E830) { 766 /* Retrieve the transmit timer */ 767 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 768 cmd->tx_tmr_value = 769 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 770 771 /* Retrieve the fc threshold */ 772 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 773 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 774 } else { 775 /* Retrieve the transmit timer */ 776 val = rd32(hw, 777 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 778 cmd->tx_tmr_value = 779 le16_encode_bits(val, 780 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 781 782 /* Retrieve the fc threshold */ 783 val = rd32(hw, 784 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 785 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 786 } 787 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 788 } 789 790 /** 791 * ice_aq_set_mac_cfg 792 * @hw: pointer to the HW struct 793 * @max_frame_size: Maximum Frame Size to be supported 794 * @cd: pointer to command details structure or NULL 795 * 796 * Set MAC configuration (0x0603) 797 */ 798 int 799 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 800 { 801 struct ice_aqc_set_mac_cfg *cmd; 802 struct libie_aq_desc desc; 803 804 cmd = libie_aq_raw(&desc); 805 806 if (max_frame_size == 0) 807 return -EINVAL; 808 809 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 810 811 cmd->max_frame_size = cpu_to_le16(max_frame_size); 812 813 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 814 815 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 816 } 817 818 /** 819 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 820 * @hw: pointer to the HW struct 821 */ 822 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 823 { 824 struct ice_switch_info *sw; 825 int status; 826 827 hw->switch_info = devm_kzalloc_obj(ice_hw_to_dev(hw), *hw->switch_info); 828 sw = hw->switch_info; 829 830 if (!sw) 831 return -ENOMEM; 832 833 INIT_LIST_HEAD(&sw->vsi_list_map_head); 834 sw->prof_res_bm_init = 0; 835 836 /* Initialize recipe count with default recipes read from NVM */ 837 sw->recp_cnt = ICE_SW_LKUP_LAST; 838 839 status = ice_init_def_sw_recp(hw); 840 if (status) { 841 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 842 return status; 843 } 844 return 0; 845 } 846 847 /** 848 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 849 * @hw: pointer to the HW struct 850 */ 851 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 852 { 853 struct ice_switch_info *sw = hw->switch_info; 854 struct ice_vsi_list_map_info *v_pos_map; 855 struct ice_vsi_list_map_info *v_tmp_map; 856 struct ice_sw_recipe *recps; 857 u8 i; 858 859 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 860 list_entry) { 861 list_del(&v_pos_map->list_entry); 862 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 863 } 864 recps = sw->recp_list; 865 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 866 recps[i].root_rid = i; 867 868 if (recps[i].adv_rule) { 869 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 870 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 871 872 mutex_destroy(&recps[i].filt_rule_lock); 873 list_for_each_entry_safe(lst_itr, tmp_entry, 874 &recps[i].filt_rules, 875 list_entry) { 876 list_del(&lst_itr->list_entry); 877 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 878 devm_kfree(ice_hw_to_dev(hw), lst_itr); 879 } 880 } else { 881 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 882 883 mutex_destroy(&recps[i].filt_rule_lock); 884 list_for_each_entry_safe(lst_itr, tmp_entry, 885 &recps[i].filt_rules, 886 list_entry) { 887 list_del(&lst_itr->list_entry); 888 devm_kfree(ice_hw_to_dev(hw), lst_itr); 889 } 890 } 891 } 892 ice_rm_all_sw_replay_rule_info(hw); 893 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 894 devm_kfree(ice_hw_to_dev(hw), sw); 895 } 896 897 /** 898 * ice_get_itr_intrl_gran 899 * @hw: pointer to the HW struct 900 * 901 * Determines the ITR/INTRL granularities based on the maximum aggregate 902 * bandwidth according to the device's configuration during power-on. 903 */ 904 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 905 { 906 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 907 rd32(hw, GL_PWR_MODE_CTL)); 908 909 switch (max_agg_bw) { 910 case ICE_MAX_AGG_BW_200G: 911 case ICE_MAX_AGG_BW_100G: 912 case ICE_MAX_AGG_BW_50G: 913 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 914 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 915 break; 916 case ICE_MAX_AGG_BW_25G: 917 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 918 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 919 break; 920 } 921 } 922 923 /** 924 * ice_wait_fw_load - wait for PHY firmware loading to complete 925 * @hw: pointer to the hardware structure 926 * @timeout: milliseconds that can elapse before timing out, 0 to bypass waiting 927 * 928 * Return: 929 * * 0 on success 930 * * negative on timeout 931 */ 932 static int ice_wait_fw_load(struct ice_hw *hw, u32 timeout) 933 { 934 int fw_loading_reg; 935 936 if (!timeout) 937 return 0; 938 939 fw_loading_reg = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 940 /* notify the user only once if PHY FW is still loading */ 941 if (fw_loading_reg) 942 dev_info(ice_hw_to_dev(hw), "Link initialization is blocked by PHY FW initialization. Link initialization will continue after PHY FW initialization completes.\n"); 943 else 944 return 0; 945 946 return rd32_poll_timeout(hw, GL_MNG_FWSM, fw_loading_reg, 947 !(fw_loading_reg & GL_MNG_FWSM_FW_LOADING_M), 948 10000, timeout * 1000); 949 } 950 951 static int __fwlog_send_cmd(void *priv, struct libie_aq_desc *desc, void *buf, 952 u16 size) 953 { 954 struct ice_hw *hw = priv; 955 956 return ice_aq_send_cmd(hw, desc, buf, size, NULL); 957 } 958 959 static int __fwlog_init(struct ice_hw *hw) 960 { 961 struct ice_pf *pf = hw->back; 962 struct libie_fwlog_api api = { 963 .pdev = pf->pdev, 964 .send_cmd = __fwlog_send_cmd, 965 .priv = hw, 966 }; 967 int err; 968 969 /* only support fw log commands on PF 0 */ 970 if (hw->bus.func) 971 return -EINVAL; 972 973 err = ice_debugfs_pf_init(pf); 974 if (err) 975 return err; 976 977 api.debugfs_root = pf->ice_debugfs_pf; 978 979 return libie_fwlog_init(&hw->fwlog, &api); 980 } 981 982 /** 983 * ice_init_hw - main hardware initialization routine 984 * @hw: pointer to the hardware structure 985 */ 986 int ice_init_hw(struct ice_hw *hw) 987 { 988 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 989 void *mac_buf __free(kfree) = NULL; 990 u16 mac_buf_len; 991 int status; 992 993 /* Set MAC type based on DeviceID */ 994 status = ice_set_mac_type(hw); 995 if (status) 996 return status; 997 998 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 999 1000 status = ice_reset(hw, ICE_RESET_PFR); 1001 if (status) 1002 return status; 1003 1004 ice_get_itr_intrl_gran(hw); 1005 1006 status = ice_create_all_ctrlq(hw); 1007 if (status) 1008 goto err_unroll_cqinit; 1009 1010 status = __fwlog_init(hw); 1011 if (status) 1012 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1013 status); 1014 1015 status = ice_clear_pf_cfg(hw); 1016 if (status) 1017 goto err_unroll_cqinit; 1018 1019 /* Set bit to enable Flow Director filters */ 1020 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1021 INIT_LIST_HEAD(&hw->fdir_list_head); 1022 1023 ice_clear_pxe_mode(hw); 1024 1025 status = ice_init_nvm(hw); 1026 if (status) 1027 goto err_unroll_cqinit; 1028 1029 status = ice_get_caps(hw); 1030 if (status) 1031 goto err_unroll_cqinit; 1032 1033 if (!hw->port_info) 1034 hw->port_info = devm_kzalloc_obj(ice_hw_to_dev(hw), 1035 *hw->port_info); 1036 if (!hw->port_info) { 1037 status = -ENOMEM; 1038 goto err_unroll_cqinit; 1039 } 1040 1041 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1042 /* set the back pointer to HW */ 1043 hw->port_info->hw = hw; 1044 1045 /* Initialize port_info struct with switch configuration data */ 1046 status = ice_get_initial_sw_cfg(hw); 1047 if (status) 1048 goto err_unroll_alloc; 1049 1050 hw->evb_veb = true; 1051 1052 xa_init_flags(&hw->sched_node_ids, XA_FLAGS_ALLOC); 1053 1054 /* Query the allocated resources for Tx scheduler */ 1055 status = ice_sched_query_res_alloc(hw); 1056 if (status) { 1057 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1058 goto err_unroll_xarray; 1059 } 1060 ice_sched_get_psm_clk_freq(hw); 1061 1062 /* Initialize port_info struct with scheduler data */ 1063 status = ice_sched_init_port(hw->port_info); 1064 if (status) 1065 goto err_unroll_sched; 1066 1067 pcaps = kzalloc_obj(*pcaps); 1068 if (!pcaps) { 1069 status = -ENOMEM; 1070 goto err_unroll_sched; 1071 } 1072 1073 /* Initialize port_info struct with PHY capabilities */ 1074 status = ice_aq_get_phy_caps(hw->port_info, false, 1075 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1076 NULL); 1077 if (status) 1078 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1079 status); 1080 1081 /* Initialize port_info struct with link information */ 1082 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1083 if (status) 1084 goto err_unroll_sched; 1085 1086 /* need a valid SW entry point to build a Tx tree */ 1087 if (!hw->sw_entry_point_layer) { 1088 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1089 status = -EIO; 1090 goto err_unroll_sched; 1091 } 1092 INIT_LIST_HEAD(&hw->agg_list); 1093 /* Initialize max burst size */ 1094 if (!hw->max_burst_size) 1095 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1096 1097 status = ice_init_fltr_mgmt_struct(hw); 1098 if (status) 1099 goto err_unroll_sched; 1100 1101 /* Get MAC information */ 1102 /* A single port can report up to two (LAN and WoL) addresses */ 1103 mac_buf = kzalloc_objs(struct ice_aqc_manage_mac_read_resp, 2); 1104 if (!mac_buf) { 1105 status = -ENOMEM; 1106 goto err_unroll_fltr_mgmt_struct; 1107 } 1108 1109 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1110 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1111 1112 if (status) 1113 goto err_unroll_fltr_mgmt_struct; 1114 /* enable jumbo frame support at MAC level */ 1115 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1116 if (status) 1117 goto err_unroll_fltr_mgmt_struct; 1118 /* Obtain counter base index which would be used by flow director */ 1119 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1120 if (status) 1121 goto err_unroll_fltr_mgmt_struct; 1122 status = ice_init_hw_tbls(hw); 1123 if (status) 1124 goto err_unroll_fltr_mgmt_struct; 1125 1126 mutex_init(&hw->tnl_lock); 1127 ice_init_chk_recipe_reuse_support(hw); 1128 1129 /* Some cards require longer initialization times 1130 * due to necessity of loading FW from an external source. 1131 * This can take even half a minute. 1132 */ 1133 status = ice_wait_fw_load(hw, 30000); 1134 if (status) { 1135 dev_err(ice_hw_to_dev(hw), "ice_wait_fw_load timed out"); 1136 goto err_unroll_fltr_mgmt_struct; 1137 } 1138 1139 hw->lane_num = ice_get_phy_lane_number(hw); 1140 1141 return 0; 1142 err_unroll_fltr_mgmt_struct: 1143 ice_cleanup_fltr_mgmt_struct(hw); 1144 err_unroll_sched: 1145 ice_sched_cleanup_all(hw); 1146 err_unroll_xarray: 1147 xa_destroy(&hw->sched_node_ids); 1148 err_unroll_alloc: 1149 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1150 err_unroll_cqinit: 1151 ice_destroy_all_ctrlq(hw); 1152 return status; 1153 } 1154 1155 static void __fwlog_deinit(struct ice_hw *hw) 1156 { 1157 /* only support fw log commands on PF 0 */ 1158 if (hw->bus.func) 1159 return; 1160 1161 ice_debugfs_pf_deinit(hw->back); 1162 libie_fwlog_deinit(&hw->fwlog); 1163 } 1164 1165 /** 1166 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1167 * @hw: pointer to the hardware structure 1168 * 1169 * This should be called only during nominal operation, not as a result of 1170 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1171 * applicable initializations if it fails for any reason. 1172 */ 1173 void ice_deinit_hw(struct ice_hw *hw) 1174 { 1175 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1176 ice_cleanup_fltr_mgmt_struct(hw); 1177 1178 ice_sched_cleanup_all(hw); 1179 ice_sched_clear_agg(hw); 1180 ice_free_seg(hw); 1181 ice_free_hw_tbls(hw); 1182 mutex_destroy(&hw->tnl_lock); 1183 __fwlog_deinit(hw); 1184 ice_destroy_all_ctrlq(hw); 1185 1186 /* Clear VSI contexts if not already cleared */ 1187 ice_clear_all_vsi_ctx(hw); 1188 1189 xa_destroy(&hw->sched_node_ids); 1190 } 1191 1192 /** 1193 * ice_check_reset - Check to see if a global reset is complete 1194 * @hw: pointer to the hardware structure 1195 */ 1196 int ice_check_reset(struct ice_hw *hw) 1197 { 1198 u32 cnt, reg = 0, grst_timeout, uld_mask; 1199 1200 /* Poll for Device Active state in case a recent CORER, GLOBR, 1201 * or EMPR has occurred. The grst delay value is in 100ms units. 1202 * Add 1sec for outstanding AQ commands that can take a long time. 1203 */ 1204 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1205 rd32(hw, GLGEN_RSTCTL)) + 10; 1206 1207 for (cnt = 0; cnt < grst_timeout; cnt++) { 1208 mdelay(100); 1209 reg = rd32(hw, GLGEN_RSTAT); 1210 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1211 break; 1212 } 1213 1214 if (cnt == grst_timeout) { 1215 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1216 return -EIO; 1217 } 1218 1219 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1220 GLNVM_ULD_PCIER_DONE_1_M |\ 1221 GLNVM_ULD_CORER_DONE_M |\ 1222 GLNVM_ULD_GLOBR_DONE_M |\ 1223 GLNVM_ULD_POR_DONE_M |\ 1224 GLNVM_ULD_POR_DONE_1_M |\ 1225 GLNVM_ULD_PCIER_DONE_2_M) 1226 1227 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1228 GLNVM_ULD_PE_DONE_M : 0); 1229 1230 /* Device is Active; check Global Reset processes are done */ 1231 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1232 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1233 if (reg == uld_mask) { 1234 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1235 break; 1236 } 1237 mdelay(10); 1238 } 1239 1240 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1241 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1242 reg); 1243 return -EIO; 1244 } 1245 1246 return 0; 1247 } 1248 1249 /** 1250 * ice_pf_reset - Reset the PF 1251 * @hw: pointer to the hardware structure 1252 * 1253 * If a global reset has been triggered, this function checks 1254 * for its completion and then issues the PF reset 1255 */ 1256 static int ice_pf_reset(struct ice_hw *hw) 1257 { 1258 u32 cnt, reg; 1259 1260 /* If at function entry a global reset was already in progress, i.e. 1261 * state is not 'device active' or any of the reset done bits are not 1262 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1263 * global reset is done. 1264 */ 1265 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1266 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1267 /* poll on global reset currently in progress until done */ 1268 if (ice_check_reset(hw)) 1269 return -EIO; 1270 1271 return 0; 1272 } 1273 1274 /* Reset the PF */ 1275 reg = rd32(hw, PFGEN_CTRL); 1276 1277 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1278 1279 /* Wait for the PFR to complete. The wait time is the global config lock 1280 * timeout plus the PFR timeout which will account for a possible reset 1281 * that is occurring during a download package operation. 1282 */ 1283 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1284 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1285 reg = rd32(hw, PFGEN_CTRL); 1286 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1287 break; 1288 1289 mdelay(1); 1290 } 1291 1292 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1293 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1294 return -EIO; 1295 } 1296 1297 return 0; 1298 } 1299 1300 /** 1301 * ice_reset - Perform different types of reset 1302 * @hw: pointer to the hardware structure 1303 * @req: reset request 1304 * 1305 * This function triggers a reset as specified by the req parameter. 1306 * 1307 * Note: 1308 * If anything other than a PF reset is triggered, PXE mode is restored. 1309 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1310 * interface has been restored in the rebuild flow. 1311 */ 1312 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1313 { 1314 u32 val = 0; 1315 1316 switch (req) { 1317 case ICE_RESET_PFR: 1318 return ice_pf_reset(hw); 1319 case ICE_RESET_CORER: 1320 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1321 val = GLGEN_RTRIG_CORER_M; 1322 break; 1323 case ICE_RESET_GLOBR: 1324 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1325 val = GLGEN_RTRIG_GLOBR_M; 1326 break; 1327 default: 1328 return -EINVAL; 1329 } 1330 1331 val |= rd32(hw, GLGEN_RTRIG); 1332 wr32(hw, GLGEN_RTRIG, val); 1333 ice_flush(hw); 1334 1335 /* wait for the FW to be ready */ 1336 return ice_check_reset(hw); 1337 } 1338 1339 /** 1340 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1341 * @hw: pointer to the hardware structure 1342 * @rxq_ctx: pointer to the packed Rx queue context 1343 * @rxq_index: the index of the Rx queue 1344 */ 1345 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1346 const ice_rxq_ctx_buf_t *rxq_ctx, 1347 u32 rxq_index) 1348 { 1349 /* Copy each dword separately to HW */ 1350 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1351 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1352 1353 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1354 1355 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1356 } 1357 } 1358 1359 /** 1360 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1361 * @hw: pointer to the hardware structure 1362 * @rxq_ctx: pointer to the packed Rx queue context 1363 * @rxq_index: the index of the Rx queue 1364 */ 1365 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1366 ice_rxq_ctx_buf_t *rxq_ctx, 1367 u32 rxq_index) 1368 { 1369 u32 *ctx = (u32 *)rxq_ctx; 1370 1371 /* Copy each dword separately from HW */ 1372 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1373 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1374 1375 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1376 } 1377 } 1378 1379 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1380 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1381 1382 /* LAN Rx Queue Context */ 1383 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1384 /* Field Width LSB */ 1385 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1386 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1387 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1388 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1389 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1390 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1391 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1392 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1393 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1394 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1395 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1396 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1397 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1398 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1399 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1400 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1401 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1402 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1403 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1404 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1405 }; 1406 1407 /** 1408 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1409 * @ctx: the Rx queue context to pack 1410 * @buf: the HW buffer to pack into 1411 * 1412 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1413 * bit-packed HW layout. 1414 */ 1415 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1416 ice_rxq_ctx_buf_t *buf) 1417 { 1418 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1419 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1420 } 1421 1422 /** 1423 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1424 * @buf: the HW buffer to unpack from 1425 * @ctx: the Rx queue context to unpack 1426 * 1427 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1428 * structure. 1429 */ 1430 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1431 struct ice_rlan_ctx *ctx) 1432 { 1433 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1434 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1435 } 1436 1437 /** 1438 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1439 * @hw: pointer to the hardware structure 1440 * @rlan_ctx: pointer to the unpacked Rx queue context 1441 * @rxq_index: the index of the Rx queue 1442 * 1443 * Pack the sparse Rx Queue context into dense hardware format and write it 1444 * into the HW register space. 1445 * 1446 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1447 */ 1448 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1449 u32 rxq_index) 1450 { 1451 ice_rxq_ctx_buf_t buf = {}; 1452 1453 if (rxq_index > QRX_CTRL_MAX_INDEX) 1454 return -EINVAL; 1455 1456 ice_pack_rxq_ctx(rlan_ctx, &buf); 1457 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1458 1459 return 0; 1460 } 1461 1462 /** 1463 * ice_read_rxq_ctx - Read Rx queue context from HW 1464 * @hw: pointer to the hardware structure 1465 * @rlan_ctx: pointer to the Rx queue context 1466 * @rxq_index: the index of the Rx queue 1467 * 1468 * Read the Rx queue context from the hardware registers, and unpack it into 1469 * the sparse Rx queue context structure. 1470 * 1471 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1472 */ 1473 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1474 u32 rxq_index) 1475 { 1476 ice_rxq_ctx_buf_t buf = {}; 1477 1478 if (rxq_index > QRX_CTRL_MAX_INDEX) 1479 return -EINVAL; 1480 1481 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1482 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1483 1484 return 0; 1485 } 1486 1487 /* LAN Tx Queue Context */ 1488 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1489 /* Field Width LSB */ 1490 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1491 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1492 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1493 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1494 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1495 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1496 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1497 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1498 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1499 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1500 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1501 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1502 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1503 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1504 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1505 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1506 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1507 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1508 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1509 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1510 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1511 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1512 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1513 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1514 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1515 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1516 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1517 }; 1518 1519 /** 1520 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1521 * @ctx: the Tx queue context to pack 1522 * @buf: the Admin Queue HW buffer to pack into 1523 * 1524 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1525 * bit-packed Admin Queue layout. 1526 */ 1527 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1528 { 1529 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1530 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1531 } 1532 1533 /** 1534 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1535 * @ctx: the Tx queue context to pack 1536 * @buf: the HW buffer to pack into 1537 * 1538 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1539 * bit-packed HW layout, including the internal data portion. 1540 */ 1541 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1542 ice_txq_ctx_buf_full_t *buf) 1543 { 1544 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1545 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1546 } 1547 1548 /** 1549 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1550 * @buf: the HW buffer to unpack from 1551 * @ctx: the Tx queue context to unpack 1552 * 1553 * Unpack the Tx queue context from the HW buffer (including the full internal 1554 * state) into the CPU-friendly structure. 1555 */ 1556 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1557 struct ice_tlan_ctx *ctx) 1558 { 1559 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1560 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1561 } 1562 1563 /** 1564 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1565 * @hw: pointer to the hardware structure 1566 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1567 * @txq_index: the index of the Tx queue 1568 * 1569 * Copy Tx Queue context from HW register space to dense structure 1570 */ 1571 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1572 ice_txq_ctx_buf_full_t *txq_ctx, 1573 u32 txq_index) 1574 { 1575 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1576 u32 *ctx = (u32 *)txq_ctx; 1577 u32 txq_base, reg; 1578 1579 /* Get Tx queue base within card space */ 1580 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1581 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1582 1583 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1584 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1585 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1586 txq_base + txq_index) | 1587 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1588 1589 /* Prevent other PFs on the same adapter from accessing the Tx queue 1590 * context interface concurrently. 1591 */ 1592 spin_lock(&pf->adapter->txq_ctx_lock); 1593 1594 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1595 ice_flush(hw); 1596 1597 /* Copy each dword separately from HW */ 1598 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1599 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1600 1601 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1602 } 1603 1604 spin_unlock(&pf->adapter->txq_ctx_lock); 1605 } 1606 1607 /** 1608 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1609 * @hw: pointer to the hardware structure 1610 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1611 * @txq_index: the index of the Tx queue 1612 */ 1613 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1614 const ice_txq_ctx_buf_full_t *txq_ctx, 1615 u32 txq_index) 1616 { 1617 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1618 u32 txq_base, reg; 1619 1620 /* Get Tx queue base within card space */ 1621 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1622 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1623 1624 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1625 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1626 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1627 txq_base + txq_index) | 1628 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1629 1630 /* Prevent other PFs on the same adapter from accessing the Tx queue 1631 * context interface concurrently. 1632 */ 1633 spin_lock(&pf->adapter->txq_ctx_lock); 1634 1635 /* Copy each dword separately to HW */ 1636 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1637 u32 ctx = ((const u32 *)txq_ctx)[i]; 1638 1639 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1640 1641 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1642 } 1643 1644 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1645 ice_flush(hw); 1646 1647 spin_unlock(&pf->adapter->txq_ctx_lock); 1648 } 1649 1650 /** 1651 * ice_read_txq_ctx - Read Tx queue context from HW 1652 * @hw: pointer to the hardware structure 1653 * @tlan_ctx: pointer to the Tx queue context 1654 * @txq_index: the index of the Tx queue 1655 * 1656 * Read the Tx queue context from the HW registers, then unpack it into the 1657 * ice_tlan_ctx structure for use. 1658 * 1659 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1660 */ 1661 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1662 u32 txq_index) 1663 { 1664 ice_txq_ctx_buf_full_t buf = {}; 1665 1666 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1667 return -EINVAL; 1668 1669 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1670 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1671 1672 return 0; 1673 } 1674 1675 /** 1676 * ice_write_txq_ctx - Write Tx queue context to HW 1677 * @hw: pointer to the hardware structure 1678 * @tlan_ctx: pointer to the Tx queue context 1679 * @txq_index: the index of the Tx queue 1680 * 1681 * Pack the Tx queue context into the dense HW layout, then write it into the 1682 * HW registers. 1683 * 1684 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1685 */ 1686 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1687 u32 txq_index) 1688 { 1689 ice_txq_ctx_buf_full_t buf = {}; 1690 1691 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1692 return -EINVAL; 1693 1694 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1695 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1696 1697 return 0; 1698 } 1699 1700 /* Tx time Queue Context */ 1701 static const struct packed_field_u8 ice_txtime_ctx_fields[] = { 1702 /* Field Width LSB */ 1703 ICE_CTX_STORE(ice_txtime_ctx, base, 57, 0), 1704 ICE_CTX_STORE(ice_txtime_ctx, pf_num, 3, 57), 1705 ICE_CTX_STORE(ice_txtime_ctx, vmvf_num, 10, 60), 1706 ICE_CTX_STORE(ice_txtime_ctx, vmvf_type, 2, 70), 1707 ICE_CTX_STORE(ice_txtime_ctx, src_vsi, 10, 72), 1708 ICE_CTX_STORE(ice_txtime_ctx, cpuid, 8, 82), 1709 ICE_CTX_STORE(ice_txtime_ctx, tphrd_desc, 1, 90), 1710 ICE_CTX_STORE(ice_txtime_ctx, qlen, 13, 91), 1711 ICE_CTX_STORE(ice_txtime_ctx, timer_num, 1, 104), 1712 ICE_CTX_STORE(ice_txtime_ctx, txtime_ena_q, 1, 105), 1713 ICE_CTX_STORE(ice_txtime_ctx, drbell_mode_32, 1, 106), 1714 ICE_CTX_STORE(ice_txtime_ctx, ts_res, 4, 107), 1715 ICE_CTX_STORE(ice_txtime_ctx, ts_round_type, 2, 111), 1716 ICE_CTX_STORE(ice_txtime_ctx, ts_pacing_slot, 3, 113), 1717 ICE_CTX_STORE(ice_txtime_ctx, merging_ena, 1, 116), 1718 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_prof_id, 4, 117), 1719 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_cache_line_aln_thld, 4, 121), 1720 ICE_CTX_STORE(ice_txtime_ctx, tx_pipe_delay_mode, 1, 125), 1721 }; 1722 1723 /** 1724 * ice_pack_txtime_ctx - pack Tx time queue context into a HW buffer 1725 * @ctx: the Tx time queue context to pack 1726 * @buf: the HW buffer to pack into 1727 * 1728 * Pack the Tx time queue context from the CPU-friendly unpacked buffer into 1729 * its bit-packed HW layout. 1730 */ 1731 void ice_pack_txtime_ctx(const struct ice_txtime_ctx *ctx, 1732 ice_txtime_ctx_buf_t *buf) 1733 { 1734 pack_fields(buf, sizeof(*buf), ctx, ice_txtime_ctx_fields, 1735 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1736 } 1737 1738 /* Sideband Queue command wrappers */ 1739 1740 /** 1741 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1742 * @hw: pointer to the HW struct 1743 * @desc: descriptor describing the command 1744 * @buf: buffer to use for indirect commands (NULL for direct commands) 1745 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1746 * @cd: pointer to command details structure 1747 */ 1748 static int 1749 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1750 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1751 { 1752 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1753 (struct libie_aq_desc *)desc, buf, buf_size, cd); 1754 } 1755 1756 /** 1757 * ice_sbq_rw_reg - Fill Sideband Queue command 1758 * @hw: pointer to the HW struct 1759 * @in: message info to be filled in descriptor 1760 * @flags: control queue descriptor flags 1761 */ 1762 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1763 { 1764 struct ice_sbq_cmd_desc desc = {0}; 1765 struct ice_sbq_msg_req msg = {0}; 1766 u16 msg_len; 1767 int status; 1768 1769 msg_len = sizeof(msg); 1770 1771 msg.dest_dev = in->dest_dev; 1772 msg.opcode = in->opcode; 1773 msg.flags = ICE_SBQ_MSG_FLAGS; 1774 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1775 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1776 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1777 1778 if (in->opcode) 1779 msg.data = cpu_to_le32(in->data); 1780 else 1781 /* data read comes back in completion, so shorten the struct by 1782 * sizeof(msg.data) 1783 */ 1784 msg_len -= sizeof(msg.data); 1785 1786 desc.flags = cpu_to_le16(flags); 1787 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1788 desc.param0.cmd_len = cpu_to_le16(msg_len); 1789 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1790 if (!status && !in->opcode) 1791 in->data = le32_to_cpu 1792 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1793 return status; 1794 } 1795 1796 /* FW Admin Queue command wrappers */ 1797 1798 /* Software lock/mutex that is meant to be held while the Global Config Lock 1799 * in firmware is acquired by the software to prevent most (but not all) types 1800 * of AQ commands from being sent to FW 1801 */ 1802 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1803 1804 /** 1805 * ice_should_retry_sq_send_cmd 1806 * @opcode: AQ opcode 1807 * 1808 * Decide if we should retry the send command routine for the ATQ, depending 1809 * on the opcode. 1810 */ 1811 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1812 { 1813 switch (opcode) { 1814 case ice_aqc_opc_get_link_topo: 1815 case ice_aqc_opc_lldp_stop: 1816 case ice_aqc_opc_lldp_start: 1817 case ice_aqc_opc_lldp_filter_ctrl: 1818 case ice_aqc_opc_sff_eeprom: 1819 return true; 1820 } 1821 1822 return false; 1823 } 1824 1825 /** 1826 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1827 * @hw: pointer to the HW struct 1828 * @cq: pointer to the specific Control queue 1829 * @desc: prefilled descriptor describing the command 1830 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1831 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1832 * @cd: pointer to command details structure 1833 * 1834 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1835 * Queue if the EBUSY AQ error is returned. 1836 */ 1837 static int 1838 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1839 struct libie_aq_desc *desc, void *buf, u16 buf_size, 1840 struct ice_sq_cd *cd) 1841 { 1842 struct libie_aq_desc desc_cpy; 1843 bool is_cmd_for_retry; 1844 u8 *buf_cpy = NULL; 1845 u8 idx = 0; 1846 u16 opcode; 1847 int status; 1848 1849 opcode = le16_to_cpu(desc->opcode); 1850 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1851 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1852 1853 if (is_cmd_for_retry) { 1854 if (buf) { 1855 buf_cpy = kmemdup(buf, buf_size, GFP_KERNEL); 1856 if (!buf_cpy) 1857 return -ENOMEM; 1858 } 1859 1860 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1861 } 1862 1863 do { 1864 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1865 1866 if (!is_cmd_for_retry || !status || 1867 hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1868 break; 1869 1870 if (buf_cpy) 1871 memcpy(buf, buf_cpy, buf_size); 1872 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1873 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1874 1875 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1876 1877 kfree(buf_cpy); 1878 return status; 1879 } 1880 1881 /** 1882 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1883 * @hw: pointer to the HW struct 1884 * @desc: descriptor describing the command 1885 * @buf: buffer to use for indirect commands (NULL for direct commands) 1886 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1887 * @cd: pointer to command details structure 1888 * 1889 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1890 */ 1891 int 1892 ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1893 u16 buf_size, struct ice_sq_cd *cd) 1894 { 1895 struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1896 bool lock_acquired = false; 1897 int status; 1898 1899 /* When a package download is in process (i.e. when the firmware's 1900 * Global Configuration Lock resource is held), only the Download 1901 * Package, Get Version, Get Package Info List, Upload Section, 1902 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1903 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1904 * Recipes to Profile Association, and Release Resource (with resource 1905 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1906 * must block until the package download completes and the Global Config 1907 * Lock is released. See also ice_acquire_global_cfg_lock(). 1908 */ 1909 switch (le16_to_cpu(desc->opcode)) { 1910 case ice_aqc_opc_download_pkg: 1911 case ice_aqc_opc_get_pkg_info_list: 1912 case ice_aqc_opc_get_ver: 1913 case ice_aqc_opc_upload_section: 1914 case ice_aqc_opc_update_pkg: 1915 case ice_aqc_opc_set_port_params: 1916 case ice_aqc_opc_get_vlan_mode_parameters: 1917 case ice_aqc_opc_set_vlan_mode_parameters: 1918 case ice_aqc_opc_set_tx_topo: 1919 case ice_aqc_opc_get_tx_topo: 1920 case ice_aqc_opc_add_recipe: 1921 case ice_aqc_opc_recipe_to_profile: 1922 case ice_aqc_opc_get_recipe: 1923 case ice_aqc_opc_get_recipe_to_profile: 1924 break; 1925 case ice_aqc_opc_release_res: 1926 if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1927 break; 1928 fallthrough; 1929 default: 1930 mutex_lock(&ice_global_cfg_lock_sw); 1931 lock_acquired = true; 1932 break; 1933 } 1934 1935 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1936 if (lock_acquired) 1937 mutex_unlock(&ice_global_cfg_lock_sw); 1938 1939 return status; 1940 } 1941 1942 /** 1943 * ice_aq_get_fw_ver 1944 * @hw: pointer to the HW struct 1945 * @cd: pointer to command details structure or NULL 1946 * 1947 * Get the firmware version (0x0001) from the admin queue commands 1948 */ 1949 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1950 { 1951 struct libie_aqc_get_ver *resp; 1952 struct libie_aq_desc desc; 1953 int status; 1954 1955 resp = &desc.params.get_ver; 1956 1957 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1958 1959 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1960 1961 if (!status) { 1962 hw->fw_branch = resp->fw_branch; 1963 hw->fw_maj_ver = resp->fw_major; 1964 hw->fw_min_ver = resp->fw_minor; 1965 hw->fw_patch = resp->fw_patch; 1966 hw->fw_build = le32_to_cpu(resp->fw_build); 1967 hw->api_branch = resp->api_branch; 1968 hw->api_maj_ver = resp->api_major; 1969 hw->api_min_ver = resp->api_minor; 1970 hw->api_patch = resp->api_patch; 1971 } 1972 1973 return status; 1974 } 1975 1976 /** 1977 * ice_aq_send_driver_ver 1978 * @hw: pointer to the HW struct 1979 * @dv: driver's major, minor version 1980 * @cd: pointer to command details structure or NULL 1981 * 1982 * Send the driver version (0x0002) to the firmware 1983 */ 1984 int 1985 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1986 struct ice_sq_cd *cd) 1987 { 1988 struct libie_aqc_driver_ver *cmd; 1989 struct libie_aq_desc desc; 1990 u16 len; 1991 1992 cmd = &desc.params.driver_ver; 1993 1994 if (!dv) 1995 return -EINVAL; 1996 1997 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1998 1999 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2000 cmd->major_ver = dv->major_ver; 2001 cmd->minor_ver = dv->minor_ver; 2002 cmd->build_ver = dv->build_ver; 2003 cmd->subbuild_ver = dv->subbuild_ver; 2004 2005 len = 0; 2006 while (len < sizeof(dv->driver_string) && 2007 isascii(dv->driver_string[len]) && dv->driver_string[len]) 2008 len++; 2009 2010 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 2011 } 2012 2013 /** 2014 * ice_aq_q_shutdown 2015 * @hw: pointer to the HW struct 2016 * @unloading: is the driver unloading itself 2017 * 2018 * Tell the Firmware that we're shutting down the AdminQ and whether 2019 * or not the driver is unloading as well (0x0003). 2020 */ 2021 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 2022 { 2023 struct ice_aqc_q_shutdown *cmd; 2024 struct libie_aq_desc desc; 2025 2026 cmd = libie_aq_raw(&desc); 2027 2028 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 2029 2030 if (unloading) 2031 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 2032 2033 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2034 } 2035 2036 /** 2037 * ice_aq_req_res 2038 * @hw: pointer to the HW struct 2039 * @res: resource ID 2040 * @access: access type 2041 * @sdp_number: resource number 2042 * @timeout: the maximum time in ms that the driver may hold the resource 2043 * @cd: pointer to command details structure or NULL 2044 * 2045 * Requests common resource using the admin queue commands (0x0008). 2046 * When attempting to acquire the Global Config Lock, the driver can 2047 * learn of three states: 2048 * 1) 0 - acquired lock, and can perform download package 2049 * 2) -EIO - did not get lock, driver should fail to load 2050 * 3) -EALREADY - did not get lock, but another driver has 2051 * successfully downloaded the package; the driver does 2052 * not have to download the package and can continue 2053 * loading 2054 * 2055 * Note that if the caller is in an acquire lock, perform action, release lock 2056 * phase of operation, it is possible that the FW may detect a timeout and issue 2057 * a CORER. In this case, the driver will receive a CORER interrupt and will 2058 * have to determine its cause. The calling thread that is handling this flow 2059 * will likely get an error propagated back to it indicating the Download 2060 * Package, Update Package or the Release Resource AQ commands timed out. 2061 */ 2062 static int 2063 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2064 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2065 struct ice_sq_cd *cd) 2066 { 2067 struct libie_aqc_req_res *cmd_resp; 2068 struct libie_aq_desc desc; 2069 int status; 2070 2071 cmd_resp = &desc.params.res_owner; 2072 2073 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2074 2075 cmd_resp->res_id = cpu_to_le16(res); 2076 cmd_resp->access_type = cpu_to_le16(access); 2077 cmd_resp->res_number = cpu_to_le32(sdp_number); 2078 cmd_resp->timeout = cpu_to_le32(*timeout); 2079 *timeout = 0; 2080 2081 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2082 2083 /* The completion specifies the maximum time in ms that the driver 2084 * may hold the resource in the Timeout field. 2085 */ 2086 2087 /* Global config lock response utilizes an additional status field. 2088 * 2089 * If the Global config lock resource is held by some other driver, the 2090 * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2091 * and the timeout field indicates the maximum time the current owner 2092 * of the resource has to free it. 2093 */ 2094 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2095 if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2096 *timeout = le32_to_cpu(cmd_resp->timeout); 2097 return 0; 2098 } else if (le16_to_cpu(cmd_resp->status) == 2099 LIBIE_AQ_RES_GLBL_IN_PROG) { 2100 *timeout = le32_to_cpu(cmd_resp->timeout); 2101 return -EIO; 2102 } else if (le16_to_cpu(cmd_resp->status) == 2103 LIBIE_AQ_RES_GLBL_DONE) { 2104 return -EALREADY; 2105 } 2106 2107 /* invalid FW response, force a timeout immediately */ 2108 *timeout = 0; 2109 return -EIO; 2110 } 2111 2112 /* If the resource is held by some other driver, the command completes 2113 * with a busy return value and the timeout field indicates the maximum 2114 * time the current owner of the resource has to free it. 2115 */ 2116 if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2117 *timeout = le32_to_cpu(cmd_resp->timeout); 2118 2119 return status; 2120 } 2121 2122 /** 2123 * ice_aq_release_res 2124 * @hw: pointer to the HW struct 2125 * @res: resource ID 2126 * @sdp_number: resource number 2127 * @cd: pointer to command details structure or NULL 2128 * 2129 * release common resource using the admin queue commands (0x0009) 2130 */ 2131 static int 2132 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2133 struct ice_sq_cd *cd) 2134 { 2135 struct libie_aqc_req_res *cmd; 2136 struct libie_aq_desc desc; 2137 2138 cmd = &desc.params.res_owner; 2139 2140 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2141 2142 cmd->res_id = cpu_to_le16(res); 2143 cmd->res_number = cpu_to_le32(sdp_number); 2144 2145 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2146 } 2147 2148 /** 2149 * ice_acquire_res 2150 * @hw: pointer to the HW structure 2151 * @res: resource ID 2152 * @access: access type (read or write) 2153 * @timeout: timeout in milliseconds 2154 * 2155 * This function will attempt to acquire the ownership of a resource. 2156 */ 2157 int 2158 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2159 enum ice_aq_res_access_type access, u32 timeout) 2160 { 2161 #define ICE_RES_POLLING_DELAY_MS 10 2162 u32 delay = ICE_RES_POLLING_DELAY_MS; 2163 u32 time_left = timeout; 2164 int status; 2165 2166 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2167 2168 /* A return code of -EALREADY means that another driver has 2169 * previously acquired the resource and performed any necessary updates; 2170 * in this case the caller does not obtain the resource and has no 2171 * further work to do. 2172 */ 2173 if (status == -EALREADY) 2174 goto ice_acquire_res_exit; 2175 2176 if (status) 2177 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2178 2179 /* If necessary, poll until the current lock owner timeouts */ 2180 timeout = time_left; 2181 while (status && timeout && time_left) { 2182 mdelay(delay); 2183 timeout = (timeout > delay) ? timeout - delay : 0; 2184 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2185 2186 if (status == -EALREADY) 2187 /* lock free, but no work to do */ 2188 break; 2189 2190 if (!status) 2191 /* lock acquired */ 2192 break; 2193 } 2194 if (status && status != -EALREADY) 2195 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2196 2197 ice_acquire_res_exit: 2198 if (status == -EALREADY) { 2199 if (access == ICE_RES_WRITE) 2200 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2201 else 2202 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2203 } 2204 return status; 2205 } 2206 2207 /** 2208 * ice_release_res 2209 * @hw: pointer to the HW structure 2210 * @res: resource ID 2211 * 2212 * This function will release a resource using the proper Admin Command. 2213 */ 2214 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2215 { 2216 unsigned long timeout; 2217 int status; 2218 2219 /* there are some rare cases when trying to release the resource 2220 * results in an admin queue timeout, so handle them correctly 2221 */ 2222 timeout = jiffies + 10 * usecs_to_jiffies(ICE_CTL_Q_SQ_CMD_TIMEOUT); 2223 do { 2224 status = ice_aq_release_res(hw, res, 0, NULL); 2225 if (status != -EIO) 2226 break; 2227 usleep_range(1000, 2000); 2228 } while (time_before(jiffies, timeout)); 2229 } 2230 2231 /** 2232 * ice_aq_alloc_free_res - command to allocate/free resources 2233 * @hw: pointer to the HW struct 2234 * @buf: Indirect buffer to hold data parameters and response 2235 * @buf_size: size of buffer for indirect commands 2236 * @opc: pass in the command opcode 2237 * 2238 * Helper function to allocate/free resources using the admin queue commands 2239 */ 2240 int ice_aq_alloc_free_res(struct ice_hw *hw, 2241 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2242 enum ice_adminq_opc opc) 2243 { 2244 struct ice_aqc_alloc_free_res_cmd *cmd; 2245 struct libie_aq_desc desc; 2246 2247 cmd = libie_aq_raw(&desc); 2248 2249 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2250 return -EINVAL; 2251 2252 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2253 2254 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2255 2256 cmd->num_entries = cpu_to_le16(1); 2257 2258 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2259 } 2260 2261 /** 2262 * ice_alloc_hw_res - allocate resource 2263 * @hw: pointer to the HW struct 2264 * @type: type of resource 2265 * @num: number of resources to allocate 2266 * @btm: allocate from bottom 2267 * @res: pointer to array that will receive the resources 2268 */ 2269 int 2270 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2271 { 2272 struct ice_aqc_alloc_free_res_elem *buf; 2273 u16 buf_len; 2274 int status; 2275 2276 buf_len = struct_size(buf, elem, num); 2277 buf = kzalloc(buf_len, GFP_KERNEL); 2278 if (!buf) 2279 return -ENOMEM; 2280 2281 /* Prepare buffer to allocate resource. */ 2282 buf->num_elems = cpu_to_le16(num); 2283 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2284 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2285 if (btm) 2286 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2287 2288 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2289 if (status) 2290 goto ice_alloc_res_exit; 2291 2292 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2293 2294 ice_alloc_res_exit: 2295 kfree(buf); 2296 return status; 2297 } 2298 2299 /** 2300 * ice_free_hw_res - free allocated HW resource 2301 * @hw: pointer to the HW struct 2302 * @type: type of resource to free 2303 * @num: number of resources 2304 * @res: pointer to array that contains the resources to free 2305 */ 2306 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2307 { 2308 struct ice_aqc_alloc_free_res_elem *buf; 2309 u16 buf_len; 2310 int status; 2311 2312 buf_len = struct_size(buf, elem, num); 2313 buf = kzalloc(buf_len, GFP_KERNEL); 2314 if (!buf) 2315 return -ENOMEM; 2316 2317 /* Prepare buffer to free resource. */ 2318 buf->num_elems = cpu_to_le16(num); 2319 buf->res_type = cpu_to_le16(type); 2320 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2321 2322 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2323 if (status) 2324 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2325 2326 kfree(buf); 2327 return status; 2328 } 2329 2330 /** 2331 * ice_get_num_per_func - determine number of resources per PF 2332 * @hw: pointer to the HW structure 2333 * @max: value to be evenly split between each PF 2334 * 2335 * Determine the number of valid functions by going through the bitmap returned 2336 * from parsing capabilities and use this to calculate the number of resources 2337 * per PF based on the max value passed in. 2338 */ 2339 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2340 { 2341 u8 funcs; 2342 2343 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2344 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2345 ICE_CAPS_VALID_FUNCS_M); 2346 2347 if (!funcs) 2348 return 0; 2349 2350 return max / funcs; 2351 } 2352 2353 /** 2354 * ice_parse_common_caps - parse common device/function capabilities 2355 * @hw: pointer to the HW struct 2356 * @caps: pointer to common capabilities structure 2357 * @elem: the capability element to parse 2358 * @prefix: message prefix for tracing capabilities 2359 * 2360 * Given a capability element, extract relevant details into the common 2361 * capability structure. 2362 * 2363 * Returns: true if the capability matches one of the common capability ids, 2364 * false otherwise. 2365 */ 2366 static bool 2367 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2368 struct libie_aqc_list_caps_elem *elem, const char *prefix) 2369 { 2370 u32 logical_id = le32_to_cpu(elem->logical_id); 2371 u32 phys_id = le32_to_cpu(elem->phys_id); 2372 u32 number = le32_to_cpu(elem->number); 2373 u16 cap = le16_to_cpu(elem->cap); 2374 bool found = true; 2375 2376 switch (cap) { 2377 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2378 caps->valid_functions = number; 2379 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2380 caps->valid_functions); 2381 break; 2382 case LIBIE_AQC_CAPS_SRIOV: 2383 caps->sr_iov_1_1 = (number == 1); 2384 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2385 caps->sr_iov_1_1); 2386 break; 2387 case LIBIE_AQC_CAPS_DCB: 2388 caps->dcb = (number == 1); 2389 caps->active_tc_bitmap = logical_id; 2390 caps->maxtc = phys_id; 2391 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2392 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2393 caps->active_tc_bitmap); 2394 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2395 break; 2396 case LIBIE_AQC_CAPS_RSS: 2397 caps->rss_table_size = number; 2398 caps->rss_table_entry_width = logical_id; 2399 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2400 caps->rss_table_size); 2401 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2402 caps->rss_table_entry_width); 2403 break; 2404 case LIBIE_AQC_CAPS_RXQS: 2405 caps->num_rxq = number; 2406 caps->rxq_first_id = phys_id; 2407 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2408 caps->num_rxq); 2409 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2410 caps->rxq_first_id); 2411 break; 2412 case LIBIE_AQC_CAPS_TXQS: 2413 caps->num_txq = number; 2414 caps->txq_first_id = phys_id; 2415 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2416 caps->num_txq); 2417 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2418 caps->txq_first_id); 2419 break; 2420 case LIBIE_AQC_CAPS_MSIX: 2421 caps->num_msix_vectors = number; 2422 caps->msix_vector_first_id = phys_id; 2423 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2424 caps->num_msix_vectors); 2425 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2426 caps->msix_vector_first_id); 2427 break; 2428 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2429 caps->nvm_update_pending_nvm = true; 2430 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2431 break; 2432 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2433 caps->nvm_update_pending_orom = true; 2434 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2435 break; 2436 case LIBIE_AQC_CAPS_PENDING_NET_VER: 2437 caps->nvm_update_pending_netlist = true; 2438 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2439 break; 2440 case LIBIE_AQC_CAPS_NVM_MGMT: 2441 caps->nvm_unified_update = 2442 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2443 true : false; 2444 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2445 caps->nvm_unified_update); 2446 break; 2447 case LIBIE_AQC_CAPS_RDMA: 2448 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2449 caps->rdma = (number == 1); 2450 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2451 break; 2452 case LIBIE_AQC_CAPS_MAX_MTU: 2453 caps->max_mtu = number; 2454 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2455 prefix, caps->max_mtu); 2456 break; 2457 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2458 caps->pcie_reset_avoidance = (number > 0); 2459 ice_debug(hw, ICE_DBG_INIT, 2460 "%s: pcie_reset_avoidance = %d\n", prefix, 2461 caps->pcie_reset_avoidance); 2462 break; 2463 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2464 caps->reset_restrict_support = (number == 1); 2465 ice_debug(hw, ICE_DBG_INIT, 2466 "%s: reset_restrict_support = %d\n", prefix, 2467 caps->reset_restrict_support); 2468 break; 2469 case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2470 caps->roce_lag = number & LIBIE_AQC_BIT_ROCEV2_LAG; 2471 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2472 prefix, caps->roce_lag); 2473 caps->sriov_lag = number & LIBIE_AQC_BIT_SRIOV_LAG; 2474 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2475 prefix, caps->sriov_lag); 2476 caps->sriov_aa_lag = number & LIBIE_AQC_BIT_SRIOV_AA_LAG; 2477 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_aa_lag = %u\n", 2478 prefix, caps->sriov_aa_lag); 2479 break; 2480 case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2481 caps->tx_sched_topo_comp_mode_en = (number == 1); 2482 break; 2483 default: 2484 /* Not one of the recognized common capabilities */ 2485 found = false; 2486 } 2487 2488 return found; 2489 } 2490 2491 /** 2492 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2493 * @hw: pointer to the HW structure 2494 * @caps: pointer to capabilities structure to fix 2495 * 2496 * Re-calculate the capabilities that are dependent on the number of physical 2497 * ports; i.e. some features are not supported or function differently on 2498 * devices with more than 4 ports. 2499 */ 2500 static void 2501 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2502 { 2503 /* This assumes device capabilities are always scanned before function 2504 * capabilities during the initialization flow. 2505 */ 2506 if (hw->dev_caps.num_funcs > 4) { 2507 /* Max 4 TCs per port */ 2508 caps->maxtc = 4; 2509 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2510 caps->maxtc); 2511 if (caps->rdma) { 2512 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2513 caps->rdma = 0; 2514 } 2515 2516 /* print message only when processing device capabilities 2517 * during initialization. 2518 */ 2519 if (caps == &hw->dev_caps.common_cap) 2520 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2521 } 2522 } 2523 2524 /** 2525 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2526 * @hw: pointer to the HW struct 2527 * @func_p: pointer to function capabilities structure 2528 * @cap: pointer to the capability element to parse 2529 * 2530 * Extract function capabilities for ICE_AQC_CAPS_VF. 2531 */ 2532 static void 2533 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2534 struct libie_aqc_list_caps_elem *cap) 2535 { 2536 u32 logical_id = le32_to_cpu(cap->logical_id); 2537 u32 number = le32_to_cpu(cap->number); 2538 2539 func_p->num_allocd_vfs = number; 2540 func_p->vf_base_id = logical_id; 2541 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2542 func_p->num_allocd_vfs); 2543 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2544 func_p->vf_base_id); 2545 } 2546 2547 /** 2548 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2549 * @hw: pointer to the HW struct 2550 * @func_p: pointer to function capabilities structure 2551 * @cap: pointer to the capability element to parse 2552 * 2553 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2554 */ 2555 static void 2556 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2557 struct libie_aqc_list_caps_elem *cap) 2558 { 2559 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2560 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2561 le32_to_cpu(cap->number)); 2562 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2563 func_p->guar_num_vsi); 2564 } 2565 2566 /** 2567 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2568 * @hw: pointer to the HW struct 2569 * @func_p: pointer to function capabilities structure 2570 * @cap: pointer to the capability element to parse 2571 * 2572 * Extract function capabilities for ICE_AQC_CAPS_1588. 2573 */ 2574 static void 2575 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2576 struct libie_aqc_list_caps_elem *cap) 2577 { 2578 struct ice_ts_func_info *info = &func_p->ts_func_info; 2579 u32 number = le32_to_cpu(cap->number); 2580 2581 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2582 func_p->common_cap.ieee_1588 = info->ena; 2583 2584 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2585 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2586 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2587 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2588 2589 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2590 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2591 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2592 } else { 2593 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2594 info->clk_src = ICE_CLK_SRC_TIME_REF; 2595 } 2596 2597 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2598 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2599 } else { 2600 /* Unknown clock frequency, so assume a (probably incorrect) 2601 * default to avoid out-of-bounds look ups of frequency 2602 * related information. 2603 */ 2604 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2605 info->clk_freq); 2606 info->time_ref = ICE_TSPLL_FREQ_25_000; 2607 } 2608 2609 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2610 func_p->common_cap.ieee_1588); 2611 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2612 info->src_tmr_owned); 2613 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2614 info->tmr_ena); 2615 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2616 info->tmr_index_owned); 2617 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2618 info->tmr_index_assoc); 2619 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2620 info->clk_freq); 2621 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2622 info->clk_src); 2623 } 2624 2625 /** 2626 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2627 * @hw: pointer to the HW struct 2628 * @func_p: pointer to function capabilities structure 2629 * 2630 * Extract function capabilities for ICE_AQC_CAPS_FD. 2631 */ 2632 static void 2633 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2634 { 2635 u32 reg_val, gsize, bsize; 2636 2637 reg_val = rd32(hw, GLQF_FD_SIZE); 2638 switch (hw->mac_type) { 2639 case ICE_MAC_E830: 2640 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2641 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2642 break; 2643 case ICE_MAC_E810: 2644 default: 2645 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2646 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2647 } 2648 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2649 func_p->fd_fltr_best_effort = bsize; 2650 2651 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2652 func_p->fd_fltr_guar); 2653 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2654 func_p->fd_fltr_best_effort); 2655 } 2656 2657 /** 2658 * ice_parse_func_caps - Parse function capabilities 2659 * @hw: pointer to the HW struct 2660 * @func_p: pointer to function capabilities structure 2661 * @buf: buffer containing the function capability records 2662 * @cap_count: the number of capabilities 2663 * 2664 * Helper function to parse function (0x000A) capabilities list. For 2665 * capabilities shared between device and function, this relies on 2666 * ice_parse_common_caps. 2667 * 2668 * Loop through the list of provided capabilities and extract the relevant 2669 * data into the function capabilities structured. 2670 */ 2671 static void 2672 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2673 void *buf, u32 cap_count) 2674 { 2675 struct libie_aqc_list_caps_elem *cap_resp; 2676 u32 i; 2677 2678 cap_resp = buf; 2679 2680 memset(func_p, 0, sizeof(*func_p)); 2681 2682 for (i = 0; i < cap_count; i++) { 2683 u16 cap = le16_to_cpu(cap_resp[i].cap); 2684 bool found; 2685 2686 found = ice_parse_common_caps(hw, &func_p->common_cap, 2687 &cap_resp[i], "func caps"); 2688 2689 switch (cap) { 2690 case LIBIE_AQC_CAPS_VF: 2691 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2692 break; 2693 case LIBIE_AQC_CAPS_VSI: 2694 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2695 break; 2696 case LIBIE_AQC_CAPS_1588: 2697 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2698 break; 2699 case LIBIE_AQC_CAPS_FD: 2700 ice_parse_fdir_func_caps(hw, func_p); 2701 break; 2702 default: 2703 /* Don't list common capabilities as unknown */ 2704 if (!found) 2705 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2706 i, cap); 2707 break; 2708 } 2709 } 2710 2711 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2712 } 2713 2714 /** 2715 * ice_func_id_to_logical_id - map from function id to logical pf id 2716 * @active_function_bitmap: active function bitmap 2717 * @pf_id: function number of device 2718 * 2719 * Return: logical PF ID. 2720 */ 2721 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2722 { 2723 u8 logical_id = 0; 2724 u8 i; 2725 2726 for (i = 0; i < pf_id; i++) 2727 if (active_function_bitmap & BIT(i)) 2728 logical_id++; 2729 2730 return logical_id; 2731 } 2732 2733 /** 2734 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2735 * @hw: pointer to the HW struct 2736 * @dev_p: pointer to device capabilities structure 2737 * @cap: capability element to parse 2738 * 2739 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2740 */ 2741 static void 2742 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2743 struct libie_aqc_list_caps_elem *cap) 2744 { 2745 u32 number = le32_to_cpu(cap->number); 2746 2747 dev_p->num_funcs = hweight32(number); 2748 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2749 dev_p->num_funcs); 2750 2751 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2752 } 2753 2754 /** 2755 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2756 * @hw: pointer to the HW struct 2757 * @dev_p: pointer to device capabilities structure 2758 * @cap: capability element to parse 2759 * 2760 * Parse ICE_AQC_CAPS_VF for device capabilities. 2761 */ 2762 static void 2763 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2764 struct libie_aqc_list_caps_elem *cap) 2765 { 2766 u32 number = le32_to_cpu(cap->number); 2767 2768 dev_p->num_vfs_exposed = number; 2769 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2770 dev_p->num_vfs_exposed); 2771 } 2772 2773 /** 2774 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2775 * @hw: pointer to the HW struct 2776 * @dev_p: pointer to device capabilities structure 2777 * @cap: capability element to parse 2778 * 2779 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2780 */ 2781 static void 2782 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2783 struct libie_aqc_list_caps_elem *cap) 2784 { 2785 u32 number = le32_to_cpu(cap->number); 2786 2787 dev_p->num_vsi_allocd_to_host = number; 2788 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2789 dev_p->num_vsi_allocd_to_host); 2790 } 2791 2792 /** 2793 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2794 * @hw: pointer to the HW struct 2795 * @dev_p: pointer to device capabilities structure 2796 * @cap: capability element to parse 2797 * 2798 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2799 */ 2800 static void 2801 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2802 struct libie_aqc_list_caps_elem *cap) 2803 { 2804 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2805 u32 logical_id = le32_to_cpu(cap->logical_id); 2806 u32 phys_id = le32_to_cpu(cap->phys_id); 2807 u32 number = le32_to_cpu(cap->number); 2808 2809 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2810 dev_p->common_cap.ieee_1588 = info->ena; 2811 2812 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2813 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2814 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2815 2816 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2817 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2818 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2819 2820 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2821 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2822 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2823 2824 info->ena_ports = logical_id; 2825 info->tmr_own_map = phys_id; 2826 2827 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2828 dev_p->common_cap.ieee_1588); 2829 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2830 info->tmr0_owner); 2831 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2832 info->tmr0_owned); 2833 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2834 info->tmr0_ena); 2835 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2836 info->tmr1_owner); 2837 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2838 info->tmr1_owned); 2839 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2840 info->tmr1_ena); 2841 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2842 info->ts_ll_read); 2843 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2844 info->ts_ll_int_read); 2845 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2846 info->ll_phy_tmr_update); 2847 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2848 info->ena_ports); 2849 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2850 info->tmr_own_map); 2851 } 2852 2853 /** 2854 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2855 * @hw: pointer to the HW struct 2856 * @dev_p: pointer to device capabilities structure 2857 * @cap: capability element to parse 2858 * 2859 * Parse ICE_AQC_CAPS_FD for device capabilities. 2860 */ 2861 static void 2862 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2863 struct libie_aqc_list_caps_elem *cap) 2864 { 2865 u32 number = le32_to_cpu(cap->number); 2866 2867 dev_p->num_flow_director_fltr = number; 2868 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2869 dev_p->num_flow_director_fltr); 2870 } 2871 2872 /** 2873 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2874 * @hw: pointer to the HW struct 2875 * @dev_p: pointer to device capabilities structure 2876 * @cap: capability element to parse 2877 * 2878 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2879 * enabled sensors. 2880 */ 2881 static void 2882 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2883 struct libie_aqc_list_caps_elem *cap) 2884 { 2885 dev_p->supported_sensors = le32_to_cpu(cap->number); 2886 2887 ice_debug(hw, ICE_DBG_INIT, 2888 "dev caps: supported sensors (bitmap) = 0x%x\n", 2889 dev_p->supported_sensors); 2890 } 2891 2892 /** 2893 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2894 * @hw: pointer to the HW struct 2895 * @dev_p: pointer to device capabilities structure 2896 * @cap: capability element to parse 2897 * 2898 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2899 */ 2900 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2901 struct ice_hw_dev_caps *dev_p, 2902 struct libie_aqc_list_caps_elem *cap) 2903 { 2904 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2905 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2906 2907 dev_info(ice_hw_to_dev(hw), 2908 "PF is configured in %s mode with IP instance ID %d\n", 2909 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2910 "primary" : "secondary", dev_p->nac_topo.id); 2911 2912 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2913 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2914 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2915 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2916 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2917 dev_p->nac_topo.id); 2918 } 2919 2920 /** 2921 * ice_parse_dev_caps - Parse device capabilities 2922 * @hw: pointer to the HW struct 2923 * @dev_p: pointer to device capabilities structure 2924 * @buf: buffer containing the device capability records 2925 * @cap_count: the number of capabilities 2926 * 2927 * Helper device to parse device (0x000B) capabilities list. For 2928 * capabilities shared between device and function, this relies on 2929 * ice_parse_common_caps. 2930 * 2931 * Loop through the list of provided capabilities and extract the relevant 2932 * data into the device capabilities structured. 2933 */ 2934 static void 2935 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2936 void *buf, u32 cap_count) 2937 { 2938 struct libie_aqc_list_caps_elem *cap_resp; 2939 u32 i; 2940 2941 cap_resp = buf; 2942 2943 memset(dev_p, 0, sizeof(*dev_p)); 2944 2945 for (i = 0; i < cap_count; i++) { 2946 u16 cap = le16_to_cpu(cap_resp[i].cap); 2947 bool found; 2948 2949 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2950 &cap_resp[i], "dev caps"); 2951 2952 switch (cap) { 2953 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2954 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2955 break; 2956 case LIBIE_AQC_CAPS_VF: 2957 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2958 break; 2959 case LIBIE_AQC_CAPS_VSI: 2960 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2961 break; 2962 case LIBIE_AQC_CAPS_1588: 2963 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2964 break; 2965 case LIBIE_AQC_CAPS_FD: 2966 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2967 break; 2968 case LIBIE_AQC_CAPS_SENSOR_READING: 2969 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2970 break; 2971 case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 2972 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2973 break; 2974 default: 2975 /* Don't list common capabilities as unknown */ 2976 if (!found) 2977 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2978 i, cap); 2979 break; 2980 } 2981 } 2982 2983 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2984 } 2985 2986 /** 2987 * ice_is_phy_rclk_in_netlist 2988 * @hw: pointer to the hw struct 2989 * 2990 * Check if the PHY Recovered Clock device is present in the netlist 2991 */ 2992 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2993 { 2994 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2995 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2996 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2997 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2998 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2999 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 3000 return false; 3001 3002 return true; 3003 } 3004 3005 /** 3006 * ice_is_clock_mux_in_netlist 3007 * @hw: pointer to the hw struct 3008 * 3009 * Check if the Clock Multiplexer device is present in the netlist 3010 */ 3011 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 3012 { 3013 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 3014 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3015 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 3016 NULL)) 3017 return false; 3018 3019 return true; 3020 } 3021 3022 /** 3023 * ice_is_cgu_in_netlist - check for CGU presence 3024 * @hw: pointer to the hw struct 3025 * 3026 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 3027 * Save the CGU part number in the hw structure for later use. 3028 * Return: 3029 * * true - cgu is present 3030 * * false - cgu is not present 3031 */ 3032 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 3033 { 3034 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3035 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3036 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 3037 NULL)) { 3038 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 3039 return true; 3040 } else if (!ice_find_netlist_node(hw, 3041 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3042 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3043 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 3044 NULL)) { 3045 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 3046 return true; 3047 } 3048 3049 return false; 3050 } 3051 3052 /** 3053 * ice_is_gps_in_netlist 3054 * @hw: pointer to the hw struct 3055 * 3056 * Check if the GPS generic device is present in the netlist 3057 */ 3058 bool ice_is_gps_in_netlist(struct ice_hw *hw) 3059 { 3060 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3061 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3062 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3063 return false; 3064 3065 return true; 3066 } 3067 3068 /** 3069 * ice_aq_list_caps - query function/device capabilities 3070 * @hw: pointer to the HW struct 3071 * @buf: a buffer to hold the capabilities 3072 * @buf_size: size of the buffer 3073 * @cap_count: if not NULL, set to the number of capabilities reported 3074 * @opc: capabilities type to discover, device or function 3075 * @cd: pointer to command details structure or NULL 3076 * 3077 * Get the function (0x000A) or device (0x000B) capabilities description from 3078 * firmware and store it in the buffer. 3079 * 3080 * If the cap_count pointer is not NULL, then it is set to the number of 3081 * capabilities firmware will report. Note that if the buffer size is too 3082 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3083 * cap_count will still be updated in this case. It is recommended that the 3084 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3085 * firmware could return) to avoid this. 3086 */ 3087 int 3088 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3089 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3090 { 3091 struct libie_aqc_list_caps *cmd; 3092 struct libie_aq_desc desc; 3093 int status; 3094 3095 cmd = &desc.params.get_cap; 3096 3097 if (opc != ice_aqc_opc_list_func_caps && 3098 opc != ice_aqc_opc_list_dev_caps) 3099 return -EINVAL; 3100 3101 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3102 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3103 3104 if (cap_count) 3105 *cap_count = le32_to_cpu(cmd->count); 3106 3107 return status; 3108 } 3109 3110 /** 3111 * ice_discover_dev_caps - Read and extract device capabilities 3112 * @hw: pointer to the hardware structure 3113 * @dev_caps: pointer to device capabilities structure 3114 * 3115 * Read the device capabilities and extract them into the dev_caps structure 3116 * for later use. 3117 */ 3118 int 3119 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3120 { 3121 u32 cap_count = 0; 3122 void *cbuf; 3123 int status; 3124 3125 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3126 if (!cbuf) 3127 return -ENOMEM; 3128 3129 /* Although the driver doesn't know the number of capabilities the 3130 * device will return, we can simply send a 4KB buffer, the maximum 3131 * possible size that firmware can return. 3132 */ 3133 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3134 3135 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3136 ice_aqc_opc_list_dev_caps, NULL); 3137 if (!status) 3138 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3139 kfree(cbuf); 3140 3141 return status; 3142 } 3143 3144 /** 3145 * ice_discover_func_caps - Read and extract function capabilities 3146 * @hw: pointer to the hardware structure 3147 * @func_caps: pointer to function capabilities structure 3148 * 3149 * Read the function capabilities and extract them into the func_caps structure 3150 * for later use. 3151 */ 3152 static int 3153 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3154 { 3155 u32 cap_count = 0; 3156 void *cbuf; 3157 int status; 3158 3159 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3160 if (!cbuf) 3161 return -ENOMEM; 3162 3163 /* Although the driver doesn't know the number of capabilities the 3164 * device will return, we can simply send a 4KB buffer, the maximum 3165 * possible size that firmware can return. 3166 */ 3167 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3168 3169 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3170 ice_aqc_opc_list_func_caps, NULL); 3171 if (!status) 3172 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3173 kfree(cbuf); 3174 3175 return status; 3176 } 3177 3178 /** 3179 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3180 * @hw: pointer to the hardware structure 3181 */ 3182 void ice_set_safe_mode_caps(struct ice_hw *hw) 3183 { 3184 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3185 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3186 struct ice_hw_common_caps cached_caps; 3187 u32 num_funcs; 3188 3189 /* cache some func_caps values that should be restored after memset */ 3190 cached_caps = func_caps->common_cap; 3191 3192 /* unset func capabilities */ 3193 memset(func_caps, 0, sizeof(*func_caps)); 3194 3195 #define ICE_RESTORE_FUNC_CAP(name) \ 3196 func_caps->common_cap.name = cached_caps.name 3197 3198 /* restore cached values */ 3199 ICE_RESTORE_FUNC_CAP(valid_functions); 3200 ICE_RESTORE_FUNC_CAP(txq_first_id); 3201 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3202 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3203 ICE_RESTORE_FUNC_CAP(max_mtu); 3204 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3205 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3206 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3207 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3208 3209 /* one Tx and one Rx queue in safe mode */ 3210 func_caps->common_cap.num_rxq = 1; 3211 func_caps->common_cap.num_txq = 1; 3212 3213 /* two MSIX vectors, one for traffic and one for misc causes */ 3214 func_caps->common_cap.num_msix_vectors = 2; 3215 func_caps->guar_num_vsi = 1; 3216 3217 /* cache some dev_caps values that should be restored after memset */ 3218 cached_caps = dev_caps->common_cap; 3219 num_funcs = dev_caps->num_funcs; 3220 3221 /* unset dev capabilities */ 3222 memset(dev_caps, 0, sizeof(*dev_caps)); 3223 3224 #define ICE_RESTORE_DEV_CAP(name) \ 3225 dev_caps->common_cap.name = cached_caps.name 3226 3227 /* restore cached values */ 3228 ICE_RESTORE_DEV_CAP(valid_functions); 3229 ICE_RESTORE_DEV_CAP(txq_first_id); 3230 ICE_RESTORE_DEV_CAP(rxq_first_id); 3231 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3232 ICE_RESTORE_DEV_CAP(max_mtu); 3233 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3234 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3235 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3236 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3237 dev_caps->num_funcs = num_funcs; 3238 3239 /* one Tx and one Rx queue per function in safe mode */ 3240 dev_caps->common_cap.num_rxq = num_funcs; 3241 dev_caps->common_cap.num_txq = num_funcs; 3242 3243 /* two MSIX vectors per function */ 3244 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3245 } 3246 3247 /** 3248 * ice_get_caps - get info about the HW 3249 * @hw: pointer to the hardware structure 3250 */ 3251 int ice_get_caps(struct ice_hw *hw) 3252 { 3253 int status; 3254 3255 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3256 if (status) 3257 return status; 3258 3259 return ice_discover_func_caps(hw, &hw->func_caps); 3260 } 3261 3262 /** 3263 * ice_aq_manage_mac_write - manage MAC address write command 3264 * @hw: pointer to the HW struct 3265 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3266 * @flags: flags to control write behavior 3267 * @cd: pointer to command details structure or NULL 3268 * 3269 * This function is used to write MAC address to the NVM (0x0108). 3270 */ 3271 int 3272 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3273 struct ice_sq_cd *cd) 3274 { 3275 struct ice_aqc_manage_mac_write *cmd; 3276 struct libie_aq_desc desc; 3277 3278 cmd = libie_aq_raw(&desc); 3279 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3280 3281 cmd->flags = flags; 3282 ether_addr_copy(cmd->mac_addr, mac_addr); 3283 3284 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3285 } 3286 3287 /** 3288 * ice_aq_clear_pxe_mode 3289 * @hw: pointer to the HW struct 3290 * 3291 * Tell the firmware that the driver is taking over from PXE (0x0110). 3292 */ 3293 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3294 { 3295 struct ice_aqc_clear_pxe *cmd; 3296 struct libie_aq_desc desc; 3297 3298 cmd = libie_aq_raw(&desc); 3299 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3300 cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3301 3302 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3303 } 3304 3305 /** 3306 * ice_clear_pxe_mode - clear pxe operations mode 3307 * @hw: pointer to the HW struct 3308 * 3309 * Make sure all PXE mode settings are cleared, including things 3310 * like descriptor fetch/write-back mode. 3311 */ 3312 void ice_clear_pxe_mode(struct ice_hw *hw) 3313 { 3314 if (ice_check_sq_alive(hw, &hw->adminq)) 3315 ice_aq_clear_pxe_mode(hw); 3316 } 3317 3318 /** 3319 * ice_aq_set_port_params - set physical port parameters. 3320 * @pi: pointer to the port info struct 3321 * @double_vlan: if set double VLAN is enabled 3322 * @cd: pointer to command details structure or NULL 3323 * 3324 * Set Physical port parameters (0x0203) 3325 */ 3326 int 3327 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3328 struct ice_sq_cd *cd) 3329 3330 { 3331 struct ice_aqc_set_port_params *cmd; 3332 struct ice_hw *hw = pi->hw; 3333 struct libie_aq_desc desc; 3334 u16 cmd_flags = 0; 3335 3336 cmd = libie_aq_raw(&desc); 3337 3338 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3339 if (double_vlan) 3340 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3341 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3342 3343 cmd->local_fwd_mode = pi->local_fwd_mode | 3344 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3345 3346 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3347 } 3348 3349 /** 3350 * ice_is_100m_speed_supported 3351 * @hw: pointer to the HW struct 3352 * 3353 * returns true if 100M speeds are supported by the device, 3354 * false otherwise. 3355 */ 3356 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3357 { 3358 switch (hw->device_id) { 3359 case ICE_DEV_ID_E822C_SGMII: 3360 case ICE_DEV_ID_E822L_SGMII: 3361 case ICE_DEV_ID_E823L_1GBE: 3362 case ICE_DEV_ID_E823C_SGMII: 3363 case ICE_DEV_ID_E825C_SGMII: 3364 return true; 3365 default: 3366 return false; 3367 } 3368 } 3369 3370 /** 3371 * ice_get_link_speed_based_on_phy_type - returns link speed 3372 * @phy_type_low: lower part of phy_type 3373 * @phy_type_high: higher part of phy_type 3374 * 3375 * This helper function will convert an entry in PHY type structure 3376 * [phy_type_low, phy_type_high] to its corresponding link speed. 3377 * Note: In the structure of [phy_type_low, phy_type_high], there should 3378 * be one bit set, as this function will convert one PHY type to its 3379 * speed. 3380 * 3381 * Return: 3382 * * PHY speed for recognized PHY type 3383 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3384 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3385 */ 3386 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3387 { 3388 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3389 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3390 3391 switch (phy_type_low) { 3392 case ICE_PHY_TYPE_LOW_100BASE_TX: 3393 case ICE_PHY_TYPE_LOW_100M_SGMII: 3394 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3395 break; 3396 case ICE_PHY_TYPE_LOW_1000BASE_T: 3397 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3398 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3399 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3400 case ICE_PHY_TYPE_LOW_1G_SGMII: 3401 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3402 break; 3403 case ICE_PHY_TYPE_LOW_2500BASE_T: 3404 case ICE_PHY_TYPE_LOW_2500BASE_X: 3405 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3406 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3407 break; 3408 case ICE_PHY_TYPE_LOW_5GBASE_T: 3409 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3410 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3411 break; 3412 case ICE_PHY_TYPE_LOW_10GBASE_T: 3413 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3414 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3415 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3416 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3417 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3418 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3419 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3420 break; 3421 case ICE_PHY_TYPE_LOW_25GBASE_T: 3422 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3423 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3424 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3425 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3426 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3427 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3428 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3429 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3430 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3431 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3432 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3433 break; 3434 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3435 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3436 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3437 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3438 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3439 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3440 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3441 break; 3442 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3443 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3444 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3445 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3446 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3447 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3448 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3449 case ICE_PHY_TYPE_LOW_50G_AUI2: 3450 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3451 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3452 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3453 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3454 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3455 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3456 case ICE_PHY_TYPE_LOW_50G_AUI1: 3457 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3458 break; 3459 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3460 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3461 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3462 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3463 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3464 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3465 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3466 case ICE_PHY_TYPE_LOW_100G_AUI4: 3467 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3468 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3469 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3470 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3471 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3472 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3473 break; 3474 default: 3475 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3476 break; 3477 } 3478 3479 switch (phy_type_high) { 3480 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3481 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3482 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3483 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3484 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3485 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3486 break; 3487 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3488 case ICE_PHY_TYPE_HIGH_200G_SR4: 3489 case ICE_PHY_TYPE_HIGH_200G_FR4: 3490 case ICE_PHY_TYPE_HIGH_200G_LR4: 3491 case ICE_PHY_TYPE_HIGH_200G_DR4: 3492 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3493 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3494 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3495 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3496 break; 3497 default: 3498 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3499 break; 3500 } 3501 3502 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3503 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3504 return ICE_AQ_LINK_SPEED_UNKNOWN; 3505 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3506 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3507 return ICE_AQ_LINK_SPEED_UNKNOWN; 3508 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3509 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3510 return speed_phy_type_low; 3511 else 3512 return speed_phy_type_high; 3513 } 3514 3515 /** 3516 * ice_update_phy_type 3517 * @phy_type_low: pointer to the lower part of phy_type 3518 * @phy_type_high: pointer to the higher part of phy_type 3519 * @link_speeds_bitmap: targeted link speeds bitmap 3520 * 3521 * Note: For the link_speeds_bitmap structure, you can check it at 3522 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3523 * link_speeds_bitmap include multiple speeds. 3524 * 3525 * Each entry in this [phy_type_low, phy_type_high] structure will 3526 * present a certain link speed. This helper function will turn on bits 3527 * in [phy_type_low, phy_type_high] structure based on the value of 3528 * link_speeds_bitmap input parameter. 3529 */ 3530 void 3531 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3532 u16 link_speeds_bitmap) 3533 { 3534 u64 pt_high; 3535 u64 pt_low; 3536 int index; 3537 u16 speed; 3538 3539 /* We first check with low part of phy_type */ 3540 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3541 pt_low = BIT_ULL(index); 3542 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3543 3544 if (link_speeds_bitmap & speed) 3545 *phy_type_low |= BIT_ULL(index); 3546 } 3547 3548 /* We then check with high part of phy_type */ 3549 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3550 pt_high = BIT_ULL(index); 3551 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3552 3553 if (link_speeds_bitmap & speed) 3554 *phy_type_high |= BIT_ULL(index); 3555 } 3556 } 3557 3558 /** 3559 * ice_aq_set_phy_cfg 3560 * @hw: pointer to the HW struct 3561 * @pi: port info structure of the interested logical port 3562 * @cfg: structure with PHY configuration data to be set 3563 * @cd: pointer to command details structure or NULL 3564 * 3565 * Set the various PHY configuration parameters supported on the Port. 3566 * One or more of the Set PHY config parameters may be ignored in an MFP 3567 * mode as the PF may not have the privilege to set some of the PHY Config 3568 * parameters. This status will be indicated by the command response (0x0601). 3569 */ 3570 int 3571 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3572 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3573 { 3574 struct ice_aqc_set_phy_cfg *cmd; 3575 struct libie_aq_desc desc; 3576 int status; 3577 3578 if (!cfg) 3579 return -EINVAL; 3580 3581 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3582 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3583 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3584 cfg->caps); 3585 3586 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3587 } 3588 3589 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3590 cmd = libie_aq_raw(&desc); 3591 cmd->lport_num = pi->lport; 3592 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3593 3594 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3595 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3596 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3597 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3598 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3599 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3600 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3601 cfg->low_power_ctrl_an); 3602 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3603 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3604 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3605 cfg->link_fec_opt); 3606 3607 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3608 if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3609 status = 0; 3610 3611 if (!status) 3612 pi->phy.curr_user_phy_cfg = *cfg; 3613 3614 return status; 3615 } 3616 3617 /** 3618 * ice_update_link_info - update status of the HW network link 3619 * @pi: port info structure of the interested logical port 3620 */ 3621 int ice_update_link_info(struct ice_port_info *pi) 3622 { 3623 struct ice_link_status *li; 3624 int status; 3625 3626 if (!pi) 3627 return -EINVAL; 3628 3629 li = &pi->phy.link_info; 3630 3631 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3632 if (status) 3633 return status; 3634 3635 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3636 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3637 3638 pcaps = kzalloc_obj(*pcaps); 3639 if (!pcaps) 3640 return -ENOMEM; 3641 3642 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3643 pcaps, NULL); 3644 } 3645 3646 return status; 3647 } 3648 3649 /** 3650 * ice_aq_get_phy_equalization - function to read serdes equaliser 3651 * value from firmware using admin queue command. 3652 * @hw: pointer to the HW struct 3653 * @data_in: represents the serdes equalization parameter requested 3654 * @op_code: represents the serdes number and flag to represent tx or rx 3655 * @serdes_num: represents the serdes number 3656 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3657 * 3658 * Return: non-zero status on error and 0 on success. 3659 */ 3660 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3661 u8 serdes_num, int *output) 3662 { 3663 struct ice_aqc_dnl_call_command *cmd; 3664 struct ice_aqc_dnl_call buf = {}; 3665 struct libie_aq_desc desc; 3666 int err; 3667 3668 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3669 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3670 cpu_to_le16(op_code | (serdes_num & 0xF)); 3671 cmd = libie_aq_raw(&desc); 3672 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3673 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3674 LIBIE_AQ_FLAG_RD | 3675 LIBIE_AQ_FLAG_SI); 3676 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3677 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3678 3679 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3680 NULL); 3681 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3682 3683 return err; 3684 } 3685 3686 #define FEC_REG_PORT(port) { \ 3687 FEC_CORR_LOW_REG_PORT##port, \ 3688 FEC_CORR_HIGH_REG_PORT##port, \ 3689 FEC_UNCORR_LOW_REG_PORT##port, \ 3690 FEC_UNCORR_HIGH_REG_PORT##port, \ 3691 } 3692 3693 static const u32 fec_reg[][ICE_FEC_MAX] = { 3694 FEC_REG_PORT(0), 3695 FEC_REG_PORT(1), 3696 FEC_REG_PORT(2), 3697 FEC_REG_PORT(3) 3698 }; 3699 3700 /** 3701 * ice_aq_get_fec_stats - reads fec stats from phy 3702 * @hw: pointer to the HW struct 3703 * @pcs_quad: represents pcsquad of user input serdes 3704 * @pcs_port: represents the pcs port number part of above pcs quad 3705 * @fec_type: represents FEC stats type 3706 * @output: pointer to the caller-supplied buffer to return requested fec stats 3707 * 3708 * Return: non-zero status on error and 0 on success. 3709 */ 3710 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3711 enum ice_fec_stats_types fec_type, u32 *output) 3712 { 3713 u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3714 struct ice_sbq_msg_input msg = {}; 3715 u32 receiver_id, reg_offset; 3716 int err; 3717 3718 if (pcs_port > 3) 3719 return -EINVAL; 3720 3721 reg_offset = fec_reg[pcs_port][fec_type]; 3722 3723 if (pcs_quad == 0) 3724 receiver_id = FEC_RECEIVER_ID_PCS0; 3725 else if (pcs_quad == 1) 3726 receiver_id = FEC_RECEIVER_ID_PCS1; 3727 else 3728 return -EINVAL; 3729 3730 msg.msg_addr_low = lower_16_bits(reg_offset); 3731 msg.msg_addr_high = receiver_id; 3732 msg.opcode = ice_sbq_msg_rd; 3733 msg.dest_dev = ice_sbq_dev_phy_0; 3734 3735 err = ice_sbq_rw_reg(hw, &msg, flag); 3736 if (err) 3737 return err; 3738 3739 *output = msg.data; 3740 return 0; 3741 } 3742 3743 /** 3744 * ice_cache_phy_user_req 3745 * @pi: port information structure 3746 * @cache_data: PHY logging data 3747 * @cache_mode: PHY logging mode 3748 * 3749 * Log the user request on (FC, FEC, SPEED) for later use. 3750 */ 3751 static void 3752 ice_cache_phy_user_req(struct ice_port_info *pi, 3753 struct ice_phy_cache_mode_data cache_data, 3754 enum ice_phy_cache_mode cache_mode) 3755 { 3756 if (!pi) 3757 return; 3758 3759 switch (cache_mode) { 3760 case ICE_FC_MODE: 3761 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3762 break; 3763 case ICE_SPEED_MODE: 3764 pi->phy.curr_user_speed_req = 3765 cache_data.data.curr_user_speed_req; 3766 break; 3767 case ICE_FEC_MODE: 3768 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3769 break; 3770 default: 3771 break; 3772 } 3773 } 3774 3775 /** 3776 * ice_caps_to_fc_mode 3777 * @caps: PHY capabilities 3778 * 3779 * Convert PHY FC capabilities to ice FC mode 3780 */ 3781 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3782 { 3783 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3784 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3785 return ICE_FC_FULL; 3786 3787 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3788 return ICE_FC_TX_PAUSE; 3789 3790 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3791 return ICE_FC_RX_PAUSE; 3792 3793 return ICE_FC_NONE; 3794 } 3795 3796 /** 3797 * ice_caps_to_fec_mode 3798 * @caps: PHY capabilities 3799 * @fec_options: Link FEC options 3800 * 3801 * Convert PHY FEC capabilities to ice FEC mode 3802 */ 3803 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3804 { 3805 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3806 return ICE_FEC_AUTO; 3807 3808 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3809 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3810 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3811 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3812 return ICE_FEC_BASER; 3813 3814 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3815 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3816 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3817 return ICE_FEC_RS; 3818 3819 return ICE_FEC_NONE; 3820 } 3821 3822 /** 3823 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3824 * @pi: port information structure 3825 * @cfg: PHY configuration data to set FC mode 3826 * @req_mode: FC mode to configure 3827 */ 3828 int 3829 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3830 enum ice_fc_mode req_mode) 3831 { 3832 struct ice_phy_cache_mode_data cache_data; 3833 u8 pause_mask = 0x0; 3834 3835 if (!pi || !cfg) 3836 return -EINVAL; 3837 3838 switch (req_mode) { 3839 case ICE_FC_FULL: 3840 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3841 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3842 break; 3843 case ICE_FC_RX_PAUSE: 3844 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3845 break; 3846 case ICE_FC_TX_PAUSE: 3847 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3848 break; 3849 default: 3850 break; 3851 } 3852 3853 /* clear the old pause settings */ 3854 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3855 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3856 3857 /* set the new capabilities */ 3858 cfg->caps |= pause_mask; 3859 3860 /* Cache user FC request */ 3861 cache_data.data.curr_user_fc_req = req_mode; 3862 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3863 3864 return 0; 3865 } 3866 3867 /** 3868 * ice_set_fc 3869 * @pi: port information structure 3870 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3871 * @ena_auto_link_update: enable automatic link update 3872 * 3873 * Set the requested flow control mode. 3874 */ 3875 int 3876 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3877 { 3878 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3879 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3880 struct ice_hw *hw; 3881 int status; 3882 3883 if (!pi || !aq_failures) 3884 return -EINVAL; 3885 3886 hw = pi->hw; 3887 3888 pcaps = kzalloc_obj(*pcaps); 3889 if (!pcaps) 3890 return -ENOMEM; 3891 3892 /* Get the current PHY config */ 3893 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3894 pcaps, NULL); 3895 if (status) { 3896 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3897 goto out; 3898 } 3899 3900 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3901 3902 /* Configure the set PHY data */ 3903 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3904 if (status) 3905 goto out; 3906 3907 /* If the capabilities have changed, then set the new config */ 3908 if (cfg.caps != pcaps->caps) { 3909 int retry_count, retry_max = 10; 3910 3911 /* Auto restart link so settings take effect */ 3912 if (ena_auto_link_update) 3913 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3914 3915 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3916 if (status) { 3917 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3918 goto out; 3919 } 3920 3921 /* Update the link info 3922 * It sometimes takes a really long time for link to 3923 * come back from the atomic reset. Thus, we wait a 3924 * little bit. 3925 */ 3926 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3927 status = ice_update_link_info(pi); 3928 3929 if (!status) 3930 break; 3931 3932 mdelay(100); 3933 } 3934 3935 if (status) 3936 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3937 } 3938 3939 out: 3940 return status; 3941 } 3942 3943 /** 3944 * ice_phy_caps_equals_cfg 3945 * @phy_caps: PHY capabilities 3946 * @phy_cfg: PHY configuration 3947 * 3948 * Helper function to determine if PHY capabilities matches PHY 3949 * configuration 3950 */ 3951 bool 3952 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3953 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3954 { 3955 u8 caps_mask, cfg_mask; 3956 3957 if (!phy_caps || !phy_cfg) 3958 return false; 3959 3960 /* These bits are not common between capabilities and configuration. 3961 * Do not use them to determine equality. 3962 */ 3963 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3964 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3965 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3966 3967 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3968 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3969 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3970 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3971 phy_caps->eee_cap != phy_cfg->eee_cap || 3972 phy_caps->eeer_value != phy_cfg->eeer_value || 3973 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3974 return false; 3975 3976 return true; 3977 } 3978 3979 /** 3980 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3981 * @pi: port information structure 3982 * @caps: PHY ability structure to copy date from 3983 * @cfg: PHY configuration structure to copy data to 3984 * 3985 * Helper function to copy AQC PHY get ability data to PHY set configuration 3986 * data structure 3987 */ 3988 void 3989 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3990 struct ice_aqc_get_phy_caps_data *caps, 3991 struct ice_aqc_set_phy_cfg_data *cfg) 3992 { 3993 if (!pi || !caps || !cfg) 3994 return; 3995 3996 memset(cfg, 0, sizeof(*cfg)); 3997 cfg->phy_type_low = caps->phy_type_low; 3998 cfg->phy_type_high = caps->phy_type_high; 3999 cfg->caps = caps->caps; 4000 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 4001 cfg->eee_cap = caps->eee_cap; 4002 cfg->eeer_value = caps->eeer_value; 4003 cfg->link_fec_opt = caps->link_fec_options; 4004 cfg->module_compliance_enforcement = 4005 caps->module_compliance_enforcement; 4006 } 4007 4008 /** 4009 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 4010 * @pi: port information structure 4011 * @cfg: PHY configuration data to set FEC mode 4012 * @fec: FEC mode to configure 4013 */ 4014 int 4015 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 4016 enum ice_fec_mode fec) 4017 { 4018 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 4019 struct ice_hw *hw; 4020 int status; 4021 4022 if (!pi || !cfg) 4023 return -EINVAL; 4024 4025 hw = pi->hw; 4026 4027 pcaps = kzalloc_obj(*pcaps); 4028 if (!pcaps) 4029 return -ENOMEM; 4030 4031 status = ice_aq_get_phy_caps(pi, false, 4032 (ice_fw_supports_report_dflt_cfg(hw) ? 4033 ICE_AQC_REPORT_DFLT_CFG : 4034 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 4035 if (status) 4036 goto out; 4037 4038 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 4039 cfg->link_fec_opt = pcaps->link_fec_options; 4040 4041 switch (fec) { 4042 case ICE_FEC_BASER: 4043 /* Clear RS bits, and AND BASE-R ability 4044 * bits and OR request bits. 4045 */ 4046 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 4047 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 4048 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 4049 ICE_AQC_PHY_FEC_25G_KR_REQ; 4050 break; 4051 case ICE_FEC_RS: 4052 /* Clear BASE-R bits, and AND RS ability 4053 * bits and OR request bits. 4054 */ 4055 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 4056 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4057 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4058 break; 4059 case ICE_FEC_NONE: 4060 /* Clear all FEC option bits. */ 4061 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4062 break; 4063 case ICE_FEC_AUTO: 4064 /* AND auto FEC bit, and all caps bits. */ 4065 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4066 cfg->link_fec_opt |= pcaps->link_fec_options; 4067 break; 4068 default: 4069 status = -EINVAL; 4070 break; 4071 } 4072 4073 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4074 !ice_fw_supports_report_dflt_cfg(hw)) { 4075 struct ice_link_default_override_tlv tlv = { 0 }; 4076 4077 status = ice_get_link_default_override(&tlv, pi); 4078 if (status) 4079 goto out; 4080 4081 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4082 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4083 cfg->link_fec_opt = tlv.fec_options; 4084 } 4085 4086 out: 4087 return status; 4088 } 4089 4090 /** 4091 * ice_get_link_status - get status of the HW network link 4092 * @pi: port information structure 4093 * @link_up: pointer to bool (true/false = linkup/linkdown) 4094 * 4095 * Variable link_up is true if link is up, false if link is down. 4096 * The variable link_up is invalid if status is non zero. As a 4097 * result of this call, link status reporting becomes enabled 4098 */ 4099 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4100 { 4101 struct ice_phy_info *phy_info; 4102 int status = 0; 4103 4104 if (!pi || !link_up) 4105 return -EINVAL; 4106 4107 phy_info = &pi->phy; 4108 4109 if (phy_info->get_link_info) { 4110 status = ice_update_link_info(pi); 4111 4112 if (status) 4113 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4114 status); 4115 } 4116 4117 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4118 4119 return status; 4120 } 4121 4122 /** 4123 * ice_aq_set_link_restart_an 4124 * @pi: pointer to the port information structure 4125 * @ena_link: if true: enable link, if false: disable link 4126 * @cd: pointer to command details structure or NULL 4127 * @refclk: the new TX reference clock, 0 if no change 4128 * 4129 * Sets up the link and restarts the Auto-Negotiation over the link. 4130 */ 4131 int 4132 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4133 struct ice_sq_cd *cd, u8 refclk) 4134 { 4135 struct ice_aqc_restart_an *cmd; 4136 struct libie_aq_desc desc; 4137 4138 cmd = libie_aq_raw(&desc); 4139 4140 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4141 4142 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4143 cmd->lport_num = pi->lport; 4144 if (ena_link) 4145 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4146 else 4147 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4148 4149 cmd->cmd_flags |= FIELD_PREP(ICE_AQC_RESTART_AN_REFCLK_M, refclk); 4150 4151 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4152 } 4153 4154 /** 4155 * ice_aq_set_event_mask 4156 * @hw: pointer to the HW struct 4157 * @port_num: port number of the physical function 4158 * @mask: event mask to be set 4159 * @cd: pointer to command details structure or NULL 4160 * 4161 * Set event mask (0x0613) 4162 */ 4163 int 4164 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4165 struct ice_sq_cd *cd) 4166 { 4167 struct ice_aqc_set_event_mask *cmd; 4168 struct libie_aq_desc desc; 4169 4170 cmd = libie_aq_raw(&desc); 4171 4172 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4173 4174 cmd->lport_num = port_num; 4175 4176 cmd->event_mask = cpu_to_le16(mask); 4177 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4178 } 4179 4180 /** 4181 * ice_aq_set_mac_loopback 4182 * @hw: pointer to the HW struct 4183 * @ena_lpbk: Enable or Disable loopback 4184 * @cd: pointer to command details structure or NULL 4185 * 4186 * Enable/disable loopback on a given port 4187 */ 4188 int 4189 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4190 { 4191 struct ice_aqc_set_mac_lb *cmd; 4192 struct libie_aq_desc desc; 4193 4194 cmd = libie_aq_raw(&desc); 4195 4196 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4197 if (ena_lpbk) 4198 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4199 4200 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4201 } 4202 4203 /** 4204 * ice_aq_set_port_id_led 4205 * @pi: pointer to the port information 4206 * @is_orig_mode: is this LED set to original mode (by the net-list) 4207 * @cd: pointer to command details structure or NULL 4208 * 4209 * Set LED value for the given port (0x06e9) 4210 */ 4211 int 4212 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4213 struct ice_sq_cd *cd) 4214 { 4215 struct ice_aqc_set_port_id_led *cmd; 4216 struct ice_hw *hw = pi->hw; 4217 struct libie_aq_desc desc; 4218 4219 cmd = libie_aq_raw(&desc); 4220 4221 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4222 4223 if (is_orig_mode) 4224 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4225 else 4226 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4227 4228 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4229 } 4230 4231 /** 4232 * ice_aq_get_port_options 4233 * @hw: pointer to the HW struct 4234 * @options: buffer for the resultant port options 4235 * @option_count: input - size of the buffer in port options structures, 4236 * output - number of returned port options 4237 * @lport: logical port to call the command with (optional) 4238 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4239 * when PF owns more than 1 port it must be true 4240 * @active_option_idx: index of active port option in returned buffer 4241 * @active_option_valid: active option in returned buffer is valid 4242 * @pending_option_idx: index of pending port option in returned buffer 4243 * @pending_option_valid: pending option in returned buffer is valid 4244 * 4245 * Calls Get Port Options AQC (0x06ea) and verifies result. 4246 */ 4247 int 4248 ice_aq_get_port_options(struct ice_hw *hw, 4249 struct ice_aqc_get_port_options_elem *options, 4250 u8 *option_count, u8 lport, bool lport_valid, 4251 u8 *active_option_idx, bool *active_option_valid, 4252 u8 *pending_option_idx, bool *pending_option_valid) 4253 { 4254 struct ice_aqc_get_port_options *cmd; 4255 struct libie_aq_desc desc; 4256 int status; 4257 u8 i; 4258 4259 /* options buffer shall be able to hold max returned options */ 4260 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4261 return -EINVAL; 4262 4263 cmd = libie_aq_raw(&desc); 4264 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4265 4266 if (lport_valid) 4267 cmd->lport_num = lport; 4268 cmd->lport_num_valid = lport_valid; 4269 4270 status = ice_aq_send_cmd(hw, &desc, options, 4271 *option_count * sizeof(*options), NULL); 4272 if (status) 4273 return status; 4274 4275 /* verify direct FW response & set output parameters */ 4276 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4277 cmd->port_options_count); 4278 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4279 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4280 cmd->port_options); 4281 if (*active_option_valid) { 4282 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4283 cmd->port_options); 4284 if (*active_option_idx > (*option_count - 1)) 4285 return -EIO; 4286 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4287 *active_option_idx); 4288 } 4289 4290 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4291 cmd->pending_port_option_status); 4292 if (*pending_option_valid) { 4293 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4294 cmd->pending_port_option_status); 4295 if (*pending_option_idx > (*option_count - 1)) 4296 return -EIO; 4297 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4298 *pending_option_idx); 4299 } 4300 4301 /* mask output options fields */ 4302 for (i = 0; i < *option_count; i++) { 4303 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4304 options[i].pmd); 4305 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4306 options[i].max_lane_speed); 4307 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4308 options[i].pmd, options[i].max_lane_speed); 4309 } 4310 4311 return 0; 4312 } 4313 4314 /** 4315 * ice_aq_set_port_option 4316 * @hw: pointer to the HW struct 4317 * @lport: logical port to call the command with 4318 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4319 * when PF owns more than 1 port it must be true 4320 * @new_option: new port option to be written 4321 * 4322 * Calls Set Port Options AQC (0x06eb). 4323 */ 4324 int 4325 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4326 u8 new_option) 4327 { 4328 struct ice_aqc_set_port_option *cmd; 4329 struct libie_aq_desc desc; 4330 4331 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4332 return -EINVAL; 4333 4334 cmd = libie_aq_raw(&desc); 4335 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4336 4337 if (lport_valid) 4338 cmd->lport_num = lport; 4339 4340 cmd->lport_num_valid = lport_valid; 4341 cmd->selected_port_option = new_option; 4342 4343 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4344 } 4345 4346 /** 4347 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4348 * @hw: pointer to the hw struct 4349 * 4350 * Return: PHY lane number on success, negative error code otherwise. 4351 */ 4352 int ice_get_phy_lane_number(struct ice_hw *hw) 4353 { 4354 struct ice_aqc_get_port_options_elem *options; 4355 unsigned int lport = 0; 4356 unsigned int lane; 4357 int err; 4358 4359 /* E82X does not have sequential IDs, lane number is PF ID. 4360 * For E825 device, the exception is the variant with external 4361 * PHY (0x579F), in which there is also 1:1 pf_id -> lane_number 4362 * mapping. 4363 */ 4364 if (hw->mac_type == ICE_MAC_GENERIC || 4365 hw->device_id == ICE_DEV_ID_E825C_SGMII) 4366 return hw->pf_id; 4367 4368 options = kzalloc_objs(*options, ICE_AQC_PORT_OPT_MAX); 4369 if (!options) 4370 return -ENOMEM; 4371 4372 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4373 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4374 u8 speed, active_idx, pending_idx; 4375 bool active_valid, pending_valid; 4376 4377 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4378 true, &active_idx, &active_valid, 4379 &pending_idx, &pending_valid); 4380 if (err) 4381 goto err; 4382 4383 if (!active_valid) 4384 continue; 4385 4386 speed = options[active_idx].max_lane_speed; 4387 /* If we don't get speed for this lane, it's unoccupied */ 4388 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4389 continue; 4390 4391 if (hw->pf_id == lport) { 4392 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4393 ice_is_dual(hw) && !ice_is_primary(hw)) 4394 lane += ICE_PORTS_PER_QUAD; 4395 kfree(options); 4396 return lane; 4397 } 4398 lport++; 4399 } 4400 4401 /* PHY lane not found */ 4402 err = -ENXIO; 4403 err: 4404 kfree(options); 4405 return err; 4406 } 4407 4408 /** 4409 * ice_aq_sff_eeprom 4410 * @hw: pointer to the HW struct 4411 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4412 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4413 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4414 * @page: QSFP page 4415 * @set_page: set or ignore the page 4416 * @data: pointer to data buffer to be read/written to the I2C device. 4417 * @length: 1-16 for read, 1 for write. 4418 * @write: 0 read, 1 for write. 4419 * @cd: pointer to command details structure or NULL 4420 * 4421 * Read/Write SFF EEPROM (0x06EE) 4422 */ 4423 int 4424 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4425 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4426 bool write, struct ice_sq_cd *cd) 4427 { 4428 struct ice_aqc_sff_eeprom *cmd; 4429 struct libie_aq_desc desc; 4430 u16 i2c_bus_addr; 4431 int status; 4432 4433 if (!data || (mem_addr & 0xff00)) 4434 return -EINVAL; 4435 4436 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4437 cmd = libie_aq_raw(&desc); 4438 desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4439 cmd->lport_num = (u8)(lport & 0xff); 4440 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4441 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4442 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4443 if (write) 4444 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4445 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4446 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4447 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4448 4449 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4450 return status; 4451 } 4452 4453 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4454 { 4455 switch (type) { 4456 case ICE_LUT_VSI: 4457 return ICE_LUT_VSI_SIZE; 4458 case ICE_LUT_GLOBAL: 4459 return ICE_LUT_GLOBAL_SIZE; 4460 case ICE_LUT_PF: 4461 return ICE_LUT_PF_SIZE; 4462 } 4463 WARN_ONCE(1, "incorrect type passed"); 4464 return ICE_LUT_VSI_SIZE; 4465 } 4466 4467 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4468 { 4469 switch (size) { 4470 case ICE_LUT_VSI_SIZE: 4471 return ICE_AQC_LUT_SIZE_SMALL; 4472 case ICE_LUT_GLOBAL_SIZE: 4473 return ICE_AQC_LUT_SIZE_512; 4474 case ICE_LUT_PF_SIZE: 4475 return ICE_AQC_LUT_SIZE_2K; 4476 } 4477 WARN_ONCE(1, "incorrect size passed"); 4478 return 0; 4479 } 4480 4481 /** 4482 * __ice_aq_get_set_rss_lut 4483 * @hw: pointer to the hardware structure 4484 * @params: RSS LUT parameters 4485 * @set: set true to set the table, false to get the table 4486 * 4487 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4488 */ 4489 static int 4490 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4491 struct ice_aq_get_set_rss_lut_params *params, bool set) 4492 { 4493 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4494 enum ice_lut_type lut_type = params->lut_type; 4495 struct ice_aqc_get_set_rss_lut *desc_params; 4496 enum ice_aqc_lut_flags flags; 4497 enum ice_lut_size lut_size; 4498 struct libie_aq_desc desc; 4499 u8 *lut = params->lut; 4500 4501 4502 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4503 return -EINVAL; 4504 4505 lut_size = ice_lut_type_to_size(lut_type); 4506 if (lut_size > params->lut_size) 4507 return -EINVAL; 4508 else if (set && lut_size != params->lut_size) 4509 return -EINVAL; 4510 4511 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4512 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4513 if (set) 4514 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4515 4516 desc_params = libie_aq_raw(&desc); 4517 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4518 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4519 4520 if (lut_type == ICE_LUT_GLOBAL) 4521 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4522 params->global_lut_id); 4523 4524 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4525 desc_params->flags = cpu_to_le16(flags); 4526 4527 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4528 } 4529 4530 /** 4531 * ice_aq_get_rss_lut 4532 * @hw: pointer to the hardware structure 4533 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4534 * 4535 * get the RSS lookup table, PF or VSI type 4536 */ 4537 int 4538 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4539 { 4540 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4541 } 4542 4543 /** 4544 * ice_aq_set_rss_lut 4545 * @hw: pointer to the hardware structure 4546 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4547 * 4548 * set the RSS lookup table, PF or VSI type 4549 */ 4550 int 4551 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4552 { 4553 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4554 } 4555 4556 /** 4557 * __ice_aq_get_set_rss_key 4558 * @hw: pointer to the HW struct 4559 * @vsi_id: VSI FW index 4560 * @key: pointer to key info struct 4561 * @set: set true to set the key, false to get the key 4562 * 4563 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4564 */ 4565 static int 4566 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4567 struct ice_aqc_get_set_rss_keys *key, bool set) 4568 { 4569 struct ice_aqc_get_set_rss_key *desc_params; 4570 u16 key_size = sizeof(*key); 4571 struct libie_aq_desc desc; 4572 4573 if (set) { 4574 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4575 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4576 } else { 4577 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4578 } 4579 4580 desc_params = libie_aq_raw(&desc); 4581 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4582 4583 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4584 } 4585 4586 /** 4587 * ice_aq_get_rss_key 4588 * @hw: pointer to the HW struct 4589 * @vsi_handle: software VSI handle 4590 * @key: pointer to key info struct 4591 * 4592 * get the RSS key per VSI 4593 */ 4594 int 4595 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4596 struct ice_aqc_get_set_rss_keys *key) 4597 { 4598 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4599 return -EINVAL; 4600 4601 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4602 key, false); 4603 } 4604 4605 /** 4606 * ice_aq_set_rss_key 4607 * @hw: pointer to the HW struct 4608 * @vsi_handle: software VSI handle 4609 * @keys: pointer to key info struct 4610 * 4611 * set the RSS key per VSI 4612 */ 4613 int 4614 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4615 struct ice_aqc_get_set_rss_keys *keys) 4616 { 4617 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4618 return -EINVAL; 4619 4620 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4621 keys, true); 4622 } 4623 4624 /** 4625 * ice_aq_add_lan_txq 4626 * @hw: pointer to the hardware structure 4627 * @num_qgrps: Number of added queue groups 4628 * @qg_list: list of queue groups to be added 4629 * @buf_size: size of buffer for indirect command 4630 * @cd: pointer to command details structure or NULL 4631 * 4632 * Add Tx LAN queue (0x0C30) 4633 * 4634 * NOTE: 4635 * Prior to calling add Tx LAN queue: 4636 * Initialize the following as part of the Tx queue context: 4637 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4638 * Cache profile and Packet shaper profile. 4639 * 4640 * After add Tx LAN queue AQ command is completed: 4641 * Interrupts should be associated with specific queues, 4642 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4643 * flow. 4644 */ 4645 static int 4646 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4647 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4648 struct ice_sq_cd *cd) 4649 { 4650 struct ice_aqc_add_tx_qgrp *list; 4651 struct ice_aqc_add_txqs *cmd; 4652 struct libie_aq_desc desc; 4653 u16 i, sum_size = 0; 4654 4655 cmd = libie_aq_raw(&desc); 4656 4657 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4658 4659 if (!qg_list) 4660 return -EINVAL; 4661 4662 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4663 return -EINVAL; 4664 4665 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4666 sum_size += struct_size(list, txqs, list->num_txqs); 4667 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4668 list->num_txqs); 4669 } 4670 4671 if (buf_size != sum_size) 4672 return -EINVAL; 4673 4674 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4675 4676 cmd->num_qgrps = num_qgrps; 4677 4678 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4679 } 4680 4681 /** 4682 * ice_aq_dis_lan_txq 4683 * @hw: pointer to the hardware structure 4684 * @num_qgrps: number of groups in the list 4685 * @qg_list: the list of groups to disable 4686 * @buf_size: the total size of the qg_list buffer in bytes 4687 * @rst_src: if called due to reset, specifies the reset source 4688 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4689 * @cd: pointer to command details structure or NULL 4690 * 4691 * Disable LAN Tx queue (0x0C31) 4692 */ 4693 static int 4694 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4695 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4696 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4697 struct ice_sq_cd *cd) 4698 { 4699 struct ice_aqc_dis_txq_item *item; 4700 struct ice_aqc_dis_txqs *cmd; 4701 struct libie_aq_desc desc; 4702 u16 vmvf_and_timeout; 4703 u16 i, sz = 0; 4704 int status; 4705 4706 cmd = libie_aq_raw(&desc); 4707 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4708 4709 /* qg_list can be NULL only in VM/VF reset flow */ 4710 if (!qg_list && !rst_src) 4711 return -EINVAL; 4712 4713 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4714 return -EINVAL; 4715 4716 cmd->num_entries = num_qgrps; 4717 4718 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4719 4720 switch (rst_src) { 4721 case ICE_VM_RESET: 4722 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4723 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4724 break; 4725 case ICE_VF_RESET: 4726 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4727 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4728 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4729 ICE_AQC_Q_DIS_VMVF_NUM_M; 4730 break; 4731 case ICE_NO_RESET: 4732 default: 4733 break; 4734 } 4735 4736 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4737 4738 /* flush pipe on time out */ 4739 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4740 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4741 if (!qg_list) 4742 goto do_aq; 4743 4744 /* set RD bit to indicate that command buffer is provided by the driver 4745 * and it needs to be read by the firmware 4746 */ 4747 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4748 4749 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4750 u16 item_size = struct_size(item, q_id, item->num_qs); 4751 4752 /* If the num of queues is even, add 2 bytes of padding */ 4753 if ((item->num_qs % 2) == 0) 4754 item_size += 2; 4755 4756 sz += item_size; 4757 4758 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4759 } 4760 4761 if (buf_size != sz) 4762 return -EINVAL; 4763 4764 do_aq: 4765 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4766 if (status) { 4767 if (!qg_list) 4768 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4769 vmvf_num, hw->adminq.sq_last_status); 4770 else 4771 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4772 le16_to_cpu(qg_list[0].q_id[0]), 4773 hw->adminq.sq_last_status); 4774 } 4775 return status; 4776 } 4777 4778 /** 4779 * ice_aq_cfg_lan_txq - send AQ command 0x0C32 to FW 4780 * @hw: pointer to the hardware structure 4781 * @buf: buffer for command 4782 * @buf_size: size of buffer in bytes 4783 * @num_qs: number of queues being configured 4784 * @oldport: origination lport 4785 * @newport: destination lport 4786 * @mode: cmd_type for move to use 4787 * @cd: pointer to command details structure or NULL 4788 * 4789 * Move/Configure LAN Tx queue (0x0C32) 4790 * 4791 * Return: Zero on success, associated error code on failure. 4792 */ 4793 int 4794 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4795 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4796 u8 mode, struct ice_sq_cd *cd) 4797 { 4798 struct ice_aqc_cfg_txqs *cmd; 4799 struct libie_aq_desc desc; 4800 int status; 4801 4802 cmd = libie_aq_raw(&desc); 4803 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4804 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4805 4806 if (!buf) 4807 return -EINVAL; 4808 4809 cmd->cmd_type = mode; 4810 cmd->num_qs = num_qs; 4811 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4812 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4813 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_MODE_M, 4814 ICE_AQC_Q_CFG_MODE_KEEP_OWN); 4815 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4816 cmd->blocked_cgds = 0; 4817 4818 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4819 if (status) 4820 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4821 hw->adminq.sq_last_status); 4822 return status; 4823 } 4824 4825 /** 4826 * ice_aq_add_rdma_qsets 4827 * @hw: pointer to the hardware structure 4828 * @num_qset_grps: Number of RDMA Qset groups 4829 * @qset_list: list of Qset groups to be added 4830 * @buf_size: size of buffer for indirect command 4831 * @cd: pointer to command details structure or NULL 4832 * 4833 * Add Tx RDMA Qsets (0x0C33) 4834 */ 4835 static int 4836 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4837 struct ice_aqc_add_rdma_qset_data *qset_list, 4838 u16 buf_size, struct ice_sq_cd *cd) 4839 { 4840 struct ice_aqc_add_rdma_qset_data *list; 4841 struct ice_aqc_add_rdma_qset *cmd; 4842 struct libie_aq_desc desc; 4843 u16 i, sum_size = 0; 4844 4845 cmd = libie_aq_raw(&desc); 4846 4847 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4848 4849 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4850 return -EINVAL; 4851 4852 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4853 u16 num_qsets = le16_to_cpu(list->num_qsets); 4854 4855 sum_size += struct_size(list, rdma_qsets, num_qsets); 4856 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4857 num_qsets); 4858 } 4859 4860 if (buf_size != sum_size) 4861 return -EINVAL; 4862 4863 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4864 4865 cmd->num_qset_grps = num_qset_grps; 4866 4867 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4868 } 4869 4870 /** 4871 * ice_aq_set_txtimeq - set Tx time queues 4872 * @hw: pointer to the hardware structure 4873 * @txtimeq: first Tx time queue id to configure 4874 * @q_count: number of queues to configure 4875 * @txtime_qg: queue group to be set 4876 * @buf_size: size of buffer for indirect command 4877 * @cd: pointer to command details structure or NULL 4878 * 4879 * Set Tx Time queue (0x0C35) 4880 * Return: 0 on success or negative value on failure. 4881 */ 4882 int 4883 ice_aq_set_txtimeq(struct ice_hw *hw, u16 txtimeq, u8 q_count, 4884 struct ice_aqc_set_txtime_qgrp *txtime_qg, u16 buf_size, 4885 struct ice_sq_cd *cd) 4886 { 4887 struct ice_aqc_set_txtimeqs *cmd; 4888 struct libie_aq_desc desc; 4889 u16 size; 4890 4891 if (!txtime_qg || txtimeq > ICE_TXTIME_MAX_QUEUE || 4892 q_count < 1 || q_count > ICE_SET_TXTIME_MAX_Q_AMOUNT) 4893 return -EINVAL; 4894 4895 size = struct_size(txtime_qg, txtimeqs, q_count); 4896 if (buf_size != size) 4897 return -EINVAL; 4898 4899 cmd = libie_aq_raw(&desc); 4900 4901 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_txtimeqs); 4902 4903 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4904 4905 cmd->q_id = cpu_to_le16(txtimeq); 4906 cmd->q_amount = cpu_to_le16(q_count); 4907 return ice_aq_send_cmd(hw, &desc, txtime_qg, buf_size, cd); 4908 } 4909 4910 /* End of FW Admin Queue command wrappers */ 4911 4912 /** 4913 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4914 * @hw: pointer to the HW struct 4915 * @vsi_handle: software VSI handle 4916 * @tc: TC number 4917 * @q_handle: software queue handle 4918 */ 4919 struct ice_q_ctx * 4920 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4921 { 4922 struct ice_vsi_ctx *vsi; 4923 struct ice_q_ctx *q_ctx; 4924 4925 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4926 if (!vsi) 4927 return NULL; 4928 if (q_handle >= vsi->num_lan_q_entries[tc]) 4929 return NULL; 4930 if (!vsi->lan_q_ctx[tc]) 4931 return NULL; 4932 q_ctx = vsi->lan_q_ctx[tc]; 4933 return &q_ctx[q_handle]; 4934 } 4935 4936 /** 4937 * ice_ena_vsi_txq 4938 * @pi: port information structure 4939 * @vsi_handle: software VSI handle 4940 * @tc: TC number 4941 * @q_handle: software queue handle 4942 * @num_qgrps: Number of added queue groups 4943 * @buf: list of queue groups to be added 4944 * @buf_size: size of buffer for indirect command 4945 * @cd: pointer to command details structure or NULL 4946 * 4947 * This function adds one LAN queue 4948 */ 4949 int 4950 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4951 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4952 struct ice_sq_cd *cd) 4953 { 4954 struct ice_aqc_txsched_elem_data node = { 0 }; 4955 struct ice_sched_node *parent; 4956 struct ice_q_ctx *q_ctx; 4957 struct ice_hw *hw; 4958 int status; 4959 4960 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4961 return -EIO; 4962 4963 if (num_qgrps > 1 || buf->num_txqs > 1) 4964 return -ENOSPC; 4965 4966 hw = pi->hw; 4967 4968 if (!ice_is_vsi_valid(hw, vsi_handle)) 4969 return -EINVAL; 4970 4971 mutex_lock(&pi->sched_lock); 4972 4973 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4974 if (!q_ctx) { 4975 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4976 q_handle); 4977 status = -EINVAL; 4978 goto ena_txq_exit; 4979 } 4980 4981 /* find a parent node */ 4982 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4983 ICE_SCHED_NODE_OWNER_LAN); 4984 if (!parent) { 4985 status = -EINVAL; 4986 goto ena_txq_exit; 4987 } 4988 4989 buf->parent_teid = parent->info.node_teid; 4990 node.parent_teid = parent->info.node_teid; 4991 /* Mark that the values in the "generic" section as valid. The default 4992 * value in the "generic" section is zero. This means that : 4993 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4994 * - 0 priority among siblings, indicated by Bit 1-3. 4995 * - WFQ, indicated by Bit 4. 4996 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4997 * Bit 5-6. 4998 * - Bit 7 is reserved. 4999 * Without setting the generic section as valid in valid_sections, the 5000 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 5001 */ 5002 buf->txqs[0].info.valid_sections = 5003 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5004 ICE_AQC_ELEM_VALID_EIR; 5005 buf->txqs[0].info.generic = 0; 5006 buf->txqs[0].info.cir_bw.bw_profile_idx = 5007 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5008 buf->txqs[0].info.cir_bw.bw_alloc = 5009 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5010 buf->txqs[0].info.eir_bw.bw_profile_idx = 5011 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5012 buf->txqs[0].info.eir_bw.bw_alloc = 5013 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5014 5015 /* add the LAN queue */ 5016 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 5017 if (status) { 5018 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 5019 le16_to_cpu(buf->txqs[0].txq_id), 5020 hw->adminq.sq_last_status); 5021 goto ena_txq_exit; 5022 } 5023 5024 node.node_teid = buf->txqs[0].q_teid; 5025 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5026 q_ctx->q_handle = q_handle; 5027 q_ctx->q_teid = le32_to_cpu(node.node_teid); 5028 5029 /* add a leaf node into scheduler tree queue layer */ 5030 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 5031 if (!status) 5032 status = ice_sched_replay_q_bw(pi, q_ctx); 5033 5034 ena_txq_exit: 5035 mutex_unlock(&pi->sched_lock); 5036 return status; 5037 } 5038 5039 /** 5040 * ice_dis_vsi_txq 5041 * @pi: port information structure 5042 * @vsi_handle: software VSI handle 5043 * @tc: TC number 5044 * @num_queues: number of queues 5045 * @q_handles: pointer to software queue handle array 5046 * @q_ids: pointer to the q_id array 5047 * @q_teids: pointer to queue node teids 5048 * @rst_src: if called due to reset, specifies the reset source 5049 * @vmvf_num: the relative VM or VF number that is undergoing the reset 5050 * @cd: pointer to command details structure or NULL 5051 * 5052 * This function removes queues and their corresponding nodes in SW DB 5053 */ 5054 int 5055 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 5056 u16 *q_handles, u16 *q_ids, u32 *q_teids, 5057 enum ice_disq_rst_src rst_src, u16 vmvf_num, 5058 struct ice_sq_cd *cd) 5059 { 5060 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5061 u16 i, buf_size = __struct_size(qg_list); 5062 struct ice_q_ctx *q_ctx; 5063 int status = -ENOENT; 5064 struct ice_hw *hw; 5065 5066 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5067 return -EIO; 5068 5069 hw = pi->hw; 5070 5071 if (!num_queues) { 5072 /* if queue is disabled already yet the disable queue command 5073 * has to be sent to complete the VF reset, then call 5074 * ice_aq_dis_lan_txq without any queue information 5075 */ 5076 if (rst_src) 5077 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 5078 vmvf_num, NULL); 5079 return -EIO; 5080 } 5081 5082 mutex_lock(&pi->sched_lock); 5083 5084 for (i = 0; i < num_queues; i++) { 5085 struct ice_sched_node *node; 5086 5087 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 5088 if (!node) 5089 continue; 5090 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 5091 if (!q_ctx) { 5092 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 5093 q_handles[i]); 5094 continue; 5095 } 5096 if (q_ctx->q_handle != q_handles[i]) { 5097 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 5098 q_ctx->q_handle, q_handles[i]); 5099 continue; 5100 } 5101 qg_list->parent_teid = node->info.parent_teid; 5102 qg_list->num_qs = 1; 5103 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 5104 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5105 vmvf_num, cd); 5106 5107 if (status) 5108 break; 5109 ice_free_sched_node(pi, node); 5110 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5111 q_ctx->q_teid = ICE_INVAL_TEID; 5112 } 5113 mutex_unlock(&pi->sched_lock); 5114 return status; 5115 } 5116 5117 /** 5118 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5119 * @pi: port information structure 5120 * @vsi_handle: software VSI handle 5121 * @tc_bitmap: TC bitmap 5122 * @maxqs: max queues array per TC 5123 * @owner: LAN or RDMA 5124 * 5125 * This function adds/updates the VSI queues per TC. 5126 */ 5127 static int 5128 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5129 u16 *maxqs, u8 owner) 5130 { 5131 int status = 0; 5132 u8 i; 5133 5134 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5135 return -EIO; 5136 5137 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5138 return -EINVAL; 5139 5140 mutex_lock(&pi->sched_lock); 5141 5142 ice_for_each_traffic_class(i) { 5143 /* configuration is possible only if TC node is present */ 5144 if (!ice_sched_get_tc_node(pi, i)) 5145 continue; 5146 5147 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5148 ice_is_tc_ena(tc_bitmap, i)); 5149 if (status) 5150 break; 5151 } 5152 5153 mutex_unlock(&pi->sched_lock); 5154 return status; 5155 } 5156 5157 /** 5158 * ice_cfg_vsi_lan - configure VSI LAN queues 5159 * @pi: port information structure 5160 * @vsi_handle: software VSI handle 5161 * @tc_bitmap: TC bitmap 5162 * @max_lanqs: max LAN queues array per TC 5163 * 5164 * This function adds/updates the VSI LAN queues per TC. 5165 */ 5166 int 5167 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5168 u16 *max_lanqs) 5169 { 5170 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5171 ICE_SCHED_NODE_OWNER_LAN); 5172 } 5173 5174 /** 5175 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5176 * @pi: port information structure 5177 * @vsi_handle: software VSI handle 5178 * @tc_bitmap: TC bitmap 5179 * @max_rdmaqs: max RDMA queues array per TC 5180 * 5181 * This function adds/updates the VSI RDMA queues per TC. 5182 */ 5183 int 5184 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5185 u16 *max_rdmaqs) 5186 { 5187 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5188 ICE_SCHED_NODE_OWNER_RDMA); 5189 } 5190 5191 /** 5192 * ice_ena_vsi_rdma_qset 5193 * @pi: port information structure 5194 * @vsi_handle: software VSI handle 5195 * @tc: TC number 5196 * @rdma_qset: pointer to RDMA Qset 5197 * @num_qsets: number of RDMA Qsets 5198 * @qset_teid: pointer to Qset node TEIDs 5199 * 5200 * This function adds RDMA Qset 5201 */ 5202 int 5203 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5204 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5205 { 5206 struct ice_aqc_txsched_elem_data node = { 0 }; 5207 struct ice_aqc_add_rdma_qset_data *buf; 5208 struct ice_sched_node *parent; 5209 struct ice_hw *hw; 5210 u16 i, buf_size; 5211 int ret; 5212 5213 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5214 return -EIO; 5215 hw = pi->hw; 5216 5217 if (!ice_is_vsi_valid(hw, vsi_handle)) 5218 return -EINVAL; 5219 5220 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5221 buf = kzalloc(buf_size, GFP_KERNEL); 5222 if (!buf) 5223 return -ENOMEM; 5224 mutex_lock(&pi->sched_lock); 5225 5226 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5227 ICE_SCHED_NODE_OWNER_RDMA); 5228 if (!parent) { 5229 ret = -EINVAL; 5230 goto rdma_error_exit; 5231 } 5232 buf->parent_teid = parent->info.node_teid; 5233 node.parent_teid = parent->info.node_teid; 5234 5235 buf->num_qsets = cpu_to_le16(num_qsets); 5236 for (i = 0; i < num_qsets; i++) { 5237 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5238 buf->rdma_qsets[i].info.valid_sections = 5239 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5240 ICE_AQC_ELEM_VALID_EIR; 5241 buf->rdma_qsets[i].info.generic = 0; 5242 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5243 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5244 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5245 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5246 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5247 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5248 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5249 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5250 } 5251 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5252 if (ret) { 5253 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5254 goto rdma_error_exit; 5255 } 5256 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5257 for (i = 0; i < num_qsets; i++) { 5258 node.node_teid = buf->rdma_qsets[i].qset_teid; 5259 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5260 &node, NULL); 5261 if (ret) 5262 break; 5263 qset_teid[i] = le32_to_cpu(node.node_teid); 5264 } 5265 rdma_error_exit: 5266 mutex_unlock(&pi->sched_lock); 5267 kfree(buf); 5268 return ret; 5269 } 5270 5271 /** 5272 * ice_dis_vsi_rdma_qset - free RDMA resources 5273 * @pi: port_info struct 5274 * @count: number of RDMA Qsets to free 5275 * @qset_teid: TEID of Qset node 5276 * @q_id: list of queue IDs being disabled 5277 */ 5278 int 5279 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5280 u16 *q_id) 5281 { 5282 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5283 u16 qg_size = __struct_size(qg_list); 5284 struct ice_hw *hw; 5285 int status = 0; 5286 int i; 5287 5288 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5289 return -EIO; 5290 5291 hw = pi->hw; 5292 5293 mutex_lock(&pi->sched_lock); 5294 5295 for (i = 0; i < count; i++) { 5296 struct ice_sched_node *node; 5297 5298 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5299 if (!node) 5300 continue; 5301 5302 qg_list->parent_teid = node->info.parent_teid; 5303 qg_list->num_qs = 1; 5304 qg_list->q_id[0] = 5305 cpu_to_le16(q_id[i] | 5306 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5307 5308 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5309 ICE_NO_RESET, 0, NULL); 5310 if (status) 5311 break; 5312 5313 ice_free_sched_node(pi, node); 5314 } 5315 5316 mutex_unlock(&pi->sched_lock); 5317 return status; 5318 } 5319 5320 /** 5321 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5322 * @hw: pointer to the HW struct 5323 * @dpll_idx: index of dpll to be measured 5324 * @meas: array to be filled with results 5325 * @meas_num: max number of results array can hold 5326 * 5327 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5328 * pins on given dpll. 5329 * 5330 * Return: 0 on success or negative value on failure. 5331 */ 5332 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5333 struct ice_cgu_input_measure *meas, 5334 u16 meas_num) 5335 { 5336 struct ice_aqc_get_cgu_input_measure *cmd; 5337 struct libie_aq_desc desc; 5338 5339 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5340 cmd = libie_aq_raw(&desc); 5341 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5342 5343 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5344 } 5345 5346 /** 5347 * ice_aq_get_cgu_abilities - get cgu abilities 5348 * @hw: pointer to the HW struct 5349 * @abilities: CGU abilities 5350 * 5351 * Get CGU abilities (0x0C61) 5352 * Return: 0 on success or negative value on failure. 5353 */ 5354 int 5355 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5356 struct ice_aqc_get_cgu_abilities *abilities) 5357 { 5358 struct libie_aq_desc desc; 5359 5360 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5361 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5362 } 5363 5364 /** 5365 * ice_aq_set_input_pin_cfg - set input pin config 5366 * @hw: pointer to the HW struct 5367 * @input_idx: Input index 5368 * @flags1: Input flags 5369 * @flags2: Input flags 5370 * @freq: Frequency in Hz 5371 * @phase_delay: Delay in ps 5372 * 5373 * Set CGU input config (0x0C62) 5374 * Return: 0 on success or negative value on failure. 5375 */ 5376 int 5377 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5378 u32 freq, s32 phase_delay) 5379 { 5380 struct ice_aqc_set_cgu_input_config *cmd; 5381 struct libie_aq_desc desc; 5382 5383 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5384 cmd = libie_aq_raw(&desc); 5385 cmd->input_idx = input_idx; 5386 cmd->flags1 = flags1; 5387 cmd->flags2 = flags2; 5388 cmd->freq = cpu_to_le32(freq); 5389 cmd->phase_delay = cpu_to_le32(phase_delay); 5390 5391 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5392 } 5393 5394 /** 5395 * ice_aq_get_input_pin_cfg - get input pin config 5396 * @hw: pointer to the HW struct 5397 * @input_idx: Input index 5398 * @status: Pin status 5399 * @type: Pin type 5400 * @flags1: Input flags 5401 * @flags2: Input flags 5402 * @freq: Frequency in Hz 5403 * @phase_delay: Delay in ps 5404 * 5405 * Get CGU input config (0x0C63) 5406 * Return: 0 on success or negative value on failure. 5407 */ 5408 int 5409 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5410 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5411 { 5412 struct ice_aqc_get_cgu_input_config *cmd; 5413 struct libie_aq_desc desc; 5414 int ret; 5415 5416 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5417 cmd = libie_aq_raw(&desc); 5418 cmd->input_idx = input_idx; 5419 5420 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5421 if (!ret) { 5422 if (status) 5423 *status = cmd->status; 5424 if (type) 5425 *type = cmd->type; 5426 if (flags1) 5427 *flags1 = cmd->flags1; 5428 if (flags2) 5429 *flags2 = cmd->flags2; 5430 if (freq) 5431 *freq = le32_to_cpu(cmd->freq); 5432 if (phase_delay) 5433 *phase_delay = le32_to_cpu(cmd->phase_delay); 5434 } 5435 5436 return ret; 5437 } 5438 5439 /** 5440 * ice_aq_set_output_pin_cfg - set output pin config 5441 * @hw: pointer to the HW struct 5442 * @output_idx: Output index 5443 * @flags: Output flags 5444 * @src_sel: Index of DPLL block 5445 * @freq: Output frequency 5446 * @phase_delay: Output phase compensation 5447 * 5448 * Set CGU output config (0x0C64) 5449 * Return: 0 on success or negative value on failure. 5450 */ 5451 int 5452 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5453 u8 src_sel, u32 freq, s32 phase_delay) 5454 { 5455 struct ice_aqc_set_cgu_output_config *cmd; 5456 struct libie_aq_desc desc; 5457 5458 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5459 cmd = libie_aq_raw(&desc); 5460 cmd->output_idx = output_idx; 5461 cmd->flags = flags; 5462 cmd->src_sel = src_sel; 5463 cmd->freq = cpu_to_le32(freq); 5464 cmd->phase_delay = cpu_to_le32(phase_delay); 5465 5466 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5467 } 5468 5469 /** 5470 * ice_aq_get_output_pin_cfg - get output pin config 5471 * @hw: pointer to the HW struct 5472 * @output_idx: Output index 5473 * @flags: Output flags 5474 * @src_sel: Internal DPLL source 5475 * @freq: Output frequency 5476 * @src_freq: Source frequency 5477 * 5478 * Get CGU output config (0x0C65) 5479 * Return: 0 on success or negative value on failure. 5480 */ 5481 int 5482 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5483 u8 *src_sel, u32 *freq, u32 *src_freq) 5484 { 5485 struct ice_aqc_get_cgu_output_config *cmd; 5486 struct libie_aq_desc desc; 5487 int ret; 5488 5489 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5490 cmd = libie_aq_raw(&desc); 5491 cmd->output_idx = output_idx; 5492 5493 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5494 if (!ret) { 5495 if (flags) 5496 *flags = cmd->flags; 5497 if (src_sel) 5498 *src_sel = cmd->src_sel; 5499 if (freq) 5500 *freq = le32_to_cpu(cmd->freq); 5501 if (src_freq) 5502 *src_freq = le32_to_cpu(cmd->src_freq); 5503 } 5504 5505 return ret; 5506 } 5507 5508 /** 5509 * ice_aq_get_cgu_dpll_status - get dpll status 5510 * @hw: pointer to the HW struct 5511 * @dpll_num: DPLL index 5512 * @ref_state: Reference clock state 5513 * @config: current DPLL config 5514 * @dpll_state: current DPLL state 5515 * @phase_offset: Phase offset in ns 5516 * @eec_mode: EEC_mode 5517 * 5518 * Get CGU DPLL status (0x0C66) 5519 * Return: 0 on success or negative value on failure. 5520 */ 5521 int 5522 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5523 u8 *dpll_state, u8 *config, s64 *phase_offset, 5524 u8 *eec_mode) 5525 { 5526 struct ice_aqc_get_cgu_dpll_status *cmd; 5527 struct libie_aq_desc desc; 5528 int status; 5529 5530 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5531 cmd = libie_aq_raw(&desc); 5532 cmd->dpll_num = dpll_num; 5533 5534 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5535 if (!status) { 5536 *ref_state = cmd->ref_state; 5537 *dpll_state = cmd->dpll_state; 5538 *config = cmd->config; 5539 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5540 *phase_offset <<= 32; 5541 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5542 *phase_offset = sign_extend64(*phase_offset, 47); 5543 *eec_mode = cmd->eec_mode; 5544 } 5545 5546 return status; 5547 } 5548 5549 /** 5550 * ice_aq_set_cgu_dpll_config - set dpll config 5551 * @hw: pointer to the HW struct 5552 * @dpll_num: DPLL index 5553 * @ref_state: Reference clock state 5554 * @config: DPLL config 5555 * @eec_mode: EEC mode 5556 * 5557 * Set CGU DPLL config (0x0C67) 5558 * Return: 0 on success or negative value on failure. 5559 */ 5560 int 5561 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5562 u8 config, u8 eec_mode) 5563 { 5564 struct ice_aqc_set_cgu_dpll_config *cmd; 5565 struct libie_aq_desc desc; 5566 5567 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5568 cmd = libie_aq_raw(&desc); 5569 cmd->dpll_num = dpll_num; 5570 cmd->ref_state = ref_state; 5571 cmd->config = config; 5572 cmd->eec_mode = eec_mode; 5573 5574 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5575 } 5576 5577 /** 5578 * ice_aq_set_cgu_ref_prio - set input reference priority 5579 * @hw: pointer to the HW struct 5580 * @dpll_num: DPLL index 5581 * @ref_idx: Reference pin index 5582 * @ref_priority: Reference input priority 5583 * 5584 * Set CGU reference priority (0x0C68) 5585 * Return: 0 on success or negative value on failure. 5586 */ 5587 int 5588 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5589 u8 ref_priority) 5590 { 5591 struct ice_aqc_set_cgu_ref_prio *cmd; 5592 struct libie_aq_desc desc; 5593 5594 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5595 cmd = libie_aq_raw(&desc); 5596 cmd->dpll_num = dpll_num; 5597 cmd->ref_idx = ref_idx; 5598 cmd->ref_priority = ref_priority; 5599 5600 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5601 } 5602 5603 /** 5604 * ice_aq_get_cgu_ref_prio - get input reference priority 5605 * @hw: pointer to the HW struct 5606 * @dpll_num: DPLL index 5607 * @ref_idx: Reference pin index 5608 * @ref_prio: Reference input priority 5609 * 5610 * Get CGU reference priority (0x0C69) 5611 * Return: 0 on success or negative value on failure. 5612 */ 5613 int 5614 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5615 u8 *ref_prio) 5616 { 5617 struct ice_aqc_get_cgu_ref_prio *cmd; 5618 struct libie_aq_desc desc; 5619 int status; 5620 5621 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5622 cmd = libie_aq_raw(&desc); 5623 cmd->dpll_num = dpll_num; 5624 cmd->ref_idx = ref_idx; 5625 5626 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5627 if (!status) 5628 *ref_prio = cmd->ref_priority; 5629 5630 return status; 5631 } 5632 5633 /** 5634 * ice_aq_get_cgu_info - get cgu info 5635 * @hw: pointer to the HW struct 5636 * @cgu_id: CGU ID 5637 * @cgu_cfg_ver: CGU config version 5638 * @cgu_fw_ver: CGU firmware version 5639 * 5640 * Get CGU info (0x0C6A) 5641 * Return: 0 on success or negative value on failure. 5642 */ 5643 int 5644 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5645 u32 *cgu_fw_ver) 5646 { 5647 struct ice_aqc_get_cgu_info *cmd; 5648 struct libie_aq_desc desc; 5649 int status; 5650 5651 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5652 cmd = libie_aq_raw(&desc); 5653 5654 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5655 if (!status) { 5656 *cgu_id = le32_to_cpu(cmd->cgu_id); 5657 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5658 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5659 } 5660 5661 return status; 5662 } 5663 5664 /** 5665 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5666 * @hw: pointer to the HW struct 5667 * @phy_output: PHY reference clock output pin 5668 * @enable: GPIO state to be applied 5669 * @freq: PHY output frequency 5670 * 5671 * Set phy recovered clock as reference (0x0630) 5672 * Return: 0 on success or negative value on failure. 5673 */ 5674 int 5675 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5676 u32 *freq) 5677 { 5678 struct ice_aqc_set_phy_rec_clk_out *cmd; 5679 struct libie_aq_desc desc; 5680 int status; 5681 5682 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5683 cmd = libie_aq_raw(&desc); 5684 cmd->phy_output = phy_output; 5685 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5686 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5687 cmd->freq = cpu_to_le32(*freq); 5688 5689 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5690 if (!status) 5691 *freq = le32_to_cpu(cmd->freq); 5692 5693 return status; 5694 } 5695 5696 /** 5697 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5698 * @hw: pointer to the HW struct 5699 * @phy_output: PHY reference clock output pin 5700 * @port_num: Port number 5701 * @flags: PHY flags 5702 * @node_handle: PHY output frequency 5703 * 5704 * Get PHY recovered clock output info (0x0631) 5705 * Return: 0 on success or negative value on failure. 5706 */ 5707 int 5708 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5709 u8 *flags, u16 *node_handle) 5710 { 5711 struct ice_aqc_get_phy_rec_clk_out *cmd; 5712 struct libie_aq_desc desc; 5713 int status; 5714 5715 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5716 cmd = libie_aq_raw(&desc); 5717 cmd->phy_output = *phy_output; 5718 5719 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5720 if (!status) { 5721 *phy_output = cmd->phy_output; 5722 if (port_num) 5723 *port_num = cmd->port_num; 5724 if (flags) 5725 *flags = cmd->flags; 5726 if (node_handle) 5727 *node_handle = le16_to_cpu(cmd->node_handle); 5728 } 5729 5730 return status; 5731 } 5732 5733 /** 5734 * ice_aq_get_sensor_reading 5735 * @hw: pointer to the HW struct 5736 * @data: pointer to data to be read from the sensor 5737 * 5738 * Get sensor reading (0x0632) 5739 */ 5740 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5741 struct ice_aqc_get_sensor_reading_resp *data) 5742 { 5743 struct ice_aqc_get_sensor_reading *cmd; 5744 struct libie_aq_desc desc; 5745 int status; 5746 5747 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5748 cmd = libie_aq_raw(&desc); 5749 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5750 #define ICE_INTERNAL_TEMP_SENSOR 0 5751 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5752 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5753 5754 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5755 if (!status) 5756 memcpy(data, &desc.params.raw, 5757 sizeof(*data)); 5758 5759 return status; 5760 } 5761 5762 /** 5763 * ice_replay_pre_init - replay pre initialization 5764 * @hw: pointer to the HW struct 5765 * 5766 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5767 */ 5768 static int ice_replay_pre_init(struct ice_hw *hw) 5769 { 5770 struct ice_switch_info *sw = hw->switch_info; 5771 u8 i; 5772 5773 /* Delete old entries from replay filter list head if there is any */ 5774 ice_rm_all_sw_replay_rule_info(hw); 5775 /* In start of replay, move entries into replay_rules list, it 5776 * will allow adding rules entries back to filt_rules list, 5777 * which is operational list. 5778 */ 5779 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5780 list_replace_init(&sw->recp_list[i].filt_rules, 5781 &sw->recp_list[i].filt_replay_rules); 5782 ice_sched_replay_agg_vsi_preinit(hw); 5783 5784 return 0; 5785 } 5786 5787 /** 5788 * ice_replay_vsi - replay VSI configuration 5789 * @hw: pointer to the HW struct 5790 * @vsi_handle: driver VSI handle 5791 * 5792 * Restore all VSI configuration after reset. It is required to call this 5793 * function with main VSI first. 5794 */ 5795 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5796 { 5797 int status; 5798 5799 if (!ice_is_vsi_valid(hw, vsi_handle)) 5800 return -EINVAL; 5801 5802 /* Replay pre-initialization if there is any */ 5803 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5804 status = ice_replay_pre_init(hw); 5805 if (status) 5806 return status; 5807 } 5808 /* Replay per VSI all RSS configurations */ 5809 status = ice_replay_rss_cfg(hw, vsi_handle); 5810 if (status) 5811 return status; 5812 /* Replay per VSI all filters */ 5813 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5814 if (!status) 5815 status = ice_replay_vsi_agg(hw, vsi_handle); 5816 return status; 5817 } 5818 5819 /** 5820 * ice_replay_post - post replay configuration cleanup 5821 * @hw: pointer to the HW struct 5822 * 5823 * Post replay cleanup. 5824 */ 5825 void ice_replay_post(struct ice_hw *hw) 5826 { 5827 /* Delete old entries from replay filter list head */ 5828 ice_rm_all_sw_replay_rule_info(hw); 5829 ice_sched_replay_agg(hw); 5830 } 5831 5832 /** 5833 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5834 * @hw: ptr to the hardware info 5835 * @reg: offset of 64 bit HW register to read from 5836 * @prev_stat_loaded: bool to specify if previous stats are loaded 5837 * @prev_stat: ptr to previous loaded stat value 5838 * @cur_stat: ptr to current stat value 5839 */ 5840 void 5841 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5842 u64 *prev_stat, u64 *cur_stat) 5843 { 5844 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5845 5846 /* device stats are not reset at PFR, they likely will not be zeroed 5847 * when the driver starts. Thus, save the value from the first read 5848 * without adding to the statistic value so that we report stats which 5849 * count up from zero. 5850 */ 5851 if (!prev_stat_loaded) { 5852 *prev_stat = new_data; 5853 return; 5854 } 5855 5856 /* Calculate the difference between the new and old values, and then 5857 * add it to the software stat value. 5858 */ 5859 if (new_data >= *prev_stat) 5860 *cur_stat += new_data - *prev_stat; 5861 else 5862 /* to manage the potential roll-over */ 5863 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5864 5865 /* Update the previously stored value to prepare for next read */ 5866 *prev_stat = new_data; 5867 } 5868 5869 /** 5870 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5871 * @hw: ptr to the hardware info 5872 * @reg: offset of HW register to read from 5873 * @prev_stat_loaded: bool to specify if previous stats are loaded 5874 * @prev_stat: ptr to previous loaded stat value 5875 * @cur_stat: ptr to current stat value 5876 */ 5877 void 5878 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5879 u64 *prev_stat, u64 *cur_stat) 5880 { 5881 u32 new_data; 5882 5883 new_data = rd32(hw, reg); 5884 5885 /* device stats are not reset at PFR, they likely will not be zeroed 5886 * when the driver starts. Thus, save the value from the first read 5887 * without adding to the statistic value so that we report stats which 5888 * count up from zero. 5889 */ 5890 if (!prev_stat_loaded) { 5891 *prev_stat = new_data; 5892 return; 5893 } 5894 5895 /* Calculate the difference between the new and old values, and then 5896 * add it to the software stat value. 5897 */ 5898 if (new_data >= *prev_stat) 5899 *cur_stat += new_data - *prev_stat; 5900 else 5901 /* to manage the potential roll-over */ 5902 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5903 5904 /* Update the previously stored value to prepare for next read */ 5905 *prev_stat = new_data; 5906 } 5907 5908 /** 5909 * ice_sched_query_elem - query element information from HW 5910 * @hw: pointer to the HW struct 5911 * @node_teid: node TEID to be queried 5912 * @buf: buffer to element information 5913 * 5914 * This function queries HW element information 5915 */ 5916 int 5917 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5918 struct ice_aqc_txsched_elem_data *buf) 5919 { 5920 u16 buf_size, num_elem_ret = 0; 5921 int status; 5922 5923 buf_size = sizeof(*buf); 5924 memset(buf, 0, buf_size); 5925 buf->node_teid = cpu_to_le32(node_teid); 5926 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5927 NULL); 5928 if (status || num_elem_ret != 1) 5929 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5930 return status; 5931 } 5932 5933 /** 5934 * ice_aq_read_i2c 5935 * @hw: pointer to the hw struct 5936 * @topo_addr: topology address for a device to communicate with 5937 * @bus_addr: 7-bit I2C bus address 5938 * @addr: I2C memory address (I2C offset) with up to 16 bits 5939 * @params: I2C parameters: bit [7] - Repeated start, 5940 * bits [6:5] data offset size, 5941 * bit [4] - I2C address type, 5942 * bits [3:0] - data size to read (0-16 bytes) 5943 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5944 * @cd: pointer to command details structure or NULL 5945 * 5946 * Read I2C (0x06E2) 5947 */ 5948 int 5949 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5950 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5951 struct ice_sq_cd *cd) 5952 { 5953 struct libie_aq_desc desc = { 0 }; 5954 struct ice_aqc_i2c *cmd; 5955 u8 data_size; 5956 int status; 5957 5958 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5959 cmd = libie_aq_raw(&desc); 5960 5961 if (!data) 5962 return -EINVAL; 5963 5964 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5965 5966 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5967 cmd->topo_addr = topo_addr; 5968 cmd->i2c_params = params; 5969 cmd->i2c_addr = addr; 5970 5971 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5972 if (!status) { 5973 struct ice_aqc_read_i2c_resp *resp; 5974 u8 i; 5975 5976 resp = libie_aq_raw(&desc); 5977 for (i = 0; i < data_size; i++) { 5978 *data = resp->i2c_data[i]; 5979 data++; 5980 } 5981 } 5982 5983 return status; 5984 } 5985 5986 /** 5987 * ice_aq_write_i2c 5988 * @hw: pointer to the hw struct 5989 * @topo_addr: topology address for a device to communicate with 5990 * @bus_addr: 7-bit I2C bus address 5991 * @addr: I2C memory address (I2C offset) with up to 16 bits 5992 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5993 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5994 * @cd: pointer to command details structure or NULL 5995 * 5996 * Write I2C (0x06E3) 5997 * 5998 * * Return: 5999 * * 0 - Successful write to the i2c device 6000 * * -EINVAL - Data size greater than 4 bytes 6001 * * -EIO - FW error 6002 */ 6003 int 6004 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 6005 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 6006 struct ice_sq_cd *cd) 6007 { 6008 struct libie_aq_desc desc = { 0 }; 6009 struct ice_aqc_i2c *cmd; 6010 u8 data_size; 6011 6012 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 6013 cmd = libie_aq_raw(&desc); 6014 6015 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 6016 6017 /* data_size limited to 4 */ 6018 if (data_size > 4) 6019 return -EINVAL; 6020 6021 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 6022 cmd->topo_addr = topo_addr; 6023 cmd->i2c_params = params; 6024 cmd->i2c_addr = addr; 6025 6026 memcpy(cmd->i2c_data, data, data_size); 6027 6028 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6029 } 6030 6031 /** 6032 * ice_get_pca9575_handle - find and return the PCA9575 controller 6033 * @hw: pointer to the hw struct 6034 * @pca9575_handle: GPIO controller's handle 6035 * 6036 * Find and return the GPIO controller's handle in the netlist. 6037 * When found - the value will be cached in the hw structure and following calls 6038 * will return cached value. 6039 * 6040 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 6041 */ 6042 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 6043 { 6044 struct ice_aqc_get_link_topo *cmd; 6045 struct libie_aq_desc desc; 6046 int err; 6047 u8 idx; 6048 6049 /* If handle was read previously return cached value */ 6050 if (hw->io_expander_handle) { 6051 *pca9575_handle = hw->io_expander_handle; 6052 return 0; 6053 } 6054 6055 #define SW_PCA9575_SFP_TOPO_IDX 2 6056 #define SW_PCA9575_QSFP_TOPO_IDX 1 6057 6058 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 6059 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 6060 idx = SW_PCA9575_SFP_TOPO_IDX; 6061 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 6062 idx = SW_PCA9575_QSFP_TOPO_IDX; 6063 else 6064 return -ENXIO; 6065 6066 /* If handle was not detected read it from the netlist */ 6067 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 6068 cmd = libie_aq_raw(&desc); 6069 cmd->addr.topo_params.node_type_ctx = 6070 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 6071 cmd->addr.topo_params.index = idx; 6072 6073 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6074 if (err) 6075 return -ENXIO; 6076 6077 /* Verify if we found the right IO expander type */ 6078 if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 6079 return -ENXIO; 6080 6081 /* If present save the handle and return it */ 6082 hw->io_expander_handle = 6083 le16_to_cpu(cmd->addr.handle); 6084 *pca9575_handle = hw->io_expander_handle; 6085 6086 return 0; 6087 } 6088 6089 /** 6090 * ice_read_pca9575_reg - read the register from the PCA9575 controller 6091 * @hw: pointer to the hw struct 6092 * @offset: GPIO controller register offset 6093 * @data: pointer to data to be read from the GPIO controller 6094 * 6095 * Return: 0 on success, negative error code otherwise. 6096 */ 6097 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 6098 { 6099 struct ice_aqc_link_topo_addr link_topo; 6100 __le16 addr; 6101 u16 handle; 6102 int err; 6103 6104 memset(&link_topo, 0, sizeof(link_topo)); 6105 6106 err = ice_get_pca9575_handle(hw, &handle); 6107 if (err) 6108 return err; 6109 6110 link_topo.handle = cpu_to_le16(handle); 6111 link_topo.topo_params.node_type_ctx = 6112 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6113 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6114 6115 addr = cpu_to_le16((u16)offset); 6116 6117 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6118 } 6119 6120 /** 6121 * ice_aq_set_gpio 6122 * @hw: pointer to the hw struct 6123 * @gpio_ctrl_handle: GPIO controller node handle 6124 * @pin_idx: IO Number of the GPIO that needs to be set 6125 * @value: SW provide IO value to set in the LSB 6126 * @cd: pointer to command details structure or NULL 6127 * 6128 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6129 */ 6130 int 6131 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6132 struct ice_sq_cd *cd) 6133 { 6134 struct libie_aq_desc desc; 6135 struct ice_aqc_gpio *cmd; 6136 6137 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6138 cmd = libie_aq_raw(&desc); 6139 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6140 cmd->gpio_num = pin_idx; 6141 cmd->gpio_val = value ? 1 : 0; 6142 6143 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6144 } 6145 6146 /** 6147 * ice_aq_get_gpio 6148 * @hw: pointer to the hw struct 6149 * @gpio_ctrl_handle: GPIO controller node handle 6150 * @pin_idx: IO Number of the GPIO that needs to be set 6151 * @value: IO value read 6152 * @cd: pointer to command details structure or NULL 6153 * 6154 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6155 * the topology 6156 */ 6157 int 6158 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6159 bool *value, struct ice_sq_cd *cd) 6160 { 6161 struct libie_aq_desc desc; 6162 struct ice_aqc_gpio *cmd; 6163 int status; 6164 6165 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6166 cmd = libie_aq_raw(&desc); 6167 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6168 cmd->gpio_num = pin_idx; 6169 6170 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6171 if (status) 6172 return status; 6173 6174 *value = !!cmd->gpio_val; 6175 return 0; 6176 } 6177 6178 /** 6179 * ice_is_fw_api_min_ver 6180 * @hw: pointer to the hardware structure 6181 * @maj: major version 6182 * @min: minor version 6183 * @patch: patch version 6184 * 6185 * Checks if the firmware API is minimum version 6186 */ 6187 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6188 { 6189 if (hw->api_maj_ver == maj) { 6190 if (hw->api_min_ver > min) 6191 return true; 6192 if (hw->api_min_ver == min && hw->api_patch >= patch) 6193 return true; 6194 } else if (hw->api_maj_ver > maj) { 6195 return true; 6196 } 6197 6198 return false; 6199 } 6200 6201 /** 6202 * ice_fw_supports_link_override 6203 * @hw: pointer to the hardware structure 6204 * 6205 * Checks if the firmware supports link override 6206 */ 6207 bool ice_fw_supports_link_override(struct ice_hw *hw) 6208 { 6209 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6210 ICE_FW_API_LINK_OVERRIDE_MIN, 6211 ICE_FW_API_LINK_OVERRIDE_PATCH); 6212 } 6213 6214 /** 6215 * ice_get_link_default_override 6216 * @ldo: pointer to the link default override struct 6217 * @pi: pointer to the port info struct 6218 * 6219 * Gets the link default override for a port 6220 */ 6221 int 6222 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6223 struct ice_port_info *pi) 6224 { 6225 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6226 struct ice_hw *hw = pi->hw; 6227 int status; 6228 6229 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6230 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6231 if (status) { 6232 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6233 return status; 6234 } 6235 6236 /* Each port has its own config; calculate for our port */ 6237 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6238 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6239 6240 /* link options first */ 6241 status = ice_read_sr_word(hw, tlv_start, &buf); 6242 if (status) { 6243 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6244 return status; 6245 } 6246 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6247 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6248 ICE_LINK_OVERRIDE_PHY_CFG_S; 6249 6250 /* link PHY config */ 6251 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6252 status = ice_read_sr_word(hw, offset, &buf); 6253 if (status) { 6254 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6255 return status; 6256 } 6257 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6258 6259 /* PHY types low */ 6260 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6261 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6262 status = ice_read_sr_word(hw, (offset + i), &buf); 6263 if (status) { 6264 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6265 return status; 6266 } 6267 /* shift 16 bits at a time to fill 64 bits */ 6268 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6269 } 6270 6271 /* PHY types high */ 6272 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6273 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6274 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6275 status = ice_read_sr_word(hw, (offset + i), &buf); 6276 if (status) { 6277 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6278 return status; 6279 } 6280 /* shift 16 bits at a time to fill 64 bits */ 6281 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6282 } 6283 6284 return status; 6285 } 6286 6287 /** 6288 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6289 * @caps: get PHY capability data 6290 */ 6291 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6292 { 6293 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6294 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6295 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6296 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6297 return true; 6298 6299 return false; 6300 } 6301 6302 /** 6303 * ice_is_fw_health_report_supported - checks if firmware supports health events 6304 * @hw: pointer to the hardware structure 6305 * 6306 * Return: true if firmware supports health status reports, 6307 * false otherwise 6308 */ 6309 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6310 { 6311 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6312 ICE_FW_API_HEALTH_REPORT_MIN, 6313 ICE_FW_API_HEALTH_REPORT_PATCH); 6314 } 6315 6316 /** 6317 * ice_aq_set_health_status_cfg - Configure FW health events 6318 * @hw: pointer to the HW struct 6319 * @event_source: type of diagnostic events to enable 6320 * 6321 * Configure the health status event types that the firmware will send to this 6322 * PF. The supported event types are: PF-specific, all PFs, and global. 6323 * 6324 * Return: 0 on success, negative error code otherwise. 6325 */ 6326 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6327 { 6328 struct ice_aqc_set_health_status_cfg *cmd; 6329 struct libie_aq_desc desc; 6330 6331 cmd = libie_aq_raw(&desc); 6332 6333 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6334 6335 cmd->event_source = event_source; 6336 6337 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6338 } 6339 6340 /** 6341 * ice_aq_set_lldp_mib - Set the LLDP MIB 6342 * @hw: pointer to the HW struct 6343 * @mib_type: Local, Remote or both Local and Remote MIBs 6344 * @buf: pointer to the caller-supplied buffer to store the MIB block 6345 * @buf_size: size of the buffer (in bytes) 6346 * @cd: pointer to command details structure or NULL 6347 * 6348 * Set the LLDP MIB. (0x0A08) 6349 */ 6350 int 6351 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6352 struct ice_sq_cd *cd) 6353 { 6354 struct ice_aqc_lldp_set_local_mib *cmd; 6355 struct libie_aq_desc desc; 6356 6357 cmd = libie_aq_raw(&desc); 6358 6359 if (buf_size == 0 || !buf) 6360 return -EINVAL; 6361 6362 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6363 6364 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6365 desc.datalen = cpu_to_le16(buf_size); 6366 6367 cmd->type = mib_type; 6368 cmd->length = cpu_to_le16(buf_size); 6369 6370 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6371 } 6372 6373 /** 6374 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6375 * @hw: pointer to HW struct 6376 */ 6377 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6378 { 6379 if (hw->mac_type != ICE_MAC_E810) 6380 return false; 6381 6382 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6383 ICE_FW_API_LLDP_FLTR_MIN, 6384 ICE_FW_API_LLDP_FLTR_PATCH); 6385 } 6386 6387 /** 6388 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6389 * @hw: pointer to HW struct 6390 * @vsi: VSI to add the filter to 6391 * @add: boolean for if adding or removing a filter 6392 * 6393 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6394 * with this HW or VSI, otherwise an error corresponding to 6395 * the AQ transaction result. 6396 */ 6397 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6398 { 6399 struct ice_aqc_lldp_filter_ctrl *cmd; 6400 struct libie_aq_desc desc; 6401 6402 if (!ice_fw_supports_lldp_fltr_ctrl(hw)) 6403 return -EOPNOTSUPP; 6404 6405 cmd = libie_aq_raw(&desc); 6406 6407 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6408 6409 if (add) 6410 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6411 else 6412 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6413 6414 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6415 6416 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6417 } 6418 6419 /** 6420 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6421 * @hw: pointer to HW struct 6422 */ 6423 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6424 { 6425 struct libie_aq_desc desc; 6426 6427 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6428 6429 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6430 } 6431 6432 /** 6433 * ice_fw_supports_report_dflt_cfg 6434 * @hw: pointer to the hardware structure 6435 * 6436 * Checks if the firmware supports report default configuration 6437 */ 6438 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6439 { 6440 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6441 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6442 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6443 } 6444 6445 /* each of the indexes into the following array match the speed of a return 6446 * value from the list of AQ returned speeds like the range: 6447 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6448 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6449 * array. The array is defined as 15 elements long because the link_speed 6450 * returned by the firmware is a 16 bit * value, but is indexed 6451 * by [fls(speed) - 1] 6452 */ 6453 static const u32 ice_aq_to_link_speed[] = { 6454 SPEED_10, /* BIT(0) */ 6455 SPEED_100, 6456 SPEED_1000, 6457 SPEED_2500, 6458 SPEED_5000, 6459 SPEED_10000, 6460 SPEED_20000, 6461 SPEED_25000, 6462 SPEED_40000, 6463 SPEED_50000, 6464 SPEED_100000, /* BIT(10) */ 6465 SPEED_200000, 6466 }; 6467 6468 /** 6469 * ice_get_link_speed - get integer speed from table 6470 * @index: array index from fls(aq speed) - 1 6471 * 6472 * Returns: u32 value containing integer speed 6473 */ 6474 u32 ice_get_link_speed(u16 index) 6475 { 6476 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6477 return 0; 6478 6479 return ice_aq_to_link_speed[index]; 6480 } 6481 6482 /** 6483 * ice_get_dest_cgu - get destination CGU dev for given HW 6484 * @hw: pointer to the HW struct 6485 * 6486 * Get CGU client id for CGU register read/write operations. 6487 * 6488 * Return: CGU device id to use in SBQ transactions. 6489 */ 6490 static enum ice_sbq_dev_id ice_get_dest_cgu(struct ice_hw *hw) 6491 { 6492 /* On dual complex E825 only complex 0 has functional CGU powering all 6493 * the PHYs. 6494 * SBQ destination device cgu points to CGU on a current complex and to 6495 * access primary CGU from the secondary complex, the driver should use 6496 * cgu_peer as a destination device. 6497 */ 6498 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && ice_is_dual(hw) && 6499 !ice_is_primary(hw)) 6500 return ice_sbq_dev_cgu_peer; 6501 return ice_sbq_dev_cgu; 6502 } 6503 6504 /** 6505 * ice_read_cgu_reg - Read a CGU register 6506 * @hw: Pointer to the HW struct 6507 * @addr: Register address to read 6508 * @val: Storage for register value read 6509 * 6510 * Read the contents of a register of the Clock Generation Unit. Only 6511 * applicable to E82X devices. 6512 * 6513 * Return: 0 on success, other error codes when failed to read from CGU. 6514 */ 6515 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6516 { 6517 struct ice_sbq_msg_input cgu_msg = { 6518 .dest_dev = ice_get_dest_cgu(hw), 6519 .opcode = ice_sbq_msg_rd, 6520 .msg_addr_low = addr 6521 }; 6522 int err; 6523 6524 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6525 if (err) { 6526 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6527 addr, err); 6528 return err; 6529 } 6530 6531 *val = cgu_msg.data; 6532 6533 return 0; 6534 } 6535 6536 /** 6537 * ice_write_cgu_reg - Write a CGU register 6538 * @hw: Pointer to the HW struct 6539 * @addr: Register address to write 6540 * @val: Value to write into the register 6541 * 6542 * Write the specified value to a register of the Clock Generation Unit. Only 6543 * applicable to E82X devices. 6544 * 6545 * Return: 0 on success, other error codes when failed to write to CGU. 6546 */ 6547 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6548 { 6549 struct ice_sbq_msg_input cgu_msg = { 6550 .dest_dev = ice_get_dest_cgu(hw), 6551 .opcode = ice_sbq_msg_wr, 6552 .msg_addr_low = addr, 6553 .data = val 6554 }; 6555 int err; 6556 6557 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6558 if (err) 6559 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6560 addr, err); 6561 6562 return err; 6563 } 6564