1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _IAVF_ADMINQ_CMD_H_ 5 #define _IAVF_ADMINQ_CMD_H_ 6 7 #include <linux/net/intel/libie/adminq.h> 8 9 /* This header file defines the iavf Admin Queue commands and is shared between 10 * iavf Firmware and Software. 11 * 12 * This file needs to comply with the Linux Kernel coding style. 13 */ 14 15 #define IAVF_FW_API_VERSION_MAJOR 0x0001 16 #define IAVF_FW_API_VERSION_MINOR_X722 0x0005 17 #define IAVF_FW_API_VERSION_MINOR_X710 0x0008 18 19 #define IAVF_FW_MINOR_VERSION(_h) ((_h)->mac.type == IAVF_MAC_XL710 ? \ 20 IAVF_FW_API_VERSION_MINOR_X710 : \ 21 IAVF_FW_API_VERSION_MINOR_X722) 22 23 /* API version 1.7 implements additional link and PHY-specific APIs */ 24 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007 25 26 /* Admin Queue command opcodes */ 27 enum iavf_admin_queue_opc { 28 /* aq commands */ 29 iavf_aqc_opc_get_version = 0x0001, 30 iavf_aqc_opc_driver_version = 0x0002, 31 iavf_aqc_opc_queue_shutdown = 0x0003, 32 iavf_aqc_opc_set_pf_context = 0x0004, 33 34 /* resource ownership */ 35 iavf_aqc_opc_request_resource = 0x0008, 36 iavf_aqc_opc_release_resource = 0x0009, 37 38 iavf_aqc_opc_list_func_capabilities = 0x000A, 39 iavf_aqc_opc_list_dev_capabilities = 0x000B, 40 41 /* Proxy commands */ 42 iavf_aqc_opc_set_proxy_config = 0x0104, 43 iavf_aqc_opc_set_ns_proxy_table_entry = 0x0105, 44 45 /* LAA */ 46 iavf_aqc_opc_mac_address_read = 0x0107, 47 iavf_aqc_opc_mac_address_write = 0x0108, 48 49 /* PXE */ 50 iavf_aqc_opc_clear_pxe_mode = 0x0110, 51 52 /* WoL commands */ 53 iavf_aqc_opc_set_wol_filter = 0x0120, 54 iavf_aqc_opc_get_wake_reason = 0x0121, 55 56 /* internal switch commands */ 57 iavf_aqc_opc_get_switch_config = 0x0200, 58 iavf_aqc_opc_add_statistics = 0x0201, 59 iavf_aqc_opc_remove_statistics = 0x0202, 60 iavf_aqc_opc_set_port_parameters = 0x0203, 61 iavf_aqc_opc_get_switch_resource_alloc = 0x0204, 62 iavf_aqc_opc_set_switch_config = 0x0205, 63 iavf_aqc_opc_rx_ctl_reg_read = 0x0206, 64 iavf_aqc_opc_rx_ctl_reg_write = 0x0207, 65 66 iavf_aqc_opc_add_vsi = 0x0210, 67 iavf_aqc_opc_update_vsi_parameters = 0x0211, 68 iavf_aqc_opc_get_vsi_parameters = 0x0212, 69 70 iavf_aqc_opc_add_pv = 0x0220, 71 iavf_aqc_opc_update_pv_parameters = 0x0221, 72 iavf_aqc_opc_get_pv_parameters = 0x0222, 73 74 iavf_aqc_opc_add_veb = 0x0230, 75 iavf_aqc_opc_update_veb_parameters = 0x0231, 76 iavf_aqc_opc_get_veb_parameters = 0x0232, 77 78 iavf_aqc_opc_delete_element = 0x0243, 79 80 iavf_aqc_opc_add_macvlan = 0x0250, 81 iavf_aqc_opc_remove_macvlan = 0x0251, 82 iavf_aqc_opc_add_vlan = 0x0252, 83 iavf_aqc_opc_remove_vlan = 0x0253, 84 iavf_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 85 iavf_aqc_opc_add_tag = 0x0255, 86 iavf_aqc_opc_remove_tag = 0x0256, 87 iavf_aqc_opc_add_multicast_etag = 0x0257, 88 iavf_aqc_opc_remove_multicast_etag = 0x0258, 89 iavf_aqc_opc_update_tag = 0x0259, 90 iavf_aqc_opc_add_control_packet_filter = 0x025A, 91 iavf_aqc_opc_remove_control_packet_filter = 0x025B, 92 iavf_aqc_opc_add_cloud_filters = 0x025C, 93 iavf_aqc_opc_remove_cloud_filters = 0x025D, 94 iavf_aqc_opc_clear_wol_switch_filters = 0x025E, 95 96 iavf_aqc_opc_add_mirror_rule = 0x0260, 97 iavf_aqc_opc_delete_mirror_rule = 0x0261, 98 99 /* Dynamic Device Personalization */ 100 iavf_aqc_opc_write_personalization_profile = 0x0270, 101 iavf_aqc_opc_get_personalization_profile_list = 0x0271, 102 103 /* DCB commands */ 104 iavf_aqc_opc_dcb_ignore_pfc = 0x0301, 105 iavf_aqc_opc_dcb_updated = 0x0302, 106 iavf_aqc_opc_set_dcb_parameters = 0x0303, 107 108 /* TX scheduler */ 109 iavf_aqc_opc_configure_vsi_bw_limit = 0x0400, 110 iavf_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 111 iavf_aqc_opc_configure_vsi_tc_bw = 0x0407, 112 iavf_aqc_opc_query_vsi_bw_config = 0x0408, 113 iavf_aqc_opc_query_vsi_ets_sla_config = 0x040A, 114 iavf_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 115 116 iavf_aqc_opc_enable_switching_comp_ets = 0x0413, 117 iavf_aqc_opc_modify_switching_comp_ets = 0x0414, 118 iavf_aqc_opc_disable_switching_comp_ets = 0x0415, 119 iavf_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 120 iavf_aqc_opc_configure_switching_comp_bw_config = 0x0417, 121 iavf_aqc_opc_query_switching_comp_ets_config = 0x0418, 122 iavf_aqc_opc_query_port_ets_config = 0x0419, 123 iavf_aqc_opc_query_switching_comp_bw_config = 0x041A, 124 iavf_aqc_opc_suspend_port_tx = 0x041B, 125 iavf_aqc_opc_resume_port_tx = 0x041C, 126 iavf_aqc_opc_configure_partition_bw = 0x041D, 127 /* hmc */ 128 iavf_aqc_opc_query_hmc_resource_profile = 0x0500, 129 iavf_aqc_opc_set_hmc_resource_profile = 0x0501, 130 131 /* phy commands*/ 132 iavf_aqc_opc_get_phy_abilities = 0x0600, 133 iavf_aqc_opc_set_phy_config = 0x0601, 134 iavf_aqc_opc_set_mac_config = 0x0603, 135 iavf_aqc_opc_set_link_restart_an = 0x0605, 136 iavf_aqc_opc_get_link_status = 0x0607, 137 iavf_aqc_opc_set_phy_int_mask = 0x0613, 138 iavf_aqc_opc_get_local_advt_reg = 0x0614, 139 iavf_aqc_opc_set_local_advt_reg = 0x0615, 140 iavf_aqc_opc_get_partner_advt = 0x0616, 141 iavf_aqc_opc_set_lb_modes = 0x0618, 142 iavf_aqc_opc_get_phy_wol_caps = 0x0621, 143 iavf_aqc_opc_set_phy_debug = 0x0622, 144 iavf_aqc_opc_upload_ext_phy_fm = 0x0625, 145 iavf_aqc_opc_run_phy_activity = 0x0626, 146 iavf_aqc_opc_set_phy_register = 0x0628, 147 iavf_aqc_opc_get_phy_register = 0x0629, 148 149 /* NVM commands */ 150 iavf_aqc_opc_nvm_read = 0x0701, 151 iavf_aqc_opc_nvm_erase = 0x0702, 152 iavf_aqc_opc_nvm_update = 0x0703, 153 iavf_aqc_opc_nvm_config_read = 0x0704, 154 iavf_aqc_opc_nvm_config_write = 0x0705, 155 iavf_aqc_opc_oem_post_update = 0x0720, 156 iavf_aqc_opc_thermal_sensor = 0x0721, 157 158 /* virtualization commands */ 159 iavf_aqc_opc_send_msg_to_pf = 0x0801, 160 iavf_aqc_opc_send_msg_to_vf = 0x0802, 161 iavf_aqc_opc_send_msg_to_peer = 0x0803, 162 163 /* alternate structure */ 164 iavf_aqc_opc_alternate_write = 0x0900, 165 iavf_aqc_opc_alternate_write_indirect = 0x0901, 166 iavf_aqc_opc_alternate_read = 0x0902, 167 iavf_aqc_opc_alternate_read_indirect = 0x0903, 168 iavf_aqc_opc_alternate_write_done = 0x0904, 169 iavf_aqc_opc_alternate_set_mode = 0x0905, 170 iavf_aqc_opc_alternate_clear_port = 0x0906, 171 172 /* LLDP commands */ 173 iavf_aqc_opc_lldp_get_mib = 0x0A00, 174 iavf_aqc_opc_lldp_update_mib = 0x0A01, 175 iavf_aqc_opc_lldp_add_tlv = 0x0A02, 176 iavf_aqc_opc_lldp_update_tlv = 0x0A03, 177 iavf_aqc_opc_lldp_delete_tlv = 0x0A04, 178 iavf_aqc_opc_lldp_stop = 0x0A05, 179 iavf_aqc_opc_lldp_start = 0x0A06, 180 181 /* Tunnel commands */ 182 iavf_aqc_opc_add_udp_tunnel = 0x0B00, 183 iavf_aqc_opc_del_udp_tunnel = 0x0B01, 184 iavf_aqc_opc_set_rss_key = 0x0B02, 185 iavf_aqc_opc_set_rss_lut = 0x0B03, 186 iavf_aqc_opc_get_rss_key = 0x0B04, 187 iavf_aqc_opc_get_rss_lut = 0x0B05, 188 189 /* Async Events */ 190 iavf_aqc_opc_event_lan_overflow = 0x1001, 191 192 /* OEM commands */ 193 iavf_aqc_opc_oem_parameter_change = 0xFE00, 194 iavf_aqc_opc_oem_device_status_change = 0xFE01, 195 iavf_aqc_opc_oem_ocsd_initialize = 0xFE02, 196 iavf_aqc_opc_oem_ocbb_initialize = 0xFE03, 197 198 /* debug commands */ 199 iavf_aqc_opc_debug_read_reg = 0xFF03, 200 iavf_aqc_opc_debug_write_reg = 0xFF04, 201 iavf_aqc_opc_debug_modify_reg = 0xFF07, 202 iavf_aqc_opc_debug_dump_internals = 0xFF08, 203 }; 204 205 /* command structures and indirect data structures */ 206 207 /* Structure naming conventions: 208 * - no suffix for direct command descriptor structures 209 * - _data for indirect sent data 210 * - _resp for indirect return data (data which is both will use _data) 211 * - _completion for direct return data 212 * - _element_ for repeated elements (may also be _data or _resp) 213 * 214 * Command structures are expected to overlay the params.raw member of the basic 215 * descriptor, and as such cannot exceed 16 bytes in length. 216 */ 217 218 /* This macro is used to generate a compilation error if a structure 219 * is not exactly the correct length. It gives a divide by zero error if the 220 * structure is not of the correct size, otherwise it creates an enum that is 221 * never used. 222 */ 223 #define IAVF_CHECK_STRUCT_LEN(n, X) enum iavf_static_assert_enum_##X \ 224 { iavf_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) } 225 226 /* This macro is used extensively to ensure that command structures are 16 227 * bytes in length as they have to map to the raw array of that size. 228 */ 229 #define IAVF_CHECK_CMD_LENGTH(X) IAVF_CHECK_STRUCT_LEN(16, X) 230 231 /* Queue Shutdown (direct 0x0003) */ 232 struct iavf_aqc_queue_shutdown { 233 __le32 driver_unloading; 234 #define IAVF_AQ_DRIVER_UNLOADING 0x1 235 u8 reserved[12]; 236 }; 237 238 IAVF_CHECK_CMD_LENGTH(iavf_aqc_queue_shutdown); 239 240 struct iavf_aqc_vsi_properties_data { 241 /* first 96 byte are written by SW */ 242 __le16 valid_sections; 243 #define IAVF_AQ_VSI_PROP_SWITCH_VALID 0x0001 244 #define IAVF_AQ_VSI_PROP_SECURITY_VALID 0x0002 245 #define IAVF_AQ_VSI_PROP_VLAN_VALID 0x0004 246 #define IAVF_AQ_VSI_PROP_CAS_PV_VALID 0x0008 247 #define IAVF_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 248 #define IAVF_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 249 #define IAVF_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 250 #define IAVF_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 251 #define IAVF_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 252 #define IAVF_AQ_VSI_PROP_SCHED_VALID 0x0200 253 /* switch section */ 254 __le16 switch_id; /* 12bit id combined with flags below */ 255 #define IAVF_AQ_VSI_SW_ID_SHIFT 0x0000 256 #define IAVF_AQ_VSI_SW_ID_MASK (0xFFF << IAVF_AQ_VSI_SW_ID_SHIFT) 257 #define IAVF_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 258 #define IAVF_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 259 #define IAVF_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 260 u8 sw_reserved[2]; 261 /* security section */ 262 u8 sec_flags; 263 #define IAVF_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 264 #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 265 #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 266 u8 sec_reserved; 267 /* VLAN section */ 268 __le16 pvid; /* VLANS include priority bits */ 269 __le16 fcoe_pvid; 270 u8 port_vlan_flags; 271 #define IAVF_AQ_VSI_PVLAN_MODE_SHIFT 0x00 272 #define IAVF_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 273 IAVF_AQ_VSI_PVLAN_MODE_SHIFT) 274 #define IAVF_AQ_VSI_PVLAN_MODE_TAGGED 0x01 275 #define IAVF_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 276 #define IAVF_AQ_VSI_PVLAN_MODE_ALL 0x03 277 #define IAVF_AQ_VSI_PVLAN_INSERT_PVID 0x04 278 #define IAVF_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 279 #define IAVF_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 280 IAVF_AQ_VSI_PVLAN_EMOD_SHIFT) 281 #define IAVF_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 282 #define IAVF_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 283 #define IAVF_AQ_VSI_PVLAN_EMOD_STR 0x10 284 #define IAVF_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 285 u8 pvlan_reserved[3]; 286 /* ingress egress up sections */ 287 __le32 ingress_table; /* bitmap, 3 bits per up */ 288 #define IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT 0 289 #define IAVF_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 290 IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT) 291 #define IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT 3 292 #define IAVF_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 293 IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT) 294 #define IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT 6 295 #define IAVF_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 296 IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT) 297 #define IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT 9 298 #define IAVF_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 299 IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT) 300 #define IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT 12 301 #define IAVF_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 302 IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT) 303 #define IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT 15 304 #define IAVF_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 305 IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT) 306 #define IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT 18 307 #define IAVF_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 308 IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT) 309 #define IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT 21 310 #define IAVF_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 311 IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT) 312 __le32 egress_table; /* same defines as for ingress table */ 313 /* cascaded PV section */ 314 __le16 cas_pv_tag; 315 u8 cas_pv_flags; 316 #define IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 317 #define IAVF_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 318 IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT) 319 #define IAVF_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 320 #define IAVF_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 321 #define IAVF_AQ_VSI_CAS_PV_TAGX_COPY 0x02 322 #define IAVF_AQ_VSI_CAS_PV_INSERT_TAG 0x10 323 #define IAVF_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 324 #define IAVF_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 325 u8 cas_pv_reserved; 326 /* queue mapping section */ 327 __le16 mapping_flags; 328 #define IAVF_AQ_VSI_QUE_MAP_CONTIG 0x0 329 #define IAVF_AQ_VSI_QUE_MAP_NONCONTIG 0x1 330 __le16 queue_mapping[16]; 331 #define IAVF_AQ_VSI_QUEUE_SHIFT 0x0 332 #define IAVF_AQ_VSI_QUEUE_MASK (0x7FF << IAVF_AQ_VSI_QUEUE_SHIFT) 333 __le16 tc_mapping[8]; 334 #define IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 335 #define IAVF_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 336 IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT) 337 #define IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 338 #define IAVF_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 339 IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT) 340 /* queueing option section */ 341 u8 queueing_opt_flags; 342 #define IAVF_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 343 #define IAVF_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 344 #define IAVF_AQ_VSI_QUE_OPT_TCP_ENA 0x10 345 #define IAVF_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 346 #define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 347 #define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 348 u8 queueing_opt_reserved[3]; 349 /* scheduler section */ 350 u8 up_enable_bits; 351 u8 sched_reserved; 352 /* outer up section */ 353 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 354 u8 cmd_reserved[8]; 355 /* last 32 bytes are written by FW */ 356 __le16 qs_handle[8]; 357 #define IAVF_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 358 __le16 stat_counter_idx; 359 __le16 sched_id; 360 u8 resp_reserved[12]; 361 }; 362 363 IAVF_CHECK_STRUCT_LEN(128, iavf_aqc_vsi_properties_data); 364 365 /* Get VEB Parameters (direct 0x0232) 366 * uses iavf_aqc_switch_seid for the descriptor 367 */ 368 struct iavf_aqc_get_veb_parameters_completion { 369 __le16 seid; 370 __le16 switch_id; 371 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 372 __le16 statistic_index; 373 __le16 vebs_used; 374 __le16 vebs_free; 375 u8 reserved[4]; 376 }; 377 378 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion); 379 380 #define IAVF_LINK_SPEED_100MB_SHIFT 0x1 381 #define IAVF_LINK_SPEED_1000MB_SHIFT 0x2 382 #define IAVF_LINK_SPEED_10GB_SHIFT 0x3 383 #define IAVF_LINK_SPEED_40GB_SHIFT 0x4 384 #define IAVF_LINK_SPEED_20GB_SHIFT 0x5 385 #define IAVF_LINK_SPEED_25GB_SHIFT 0x6 386 387 enum iavf_aq_link_speed { 388 IAVF_LINK_SPEED_UNKNOWN = 0, 389 IAVF_LINK_SPEED_100MB = BIT(IAVF_LINK_SPEED_100MB_SHIFT), 390 IAVF_LINK_SPEED_1GB = BIT(IAVF_LINK_SPEED_1000MB_SHIFT), 391 IAVF_LINK_SPEED_10GB = BIT(IAVF_LINK_SPEED_10GB_SHIFT), 392 IAVF_LINK_SPEED_40GB = BIT(IAVF_LINK_SPEED_40GB_SHIFT), 393 IAVF_LINK_SPEED_20GB = BIT(IAVF_LINK_SPEED_20GB_SHIFT), 394 IAVF_LINK_SPEED_25GB = BIT(IAVF_LINK_SPEED_25GB_SHIFT), 395 }; 396 397 /* Send to PF command (indirect 0x0801) id is only used by PF 398 * Send to VF command (indirect 0x0802) id is only used by PF 399 * Send to Peer PF command (indirect 0x0803) 400 */ 401 struct iavf_aqc_pf_vf_message { 402 __le32 id; 403 u8 reserved[4]; 404 __le32 addr_high; 405 __le32 addr_low; 406 }; 407 408 IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message); 409 410 struct iavf_aqc_get_set_rss_key { 411 #define IAVF_AQC_SET_RSS_KEY_VSI_VALID BIT(15) 412 #define IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 413 #define IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 414 IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 415 __le16 vsi_id; 416 u8 reserved[6]; 417 __le32 addr_high; 418 __le32 addr_low; 419 }; 420 421 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_key); 422 423 struct iavf_aqc_get_set_rss_key_data { 424 u8 standard_rss_key[0x28]; 425 u8 extended_hash_key[0xc]; 426 }; 427 428 IAVF_CHECK_STRUCT_LEN(0x34, iavf_aqc_get_set_rss_key_data); 429 430 struct iavf_aqc_get_set_rss_lut { 431 #define IAVF_AQC_SET_RSS_LUT_VSI_VALID BIT(15) 432 #define IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 433 #define IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 434 IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 435 __le16 vsi_id; 436 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 437 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \ 438 BIT(IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 439 440 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 441 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 442 __le16 flags; 443 u8 reserved[4]; 444 __le32 addr_high; 445 __le32 addr_low; 446 }; 447 448 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_lut); 449 #endif /* _IAVF_ADMINQ_CMD_H_ */ 450