xref: /linux/drivers/hid/intel-thc-hid/intel-quicki2c/quicki2c-dev.h (revision 32d27cf535ead3b10e926c76dc5b6301920328b0)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2024 Intel Corporation */
3 
4 #ifndef _QUICKI2C_DEV_H_
5 #define _QUICKI2C_DEV_H_
6 
7 #include <linux/hid-over-i2c.h>
8 #include <linux/workqueue.h>
9 
10 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_I2C_PORT1		0xA848
11 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_I2C_PORT2		0xA84A
12 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_I2C_PORT1	0xE348
13 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_I2C_PORT2	0xE34A
14 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_I2C_PORT1	0xE448
15 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_I2C_PORT2	0xE44A
16 #define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_I2C_PORT1 	0x4D48
17 #define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_I2C_PORT2 	0x4D4A
18 
19 /* Packet size value, the unit is 16 bytes */
20 #define MAX_PACKET_SIZE_VALUE_LNL			256
21 
22 /* HIDI2C special ACPI parameters DSD name */
23 #define QUICKI2C_ACPI_METHOD_NAME_ICRS		"ICRS"
24 #define QUICKI2C_ACPI_METHOD_NAME_ISUB		"ISUB"
25 
26 /* HIDI2C special ACPI parameters DSM methods */
27 #define QUICKI2C_ACPI_REVISION_NUM		1
28 #define QUICKI2C_ACPI_FUNC_NUM_HID_DESC_ADDR	1
29 #define QUICKI2C_ACPI_FUNC_NUM_ACTIVE_LTR_VAL	1
30 #define QUICKI2C_ACPI_FUNC_NUM_LP_LTR_VAL	2
31 
32 #define QUICKI2C_SUBIP_STANDARD_MODE_MAX_SPEED		100000
33 #define QUICKI2C_SUBIP_FAST_MODE_MAX_SPEED		400000
34 #define QUICKI2C_SUBIP_FASTPLUS_MODE_MAX_SPEED		1000000
35 #define QUICKI2C_SUBIP_HIGH_SPEED_MODE_MAX_SPEED	3400000
36 
37 #define QUICKI2C_DEFAULT_ACTIVE_LTR_VALUE	5
38 #define QUICKI2C_DEFAULT_LP_LTR_VALUE		500
39 #define QUICKI2C_RPM_TIMEOUT_MS			500
40 
41 /* PTL Max packet size detection capability is 255 Bytes */
42 #define MAX_RX_DETECT_SIZE_PTL			255
43 
44 /* Default interrupt delay is 1ms, suitable for most devices */
45 #define DEFAULT_INTERRUPT_DELAY_US		(1 * USEC_PER_MSEC)
46 
47 /*
48  * THC uses runtime auto suspend to dynamically switch between THC active LTR
49  * and low power LTR to save CPU power.
50  * Default value is 5000ms, that means if no touch event in this time, THC will
51  * change to low power LTR mode.
52  */
53 #define DEFAULT_AUTO_SUSPEND_DELAY_MS			5000
54 
55 enum quicki2c_dev_state {
56 	QUICKI2C_NONE,
57 	QUICKI2C_RESETING,
58 	QUICKI2C_RESETED,
59 	QUICKI2C_INITED,
60 	QUICKI2C_ENABLED,
61 	QUICKI2C_DISABLED,
62 };
63 
64 enum {
65 	HIDI2C_ADDRESSING_MODE_7BIT,
66 	HIDI2C_ADDRESSING_MODE_10BIT,
67 };
68 
69 /**
70  * struct quicki2c_subip_acpi_parameter - QuickI2C ACPI DSD parameters
71  * @device_address: I2C device slave address
72  * @connection_speed: I2C device expected connection speed
73  * @addressing_mode: I2C device slave address mode, 7bit or 10bit
74  *
75  * Those properties get from QUICKI2C_ACPI_METHOD_NAME_ICRS method, used for
76  * Bus parameter.
77  */
78 struct quicki2c_subip_acpi_parameter {
79 	u16 device_address;
80 	u64 connection_speed;
81 	u8 addressing_mode;
82 	u8 reserved;
83 } __packed;
84 
85 /**
86  * struct quicki2c_subip_acpi_config - QuickI2C ACPI DSD parameters
87  * @SMHX: Standard Mode (100 kbit/s) Serial Clock Line HIGH Period
88  * @SMLX: Standard Mode (100 kbit/s) Serial Clock Line LOW Period
89  * @SMTD: Standard Mode (100 kbit/s) Serial Data Line Transmit Hold Period
90  * @SMRD: Standard Mode (100 kbit/s) Serial Data Receive Hold Period
91  * @FMHX: Fast Mode (400 kbit/s) Serial Clock Line HIGH Period
92  * @FMLX: Fast Mode (400 kbit/s) Serial Clock Line LOW Period
93  * @FMTD: Fast Mode (400 kbit/s) Serial Data Line Transmit Hold Period
94  * @FMRD: Fast Mode (400 kbit/s) Serial Data Line Receive Hold Period
95  * @FMSL: Maximum length (in ic_clk_cycles) of suppressed spikes
96  *        in Standard Mode, Fast Mode and Fast Mode Plus
97  * @FPHX: Fast Mode Plus (1Mbit/sec) Serial Clock Line HIGH Period
98  * @FPLX: Fast Mode Plus (1Mbit/sec) Serial Clock Line LOW Period
99  * @FPTD: Fast Mode Plus (1Mbit/sec) Serial Data Line Transmit HOLD Period
100  * @FPRD: Fast Mode Plus (1Mbit/sec) Serial Data Line Receive HOLD Period
101  * @HMHX: High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line HIGH Period
102  * @HMLX: High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line LOW Period
103  * @HMTD: High Speed Mode Plus (3.4Mbits/sec) Serial Data Line Transmit HOLD Period
104  * @HMRD: High Speed Mode Plus (3.4Mbits/sec) Serial Data Line Receive HOLD Period
105  * @HMSL: Maximum length (in ic_clk_cycles) of suppressed spikes in High Speed Mode
106  *
107  * Those properties get from QUICKI2C_ACPI_METHOD_NAME_ISUB method, used for
108  * I2C timing configure.
109  */
110 struct quicki2c_subip_acpi_config {
111 	u64 SMHX;
112 	u64 SMLX;
113 	u64 SMTD;
114 	u64 SMRD;
115 
116 	u64 FMHX;
117 	u64 FMLX;
118 	u64 FMTD;
119 	u64 FMRD;
120 	u64 FMSL;
121 
122 	u64 FPHX;
123 	u64 FPLX;
124 	u64 FPTD;
125 	u64 FPRD;
126 
127 	u64 HMHX;
128 	u64 HMLX;
129 	u64 HMTD;
130 	u64 HMRD;
131 	u64 HMSL;
132 	u8 reserved;
133 };
134 
135 /**
136  * struct quicki2c_ddata - Driver specific data for quicki2c device
137  * @max_detect_size: Identify max packet size detect for rx
138  * @interrupt_delay: Identify interrupt detect delay for rx
139  */
140 struct quicki2c_ddata {
141 	u32 max_detect_size;
142 	u32 interrupt_delay;
143 };
144 
145 struct device;
146 struct pci_dev;
147 struct thc_device;
148 struct hid_device;
149 struct acpi_device;
150 
151 /**
152  * struct quicki2c_device -  THC QuickI2C device struct
153  * @dev: Point to kernel device
154  * @pdev: Point to PCI device
155  * @thc_hw: Point to THC device
156  * @hid_dev: Point to HID device
157  * @acpi_dev: Point to ACPI device
158  * @ddata: Point to QuickI2C platform specific driver data
159  * @state: THC I2C device state
160  * @mem_addr: MMIO memory address
161  * @dev_desc: Device descriptor for HIDI2C protocol
162  * @i2c_slave_addr: HIDI2C device slave address
163  * @hid_desc_addr: Register address for retrieve HID device descriptor
164  * @active_ltr_val: THC active LTR value
165  * @low_power_ltr_val: THC low power LTR value
166  * @i2c_speed_mode: 0 - standard mode, 1 - fast mode, 2 - fast mode plus
167  * @i2c_clock_hcnt: I2C CLK high period time (unit in cycle count)
168  * @i2c_clock_lcnt: I2C CLK low period time (unit in cycle count)
169  * @report_descriptor: Store a copy of device report descriptor
170  * @input_buf: Store a copy of latest input report data
171  * @report_buf: Store a copy of latest input/output report packet from set/get feature
172  * @report_len: The length of input/output report packet
173  * @reset_ack_wq: Workqueue for waiting reset response from device
174  * @reset_ack: Indicate reset response received or not
175  */
176 struct quicki2c_device {
177 	struct device *dev;
178 	struct pci_dev *pdev;
179 	struct thc_device *thc_hw;
180 	struct hid_device *hid_dev;
181 	struct acpi_device *acpi_dev;
182 	const struct quicki2c_ddata *ddata;
183 	enum quicki2c_dev_state state;
184 
185 	void __iomem *mem_addr;
186 
187 	struct hidi2c_dev_descriptor dev_desc;
188 	u8 i2c_slave_addr;
189 	u16 hid_desc_addr;
190 
191 	u32 active_ltr_val;
192 	u32 low_power_ltr_val;
193 
194 	u32 i2c_speed_mode;
195 	u32 i2c_clock_hcnt;
196 	u32 i2c_clock_lcnt;
197 
198 	u8 *report_descriptor;
199 	u8 *input_buf;
200 	u8 *report_buf;
201 	u32 report_len;
202 
203 	wait_queue_head_t reset_ack_wq;
204 	bool reset_ack;
205 };
206 
207 #endif /* _QUICKI2C_DEV_H_ */
208