1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * i2c_adap_pxa.c
4 *
5 * I2C adapter for the PXA I2C bus access.
6 *
7 * Copyright (C) 2002 Intrinsyc Software Inc.
8 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 *
10 * History:
11 * Apr 2002: Initial version [CS]
12 * Jun 2002: Properly separated algo/adap [FB]
13 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
14 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
15 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
16 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
17 * Feb 2005: Rework slave mode handling [RMK]
18 */
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/errno.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/i2c.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/platform_device.h>
34 #include <linux/platform_data/i2c-pxa.h>
35 #include <linux/property.h>
36 #include <linux/slab.h>
37
38 /* I2C register field definitions */
39 #define IBMR_SDAS (1 << 0)
40 #define IBMR_SCLS (1 << 1)
41
42 #define ICR_START (1 << 0) /* start bit */
43 #define ICR_STOP (1 << 1) /* stop bit */
44 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
45 #define ICR_TB (1 << 3) /* transfer byte bit */
46 #define ICR_MA (1 << 4) /* master abort */
47 #define ICR_SCLE (1 << 5) /* master clock enable */
48 #define ICR_IUE (1 << 6) /* unit enable */
49 #define ICR_GCD (1 << 7) /* general call disable */
50 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
51 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
52 #define ICR_BEIE (1 << 10) /* enable bus error ints */
53 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
54 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
55 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
56 #define ICR_UR (1 << 14) /* unit reset */
57 #define ICR_FM (1 << 15) /* fast mode */
58 #define ICR_HS (1 << 16) /* High Speed mode */
59 #define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
60 #define ICR_A3700_HS (1 << 17) /* high speed mode for armada-3700 */
61 #define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
62
63 #define ISR_RWM (1 << 0) /* read/write mode */
64 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
65 #define ISR_UB (1 << 2) /* unit busy */
66 #define ISR_IBB (1 << 3) /* bus busy */
67 #define ISR_SSD (1 << 4) /* slave stop detected */
68 #define ISR_ALD (1 << 5) /* arbitration loss detected */
69 #define ISR_ITE (1 << 6) /* tx buffer empty */
70 #define ISR_IRF (1 << 7) /* rx buffer full */
71 #define ISR_GCAD (1 << 8) /* general call address detected */
72 #define ISR_SAD (1 << 9) /* slave address detected */
73 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
74
75 #define ILCR_SLV_SHIFT 0
76 #define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
77 #define ILCR_FLV_SHIFT 9
78 #define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
79 #define ILCR_HLVL_SHIFT 18
80 #define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
81 #define ILCR_HLVH_SHIFT 27
82 #define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
83
84 #define IWCR_CNT_SHIFT 0
85 #define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
86 #define IWCR_HS_CNT1_SHIFT 5
87 #define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
88 #define IWCR_HS_CNT2_SHIFT 10
89 #define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
90
91 /* need a longer timeout if we're dealing with the fact we may well be
92 * looking at a multi-master environment
93 */
94 #define DEF_TIMEOUT 32
95
96 #define NO_SLAVE (-ENXIO)
97 #define BUS_ERROR (-EREMOTEIO)
98 #define XFER_NAKED (-ECONNREFUSED)
99 #define I2C_RETRY (-2000) /* an error has occurred retry transmit */
100
101 /* ICR initialize bit values
102 *
103 * 15 FM 0 (100 kHz operation)
104 * 14 UR 0 (No unit reset)
105 * 13 SADIE 0 (Disables the unit from interrupting on slave addresses
106 * matching its slave address)
107 * 12 ALDIE 0 (Disables the unit from interrupt when it loses arbitration
108 * in master mode)
109 * 11 SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
110 * 10 BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
111 * 9 IRFIE 1 (Enable interrupts from full buffer received)
112 * 8 ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
113 * 7 GCD 1 (Disables i2c unit response to general call messages as a slave)
114 * 6 IUE 0 (Disable unit until we change settings)
115 * 5 SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
116 * 4 MA 0 (Only send stop with the ICR stop bit)
117 * 3 TB 0 (We are not transmitting a byte initially)
118 * 2 ACKNAK 0 (Send an ACK after the unit receives a byte)
119 * 1 STOP 0 (Do not send a STOP)
120 * 0 START 0 (Do not send a START)
121 */
122 #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
123
124 /* I2C status register init values
125 *
126 * 10 BED 1 (Clear bus error detected)
127 * 9 SAD 1 (Clear slave address detected)
128 * 7 IRF 1 (Clear IDBR Receive Full)
129 * 6 ITE 1 (Clear IDBR Transmit Empty)
130 * 5 ALD 1 (Clear Arbitration Loss Detected)
131 * 4 SSD 1 (Clear Slave Stop Detected)
132 */
133 #define I2C_ISR_INIT 0x7FF /* status register init */
134
135 struct pxa_reg_layout {
136 u32 ibmr;
137 u32 idbr;
138 u32 icr;
139 u32 isr;
140 u32 isar;
141 u32 ilcr;
142 u32 iwcr;
143 u32 fm;
144 u32 hs;
145 };
146
147 enum pxa_i2c_types {
148 REGS_PXA2XX,
149 REGS_PXA3XX,
150 REGS_CE4100,
151 REGS_PXA910,
152 REGS_A3700,
153 };
154
155 /* I2C register layout definitions */
156 static struct pxa_reg_layout pxa_reg_layout[] = {
157 [REGS_PXA2XX] = {
158 .ibmr = 0x00,
159 .idbr = 0x08,
160 .icr = 0x10,
161 .isr = 0x18,
162 .isar = 0x20,
163 .fm = ICR_FM,
164 .hs = ICR_HS,
165 },
166 [REGS_PXA3XX] = {
167 .ibmr = 0x00,
168 .idbr = 0x04,
169 .icr = 0x08,
170 .isr = 0x0c,
171 .isar = 0x10,
172 .fm = ICR_FM,
173 .hs = ICR_HS,
174 },
175 [REGS_CE4100] = {
176 .ibmr = 0x14,
177 .idbr = 0x0c,
178 .icr = 0x00,
179 .isr = 0x04,
180 /* no isar register */
181 .fm = ICR_FM,
182 .hs = ICR_HS,
183 },
184 [REGS_PXA910] = {
185 .ibmr = 0x00,
186 .idbr = 0x08,
187 .icr = 0x10,
188 .isr = 0x18,
189 .isar = 0x20,
190 .ilcr = 0x28,
191 .iwcr = 0x30,
192 .fm = ICR_FM,
193 .hs = ICR_HS,
194 },
195 [REGS_A3700] = {
196 .ibmr = 0x00,
197 .idbr = 0x04,
198 .icr = 0x08,
199 .isr = 0x0c,
200 .isar = 0x10,
201 .fm = ICR_A3700_FM,
202 .hs = ICR_A3700_HS,
203 },
204 };
205
206 static const struct of_device_id i2c_pxa_dt_ids[] = {
207 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
208 { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
209 { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
210 { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
211 {}
212 };
213 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
214
215 static const struct platform_device_id i2c_pxa_id_table[] = {
216 { "pxa2xx-i2c", REGS_PXA2XX },
217 { "pxa3xx-pwri2c", REGS_PXA3XX },
218 { "ce4100-i2c", REGS_CE4100 },
219 { "pxa910-i2c", REGS_PXA910 },
220 { "armada-3700-i2c", REGS_A3700 },
221 { }
222 };
223 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
224
225 struct pxa_i2c {
226 spinlock_t lock;
227 wait_queue_head_t wait;
228 struct i2c_msg *msg;
229 unsigned int msg_num;
230 unsigned int msg_idx;
231 unsigned int msg_ptr;
232 unsigned int slave_addr;
233 unsigned int req_slave_addr;
234
235 struct i2c_adapter adap;
236 struct clk *clk;
237 #ifdef CONFIG_I2C_PXA_SLAVE
238 struct i2c_client *slave;
239 #endif
240
241 unsigned int irqlogidx;
242 u32 isrlog[32];
243 u32 icrlog[32];
244
245 void __iomem *reg_base;
246 void __iomem *reg_ibmr;
247 void __iomem *reg_idbr;
248 void __iomem *reg_icr;
249 void __iomem *reg_isr;
250 void __iomem *reg_isar;
251 void __iomem *reg_ilcr;
252 void __iomem *reg_iwcr;
253
254 unsigned long iobase;
255 unsigned long iosize;
256
257 int irq;
258 unsigned int use_pio :1;
259 unsigned int fast_mode :1;
260 unsigned int high_mode:1;
261 unsigned char master_code;
262 unsigned long rate;
263 bool highmode_enter;
264 u32 fm_mask;
265 u32 hs_mask;
266
267 struct i2c_bus_recovery_info recovery;
268 struct pinctrl *pinctrl;
269 struct pinctrl_state *pinctrl_default;
270 struct pinctrl_state *pinctrl_recovery;
271 bool reset_before_xfer;
272 };
273
274 #define _IBMR(i2c) ((i2c)->reg_ibmr)
275 #define _IDBR(i2c) ((i2c)->reg_idbr)
276 #define _ICR(i2c) ((i2c)->reg_icr)
277 #define _ISR(i2c) ((i2c)->reg_isr)
278 #define _ISAR(i2c) ((i2c)->reg_isar)
279 #define _ILCR(i2c) ((i2c)->reg_ilcr)
280 #define _IWCR(i2c) ((i2c)->reg_iwcr)
281
282 /*
283 * I2C Slave mode address
284 */
285 #define I2C_PXA_SLAVE_ADDR 0x1
286
287 #ifdef DEBUG
288
289 struct bits {
290 u32 mask;
291 const char *set;
292 const char *unset;
293 };
294 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
295
296 static inline void
decode_bits(const char * prefix,const struct bits * bits,int num,u32 val)297 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
298 {
299 printk("%s %08x:", prefix, val);
300 while (num--) {
301 const char *str = val & bits->mask ? bits->set : bits->unset;
302 if (str)
303 pr_cont(" %s", str);
304 bits++;
305 }
306 pr_cont("\n");
307 }
308
309 static const struct bits isr_bits[] = {
310 PXA_BIT(ISR_RWM, "RX", "TX"),
311 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
312 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
313 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
314 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
315 PXA_BIT(ISR_ALD, "ALD", NULL),
316 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
317 PXA_BIT(ISR_IRF, "RxFull", NULL),
318 PXA_BIT(ISR_GCAD, "GenCall", NULL),
319 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
320 PXA_BIT(ISR_BED, "BusErr", NULL),
321 };
322
decode_ISR(unsigned int val)323 static void decode_ISR(unsigned int val)
324 {
325 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
326 }
327
328 #ifdef CONFIG_I2C_PXA_SLAVE
329 static const struct bits icr_bits[] = {
330 PXA_BIT(ICR_START, "START", NULL),
331 PXA_BIT(ICR_STOP, "STOP", NULL),
332 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
333 PXA_BIT(ICR_TB, "TB", NULL),
334 PXA_BIT(ICR_MA, "MA", NULL),
335 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
336 PXA_BIT(ICR_IUE, "IUE", "iue"),
337 PXA_BIT(ICR_GCD, "GCD", NULL),
338 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
339 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
340 PXA_BIT(ICR_BEIE, "BEIE", NULL),
341 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
342 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
343 PXA_BIT(ICR_SADIE, "SADIE", NULL),
344 PXA_BIT(ICR_UR, "UR", "ur"),
345 };
346
decode_ICR(unsigned int val)347 static void decode_ICR(unsigned int val)
348 {
349 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
350 }
351 #endif
352
353 static unsigned int i2c_debug = DEBUG;
354
i2c_pxa_show_state(struct pxa_i2c * i2c,int lno,const char * fname)355 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
356 {
357 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
358 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
359 }
360
361 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
362
i2c_pxa_scream_blue_murder(struct pxa_i2c * i2c,const char * why)363 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
364 {
365 unsigned int i;
366 struct device *dev = &i2c->adap.dev;
367
368 dev_err(dev, "slave_0x%x error: %s\n",
369 i2c->req_slave_addr >> 1, why);
370 dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
371 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
372 dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
373 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
374 readl(_ISR(i2c)));
375 dev_err(dev, "log:");
376 for (i = 0; i < i2c->irqlogidx; i++)
377 pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
378 pr_cont("\n");
379 }
380
381 #else /* ifdef DEBUG */
382
383 #define i2c_debug 0
384
385 #define show_state(i2c) do { } while (0)
386 #define decode_ISR(val) do { } while (0)
387 #define decode_ICR(val) do { } while (0)
388 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
389
390 #endif /* ifdef DEBUG / else */
391
392 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
393
i2c_pxa_is_slavemode(struct pxa_i2c * i2c)394 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
395 {
396 return !(readl(_ICR(i2c)) & ICR_SCLE);
397 }
398
i2c_pxa_abort(struct pxa_i2c * i2c)399 static void i2c_pxa_abort(struct pxa_i2c *i2c)
400 {
401 int i = 250;
402
403 if (i2c_pxa_is_slavemode(i2c)) {
404 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
405 return;
406 }
407
408 while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) {
409 unsigned long icr = readl(_ICR(i2c));
410
411 icr &= ~ICR_START;
412 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
413
414 writel(icr, _ICR(i2c));
415
416 show_state(i2c);
417
418 mdelay(1);
419 i --;
420 }
421
422 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
423 _ICR(i2c));
424 }
425
i2c_pxa_wait_bus_not_busy(struct pxa_i2c * i2c)426 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
427 {
428 int timeout = DEF_TIMEOUT;
429 u32 isr;
430
431 while (1) {
432 isr = readl(_ISR(i2c));
433 if (!(isr & (ISR_IBB | ISR_UB)))
434 return 0;
435
436 if (isr & ISR_SAD)
437 timeout += 4;
438
439 if (!timeout--)
440 break;
441
442 msleep(2);
443 show_state(i2c);
444 }
445
446 show_state(i2c);
447
448 return I2C_RETRY;
449 }
450
i2c_pxa_wait_master(struct pxa_i2c * i2c)451 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
452 {
453 unsigned long timeout = jiffies + HZ*4;
454
455 while (time_before(jiffies, timeout)) {
456 if (i2c_debug > 1)
457 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
458 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
459
460 if (readl(_ISR(i2c)) & ISR_SAD) {
461 if (i2c_debug > 0)
462 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
463 goto out;
464 }
465
466 /* wait for unit and bus being not busy, and we also do a
467 * quick check of the i2c lines themselves to ensure they've
468 * gone high...
469 */
470 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 &&
471 readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) {
472 if (i2c_debug > 0)
473 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
474 return 1;
475 }
476
477 msleep(1);
478 }
479
480 if (i2c_debug > 0)
481 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
482 out:
483 return 0;
484 }
485
i2c_pxa_set_master(struct pxa_i2c * i2c)486 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
487 {
488 if (i2c_debug)
489 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
490
491 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
492 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
493 if (!i2c_pxa_wait_master(i2c)) {
494 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
495 return I2C_RETRY;
496 }
497 }
498
499 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
500 return 0;
501 }
502
503 #ifdef CONFIG_I2C_PXA_SLAVE
i2c_pxa_wait_slave(struct pxa_i2c * i2c)504 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
505 {
506 unsigned long timeout = jiffies + HZ*1;
507
508 /* wait for stop */
509
510 show_state(i2c);
511
512 while (time_before(jiffies, timeout)) {
513 if (i2c_debug > 1)
514 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
515 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
516
517 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
518 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
519 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
520 if (i2c_debug > 1)
521 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
522 return 1;
523 }
524
525 msleep(1);
526 }
527
528 if (i2c_debug > 0)
529 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
530 return 0;
531 }
532
533 /*
534 * clear the hold on the bus, and take of anything else
535 * that has been configured
536 */
i2c_pxa_set_slave(struct pxa_i2c * i2c,int errcode)537 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
538 {
539 show_state(i2c);
540
541 if (errcode < 0) {
542 udelay(100); /* simple delay */
543 } else {
544 /* we need to wait for the stop condition to end */
545
546 /* if we where in stop, then clear... */
547 if (readl(_ICR(i2c)) & ICR_STOP) {
548 udelay(100);
549 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
550 }
551
552 if (!i2c_pxa_wait_slave(i2c)) {
553 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
554 __func__);
555 return;
556 }
557 }
558
559 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
560 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
561
562 if (i2c_debug) {
563 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
564 decode_ICR(readl(_ICR(i2c)));
565 }
566 }
567 #else
568 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
569 #endif
570
i2c_pxa_do_reset(struct pxa_i2c * i2c)571 static void i2c_pxa_do_reset(struct pxa_i2c *i2c)
572 {
573 /* reset according to 9.8 */
574 writel(ICR_UR, _ICR(i2c));
575 writel(I2C_ISR_INIT, _ISR(i2c));
576 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
577
578 if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
579 writel(i2c->slave_addr, _ISAR(i2c));
580
581 /* set control register values */
582 writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
583 writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
584
585 #ifdef CONFIG_I2C_PXA_SLAVE
586 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
587 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
588 #endif
589
590 i2c_pxa_set_slave(i2c, 0);
591 }
592
i2c_pxa_enable(struct pxa_i2c * i2c)593 static void i2c_pxa_enable(struct pxa_i2c *i2c)
594 {
595 /* enable unit */
596 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
597 udelay(100);
598 }
599
i2c_pxa_reset(struct pxa_i2c * i2c)600 static void i2c_pxa_reset(struct pxa_i2c *i2c)
601 {
602 pr_debug("Resetting I2C Controller Unit\n");
603
604 /* abort any transfer currently under way */
605 i2c_pxa_abort(i2c);
606 i2c_pxa_do_reset(i2c);
607 i2c_pxa_enable(i2c);
608 }
609
610
611 #ifdef CONFIG_I2C_PXA_SLAVE
612 /*
613 * PXA I2C Slave mode
614 */
615
i2c_pxa_slave_txempty(struct pxa_i2c * i2c,u32 isr)616 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
617 {
618 if (isr & ISR_BED) {
619 /* what should we do here? */
620 } else {
621 u8 byte = 0;
622
623 if (i2c->slave != NULL)
624 i2c_slave_event(i2c->slave, I2C_SLAVE_READ_PROCESSED,
625 &byte);
626
627 writel(byte, _IDBR(i2c));
628 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
629 }
630 }
631
i2c_pxa_slave_rxfull(struct pxa_i2c * i2c,u32 isr)632 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
633 {
634 u8 byte = readl(_IDBR(i2c));
635
636 if (i2c->slave != NULL)
637 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_RECEIVED, &byte);
638
639 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
640 }
641
i2c_pxa_slave_start(struct pxa_i2c * i2c,u32 isr)642 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
643 {
644 int timeout;
645
646 if (i2c_debug > 0)
647 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
648 (isr & ISR_RWM) ? 'r' : 't');
649
650 if (i2c->slave != NULL) {
651 if (isr & ISR_RWM) {
652 u8 byte = 0;
653
654 i2c_slave_event(i2c->slave, I2C_SLAVE_READ_REQUESTED,
655 &byte);
656 writel(byte, _IDBR(i2c));
657 } else {
658 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_REQUESTED,
659 NULL);
660 }
661 }
662
663 /*
664 * slave could interrupt in the middle of us generating a
665 * start condition... if this happens, we'd better back off
666 * and stop holding the poor thing up
667 */
668 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
669 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
670
671 timeout = 0x10000;
672
673 while (1) {
674 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
675 break;
676
677 timeout--;
678
679 if (timeout <= 0) {
680 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
681 break;
682 }
683 }
684
685 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
686 }
687
i2c_pxa_slave_stop(struct pxa_i2c * i2c)688 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
689 {
690 if (i2c_debug > 2)
691 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
692
693 if (i2c->slave != NULL)
694 i2c_slave_event(i2c->slave, I2C_SLAVE_STOP, NULL);
695
696 if (i2c_debug > 2)
697 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
698
699 /*
700 * If we have a master-mode message waiting,
701 * kick it off now that the slave has completed.
702 */
703 if (i2c->msg)
704 i2c_pxa_master_complete(i2c, I2C_RETRY);
705 }
706
i2c_pxa_slave_reg(struct i2c_client * slave)707 static int i2c_pxa_slave_reg(struct i2c_client *slave)
708 {
709 struct pxa_i2c *i2c = slave->adapter->algo_data;
710
711 if (i2c->slave)
712 return -EBUSY;
713
714 if (!i2c->reg_isar)
715 return -EAFNOSUPPORT;
716
717 i2c->slave = slave;
718 i2c->slave_addr = slave->addr;
719
720 writel(i2c->slave_addr, _ISAR(i2c));
721
722 return 0;
723 }
724
i2c_pxa_slave_unreg(struct i2c_client * slave)725 static int i2c_pxa_slave_unreg(struct i2c_client *slave)
726 {
727 struct pxa_i2c *i2c = slave->adapter->algo_data;
728
729 WARN_ON(!i2c->slave);
730
731 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
732 writel(i2c->slave_addr, _ISAR(i2c));
733
734 i2c->slave = NULL;
735
736 return 0;
737 }
738 #else
i2c_pxa_slave_txempty(struct pxa_i2c * i2c,u32 isr)739 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
740 {
741 if (isr & ISR_BED) {
742 /* what should we do here? */
743 } else {
744 writel(0, _IDBR(i2c));
745 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
746 }
747 }
748
i2c_pxa_slave_rxfull(struct pxa_i2c * i2c,u32 isr)749 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
750 {
751 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
752 }
753
i2c_pxa_slave_start(struct pxa_i2c * i2c,u32 isr)754 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
755 {
756 int timeout;
757
758 /*
759 * slave could interrupt in the middle of us generating a
760 * start condition... if this happens, we'd better back off
761 * and stop holding the poor thing up
762 */
763 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
764 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
765
766 timeout = 0x10000;
767
768 while (1) {
769 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
770 break;
771
772 timeout--;
773
774 if (timeout <= 0) {
775 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
776 break;
777 }
778 }
779
780 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
781 }
782
i2c_pxa_slave_stop(struct pxa_i2c * i2c)783 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
784 {
785 if (i2c->msg)
786 i2c_pxa_master_complete(i2c, I2C_RETRY);
787 }
788 #endif
789
790 /*
791 * PXA I2C Master mode
792 */
793
i2c_pxa_start_message(struct pxa_i2c * i2c)794 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
795 {
796 u32 icr;
797
798 /*
799 * Step 1: target slave address into IDBR
800 */
801 i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
802 writel(i2c->req_slave_addr, _IDBR(i2c));
803
804 /*
805 * Step 2: initiate the write.
806 */
807 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
808 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
809 }
810
i2c_pxa_stop_message(struct pxa_i2c * i2c)811 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
812 {
813 u32 icr;
814
815 /* Clear the START, STOP, ACK, TB and MA flags */
816 icr = readl(_ICR(i2c));
817 icr &= ~(ICR_START | ICR_STOP | ICR_ACKNAK | ICR_TB | ICR_MA);
818 writel(icr, _ICR(i2c));
819 }
820
821 /*
822 * PXA I2C send master code
823 * 1. Load master code to IDBR and send it.
824 * Note for HS mode, set ICR [GPIOEN].
825 * 2. Wait until win arbitration.
826 */
i2c_pxa_send_mastercode(struct pxa_i2c * i2c)827 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
828 {
829 u32 icr;
830 long time_left;
831
832 spin_lock_irq(&i2c->lock);
833 i2c->highmode_enter = true;
834 writel(i2c->master_code, _IDBR(i2c));
835
836 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
837 icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
838 writel(icr, _ICR(i2c));
839
840 spin_unlock_irq(&i2c->lock);
841 time_left = wait_event_timeout(i2c->wait,
842 i2c->highmode_enter == false, HZ * 1);
843
844 i2c->highmode_enter = false;
845
846 return (time_left == 0) ? I2C_RETRY : 0;
847 }
848
849 /*
850 * i2c_pxa_master_complete - complete the message and wake up.
851 */
i2c_pxa_master_complete(struct pxa_i2c * i2c,int ret)852 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
853 {
854 i2c->msg_ptr = 0;
855 i2c->msg = NULL;
856 i2c->msg_idx ++;
857 i2c->msg_num = 0;
858 if (ret)
859 i2c->msg_idx = ret;
860 if (!i2c->use_pio)
861 wake_up(&i2c->wait);
862 }
863
i2c_pxa_irq_txempty(struct pxa_i2c * i2c,u32 isr)864 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
865 {
866 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
867
868 again:
869 /*
870 * If ISR_ALD is set, we lost arbitration.
871 */
872 if (isr & ISR_ALD) {
873 /*
874 * Do we need to do anything here? The PXA docs
875 * are vague about what happens.
876 */
877 i2c_pxa_scream_blue_murder(i2c, "ALD set");
878
879 /*
880 * We ignore this error. We seem to see spurious ALDs
881 * for seemingly no reason. If we handle them as I think
882 * they should, we end up causing an I2C error, which
883 * is painful for some systems.
884 */
885 return; /* ignore */
886 }
887
888 if ((isr & ISR_BED) &&
889 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
890 (isr & ISR_ACKNAK)))) {
891 int ret = BUS_ERROR;
892
893 /*
894 * I2C bus error - either the device NAK'd us, or
895 * something more serious happened. If we were NAK'd
896 * on the initial address phase, we can retry.
897 */
898 if (isr & ISR_ACKNAK) {
899 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
900 ret = NO_SLAVE;
901 else
902 ret = XFER_NAKED;
903 }
904 i2c_pxa_master_complete(i2c, ret);
905 } else if (isr & ISR_RWM) {
906 /*
907 * Read mode. We have just sent the address byte, and
908 * now we must initiate the transfer.
909 */
910 if (i2c->msg_ptr == i2c->msg->len - 1 &&
911 i2c->msg_idx == i2c->msg_num - 1)
912 icr |= ICR_STOP | ICR_ACKNAK;
913
914 icr |= ICR_ALDIE | ICR_TB;
915 } else if (i2c->msg_ptr < i2c->msg->len) {
916 /*
917 * Write mode. Write the next data byte.
918 */
919 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
920
921 icr |= ICR_ALDIE | ICR_TB;
922
923 /*
924 * If this is the last byte of the last message or last byte
925 * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
926 */
927 if ((i2c->msg_ptr == i2c->msg->len) &&
928 ((i2c->msg->flags & I2C_M_STOP) ||
929 (i2c->msg_idx == i2c->msg_num - 1)))
930 icr |= ICR_STOP;
931
932 } else if (i2c->msg_idx < i2c->msg_num - 1) {
933 /*
934 * Next segment of the message.
935 */
936 i2c->msg_ptr = 0;
937 i2c->msg_idx ++;
938 i2c->msg++;
939
940 /*
941 * If we aren't doing a repeated start and address,
942 * go back and try to send the next byte. Note that
943 * we do not support switching the R/W direction here.
944 */
945 if (i2c->msg->flags & I2C_M_NOSTART)
946 goto again;
947
948 /*
949 * Write the next address.
950 */
951 i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
952 writel(i2c->req_slave_addr, _IDBR(i2c));
953
954 /*
955 * And trigger a repeated start, and send the byte.
956 */
957 icr &= ~ICR_ALDIE;
958 icr |= ICR_START | ICR_TB;
959 } else {
960 if (i2c->msg->len == 0)
961 icr |= ICR_MA;
962 i2c_pxa_master_complete(i2c, 0);
963 }
964
965 i2c->icrlog[i2c->irqlogidx-1] = icr;
966
967 writel(icr, _ICR(i2c));
968 show_state(i2c);
969 }
970
i2c_pxa_irq_rxfull(struct pxa_i2c * i2c,u32 isr)971 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
972 {
973 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
974
975 /*
976 * Read the byte.
977 */
978 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
979
980 if (i2c->msg_ptr < i2c->msg->len) {
981 /*
982 * If this is the last byte of the last
983 * message, send a STOP.
984 */
985 if (i2c->msg_ptr == i2c->msg->len - 1)
986 icr |= ICR_STOP | ICR_ACKNAK;
987
988 icr |= ICR_ALDIE | ICR_TB;
989 } else {
990 i2c_pxa_master_complete(i2c, 0);
991 }
992
993 i2c->icrlog[i2c->irqlogidx-1] = icr;
994
995 writel(icr, _ICR(i2c));
996 }
997
998 #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
999 ISR_SAD | ISR_BED)
i2c_pxa_handler(int this_irq,void * dev_id)1000 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
1001 {
1002 struct pxa_i2c *i2c = dev_id;
1003 u32 isr = readl(_ISR(i2c));
1004
1005 if (!(isr & VALID_INT_SOURCE))
1006 return IRQ_NONE;
1007
1008 if (i2c_debug > 2 && 0) {
1009 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1010 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1011 decode_ISR(isr);
1012 }
1013
1014 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1015 i2c->isrlog[i2c->irqlogidx++] = isr;
1016
1017 show_state(i2c);
1018
1019 /*
1020 * Always clear all pending IRQs.
1021 */
1022 writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1023
1024 if (isr & ISR_SAD)
1025 i2c_pxa_slave_start(i2c, isr);
1026 if (isr & ISR_SSD)
1027 i2c_pxa_slave_stop(i2c);
1028
1029 if (i2c_pxa_is_slavemode(i2c)) {
1030 if (isr & ISR_ITE)
1031 i2c_pxa_slave_txempty(i2c, isr);
1032 if (isr & ISR_IRF)
1033 i2c_pxa_slave_rxfull(i2c, isr);
1034 } else if (i2c->msg && (!i2c->highmode_enter)) {
1035 if (isr & ISR_ITE)
1036 i2c_pxa_irq_txempty(i2c, isr);
1037 if (isr & ISR_IRF)
1038 i2c_pxa_irq_rxfull(i2c, isr);
1039 } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1040 i2c->highmode_enter = false;
1041 wake_up(&i2c->wait);
1042 } else {
1043 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1044 }
1045
1046 return IRQ_HANDLED;
1047 }
1048
1049 /*
1050 * We are protected by the adapter bus mutex.
1051 */
i2c_pxa_do_xfer(struct pxa_i2c * i2c,struct i2c_msg * msg,int num)1052 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
1053 {
1054 long time_left;
1055 int ret;
1056
1057 /*
1058 * Wait for the bus to become free.
1059 */
1060 ret = i2c_pxa_wait_bus_not_busy(i2c);
1061 if (ret) {
1062 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
1063 i2c_recover_bus(&i2c->adap);
1064 goto out;
1065 }
1066
1067 /*
1068 * Set master mode.
1069 */
1070 ret = i2c_pxa_set_master(i2c);
1071 if (ret) {
1072 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
1073 goto out;
1074 }
1075
1076 if (i2c->high_mode) {
1077 ret = i2c_pxa_send_mastercode(i2c);
1078 if (ret) {
1079 dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
1080 goto out;
1081 }
1082 }
1083
1084 spin_lock_irq(&i2c->lock);
1085
1086 i2c->msg = msg;
1087 i2c->msg_num = num;
1088 i2c->msg_idx = 0;
1089 i2c->msg_ptr = 0;
1090 i2c->irqlogidx = 0;
1091
1092 i2c_pxa_start_message(i2c);
1093
1094 spin_unlock_irq(&i2c->lock);
1095
1096 /*
1097 * The rest of the processing occurs in the interrupt handler.
1098 */
1099 time_left = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
1100 i2c_pxa_stop_message(i2c);
1101
1102 /*
1103 * We place the return code in i2c->msg_idx.
1104 */
1105 ret = i2c->msg_idx;
1106
1107 if (!time_left && i2c->msg_num) {
1108 i2c_pxa_scream_blue_murder(i2c, "timeout with active message");
1109 i2c_recover_bus(&i2c->adap);
1110 ret = I2C_RETRY;
1111 }
1112
1113 out:
1114 return ret;
1115 }
1116
i2c_pxa_internal_xfer(struct pxa_i2c * i2c,struct i2c_msg * msgs,int num,int (* xfer)(struct pxa_i2c *,struct i2c_msg *,int num))1117 static int i2c_pxa_internal_xfer(struct pxa_i2c *i2c,
1118 struct i2c_msg *msgs, int num,
1119 int (*xfer)(struct pxa_i2c *,
1120 struct i2c_msg *, int num))
1121 {
1122 int ret, i;
1123
1124 for (i = 0; ; ) {
1125 ret = xfer(i2c, msgs, num);
1126 if (ret != I2C_RETRY && ret != NO_SLAVE)
1127 goto out;
1128 if (++i >= i2c->adap.retries)
1129 break;
1130
1131 if (i2c_debug)
1132 dev_dbg(&i2c->adap.dev, "Retrying transmission\n");
1133 udelay(100);
1134 }
1135 if (ret != NO_SLAVE)
1136 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1137 ret = -EREMOTEIO;
1138 out:
1139 i2c_pxa_set_slave(i2c, ret);
1140 return ret;
1141 }
1142
i2c_pxa_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1143 static int i2c_pxa_xfer(struct i2c_adapter *adap,
1144 struct i2c_msg msgs[], int num)
1145 {
1146 struct pxa_i2c *i2c = adap->algo_data;
1147
1148 if (i2c->reset_before_xfer) {
1149 i2c_pxa_reset(i2c);
1150 i2c->reset_before_xfer = false;
1151 }
1152
1153 return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_xfer);
1154 }
1155
i2c_pxa_functionality(struct i2c_adapter * adap)1156 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1157 {
1158 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1159 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1160 }
1161
1162 static const struct i2c_algorithm i2c_pxa_algorithm = {
1163 .xfer = i2c_pxa_xfer,
1164 .functionality = i2c_pxa_functionality,
1165 #ifdef CONFIG_I2C_PXA_SLAVE
1166 .reg_slave = i2c_pxa_slave_reg,
1167 .unreg_slave = i2c_pxa_slave_unreg,
1168 #endif
1169 };
1170
1171 /* Non-interrupt mode support */
i2c_pxa_pio_set_master(struct pxa_i2c * i2c)1172 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
1173 {
1174 /* make timeout the same as for interrupt based functions */
1175 long timeout = 2 * DEF_TIMEOUT;
1176
1177 /*
1178 * Wait for the bus to become free.
1179 */
1180 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB))
1181 udelay(1000);
1182
1183 if (timeout < 0) {
1184 show_state(i2c);
1185 dev_err(&i2c->adap.dev,
1186 "i2c_pxa: timeout waiting for bus free (set_master)\n");
1187 return I2C_RETRY;
1188 }
1189
1190 /*
1191 * Set master mode.
1192 */
1193 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
1194
1195 return 0;
1196 }
1197
i2c_pxa_do_pio_xfer(struct pxa_i2c * i2c,struct i2c_msg * msg,int num)1198 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
1199 struct i2c_msg *msg, int num)
1200 {
1201 unsigned long timeout = 500000; /* 5 seconds */
1202 int ret = 0;
1203
1204 ret = i2c_pxa_pio_set_master(i2c);
1205 if (ret)
1206 goto out;
1207
1208 i2c->msg = msg;
1209 i2c->msg_num = num;
1210 i2c->msg_idx = 0;
1211 i2c->msg_ptr = 0;
1212 i2c->irqlogidx = 0;
1213
1214 i2c_pxa_start_message(i2c);
1215
1216 while (i2c->msg_num > 0 && --timeout) {
1217 i2c_pxa_handler(0, i2c);
1218 udelay(10);
1219 }
1220
1221 i2c_pxa_stop_message(i2c);
1222
1223 /*
1224 * We place the return code in i2c->msg_idx.
1225 */
1226 ret = i2c->msg_idx;
1227
1228 out:
1229 if (timeout == 0) {
1230 i2c_pxa_scream_blue_murder(i2c, "timeout (do_pio_xfer)");
1231 ret = I2C_RETRY;
1232 }
1233
1234 return ret;
1235 }
1236
i2c_pxa_pio_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1237 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
1238 struct i2c_msg msgs[], int num)
1239 {
1240 struct pxa_i2c *i2c = adap->algo_data;
1241
1242 /* If the I2C controller is disabled we need to reset it
1243 (probably due to a suspend/resume destroying state). We do
1244 this here as we can then avoid worrying about resuming the
1245 controller before its users. */
1246 if (!(readl(_ICR(i2c)) & ICR_IUE))
1247 i2c_pxa_reset(i2c);
1248
1249 return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_pio_xfer);
1250 }
1251
1252 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1253 .xfer = i2c_pxa_pio_xfer,
1254 .functionality = i2c_pxa_functionality,
1255 #ifdef CONFIG_I2C_PXA_SLAVE
1256 .reg_slave = i2c_pxa_slave_reg,
1257 .unreg_slave = i2c_pxa_slave_unreg,
1258 #endif
1259 };
1260
i2c_pxa_probe_dt(struct platform_device * pdev,struct pxa_i2c * i2c,enum pxa_i2c_types * i2c_types)1261 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1262 enum pxa_i2c_types *i2c_types)
1263 {
1264 struct device_node *np = pdev->dev.of_node;
1265
1266 if (!pdev->dev.of_node)
1267 return 1;
1268
1269 /* For device tree we always use the dynamic or alias-assigned ID */
1270 i2c->adap.nr = -1;
1271
1272 i2c->use_pio = of_property_read_bool(np, "mrvl,i2c-polling");
1273 i2c->fast_mode = of_property_read_bool(np, "mrvl,i2c-fast-mode");
1274
1275 *i2c_types = (kernel_ulong_t)device_get_match_data(&pdev->dev);
1276
1277 return 0;
1278 }
1279
i2c_pxa_probe_pdata(struct platform_device * pdev,struct pxa_i2c * i2c,enum pxa_i2c_types * i2c_types)1280 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1281 struct pxa_i2c *i2c,
1282 enum pxa_i2c_types *i2c_types)
1283 {
1284 struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1285 const struct platform_device_id *id = platform_get_device_id(pdev);
1286
1287 *i2c_types = id->driver_data;
1288 if (plat) {
1289 i2c->use_pio = plat->use_pio;
1290 i2c->fast_mode = plat->fast_mode;
1291 i2c->high_mode = plat->high_mode;
1292 i2c->master_code = plat->master_code;
1293 if (!i2c->master_code)
1294 i2c->master_code = 0xe;
1295 i2c->rate = plat->rate;
1296 }
1297 return 0;
1298 }
1299
i2c_pxa_prepare_recovery(struct i2c_adapter * adap)1300 static void i2c_pxa_prepare_recovery(struct i2c_adapter *adap)
1301 {
1302 struct pxa_i2c *i2c = adap->algo_data;
1303 u32 ibmr = readl(_IBMR(i2c));
1304
1305 /*
1306 * Program the GPIOs to reflect the current I2C bus state while
1307 * we transition to recovery; this avoids glitching the bus.
1308 */
1309 gpiod_set_value(i2c->recovery.scl_gpiod, ibmr & IBMR_SCLS);
1310 gpiod_set_value(i2c->recovery.sda_gpiod, ibmr & IBMR_SDAS);
1311
1312 WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery));
1313 }
1314
i2c_pxa_unprepare_recovery(struct i2c_adapter * adap)1315 static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap)
1316 {
1317 struct pxa_i2c *i2c = adap->algo_data;
1318 u32 isr;
1319
1320 /*
1321 * The bus should now be free. Clear up the I2C controller before
1322 * handing control of the bus back to avoid the bus changing state.
1323 */
1324 isr = readl(_ISR(i2c));
1325 if (isr & (ISR_UB | ISR_IBB)) {
1326 dev_dbg(&i2c->adap.dev,
1327 "recovery: resetting controller, ISR=0x%08x\n", isr);
1328 i2c_pxa_do_reset(i2c);
1329 }
1330
1331 WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default));
1332
1333 dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n",
1334 readl(_IBMR(i2c)), readl(_ISR(i2c)));
1335
1336 i2c_pxa_enable(i2c);
1337 }
1338
i2c_pxa_init_recovery(struct pxa_i2c * i2c)1339 static int i2c_pxa_init_recovery(struct pxa_i2c *i2c)
1340 {
1341 struct i2c_bus_recovery_info *bri = &i2c->recovery;
1342 struct device *dev = i2c->adap.dev.parent;
1343
1344 /*
1345 * When slave mode is enabled, we are not the only master on the bus.
1346 * Bus recovery can only be performed when we are the master, which
1347 * we can't be certain of. Therefore, when slave mode is enabled, do
1348 * not configure bus recovery.
1349 */
1350 if (IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
1351 return 0;
1352
1353 i2c->pinctrl = devm_pinctrl_get(dev);
1354 if (PTR_ERR(i2c->pinctrl) == -ENODEV)
1355 i2c->pinctrl = NULL;
1356 if (IS_ERR(i2c->pinctrl))
1357 return PTR_ERR(i2c->pinctrl);
1358
1359 if (!i2c->pinctrl)
1360 return 0;
1361
1362 i2c->pinctrl_default = pinctrl_lookup_state(i2c->pinctrl,
1363 PINCTRL_STATE_DEFAULT);
1364 i2c->pinctrl_recovery = pinctrl_lookup_state(i2c->pinctrl, "recovery");
1365
1366 if (IS_ERR(i2c->pinctrl_default) || IS_ERR(i2c->pinctrl_recovery)) {
1367 dev_info(dev, "missing pinmux recovery information: %ld %ld\n",
1368 PTR_ERR(i2c->pinctrl_default),
1369 PTR_ERR(i2c->pinctrl_recovery));
1370 return 0;
1371 }
1372
1373 /*
1374 * Claiming GPIOs can influence the pinmux state, and may glitch the
1375 * I2C bus. Do this carefully.
1376 */
1377 bri->scl_gpiod = devm_gpiod_get(dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1378 if (bri->scl_gpiod == ERR_PTR(-EPROBE_DEFER))
1379 return -EPROBE_DEFER;
1380 if (IS_ERR(bri->scl_gpiod)) {
1381 dev_info(dev, "missing scl gpio recovery information: %pe\n",
1382 bri->scl_gpiod);
1383 return 0;
1384 }
1385
1386 /*
1387 * We have SCL. Pull SCL low and wait a bit so that SDA glitches
1388 * have no effect.
1389 */
1390 gpiod_direction_output(bri->scl_gpiod, 0);
1391 udelay(10);
1392 bri->sda_gpiod = devm_gpiod_get(dev, "sda", GPIOD_OUT_HIGH_OPEN_DRAIN);
1393
1394 /* Wait a bit in case of a SDA glitch, and then release SCL. */
1395 udelay(10);
1396 gpiod_direction_output(bri->scl_gpiod, 1);
1397
1398 if (bri->sda_gpiod == ERR_PTR(-EPROBE_DEFER))
1399 return -EPROBE_DEFER;
1400
1401 if (IS_ERR(bri->sda_gpiod)) {
1402 dev_info(dev, "missing sda gpio recovery information: %pe\n",
1403 bri->sda_gpiod);
1404 return 0;
1405 }
1406
1407 bri->prepare_recovery = i2c_pxa_prepare_recovery;
1408 bri->unprepare_recovery = i2c_pxa_unprepare_recovery;
1409 bri->recover_bus = i2c_generic_scl_recovery;
1410
1411 i2c->adap.bus_recovery_info = bri;
1412
1413 /*
1414 * Claiming GPIOs can change the pinmux state, which confuses the
1415 * pinctrl since pinctrl's idea of the current setting is unaffected
1416 * by the pinmux change caused by claiming the GPIO. Work around that
1417 * by switching pinctrl to the GPIO state here. We do it this way to
1418 * avoid glitching the I2C bus.
1419 */
1420 pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery);
1421
1422 return pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default);
1423 }
1424
i2c_pxa_probe(struct platform_device * dev)1425 static int i2c_pxa_probe(struct platform_device *dev)
1426 {
1427 struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1428 enum pxa_i2c_types i2c_type;
1429 struct pxa_i2c *i2c;
1430 struct resource *res;
1431 int ret, irq;
1432
1433 i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1434 if (!i2c)
1435 return -ENOMEM;
1436
1437 /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1438 i2c->adap.nr = dev->id;
1439 i2c->adap.owner = THIS_MODULE;
1440 i2c->adap.retries = 5;
1441 i2c->adap.algo_data = i2c;
1442 i2c->adap.dev.parent = &dev->dev;
1443 #ifdef CONFIG_OF
1444 i2c->adap.dev.of_node = dev->dev.of_node;
1445 #endif
1446
1447 i2c->reg_base = devm_platform_get_and_ioremap_resource(dev, 0, &res);
1448 if (IS_ERR(i2c->reg_base))
1449 return PTR_ERR(i2c->reg_base);
1450
1451 irq = platform_get_irq(dev, 0);
1452 if (irq < 0)
1453 return irq;
1454
1455 ret = i2c_pxa_init_recovery(i2c);
1456 if (ret)
1457 return ret;
1458
1459 ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1460 if (ret > 0)
1461 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1462 if (ret < 0)
1463 return ret;
1464
1465 spin_lock_init(&i2c->lock);
1466 init_waitqueue_head(&i2c->wait);
1467
1468 strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1469
1470 i2c->clk = devm_clk_get(&dev->dev, NULL);
1471 if (IS_ERR(i2c->clk))
1472 return dev_err_probe(&dev->dev, PTR_ERR(i2c->clk),
1473 "failed to get the clk\n");
1474
1475 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1476 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1477 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1478 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1479 i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
1480 i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
1481
1482 if (i2c_type != REGS_CE4100)
1483 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1484
1485 if (i2c_type == REGS_PXA910) {
1486 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1487 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1488 }
1489
1490 i2c->iobase = res->start;
1491 i2c->iosize = resource_size(res);
1492
1493 i2c->irq = irq;
1494
1495 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1496 i2c->highmode_enter = false;
1497
1498 if (plat) {
1499 i2c->adap.class = plat->class;
1500 }
1501
1502 if (i2c->high_mode) {
1503 if (i2c->rate) {
1504 clk_set_rate(i2c->clk, i2c->rate);
1505 pr_info("i2c: <%s> set rate to %ld\n",
1506 i2c->adap.name, clk_get_rate(i2c->clk));
1507 } else
1508 pr_warn("i2c: <%s> clock rate not set\n",
1509 i2c->adap.name);
1510 }
1511
1512 ret = clk_prepare_enable(i2c->clk);
1513 if (ret)
1514 return dev_err_probe(&dev->dev, ret,
1515 "failed to enable clock\n");
1516
1517 if (i2c->use_pio) {
1518 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1519 } else {
1520 i2c->adap.algo = &i2c_pxa_algorithm;
1521 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1522 IRQF_SHARED | IRQF_NO_SUSPEND,
1523 dev_name(&dev->dev), i2c);
1524 if (ret) {
1525 dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1526 goto ereqirq;
1527 }
1528 }
1529
1530 /*
1531 * Skip reset on Armada 3700 when recovery is used to avoid
1532 * controller hang due to the pinctrl state changes done by
1533 * the generic recovery initialization code. The reset will
1534 * be performed later, prior to the first transfer.
1535 */
1536 if (i2c_type == REGS_A3700 && i2c->adap.bus_recovery_info)
1537 i2c->reset_before_xfer = true;
1538 else
1539 i2c_pxa_reset(i2c);
1540
1541 ret = i2c_add_numbered_adapter(&i2c->adap);
1542 if (ret < 0)
1543 goto ereqirq;
1544
1545 platform_set_drvdata(dev, i2c);
1546
1547 #ifdef CONFIG_I2C_PXA_SLAVE
1548 dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1549 i2c->slave_addr);
1550 #else
1551 dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1552 #endif
1553 return 0;
1554
1555 ereqirq:
1556 clk_disable_unprepare(i2c->clk);
1557 return ret;
1558 }
1559
i2c_pxa_remove(struct platform_device * dev)1560 static void i2c_pxa_remove(struct platform_device *dev)
1561 {
1562 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1563
1564 i2c_del_adapter(&i2c->adap);
1565
1566 clk_disable_unprepare(i2c->clk);
1567 }
1568
i2c_pxa_suspend_noirq(struct device * dev)1569 static int i2c_pxa_suspend_noirq(struct device *dev)
1570 {
1571 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1572
1573 clk_disable(i2c->clk);
1574
1575 return 0;
1576 }
1577
i2c_pxa_resume_noirq(struct device * dev)1578 static int i2c_pxa_resume_noirq(struct device *dev)
1579 {
1580 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1581
1582 clk_enable(i2c->clk);
1583 i2c_pxa_reset(i2c);
1584
1585 return 0;
1586 }
1587
1588 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1589 .suspend_noirq = i2c_pxa_suspend_noirq,
1590 .resume_noirq = i2c_pxa_resume_noirq,
1591 };
1592
1593 static struct platform_driver i2c_pxa_driver = {
1594 .probe = i2c_pxa_probe,
1595 .remove = i2c_pxa_remove,
1596 .driver = {
1597 .name = "pxa2xx-i2c",
1598 .pm = pm_sleep_ptr(&i2c_pxa_dev_pm_ops),
1599 .of_match_table = i2c_pxa_dt_ids,
1600 },
1601 .id_table = i2c_pxa_id_table,
1602 };
1603
i2c_adap_pxa_init(void)1604 static int __init i2c_adap_pxa_init(void)
1605 {
1606 return platform_driver_register(&i2c_pxa_driver);
1607 }
1608
i2c_adap_pxa_exit(void)1609 static void __exit i2c_adap_pxa_exit(void)
1610 {
1611 platform_driver_unregister(&i2c_pxa_driver);
1612 }
1613
1614 MODULE_DESCRIPTION("Intel PXA2XX I2C adapter");
1615 MODULE_LICENSE("GPL");
1616
1617 subsys_initcall(i2c_adap_pxa_init);
1618 module_exit(i2c_adap_pxa_exit);
1619