1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/array_size.h>
7 #include <linux/bitfield.h>
8 #include <linux/bits.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_platform.h>
16 #include <linux/pci.h>
17 #include <linux/pci-pwrctrl.h>
18 #include <linux/platform_device.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/string.h>
21 #include <linux/types.h>
22 #include <linux/unaligned.h>
23
24 #include "../pci.h"
25
26 #define TC9563_GPIO_CONFIG 0x801208
27 #define TC9563_RESET_GPIO 0x801210
28
29 #define TC9563_PORT_L0S_DELAY 0x82496c
30 #define TC9563_PORT_L1_DELAY 0x824970
31
32 #define TC9563_EMBEDDED_ETH_DELAY 0x8200d8
33 #define TC9563_ETH_L1_DELAY_MASK GENMASK(27, 18)
34 #define TC9563_ETH_L1_DELAY_VALUE(x) FIELD_PREP(TC9563_ETH_L1_DELAY_MASK, x)
35 #define TC9563_ETH_L0S_DELAY_MASK GENMASK(17, 13)
36 #define TC9563_ETH_L0S_DELAY_VALUE(x) FIELD_PREP(TC9563_ETH_L0S_DELAY_MASK, x)
37
38 #define TC9563_NFTS_2_5_GT 0x824978
39 #define TC9563_NFTS_5_GT 0x82497c
40
41 #define TC9563_PORT_LANE_ACCESS_ENABLE 0x828000
42
43 #define TC9563_PHY_RATE_CHANGE_OVERRIDE 0x828040
44 #define TC9563_PHY_RATE_CHANGE 0x828050
45
46 #define TC9563_TX_MARGIN 0x828234
47
48 #define TC9563_DFE_ENABLE 0x828a04
49 #define TC9563_DFE_EQ0_MODE 0x828a08
50 #define TC9563_DFE_EQ1_MODE 0x828a0c
51 #define TC9563_DFE_EQ2_MODE 0x828a14
52 #define TC9563_DFE_PD_MASK 0x828254
53
54 #define TC9563_PORT_SELECT 0x82c02c
55 #define TC9563_PORT_ACCESS_ENABLE 0x82c030
56
57 #define TC9563_POWER_CONTROL 0x82b09c
58 #define TC9563_POWER_CONTROL_OVREN 0x82b2c8
59
60 #define TC9563_GPIO_MASK 0xfffffff3
61 #define TC9563_GPIO_DEASSERT_BITS 0xc /* Clear to deassert GPIO */
62
63 #define TC9563_TX_MARGIN_MIN_UA 400000
64
65 /*
66 * From TC9563 PORSYS rev 0.2, figure 1.1 POR boot sequence
67 * wait for 10ms for the internal osc frequency to stabilize.
68 */
69 #define TC9563_OSC_STAB_DELAY_US (10 * USEC_PER_MSEC)
70
71 #define TC9563_L0S_L1_DELAY_UNIT_NS 256 /* Each unit represents 256 ns */
72
73 struct tc9563_pwrctrl_reg_setting {
74 unsigned int offset;
75 unsigned int val;
76 };
77
78 enum tc9563_pwrctrl_ports {
79 TC9563_USP,
80 TC9563_DSP1,
81 TC9563_DSP2,
82 TC9563_VDSP,
83 TC9563_MAX
84 };
85
86 struct tc9563_pwrctrl_cfg {
87 u32 l0s_delay;
88 u32 l1_delay;
89 u32 tx_amp;
90 u8 nfts[2]; /* GEN1 & GEN2 */
91 bool disable_dfe;
92 bool disable_port;
93 };
94
95 #define TC9563_PWRCTL_MAX_SUPPLY 6
96
97 static const char *const tc9563_supply_names[TC9563_PWRCTL_MAX_SUPPLY] = {
98 "vddc",
99 "vdd18",
100 "vdd09",
101 "vddio1",
102 "vddio2",
103 "vddio18",
104 };
105
106 struct tc9563_pwrctrl {
107 struct pci_pwrctrl pwrctrl;
108 struct regulator_bulk_data supplies[TC9563_PWRCTL_MAX_SUPPLY];
109 struct tc9563_pwrctrl_cfg cfg[TC9563_MAX];
110 struct tc9563_pwrctrl_cfg ep_cfg;
111 struct gpio_desc *reset_gpio;
112 struct i2c_adapter *adapter;
113 struct i2c_client *client;
114 };
115
116 /*
117 * downstream port power off sequence, hardcoding the address
118 * as we don't know register names for these register offsets.
119 */
120 static const struct tc9563_pwrctrl_reg_setting common_pwroff_seq[] = {
121 {0x82900c, 0x1},
122 {0x829010, 0x1},
123 {0x829018, 0x0},
124 {0x829020, 0x1},
125 {0x82902c, 0x1},
126 {0x829030, 0x1},
127 {0x82903c, 0x1},
128 {0x829058, 0x0},
129 {0x82905c, 0x1},
130 {0x829060, 0x1},
131 {0x8290cc, 0x1},
132 {0x8290d0, 0x1},
133 {0x8290d8, 0x1},
134 {0x8290e0, 0x1},
135 {0x8290e8, 0x1},
136 {0x8290ec, 0x1},
137 {0x8290f4, 0x1},
138 {0x82910c, 0x1},
139 {0x829110, 0x1},
140 {0x829114, 0x1},
141 };
142
143 static const struct tc9563_pwrctrl_reg_setting dsp1_pwroff_seq[] = {
144 {TC9563_PORT_ACCESS_ENABLE, 0x2},
145 {TC9563_PORT_LANE_ACCESS_ENABLE, 0x3},
146 {TC9563_POWER_CONTROL, 0x014f4804},
147 {TC9563_POWER_CONTROL_OVREN, 0x1},
148 {TC9563_PORT_ACCESS_ENABLE, 0x4},
149 };
150
151 static const struct tc9563_pwrctrl_reg_setting dsp2_pwroff_seq[] = {
152 {TC9563_PORT_ACCESS_ENABLE, 0x8},
153 {TC9563_PORT_LANE_ACCESS_ENABLE, 0x1},
154 {TC9563_POWER_CONTROL, 0x014f4804},
155 {TC9563_POWER_CONTROL_OVREN, 0x1},
156 {TC9563_PORT_ACCESS_ENABLE, 0x8},
157 };
158
159 /*
160 * Since all transfers are initiated by the probe, no locks are necessary,
161 * as there are no concurrent calls.
162 */
tc9563_pwrctrl_i2c_write(struct i2c_client * client,u32 reg_addr,u32 reg_val)163 static int tc9563_pwrctrl_i2c_write(struct i2c_client *client,
164 u32 reg_addr, u32 reg_val)
165 {
166 struct i2c_msg msg;
167 u8 msg_buf[7];
168 int ret;
169
170 msg.addr = client->addr;
171 msg.len = 7;
172 msg.flags = 0;
173
174 /* Big Endian for reg addr */
175 put_unaligned_be24(reg_addr, &msg_buf[0]);
176
177 /* Little Endian for reg val */
178 put_unaligned_le32(reg_val, &msg_buf[3]);
179
180 msg.buf = msg_buf;
181 ret = i2c_transfer(client->adapter, &msg, 1);
182 return ret == 1 ? 0 : ret;
183 }
184
tc9563_pwrctrl_i2c_read(struct i2c_client * client,u32 reg_addr,u32 * reg_val)185 static int tc9563_pwrctrl_i2c_read(struct i2c_client *client,
186 u32 reg_addr, u32 *reg_val)
187 {
188 struct i2c_msg msg[2];
189 u8 wr_data[3];
190 u32 rd_data;
191 int ret;
192
193 msg[0].addr = client->addr;
194 msg[0].len = 3;
195 msg[0].flags = 0;
196
197 /* Big Endian for reg addr */
198 put_unaligned_be24(reg_addr, &wr_data[0]);
199
200 msg[0].buf = wr_data;
201
202 msg[1].addr = client->addr;
203 msg[1].len = 4;
204 msg[1].flags = I2C_M_RD;
205
206 msg[1].buf = (u8 *)&rd_data;
207
208 ret = i2c_transfer(client->adapter, &msg[0], 2);
209 if (ret == 2) {
210 *reg_val = get_unaligned_le32(&rd_data);
211 return 0;
212 }
213
214 /* If only one message successfully completed, return -EIO */
215 return ret == 1 ? -EIO : ret;
216 }
217
tc9563_pwrctrl_i2c_bulk_write(struct i2c_client * client,const struct tc9563_pwrctrl_reg_setting * seq,int len)218 static int tc9563_pwrctrl_i2c_bulk_write(struct i2c_client *client,
219 const struct tc9563_pwrctrl_reg_setting *seq,
220 int len)
221 {
222 int ret, i;
223
224 for (i = 0; i < len; i++) {
225 ret = tc9563_pwrctrl_i2c_write(client, seq[i].offset, seq[i].val);
226 if (ret)
227 return ret;
228 }
229
230 return 0;
231 }
232
tc9563_pwrctrl_disable_port(struct tc9563_pwrctrl * tc9563,enum tc9563_pwrctrl_ports port)233 static int tc9563_pwrctrl_disable_port(struct tc9563_pwrctrl *tc9563,
234 enum tc9563_pwrctrl_ports port)
235 {
236 struct tc9563_pwrctrl_cfg *cfg = &tc9563->cfg[port];
237 const struct tc9563_pwrctrl_reg_setting *seq;
238 int ret, len;
239
240 if (!cfg->disable_port)
241 return 0;
242
243 switch (port) {
244 case TC9563_DSP1:
245 seq = dsp1_pwroff_seq;
246 len = ARRAY_SIZE(dsp1_pwroff_seq);
247 break;
248 case TC9563_DSP2:
249 seq = dsp2_pwroff_seq;
250 len = ARRAY_SIZE(dsp2_pwroff_seq);
251 break;
252 default:
253 /* Only external downstream ports DSP1/DSP2 can be powered off */
254 return 0;
255 }
256
257 ret = tc9563_pwrctrl_i2c_bulk_write(tc9563->client, seq, len);
258 if (ret)
259 return ret;
260
261 return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, common_pwroff_seq,
262 ARRAY_SIZE(common_pwroff_seq));
263 }
264
tc9563_pwrctrl_set_port_l0s_l1_entry_delay(struct tc9563_pwrctrl * tc9563,enum tc9563_pwrctrl_ports port,bool is_l1,u32 ns)265 static int tc9563_pwrctrl_set_port_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc9563,
266 enum tc9563_pwrctrl_ports port,
267 bool is_l1, u32 ns)
268 {
269 u32 units;
270 int ret;
271
272 if (ns < TC9563_L0S_L1_DELAY_UNIT_NS)
273 return 0;
274
275 /* convert to units of 256ns */
276 units = ns / TC9563_L0S_L1_DELAY_UNIT_NS;
277
278 ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_PORT_SELECT,
279 BIT(port));
280 if (ret)
281 return ret;
282
283 return tc9563_pwrctrl_i2c_write(tc9563->client,
284 is_l1 ? TC9563_PORT_L1_DELAY : TC9563_PORT_L0S_DELAY,
285 units);
286 }
287
tc9563_pwrctrl_set_eth_l0s_l1_entry_delay(struct tc9563_pwrctrl * tc9563,bool is_l1,u32 ns)288 static int tc9563_pwrctrl_set_eth_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc9563,
289 bool is_l1, u32 ns)
290 {
291 u32 rd_val, units;
292 int ret;
293
294 if (ns < TC9563_L0S_L1_DELAY_UNIT_NS)
295 return 0;
296
297 /* convert to units of 256ns */
298 units = ns / TC9563_L0S_L1_DELAY_UNIT_NS;
299
300 ret = tc9563_pwrctrl_i2c_read(tc9563->client, TC9563_EMBEDDED_ETH_DELAY,
301 &rd_val);
302 if (ret)
303 return ret;
304
305 if (is_l1)
306 rd_val = u32_replace_bits(rd_val, units,
307 TC9563_ETH_L1_DELAY_MASK);
308 else
309 rd_val = u32_replace_bits(rd_val, units,
310 TC9563_ETH_L0S_DELAY_MASK);
311
312 return tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_EMBEDDED_ETH_DELAY,
313 rd_val);
314 }
315
tc9563_pwrctrl_set_tx_amplitude(struct tc9563_pwrctrl * tc9563,enum tc9563_pwrctrl_ports port)316 static int tc9563_pwrctrl_set_tx_amplitude(struct tc9563_pwrctrl *tc9563,
317 enum tc9563_pwrctrl_ports port)
318 {
319 struct device *dev = tc9563->pwrctrl.dev;
320 u32 amp = tc9563->cfg[port].tx_amp;
321 int port_access;
322
323 if (amp < TC9563_TX_MARGIN_MIN_UA)
324 return 0;
325
326 /* txmargin = (Amp(uV) - 400000) / 3125 */
327 amp = (amp - TC9563_TX_MARGIN_MIN_UA) / 3125;
328
329 switch (port) {
330 case TC9563_USP:
331 port_access = 0x1;
332 break;
333 case TC9563_DSP1:
334 port_access = 0x2;
335 break;
336 case TC9563_DSP2:
337 port_access = 0x8;
338 break;
339 case TC9563_VDSP:
340 dev_dbg(dev, "Tx amplitude tuning not supported for VDSP\n");
341 return 0;
342 default:
343 return -EINVAL;
344 }
345
346 struct tc9563_pwrctrl_reg_setting tx_amp_seq[] = {
347 {TC9563_PORT_ACCESS_ENABLE, port_access},
348 {TC9563_PORT_LANE_ACCESS_ENABLE, 0x3},
349 {TC9563_TX_MARGIN, amp},
350 };
351
352 return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, tx_amp_seq,
353 ARRAY_SIZE(tx_amp_seq));
354 }
355
tc9563_pwrctrl_disable_dfe(struct tc9563_pwrctrl * tc9563,enum tc9563_pwrctrl_ports port)356 static int tc9563_pwrctrl_disable_dfe(struct tc9563_pwrctrl *tc9563,
357 enum tc9563_pwrctrl_ports port)
358 {
359 struct tc9563_pwrctrl_cfg *cfg = &tc9563->cfg[port];
360 struct device *dev = tc9563->pwrctrl.dev;
361 int port_access, lane_access = 0x3;
362 u32 phy_rate = 0x21;
363
364 if (!cfg->disable_dfe)
365 return 0;
366
367 switch (port) {
368 case TC9563_USP:
369 phy_rate = 0x1;
370 port_access = 0x1;
371 break;
372 case TC9563_DSP1:
373 port_access = 0x2;
374 break;
375 case TC9563_DSP2:
376 port_access = 0x8;
377 lane_access = 0x1;
378 break;
379 case TC9563_VDSP:
380 dev_dbg(dev, "DFE tuning not supported for VDSP\n");
381 return 0;
382 default:
383 return -EINVAL;
384 }
385
386 struct tc9563_pwrctrl_reg_setting disable_dfe_seq[] = {
387 {TC9563_PORT_ACCESS_ENABLE, port_access},
388 {TC9563_PORT_LANE_ACCESS_ENABLE, lane_access},
389 {TC9563_DFE_ENABLE, 0x0},
390 {TC9563_DFE_EQ0_MODE, 0x411},
391 {TC9563_DFE_EQ1_MODE, 0x11},
392 {TC9563_DFE_EQ2_MODE, 0x11},
393 {TC9563_DFE_PD_MASK, 0x7},
394 {TC9563_PHY_RATE_CHANGE_OVERRIDE, 0x10},
395 {TC9563_PHY_RATE_CHANGE, phy_rate},
396 {TC9563_PHY_RATE_CHANGE, 0x0},
397 {TC9563_PHY_RATE_CHANGE_OVERRIDE, 0x0},
398 };
399
400 return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, disable_dfe_seq,
401 ARRAY_SIZE(disable_dfe_seq));
402 }
403
tc9563_pwrctrl_set_nfts(struct tc9563_pwrctrl * tc9563,enum tc9563_pwrctrl_ports port)404 static int tc9563_pwrctrl_set_nfts(struct tc9563_pwrctrl *tc9563,
405 enum tc9563_pwrctrl_ports port)
406 {
407 u8 *nfts = tc9563->cfg[port].nfts;
408 struct tc9563_pwrctrl_reg_setting nfts_seq[] = {
409 {TC9563_NFTS_2_5_GT, nfts[0]},
410 {TC9563_NFTS_5_GT, nfts[1]},
411 };
412 struct device *dev = tc9563->pwrctrl.dev;
413 int ret;
414
415 if (!nfts[0])
416 return 0;
417
418 if (port == TC9563_VDSP) {
419 dev_dbg(dev, "N_FTS tuning not supported for VDSP\n");
420 return 0;
421 }
422
423 ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_PORT_SELECT,
424 BIT(port));
425 if (ret)
426 return ret;
427
428 return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, nfts_seq,
429 ARRAY_SIZE(nfts_seq));
430 }
431
tc9563_pwrctrl_assert_deassert_reset(struct tc9563_pwrctrl * tc9563,bool deassert)432 static int tc9563_pwrctrl_assert_deassert_reset(struct tc9563_pwrctrl *tc9563,
433 bool deassert)
434 {
435 int ret, val;
436
437 ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_GPIO_CONFIG,
438 TC9563_GPIO_MASK);
439 if (ret)
440 return ret;
441
442 val = deassert ? TC9563_GPIO_DEASSERT_BITS : 0;
443
444 return tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_RESET_GPIO, val);
445 }
446
tc9563_pwrctrl_parse_device_dt(struct device_node * node,struct tc9563_pwrctrl_cfg * cfg)447 static int tc9563_pwrctrl_parse_device_dt(struct device_node *node,
448 struct tc9563_pwrctrl_cfg *cfg)
449 {
450 int ret;
451
452 /* Disable port if the status of the port is disabled. */
453 if (!of_device_is_available(node)) {
454 cfg->disable_port = true;
455 return 0;
456 }
457
458 ret = of_property_read_u32(node, "aspm-l0s-entry-delay-ns", &cfg->l0s_delay);
459 if (ret && ret != -EINVAL)
460 return ret;
461
462 ret = of_property_read_u32(node, "aspm-l1-entry-delay-ns", &cfg->l1_delay);
463 if (ret && ret != -EINVAL)
464 return ret;
465
466 ret = of_property_read_u32(node, "toshiba,tx-amplitude-microvolt", &cfg->tx_amp);
467 if (ret && ret != -EINVAL)
468 return ret;
469
470 ret = of_property_read_u8_array(node, "n-fts", cfg->nfts, ARRAY_SIZE(cfg->nfts));
471 if (ret && ret != -EINVAL)
472 return ret;
473
474 cfg->disable_dfe = of_property_read_bool(node, "toshiba,no-dfe-support");
475
476 return 0;
477 }
478
tc9563_pwrctrl_power_off(struct pci_pwrctrl * pwrctrl)479 static int tc9563_pwrctrl_power_off(struct pci_pwrctrl *pwrctrl)
480 {
481 struct tc9563_pwrctrl *tc9563 = container_of(pwrctrl,
482 struct tc9563_pwrctrl, pwrctrl);
483
484 gpiod_set_value(tc9563->reset_gpio, 1);
485
486 regulator_bulk_disable(ARRAY_SIZE(tc9563->supplies), tc9563->supplies);
487
488 return 0;
489 }
490
tc9563_pwrctrl_power_on(struct pci_pwrctrl * pwrctrl)491 static int tc9563_pwrctrl_power_on(struct pci_pwrctrl *pwrctrl)
492 {
493 struct tc9563_pwrctrl *tc9563 = container_of(pwrctrl,
494 struct tc9563_pwrctrl, pwrctrl);
495 struct device *dev = tc9563->pwrctrl.dev;
496 struct tc9563_pwrctrl_cfg *cfg;
497 int ret, i;
498
499 ret = regulator_bulk_enable(ARRAY_SIZE(tc9563->supplies),
500 tc9563->supplies);
501 if (ret < 0)
502 return dev_err_probe(dev, ret, "cannot enable regulators\n");
503
504 gpiod_set_value(tc9563->reset_gpio, 0);
505
506 fsleep(TC9563_OSC_STAB_DELAY_US);
507
508 ret = tc9563_pwrctrl_assert_deassert_reset(tc9563, false);
509 if (ret)
510 goto power_off;
511
512 for (i = 0; i < TC9563_MAX; i++) {
513 cfg = &tc9563->cfg[i];
514 ret = tc9563_pwrctrl_disable_port(tc9563, i);
515 if (ret) {
516 dev_err(dev, "Disabling port failed\n");
517 goto power_off;
518 }
519
520 ret = tc9563_pwrctrl_set_port_l0s_l1_entry_delay(tc9563, i, false, cfg->l0s_delay);
521 if (ret) {
522 dev_err(dev, "Setting L0s entry delay failed\n");
523 goto power_off;
524 }
525
526 ret = tc9563_pwrctrl_set_port_l0s_l1_entry_delay(tc9563, i, true, cfg->l1_delay);
527 if (ret) {
528 dev_err(dev, "Setting L1 entry delay failed\n");
529 goto power_off;
530 }
531
532 ret = tc9563_pwrctrl_set_tx_amplitude(tc9563, i);
533 if (ret) {
534 dev_err(dev, "Setting Tx amplitude failed\n");
535 goto power_off;
536 }
537
538 ret = tc9563_pwrctrl_set_nfts(tc9563, i);
539 if (ret) {
540 dev_err(dev, "Setting N_FTS failed\n");
541 goto power_off;
542 }
543
544 ret = tc9563_pwrctrl_disable_dfe(tc9563, i);
545 if (ret) {
546 dev_err(dev, "Disabling DFE failed\n");
547 goto power_off;
548 }
549 }
550
551 /* Configure the integrated Ethernet MAC endpoint */
552 ret = tc9563_pwrctrl_set_eth_l0s_l1_entry_delay(tc9563, false,
553 tc9563->ep_cfg.l0s_delay);
554 if (ret) {
555 dev_err(dev, "Setting Ethernet L0s entry delay failed\n");
556 goto power_off;
557 }
558
559 ret = tc9563_pwrctrl_set_eth_l0s_l1_entry_delay(tc9563, true,
560 tc9563->ep_cfg.l1_delay);
561 if (ret) {
562 dev_err(dev, "Setting Ethernet L1 entry delay failed\n");
563 goto power_off;
564 }
565
566 ret = tc9563_pwrctrl_assert_deassert_reset(tc9563, true);
567 if (!ret)
568 return 0;
569
570 power_off:
571 tc9563_pwrctrl_power_off(&tc9563->pwrctrl);
572 return ret;
573 }
574
tc9563_pwrctrl_probe(struct platform_device * pdev)575 static int tc9563_pwrctrl_probe(struct platform_device *pdev)
576 {
577 struct device_node *node = pdev->dev.of_node;
578 struct device *dev = &pdev->dev;
579 enum tc9563_pwrctrl_ports port;
580 struct tc9563_pwrctrl *tc9563;
581 struct device_node *i2c_node;
582 int ret, addr;
583
584 tc9563 = devm_kzalloc(dev, sizeof(*tc9563), GFP_KERNEL);
585 if (!tc9563)
586 return -ENOMEM;
587
588 ret = of_property_read_u32_index(node, "i2c-parent", 1, &addr);
589 if (ret)
590 return dev_err_probe(dev, ret, "Failed to read i2c-parent property\n");
591
592 i2c_node = of_parse_phandle(dev->of_node, "i2c-parent", 0);
593 tc9563->adapter = of_get_i2c_adapter_by_node(i2c_node);
594 of_node_put(i2c_node);
595 if (!tc9563->adapter)
596 return dev_err_probe(dev, -EPROBE_DEFER, "Failed to find I2C adapter\n");
597
598 tc9563->client = i2c_new_dummy_device(tc9563->adapter, addr);
599 if (IS_ERR(tc9563->client)) {
600 dev_err(dev, "Failed to create I2C client\n");
601 i2c_put_adapter(tc9563->adapter);
602 return PTR_ERR(tc9563->client);
603 }
604
605 for (int i = 0; i < ARRAY_SIZE(tc9563_supply_names); i++)
606 tc9563->supplies[i].supply = tc9563_supply_names[i];
607
608 ret = devm_regulator_bulk_get(dev, TC9563_PWRCTL_MAX_SUPPLY,
609 tc9563->supplies);
610 if (ret) {
611 dev_err_probe(dev, ret, "failed to get supply regulator\n");
612 goto remove_i2c;
613 }
614
615 tc9563->reset_gpio = devm_gpiod_get(dev, "resx", GPIOD_OUT_HIGH);
616 if (IS_ERR(tc9563->reset_gpio)) {
617 ret = dev_err_probe(dev, PTR_ERR(tc9563->reset_gpio), "failed to get resx GPIO\n");
618 goto remove_i2c;
619 }
620
621 pci_pwrctrl_init(&tc9563->pwrctrl, dev);
622
623 ret = tc9563_pwrctrl_parse_device_dt(node, &tc9563->cfg[TC9563_USP]);
624 if (ret) {
625 dev_err(dev, "failed to parse device tree properties: %d\n", ret);
626 goto remove_i2c;
627 }
628
629 /*
630 * Downstream ports are always children of the upstream port.
631 * The first node represents DSP1, the second node represents DSP2,
632 * and so on.
633 */
634 port = TC9563_USP;
635 for_each_child_of_node_scoped(node, child) {
636 if (++port >= TC9563_MAX)
637 break;
638
639 ret = tc9563_pwrctrl_parse_device_dt(child, &tc9563->cfg[port]);
640 if (ret)
641 break;
642
643 /*
644 * The integrated Ethernet MAC Endpoint under VDSP is a single
645 * device whose functions share the same config registers.
646 */
647 if (port == TC9563_VDSP) {
648 struct device_node *eth __free(device_node) =
649 of_get_next_available_child(child, NULL);
650
651 if (eth) {
652 ret = tc9563_pwrctrl_parse_device_dt(eth,
653 &tc9563->ep_cfg);
654 if (ret)
655 break;
656 }
657 }
658 }
659 if (ret) {
660 dev_err(dev, "failed to parse device tree properties: %d\n", ret);
661 goto remove_i2c;
662 }
663
664 tc9563->pwrctrl.power_on = tc9563_pwrctrl_power_on;
665 tc9563->pwrctrl.power_off = tc9563_pwrctrl_power_off;
666
667 ret = devm_pci_pwrctrl_device_set_ready(dev, &tc9563->pwrctrl);
668 if (ret)
669 goto power_off;
670
671 return 0;
672
673 power_off:
674 tc9563_pwrctrl_power_off(&tc9563->pwrctrl);
675 remove_i2c:
676 i2c_unregister_device(tc9563->client);
677 i2c_put_adapter(tc9563->adapter);
678 return ret;
679 }
680
tc9563_pwrctrl_remove(struct platform_device * pdev)681 static void tc9563_pwrctrl_remove(struct platform_device *pdev)
682 {
683 struct pci_pwrctrl *pwrctrl = dev_get_drvdata(&pdev->dev);
684 struct tc9563_pwrctrl *tc9563 = container_of(pwrctrl,
685 struct tc9563_pwrctrl, pwrctrl);
686
687 tc9563_pwrctrl_power_off(&tc9563->pwrctrl);
688 i2c_unregister_device(tc9563->client);
689 i2c_put_adapter(tc9563->adapter);
690 }
691
692 static const struct of_device_id tc9563_pwrctrl_of_match[] = {
693 { .compatible = "pci1179,0623"},
694 { }
695 };
696 MODULE_DEVICE_TABLE(of, tc9563_pwrctrl_of_match);
697
698 static struct platform_driver tc9563_pwrctrl_driver = {
699 .driver = {
700 .name = "pwrctrl-tc9563",
701 .of_match_table = tc9563_pwrctrl_of_match,
702 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
703 },
704 .probe = tc9563_pwrctrl_probe,
705 .remove = tc9563_pwrctrl_remove,
706 };
707 module_platform_driver(tc9563_pwrctrl_driver);
708
709 MODULE_AUTHOR("Krishna chaitanya chundru <quic_krichai@quicinc.com>");
710 MODULE_DESCRIPTION("TC956x power control driver");
711 MODULE_LICENSE("GPL");
712