1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3
4 #include <linux/bits.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
26 #include <linux/dpll.h>
27
28 #define PCI_DEVICE_ID_META_TIMECARD 0x0400
29
30 #define PCI_VENDOR_ID_CELESTICA 0x18d4
31 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
32
33 #define PCI_VENDOR_ID_OROLIA 0x1ad7
34 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
35
36 #define PCI_VENDOR_ID_ADVA 0xad5a
37 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
38 #define PCI_DEVICE_ID_ADVA_TIMECARD_X1 0x0410
39
40 static struct class timecard_class = {
41 .name = "timecard",
42 };
43
44 struct ocp_reg {
45 u32 ctrl;
46 u32 status;
47 u32 select;
48 u32 version;
49 u32 time_ns;
50 u32 time_sec;
51 u32 __pad0[2];
52 u32 adjust_ns;
53 u32 adjust_sec;
54 u32 __pad1[2];
55 u32 offset_ns;
56 u32 offset_window_ns;
57 u32 __pad2[2];
58 u32 drift_ns;
59 u32 drift_window_ns;
60 u32 __pad3[6];
61 u32 servo_offset_p;
62 u32 servo_offset_i;
63 u32 servo_drift_p;
64 u32 servo_drift_i;
65 u32 status_offset;
66 u32 status_drift;
67 };
68
69 struct ptp_ocp_servo_conf {
70 u32 servo_offset_p;
71 u32 servo_offset_i;
72 u32 servo_drift_p;
73 u32 servo_drift_i;
74 };
75
76 /*
77 * Combined servo + board-variant parameters for ADVA boards.
78 * Embedded in the resource table .extra so a single ptp_ocp_adva_board_init()
79 * can handle both ADVA and ADVA-X1 without per-variant init functions.
80 */
81 struct ptp_ocp_adva_info {
82 struct ptp_ocp_servo_conf servo;
83 u32 flash_start;
84 const struct ocp_sma_op *sma_op;
85 u8 signals_nr;
86 u8 freq_in_nr;
87 const struct ocp_attr_group *attr_groups;
88 };
89
90 #define OCP_CTRL_ENABLE BIT(0)
91 #define OCP_CTRL_ADJUST_TIME BIT(1)
92 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
93 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
94 #define OCP_CTRL_ADJUST_SERVO BIT(8)
95 #define OCP_CTRL_READ_TIME_REQ BIT(30)
96 #define OCP_CTRL_READ_TIME_DONE BIT(31)
97
98 #define OCP_STATUS_IN_SYNC BIT(0)
99 #define OCP_STATUS_IN_HOLDOVER BIT(1)
100
101 #define OCP_SELECT_CLK_NONE 0
102 #define OCP_SELECT_CLK_REG 0xfe
103
104 struct tod_reg {
105 u32 ctrl;
106 u32 status;
107 u32 uart_polarity;
108 u32 version;
109 u32 adj_sec;
110 u32 __pad0[3];
111 u32 uart_baud;
112 u32 __pad1[3];
113 u32 utc_status;
114 u32 leap;
115 };
116
117 #define TOD_CTRL_PROTOCOL BIT(28)
118 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
119 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
120 #define TOD_CTRL_ENABLE BIT(0)
121 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
122 #define TOD_CTRL_GNSS_SHIFT 24
123
124 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
125 #define TOD_STATUS_UTC_VALID BIT(8)
126 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
127 #define TOD_STATUS_LEAP_VALID BIT(16)
128
129 struct ts_reg {
130 u32 enable;
131 u32 error;
132 u32 polarity;
133 u32 version;
134 u32 __pad0[4];
135 u32 cable_delay;
136 u32 __pad1[3];
137 u32 intr;
138 u32 intr_mask;
139 u32 event_count;
140 u32 __pad2[1];
141 u32 ts_count;
142 u32 time_ns;
143 u32 time_sec;
144 u32 data_width;
145 u32 data;
146 };
147
148 struct pps_reg {
149 u32 ctrl;
150 u32 status;
151 u32 __pad0[6];
152 u32 cable_delay;
153 };
154
155 #define PPS_STATUS_FILTER_ERR BIT(0)
156 #define PPS_STATUS_SUPERV_ERR BIT(1)
157
158 struct img_reg {
159 u32 version;
160 };
161
162 struct gpio_reg {
163 u32 gpio1;
164 u32 __pad0;
165 u32 gpio2;
166 u32 __pad1;
167 };
168
169 struct irig_master_reg {
170 u32 ctrl;
171 u32 status;
172 u32 __pad0;
173 u32 version;
174 u32 adj_sec;
175 u32 mode_ctrl;
176 };
177
178 #define IRIG_M_CTRL_ENABLE BIT(0)
179
180 struct irig_slave_reg {
181 u32 ctrl;
182 u32 status;
183 u32 __pad0;
184 u32 version;
185 u32 adj_sec;
186 u32 mode_ctrl;
187 };
188
189 #define IRIG_S_CTRL_ENABLE BIT(0)
190
191 struct dcf_master_reg {
192 u32 ctrl;
193 u32 status;
194 u32 __pad0;
195 u32 version;
196 u32 adj_sec;
197 };
198
199 #define DCF_M_CTRL_ENABLE BIT(0)
200
201 struct dcf_slave_reg {
202 u32 ctrl;
203 u32 status;
204 u32 __pad0;
205 u32 version;
206 u32 adj_sec;
207 };
208
209 #define DCF_S_CTRL_ENABLE BIT(0)
210
211 struct signal_reg {
212 u32 enable;
213 u32 status;
214 u32 polarity;
215 u32 version;
216 u32 __pad0[4];
217 u32 cable_delay;
218 u32 __pad1[3];
219 u32 intr;
220 u32 intr_mask;
221 u32 __pad2[2];
222 u32 start_ns;
223 u32 start_sec;
224 u32 pulse_ns;
225 u32 pulse_sec;
226 u32 period_ns;
227 u32 period_sec;
228 u32 repeat_count;
229 };
230
231 struct frequency_reg {
232 u32 ctrl;
233 u32 status;
234 };
235
236 struct board_config_reg {
237 u32 mro50_serial_activate;
238 };
239
240 #define FREQ_STATUS_VALID BIT(31)
241 #define FREQ_STATUS_ERROR BIT(30)
242 #define FREQ_STATUS_OVERRUN BIT(29)
243 #define FREQ_STATUS_MASK GENMASK(23, 0)
244
245 struct ptp_ocp_flash_info {
246 const char *name;
247 int pci_offset;
248 int data_size;
249 void *data;
250 };
251
252 struct ptp_ocp_firmware_header {
253 char magic[4];
254 __be16 pci_vendor_id;
255 __be16 pci_device_id;
256 __be32 image_size;
257 __be16 hw_revision;
258 __be16 crc;
259 };
260
261 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
262
263 struct ptp_ocp_i2c_info {
264 const char *name;
265 unsigned long fixed_rate;
266 size_t data_size;
267 void *data;
268 };
269
270 struct ptp_ocp_ext_info {
271 int index;
272 irqreturn_t (*irq_fcn)(int irq, void *priv);
273 int (*enable)(void *priv, u32 req, bool enable);
274 };
275
276 struct ptp_ocp_ext_src {
277 void __iomem *mem;
278 struct ptp_ocp *bp;
279 struct ptp_ocp_ext_info *info;
280 int irq_vec;
281 };
282
283 enum ptp_ocp_sma_mode {
284 SMA_MODE_IN,
285 SMA_MODE_OUT,
286 };
287
288 static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {
289 DPLL_PIN_FREQUENCY_1PPS,
290 DPLL_PIN_FREQUENCY_10MHZ,
291 DPLL_PIN_FREQUENCY_IRIG_B,
292 DPLL_PIN_FREQUENCY_DCF77,
293 };
294
295 struct ptp_ocp_sma_connector {
296 enum ptp_ocp_sma_mode mode;
297 bool fixed_fcn;
298 bool fixed_dir;
299 bool disabled;
300 u8 default_fcn;
301 struct dpll_pin *dpll_pin;
302 struct dpll_pin_properties dpll_prop;
303 dpll_tracker tracker;
304 };
305
306 struct ocp_attr_group {
307 u64 cap;
308 const struct attribute_group *group;
309 };
310
311 struct ocp_selector {
312 const char *name;
313 int value;
314 u64 frequency;
315 };
316
317 struct ocp_sma_op {
318 const struct ocp_selector *tbl[2];
319 void (*init)(struct ptp_ocp *bp);
320 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
321 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
322 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
323 };
324
325 #define OCP_CAP_BASIC BIT(0)
326 #define OCP_CAP_SIGNAL BIT(1)
327 #define OCP_CAP_FREQ BIT(2)
328
329 struct ptp_ocp_signal {
330 ktime_t period;
331 ktime_t pulse;
332 ktime_t phase;
333 ktime_t start;
334 int duty;
335 bool polarity;
336 bool running;
337 };
338
339 struct ptp_ocp_serial_port {
340 int line;
341 int baud;
342 };
343
344 #define OCP_BOARD_ID_LEN 13
345 #define OCP_SERIAL_LEN 6
346 #define OCP_SMA_NUM 4
347 #define OCP_SIGNAL_NUM 4
348 #define OCP_FREQ_NUM 4
349
350 enum {
351 PORT_GNSS,
352 PORT_GNSS2,
353 PORT_MAC, /* miniature atomic clock */
354 PORT_NMEA,
355
356 __PORT_COUNT,
357 };
358
359 struct ptp_ocp {
360 struct pci_dev *pdev;
361 struct device dev;
362 spinlock_t lock;
363 struct ocp_reg __iomem *reg;
364 struct tod_reg __iomem *tod;
365 struct pps_reg __iomem *pps_to_ext;
366 struct pps_reg __iomem *pps_to_clk;
367 struct board_config_reg __iomem *board_config;
368 struct gpio_reg __iomem *pps_select;
369 struct gpio_reg __iomem *sma_map1;
370 struct gpio_reg __iomem *sma_map2;
371 struct irig_master_reg __iomem *irig_out;
372 struct irig_slave_reg __iomem *irig_in;
373 struct dcf_master_reg __iomem *dcf_out;
374 struct dcf_slave_reg __iomem *dcf_in;
375 struct tod_reg __iomem *nmea_out;
376 struct frequency_reg __iomem *freq_in[OCP_FREQ_NUM];
377 struct ptp_ocp_ext_src *signal_out[OCP_SIGNAL_NUM];
378 struct ptp_ocp_ext_src *pps;
379 struct ptp_ocp_ext_src *ts0;
380 struct ptp_ocp_ext_src *ts1;
381 struct ptp_ocp_ext_src *ts2;
382 struct ptp_ocp_ext_src *ts3;
383 struct ptp_ocp_ext_src *ts4;
384 struct ocp_art_gpio_reg __iomem *art_sma;
385 struct img_reg __iomem *image;
386 struct ptp_clock *ptp;
387 struct ptp_clock_info ptp_info;
388 struct platform_device *i2c_ctrl;
389 struct platform_device *spi_flash;
390 struct clk_hw *i2c_clk;
391 struct timer_list watchdog;
392 const struct attribute_group **attr_group;
393 const struct ptp_ocp_eeprom_map *eeprom_map;
394 struct dentry *debug_root;
395 bool sync;
396 time64_t gnss_lost;
397 struct delayed_work sync_work;
398 int id;
399 int n_irqs;
400 struct ptp_ocp_serial_port port[__PORT_COUNT];
401 bool fw_loader;
402 u8 fw_tag;
403 u16 fw_version;
404 u8 board_id[OCP_BOARD_ID_LEN];
405 u8 serial[OCP_SERIAL_LEN];
406 bool has_eeprom_data;
407 u32 pps_req_map;
408 int flash_start;
409 u32 utc_tai_offset;
410 u32 ts_window_adjust;
411 u64 fw_cap;
412 struct ptp_ocp_signal signal[OCP_SIGNAL_NUM];
413 struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];
414 const struct ocp_sma_op *sma_op;
415 struct dpll_device *dpll;
416 dpll_tracker tracker;
417 int signals_nr;
418 int freq_in_nr;
419 };
420
421 #define OCP_REQ_TIMESTAMP BIT(0)
422 #define OCP_REQ_PPS BIT(1)
423
424 struct ocp_resource {
425 unsigned long offset;
426 int size;
427 int irq_vec;
428 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
429 void *extra;
430 unsigned long bp_offset;
431 const char * const name;
432 };
433
434 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
435 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
436 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
437 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
438 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
439 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
440 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
441 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
442 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
443 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
444 struct ptp_perout_request *req);
445 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
446 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
447
448 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
449
450 static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
451
452 static const struct ocp_sma_op ocp_adva_sma_op;
453 static const struct ocp_sma_op ocp_adva_x1_sma_op;
454
455 static const struct ocp_attr_group fb_timecard_groups[];
456
457 static const struct ocp_attr_group art_timecard_groups[];
458
459 static const struct ocp_attr_group adva_timecard_groups[];
460
461 static const struct ocp_attr_group adva_timecard_x1_groups[];
462
463 struct ptp_ocp_eeprom_map {
464 u16 off;
465 u16 len;
466 u32 bp_offset;
467 const void * const tag;
468 };
469
470 #define EEPROM_ENTRY(addr, member) \
471 .off = addr, \
472 .len = sizeof_field(struct ptp_ocp, member), \
473 .bp_offset = offsetof(struct ptp_ocp, member)
474
475 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
476 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
477 })
478
479 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
480 { EEPROM_ENTRY(0x43, board_id) },
481 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
482 { }
483 };
484
485 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
486 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
487 { EEPROM_ENTRY(0x200 + 0x63, serial) },
488 { }
489 };
490
491 #define bp_assign_entry(bp, res, val) ({ \
492 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
493 *(typeof(val) *)addr = val; \
494 })
495
496 #define OCP_RES_LOCATION(member) \
497 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
498
499 #define OCP_MEM_RESOURCE(member) \
500 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
501
502 #define OCP_SERIAL_RESOURCE(member) \
503 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
504
505 #define OCP_I2C_RESOURCE(member) \
506 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
507
508 #define OCP_SPI_RESOURCE(member) \
509 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
510
511 #define OCP_EXT_RESOURCE(member) \
512 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
513
514 /* This is the MSI vector mapping used.
515 * 0: PPS (TS5)
516 * 1: TS0
517 * 2: TS1
518 * 3: GNSS1
519 * 4: GNSS2
520 * 5: MAC
521 * 6: TS2
522 * 7: I2C controller
523 * 8: HWICAP (notused)
524 * 9: SPI Flash
525 * 10: NMEA
526 * 11: Signal Generator 1
527 * 12: Signal Generator 2
528 * 13: Signal Generator 3
529 * 14: Signal Generator 4
530 * 15: TS3
531 * 16: TS4
532 --
533 * 8: Orolia TS1
534 * 10: Orolia TS2
535 * 11: Orolia TS0 (GNSS)
536 * 12: Orolia PPS
537 * 14: Orolia TS3
538 * 15: Orolia TS4
539 */
540
541 static struct ocp_resource ocp_fb_resource[] = {
542 {
543 OCP_MEM_RESOURCE(reg),
544 .offset = 0x01000000, .size = 0x10000,
545 },
546 {
547 OCP_EXT_RESOURCE(ts0),
548 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
549 .extra = &(struct ptp_ocp_ext_info) {
550 .index = 0,
551 .irq_fcn = ptp_ocp_ts_irq,
552 .enable = ptp_ocp_ts_enable,
553 },
554 },
555 {
556 OCP_EXT_RESOURCE(ts1),
557 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
558 .extra = &(struct ptp_ocp_ext_info) {
559 .index = 1,
560 .irq_fcn = ptp_ocp_ts_irq,
561 .enable = ptp_ocp_ts_enable,
562 },
563 },
564 {
565 OCP_EXT_RESOURCE(ts2),
566 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
567 .extra = &(struct ptp_ocp_ext_info) {
568 .index = 2,
569 .irq_fcn = ptp_ocp_ts_irq,
570 .enable = ptp_ocp_ts_enable,
571 },
572 },
573 {
574 OCP_EXT_RESOURCE(ts3),
575 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
576 .extra = &(struct ptp_ocp_ext_info) {
577 .index = 3,
578 .irq_fcn = ptp_ocp_ts_irq,
579 .enable = ptp_ocp_ts_enable,
580 },
581 },
582 {
583 OCP_EXT_RESOURCE(ts4),
584 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
585 .extra = &(struct ptp_ocp_ext_info) {
586 .index = 4,
587 .irq_fcn = ptp_ocp_ts_irq,
588 .enable = ptp_ocp_ts_enable,
589 },
590 },
591 /* Timestamp for PHC and/or PPS generator */
592 {
593 OCP_EXT_RESOURCE(pps),
594 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
595 .extra = &(struct ptp_ocp_ext_info) {
596 .index = 5,
597 .irq_fcn = ptp_ocp_ts_irq,
598 .enable = ptp_ocp_ts_enable,
599 },
600 },
601 {
602 OCP_EXT_RESOURCE(signal_out[0]),
603 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
604 .extra = &(struct ptp_ocp_ext_info) {
605 .index = 1,
606 .irq_fcn = ptp_ocp_signal_irq,
607 .enable = ptp_ocp_signal_enable,
608 },
609 },
610 {
611 OCP_EXT_RESOURCE(signal_out[1]),
612 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
613 .extra = &(struct ptp_ocp_ext_info) {
614 .index = 2,
615 .irq_fcn = ptp_ocp_signal_irq,
616 .enable = ptp_ocp_signal_enable,
617 },
618 },
619 {
620 OCP_EXT_RESOURCE(signal_out[2]),
621 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
622 .extra = &(struct ptp_ocp_ext_info) {
623 .index = 3,
624 .irq_fcn = ptp_ocp_signal_irq,
625 .enable = ptp_ocp_signal_enable,
626 },
627 },
628 {
629 OCP_EXT_RESOURCE(signal_out[3]),
630 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
631 .extra = &(struct ptp_ocp_ext_info) {
632 .index = 4,
633 .irq_fcn = ptp_ocp_signal_irq,
634 .enable = ptp_ocp_signal_enable,
635 },
636 },
637 {
638 OCP_MEM_RESOURCE(pps_to_ext),
639 .offset = 0x01030000, .size = 0x10000,
640 },
641 {
642 OCP_MEM_RESOURCE(pps_to_clk),
643 .offset = 0x01040000, .size = 0x10000,
644 },
645 {
646 OCP_MEM_RESOURCE(tod),
647 .offset = 0x01050000, .size = 0x10000,
648 },
649 {
650 OCP_MEM_RESOURCE(irig_in),
651 .offset = 0x01070000, .size = 0x10000,
652 },
653 {
654 OCP_MEM_RESOURCE(irig_out),
655 .offset = 0x01080000, .size = 0x10000,
656 },
657 {
658 OCP_MEM_RESOURCE(dcf_in),
659 .offset = 0x01090000, .size = 0x10000,
660 },
661 {
662 OCP_MEM_RESOURCE(dcf_out),
663 .offset = 0x010A0000, .size = 0x10000,
664 },
665 {
666 OCP_MEM_RESOURCE(nmea_out),
667 .offset = 0x010B0000, .size = 0x10000,
668 },
669 {
670 OCP_MEM_RESOURCE(image),
671 .offset = 0x00020000, .size = 0x1000,
672 },
673 {
674 OCP_MEM_RESOURCE(pps_select),
675 .offset = 0x00130000, .size = 0x1000,
676 },
677 {
678 OCP_MEM_RESOURCE(sma_map1),
679 .offset = 0x00140000, .size = 0x1000,
680 },
681 {
682 OCP_MEM_RESOURCE(sma_map2),
683 .offset = 0x00220000, .size = 0x1000,
684 },
685 {
686 OCP_I2C_RESOURCE(i2c_ctrl),
687 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
688 .extra = &(struct ptp_ocp_i2c_info) {
689 .name = "xiic-i2c",
690 .fixed_rate = 50000000,
691 .data_size = sizeof(struct xiic_i2c_platform_data),
692 .data = &(struct xiic_i2c_platform_data) {
693 .num_devices = 2,
694 .devices = (struct i2c_board_info[]) {
695 { I2C_BOARD_INFO("24c02", 0x50) },
696 { I2C_BOARD_INFO("24mac402", 0x58),
697 .platform_data = "mac" },
698 },
699 },
700 },
701 },
702 {
703 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
704 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
705 .extra = &(struct ptp_ocp_serial_port) {
706 .baud = 115200,
707 },
708 },
709 {
710 OCP_SERIAL_RESOURCE(port[PORT_GNSS2]),
711 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
712 .extra = &(struct ptp_ocp_serial_port) {
713 .baud = 115200,
714 },
715 },
716 {
717 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
718 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
719 .extra = &(struct ptp_ocp_serial_port) {
720 .baud = 57600,
721 },
722 },
723 {
724 OCP_SERIAL_RESOURCE(port[PORT_NMEA]),
725 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
726 },
727 {
728 OCP_SPI_RESOURCE(spi_flash),
729 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
730 .extra = &(struct ptp_ocp_flash_info) {
731 .name = "xilinx_spi", .pci_offset = 0,
732 .data_size = sizeof(struct xspi_platform_data),
733 .data = &(struct xspi_platform_data) {
734 .num_chipselect = 1,
735 .bits_per_word = 8,
736 .num_devices = 1,
737 .force_irq = true,
738 .devices = &(struct spi_board_info) {
739 .modalias = "spi-nor",
740 },
741 },
742 },
743 },
744 {
745 OCP_MEM_RESOURCE(freq_in[0]),
746 .offset = 0x01200000, .size = 0x10000,
747 },
748 {
749 OCP_MEM_RESOURCE(freq_in[1]),
750 .offset = 0x01210000, .size = 0x10000,
751 },
752 {
753 OCP_MEM_RESOURCE(freq_in[2]),
754 .offset = 0x01220000, .size = 0x10000,
755 },
756 {
757 OCP_MEM_RESOURCE(freq_in[3]),
758 .offset = 0x01230000, .size = 0x10000,
759 },
760 {
761 .setup = ptp_ocp_fb_board_init,
762 .extra = &(struct ptp_ocp_servo_conf) {
763 .servo_offset_p = 0x2000,
764 .servo_offset_i = 0x1000,
765 .servo_drift_p = 0,
766 .servo_drift_i = 0,
767 },
768 },
769 { }
770 };
771
772 #define OCP_ART_CONFIG_SIZE 144
773 #define OCP_ART_TEMP_TABLE_SIZE 368
774
775 struct ocp_art_gpio_reg {
776 struct {
777 u32 gpio;
778 u32 __pad[3];
779 } map[4];
780 };
781
782 static struct ocp_resource ocp_art_resource[] = {
783 {
784 OCP_MEM_RESOURCE(reg),
785 .offset = 0x01000000, .size = 0x10000,
786 },
787 {
788 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
789 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
790 .extra = &(struct ptp_ocp_serial_port) {
791 .baud = 115200,
792 },
793 },
794 {
795 OCP_MEM_RESOURCE(art_sma),
796 .offset = 0x003C0000, .size = 0x1000,
797 },
798 /* Timestamp associated with GNSS1 receiver PPS */
799 {
800 OCP_EXT_RESOURCE(ts0),
801 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
802 .extra = &(struct ptp_ocp_ext_info) {
803 .index = 0,
804 .irq_fcn = ptp_ocp_ts_irq,
805 .enable = ptp_ocp_ts_enable,
806 },
807 },
808 {
809 OCP_EXT_RESOURCE(ts1),
810 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
811 .extra = &(struct ptp_ocp_ext_info) {
812 .index = 1,
813 .irq_fcn = ptp_ocp_ts_irq,
814 .enable = ptp_ocp_ts_enable,
815 },
816 },
817 {
818 OCP_EXT_RESOURCE(ts2),
819 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
820 .extra = &(struct ptp_ocp_ext_info) {
821 .index = 2,
822 .irq_fcn = ptp_ocp_ts_irq,
823 .enable = ptp_ocp_ts_enable,
824 },
825 },
826 {
827 OCP_EXT_RESOURCE(ts3),
828 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
829 .extra = &(struct ptp_ocp_ext_info) {
830 .index = 3,
831 .irq_fcn = ptp_ocp_ts_irq,
832 .enable = ptp_ocp_ts_enable,
833 },
834 },
835 {
836 OCP_EXT_RESOURCE(ts4),
837 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
838 .extra = &(struct ptp_ocp_ext_info) {
839 .index = 4,
840 .irq_fcn = ptp_ocp_ts_irq,
841 .enable = ptp_ocp_ts_enable,
842 },
843 },
844 /* Timestamp associated with Internal PPS of the card */
845 {
846 OCP_EXT_RESOURCE(pps),
847 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
848 .extra = &(struct ptp_ocp_ext_info) {
849 .index = 5,
850 .irq_fcn = ptp_ocp_ts_irq,
851 .enable = ptp_ocp_ts_enable,
852 },
853 },
854 {
855 OCP_SPI_RESOURCE(spi_flash),
856 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
857 .extra = &(struct ptp_ocp_flash_info) {
858 .name = "spi_altera", .pci_offset = 0,
859 .data_size = sizeof(struct altera_spi_platform_data),
860 .data = &(struct altera_spi_platform_data) {
861 .num_chipselect = 1,
862 .num_devices = 1,
863 .devices = &(struct spi_board_info) {
864 .modalias = "spi-nor",
865 },
866 },
867 },
868 },
869 {
870 OCP_I2C_RESOURCE(i2c_ctrl),
871 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
872 .extra = &(struct ptp_ocp_i2c_info) {
873 .name = "ocores-i2c",
874 .fixed_rate = 400000,
875 .data_size = sizeof(struct ocores_i2c_platform_data),
876 .data = &(struct ocores_i2c_platform_data) {
877 .clock_khz = 125000,
878 .bus_khz = 400,
879 .num_devices = 1,
880 .devices = &(struct i2c_board_info) {
881 I2C_BOARD_INFO("24c08", 0x50),
882 },
883 },
884 },
885 },
886 {
887 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
888 .offset = 0x00190000, .irq_vec = 7,
889 .extra = &(struct ptp_ocp_serial_port) {
890 .baud = 9600,
891 },
892 },
893 {
894 OCP_MEM_RESOURCE(board_config),
895 .offset = 0x210000, .size = 0x1000,
896 },
897 {
898 .setup = ptp_ocp_art_board_init,
899 .extra = &(struct ptp_ocp_servo_conf) {
900 .servo_offset_p = 0x2000,
901 .servo_offset_i = 0x1000,
902 .servo_drift_p = 0,
903 .servo_drift_i = 0,
904 },
905 },
906 { }
907 };
908
909 static struct ocp_resource ocp_adva_resource[] = {
910 {
911 OCP_MEM_RESOURCE(reg),
912 .offset = 0x01000000, .size = 0x10000,
913 },
914 {
915 OCP_EXT_RESOURCE(ts0),
916 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
917 .extra = &(struct ptp_ocp_ext_info) {
918 .index = 0,
919 .irq_fcn = ptp_ocp_ts_irq,
920 .enable = ptp_ocp_ts_enable,
921 },
922 },
923 {
924 OCP_EXT_RESOURCE(ts1),
925 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
926 .extra = &(struct ptp_ocp_ext_info) {
927 .index = 1,
928 .irq_fcn = ptp_ocp_ts_irq,
929 .enable = ptp_ocp_ts_enable,
930 },
931 },
932 {
933 OCP_EXT_RESOURCE(ts2),
934 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
935 .extra = &(struct ptp_ocp_ext_info) {
936 .index = 2,
937 .irq_fcn = ptp_ocp_ts_irq,
938 .enable = ptp_ocp_ts_enable,
939 },
940 },
941 /* Timestamp for PHC and/or PPS generator */
942 {
943 OCP_EXT_RESOURCE(pps),
944 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
945 .extra = &(struct ptp_ocp_ext_info) {
946 .index = 5,
947 .irq_fcn = ptp_ocp_ts_irq,
948 .enable = ptp_ocp_ts_enable,
949 },
950 },
951 {
952 OCP_EXT_RESOURCE(signal_out[0]),
953 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
954 .extra = &(struct ptp_ocp_ext_info) {
955 .index = 1,
956 .irq_fcn = ptp_ocp_signal_irq,
957 .enable = ptp_ocp_signal_enable,
958 },
959 },
960 {
961 OCP_EXT_RESOURCE(signal_out[1]),
962 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
963 .extra = &(struct ptp_ocp_ext_info) {
964 .index = 2,
965 .irq_fcn = ptp_ocp_signal_irq,
966 .enable = ptp_ocp_signal_enable,
967 },
968 },
969 {
970 OCP_MEM_RESOURCE(pps_to_ext),
971 .offset = 0x01030000, .size = 0x10000,
972 },
973 {
974 OCP_MEM_RESOURCE(pps_to_clk),
975 .offset = 0x01040000, .size = 0x10000,
976 },
977 {
978 OCP_MEM_RESOURCE(tod),
979 .offset = 0x01050000, .size = 0x10000,
980 },
981 {
982 OCP_MEM_RESOURCE(image),
983 .offset = 0x00020000, .size = 0x1000,
984 },
985 {
986 OCP_MEM_RESOURCE(pps_select),
987 .offset = 0x00130000, .size = 0x1000,
988 },
989 {
990 OCP_MEM_RESOURCE(sma_map1),
991 .offset = 0x00140000, .size = 0x1000,
992 },
993 {
994 OCP_MEM_RESOURCE(sma_map2),
995 .offset = 0x00220000, .size = 0x1000,
996 },
997 {
998 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
999 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
1000 .extra = &(struct ptp_ocp_serial_port) {
1001 .baud = 9600,
1002 },
1003 },
1004 {
1005 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
1006 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
1007 .extra = &(struct ptp_ocp_serial_port) {
1008 .baud = 115200,
1009 },
1010 },
1011 {
1012 OCP_MEM_RESOURCE(freq_in[0]),
1013 .offset = 0x01200000, .size = 0x10000,
1014 },
1015 {
1016 OCP_MEM_RESOURCE(freq_in[1]),
1017 .offset = 0x01210000, .size = 0x10000,
1018 },
1019 {
1020 OCP_SPI_RESOURCE(spi_flash),
1021 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
1022 .extra = &(struct ptp_ocp_flash_info) {
1023 .name = "spi_altera", .pci_offset = 0,
1024 .data_size = sizeof(struct altera_spi_platform_data),
1025 .data = &(struct altera_spi_platform_data) {
1026 .num_chipselect = 1,
1027 .num_devices = 1,
1028 .devices = &(struct spi_board_info) {
1029 .modalias = "spi-nor",
1030 },
1031 },
1032 },
1033 },
1034 {
1035 OCP_I2C_RESOURCE(i2c_ctrl),
1036 .offset = 0x150000, .size = 0x100, .irq_vec = 7,
1037 .extra = &(struct ptp_ocp_i2c_info) {
1038 .name = "ocores-i2c",
1039 .fixed_rate = 50000000,
1040 .data_size = sizeof(struct ocores_i2c_platform_data),
1041 .data = &(struct ocores_i2c_platform_data) {
1042 .clock_khz = 50000,
1043 .bus_khz = 100,
1044 .reg_io_width = 4, // 32-bit/4-byte
1045 .reg_shift = 2, // 32-bit addressing
1046 .num_devices = 2,
1047 .devices = (struct i2c_board_info[]) {
1048 { I2C_BOARD_INFO("24c02", 0x50) },
1049 { I2C_BOARD_INFO("24mac402", 0x58),
1050 .platform_data = "mac" },
1051 },
1052 },
1053 },
1054 },
1055 {
1056 .setup = ptp_ocp_adva_board_init,
1057 .extra = &(struct ptp_ocp_adva_info) {
1058 .servo = {
1059 .servo_offset_p = 0xc000,
1060 .servo_offset_i = 0x1000,
1061 .servo_drift_p = 0,
1062 .servo_drift_i = 0,
1063 },
1064 .flash_start = 0xA00000,
1065 .sma_op = &ocp_adva_sma_op,
1066 .signals_nr = 2,
1067 .freq_in_nr = 2,
1068 .attr_groups = adva_timecard_groups,
1069 },
1070 },
1071 { }
1072 };
1073
1074 static struct ocp_resource ocp_adva_x1_resource[] = {
1075 {
1076 OCP_MEM_RESOURCE(reg),
1077 .offset = 0x01000000, .size = 0x10000,
1078 },
1079 {
1080 OCP_EXT_RESOURCE(ts0),
1081 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
1082 .extra = &(struct ptp_ocp_ext_info) {
1083 .index = 0,
1084 .irq_fcn = ptp_ocp_ts_irq,
1085 .enable = ptp_ocp_ts_enable,
1086 },
1087 },
1088 {
1089 OCP_EXT_RESOURCE(ts1),
1090 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
1091 .extra = &(struct ptp_ocp_ext_info) {
1092 .index = 1,
1093 .irq_fcn = ptp_ocp_ts_irq,
1094 .enable = ptp_ocp_ts_enable,
1095 },
1096 },
1097 {
1098 OCP_EXT_RESOURCE(ts2),
1099 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
1100 .extra = &(struct ptp_ocp_ext_info) {
1101 .index = 2,
1102 .irq_fcn = ptp_ocp_ts_irq,
1103 .enable = ptp_ocp_ts_enable,
1104 },
1105 },
1106 {
1107 OCP_EXT_RESOURCE(ts3),
1108 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
1109 .extra = &(struct ptp_ocp_ext_info) {
1110 .index = 3,
1111 .irq_fcn = ptp_ocp_ts_irq,
1112 .enable = ptp_ocp_ts_enable,
1113 },
1114 },
1115 {
1116 OCP_EXT_RESOURCE(ts4),
1117 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
1118 .extra = &(struct ptp_ocp_ext_info) {
1119 .index = 4,
1120 .irq_fcn = ptp_ocp_ts_irq,
1121 .enable = ptp_ocp_ts_enable,
1122 },
1123 },
1124 /* Timestamp for PHC and/or PPS generator */
1125 {
1126 OCP_EXT_RESOURCE(pps),
1127 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
1128 .extra = &(struct ptp_ocp_ext_info) {
1129 .index = 5,
1130 .irq_fcn = ptp_ocp_ts_irq,
1131 .enable = ptp_ocp_ts_enable,
1132 },
1133 },
1134 {
1135 OCP_EXT_RESOURCE(signal_out[0]),
1136 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
1137 .extra = &(struct ptp_ocp_ext_info) {
1138 .index = 1,
1139 .irq_fcn = ptp_ocp_signal_irq,
1140 .enable = ptp_ocp_signal_enable,
1141 },
1142 },
1143 {
1144 OCP_EXT_RESOURCE(signal_out[1]),
1145 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
1146 .extra = &(struct ptp_ocp_ext_info) {
1147 .index = 2,
1148 .irq_fcn = ptp_ocp_signal_irq,
1149 .enable = ptp_ocp_signal_enable,
1150 },
1151 },
1152 {
1153 OCP_EXT_RESOURCE(signal_out[2]),
1154 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
1155 .extra = &(struct ptp_ocp_ext_info) {
1156 .index = 3,
1157 .irq_fcn = ptp_ocp_signal_irq,
1158 .enable = ptp_ocp_signal_enable,
1159 },
1160 },
1161 {
1162 OCP_EXT_RESOURCE(signal_out[3]),
1163 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
1164 .extra = &(struct ptp_ocp_ext_info) {
1165 .index = 4,
1166 .irq_fcn = ptp_ocp_signal_irq,
1167 .enable = ptp_ocp_signal_enable,
1168 },
1169 },
1170 {
1171 OCP_MEM_RESOURCE(pps_to_ext),
1172 .offset = 0x01030000, .size = 0x10000,
1173 },
1174 {
1175 OCP_MEM_RESOURCE(pps_to_clk),
1176 .offset = 0x01040000, .size = 0x10000,
1177 },
1178 {
1179 OCP_MEM_RESOURCE(tod),
1180 .offset = 0x01050000, .size = 0x10000,
1181 },
1182 {
1183 OCP_MEM_RESOURCE(image),
1184 .offset = 0x00020000, .size = 0x1000,
1185 },
1186 {
1187 OCP_MEM_RESOURCE(pps_select),
1188 .offset = 0x00130000, .size = 0x1000,
1189 },
1190 {
1191 OCP_MEM_RESOURCE(sma_map1),
1192 .offset = 0x00140000, .size = 0x1000,
1193 },
1194 {
1195 OCP_MEM_RESOURCE(sma_map2),
1196 .offset = 0x00220000, .size = 0x1000,
1197 },
1198 {
1199 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
1200 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
1201 .extra = &(struct ptp_ocp_serial_port) {
1202 .baud = 9600,
1203 },
1204 },
1205 {
1206 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
1207 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
1208 .extra = &(struct ptp_ocp_serial_port) {
1209 .baud = 115200,
1210 },
1211 },
1212 {
1213 OCP_MEM_RESOURCE(freq_in[0]),
1214 .offset = 0x01200000, .size = 0x10000,
1215 },
1216 {
1217 OCP_MEM_RESOURCE(freq_in[1]),
1218 .offset = 0x01210000, .size = 0x10000,
1219 },
1220 {
1221 OCP_MEM_RESOURCE(freq_in[2]),
1222 .offset = 0x01220000, .size = 0x10000,
1223 },
1224 {
1225 OCP_MEM_RESOURCE(freq_in[3]),
1226 .offset = 0x01230000, .size = 0x10000,
1227 },
1228 {
1229 OCP_SPI_RESOURCE(spi_flash),
1230 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
1231 .extra = &(struct ptp_ocp_flash_info) {
1232 .name = "xilinx_spi", .pci_offset = 0,
1233 .data_size = sizeof(struct xspi_platform_data),
1234 .data = &(struct xspi_platform_data) {
1235 .num_chipselect = 1,
1236 .bits_per_word = 8,
1237 .num_devices = 1,
1238 .force_irq = true,
1239 .devices = &(struct spi_board_info) {
1240 .modalias = "spi-nor",
1241 },
1242 },
1243 },
1244 },
1245 {
1246 OCP_I2C_RESOURCE(i2c_ctrl),
1247 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
1248 .extra = &(struct ptp_ocp_i2c_info) {
1249 .name = "xiic-i2c",
1250 .fixed_rate = 50000000,
1251 .data_size = sizeof(struct xiic_i2c_platform_data),
1252 .data = &(struct xiic_i2c_platform_data) {
1253 .num_devices = 2,
1254 .devices = (struct i2c_board_info[]) {
1255 { I2C_BOARD_INFO("24c02", 0x50) },
1256 { I2C_BOARD_INFO("24mac402", 0x58),
1257 .platform_data = "mac" },
1258 },
1259 },
1260 },
1261 },
1262 {
1263 .setup = ptp_ocp_adva_board_init,
1264 .extra = &(struct ptp_ocp_adva_info) {
1265 .servo = {
1266 .servo_offset_p = 0xc000,
1267 .servo_offset_i = 0x1000,
1268 .servo_drift_p = 0,
1269 .servo_drift_i = 0,
1270 },
1271 .flash_start = 0x1000000,
1272 .sma_op = &ocp_adva_x1_sma_op,
1273 .signals_nr = 4,
1274 .freq_in_nr = 4,
1275 .attr_groups = adva_timecard_x1_groups,
1276 },
1277 },
1278 { }
1279 };
1280
1281 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
1282 { PCI_DEVICE_DATA(META, TIMECARD, &ocp_fb_resource) },
1283 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
1284 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
1285 { PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) },
1286 { PCI_DEVICE_DATA(ADVA, TIMECARD_X1, &ocp_adva_x1_resource) },
1287 { }
1288 };
1289 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
1290
1291 static DEFINE_MUTEX(ptp_ocp_lock);
1292 static DEFINE_IDR(ptp_ocp_idr);
1293
1294 static const struct ocp_selector ptp_ocp_clock[] = {
1295 { .name = "NONE", .value = 0 },
1296 { .name = "TOD", .value = 1 },
1297 { .name = "IRIG", .value = 2 },
1298 { .name = "PPS", .value = 3 },
1299 { .name = "PTP", .value = 4 },
1300 { .name = "RTC", .value = 5 },
1301 { .name = "DCF", .value = 6 },
1302 { .name = "REGS", .value = 0xfe },
1303 { .name = "EXT", .value = 0xff },
1304 { }
1305 };
1306
1307 #define SMA_DISABLE BIT(16)
1308 #define SMA_ENABLE BIT(15)
1309 #define SMA_SELECT_MASK GENMASK(14, 0)
1310
1311 static const struct ocp_selector ptp_ocp_sma_in[] = {
1312 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1313 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1314 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1315 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1316 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1317 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1318 { .name = "DCF", .value = 0x0020, .frequency = 77500 },
1319 { .name = "TS3", .value = 0x0040, .frequency = 0 },
1320 { .name = "TS4", .value = 0x0080, .frequency = 0 },
1321 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1322 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1323 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },
1324 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },
1325 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1326 { }
1327 };
1328
1329 static const struct ocp_selector ptp_ocp_sma_out[] = {
1330 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1331 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1332 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1333 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1334 { .name = "GNSS2", .value = 0x0008, .frequency = 1 },
1335 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1336 { .name = "DCF", .value = 0x0020, .frequency = 77000 },
1337 { .name = "GEN1", .value = 0x0040 },
1338 { .name = "GEN2", .value = 0x0080 },
1339 { .name = "GEN3", .value = 0x0100 },
1340 { .name = "GEN4", .value = 0x0200 },
1341 { .name = "GND", .value = 0x2000 },
1342 { .name = "VCC", .value = 0x4000 },
1343 { }
1344 };
1345
1346 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
1347 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1348 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },
1349 { }
1350 };
1351
1352 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
1353 { .name = "PHC", .value = 0x0002, .frequency = 1 },
1354 { .name = "GNSS", .value = 0x0004, .frequency = 1 },
1355 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },
1356 { }
1357 };
1358
1359 static const struct ocp_selector ptp_ocp_adva_sma_in[] = {
1360 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1361 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1362 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1363 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1364 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1365 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1366 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1367 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1368 { }
1369 };
1370
1371 static const struct ocp_selector ptp_ocp_adva_sma_out[] = {
1372 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1373 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1374 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1375 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1376 { .name = "GEN1", .value = 0x0040 },
1377 { .name = "GEN2", .value = 0x0080 },
1378 { .name = "GND", .value = 0x2000 },
1379 { .name = "VCC", .value = 0x4000 },
1380 { }
1381 };
1382
1383 static const struct ocp_selector ptp_ocp_adva_x1_sma_in[] = {
1384 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1385 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1386 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1387 { .name = "TS3", .value = 0x0040, .frequency = 0 },
1388 { .name = "TS4", .value = 0x0080, .frequency = 0 },
1389 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1390 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1391 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },
1392 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },
1393 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1394 { }
1395 };
1396
1397 static const struct ocp_selector ptp_ocp_adva_x1_sma_out[] = {
1398 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1399 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1400 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1401 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1402 { .name = "GEN1", .value = 0x0040 },
1403 { .name = "GEN2", .value = 0x0080 },
1404 { .name = "GEN3", .value = 0x0100 },
1405 { .name = "GEN4", .value = 0x0200 },
1406 { .name = "GND", .value = 0x2000 },
1407 { .name = "VCC", .value = 0x4000 },
1408 { }
1409 };
1410
1411 static void
ptp_ocp_sma_init(struct ptp_ocp * bp)1412 ptp_ocp_sma_init(struct ptp_ocp *bp)
1413 {
1414 return bp->sma_op->init(bp);
1415 }
1416
1417 static u32
ptp_ocp_sma_get(struct ptp_ocp * bp,int sma_nr)1418 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
1419 {
1420 return bp->sma_op->get(bp, sma_nr);
1421 }
1422
1423 static int
ptp_ocp_sma_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)1424 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
1425 {
1426 return bp->sma_op->set_inputs(bp, sma_nr, val);
1427 }
1428
1429 static int
ptp_ocp_sma_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)1430 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
1431 {
1432 return bp->sma_op->set_output(bp, sma_nr, val);
1433 }
1434
1435 static const char *
ptp_ocp_select_name_from_val(const struct ocp_selector * tbl,int val)1436 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
1437 {
1438 int i;
1439
1440 for (i = 0; tbl[i].name; i++)
1441 if (tbl[i].value == val)
1442 return tbl[i].name;
1443 return NULL;
1444 }
1445
1446 static int
ptp_ocp_select_val_from_name(const struct ocp_selector * tbl,const char * name)1447 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
1448 {
1449 const char *select;
1450 int i;
1451
1452 for (i = 0; tbl[i].name; i++) {
1453 select = tbl[i].name;
1454 if (!strncasecmp(name, select, strlen(select)))
1455 return tbl[i].value;
1456 }
1457 return -EINVAL;
1458 }
1459
1460 static ssize_t
ptp_ocp_select_table_show(const struct ocp_selector * tbl,char * buf)1461 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
1462 {
1463 ssize_t count;
1464 int i;
1465
1466 count = 0;
1467 for (i = 0; tbl[i].name; i++)
1468 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
1469 if (count)
1470 count--;
1471 count += sysfs_emit_at(buf, count, "\n");
1472 return count;
1473 }
1474
1475 static int
__ptp_ocp_gettime_locked(struct ptp_ocp * bp,struct timespec64 * ts,struct ptp_system_timestamp * sts)1476 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
1477 struct ptp_system_timestamp *sts)
1478 {
1479 u32 ctrl, time_sec, time_ns;
1480 int i;
1481
1482 ptp_read_system_prets(sts);
1483
1484 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1485 iowrite32(ctrl, &bp->reg->ctrl);
1486
1487 for (i = 0; i < 100; i++) {
1488 ctrl = ioread32(&bp->reg->ctrl);
1489 if (ctrl & OCP_CTRL_READ_TIME_DONE)
1490 break;
1491 }
1492 ptp_read_system_postts(sts);
1493
1494 if (sts && bp->ts_window_adjust)
1495 sts->post_sts.systime -= bp->ts_window_adjust;
1496
1497 time_ns = ioread32(&bp->reg->time_ns);
1498 time_sec = ioread32(&bp->reg->time_sec);
1499
1500 ts->tv_sec = time_sec;
1501 ts->tv_nsec = time_ns;
1502
1503 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1504 }
1505
1506 static int
ptp_ocp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)1507 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1508 struct ptp_system_timestamp *sts)
1509 {
1510 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1511 unsigned long flags;
1512 int err;
1513
1514 spin_lock_irqsave(&bp->lock, flags);
1515 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1516 spin_unlock_irqrestore(&bp->lock, flags);
1517
1518 return err;
1519 }
1520
1521 static void
__ptp_ocp_settime_locked(struct ptp_ocp * bp,const struct timespec64 * ts)1522 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1523 {
1524 u32 ctrl, time_sec, time_ns;
1525 u32 select;
1526
1527 time_ns = ts->tv_nsec;
1528 time_sec = ts->tv_sec;
1529
1530 select = ioread32(&bp->reg->select);
1531 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1532
1533 iowrite32(time_ns, &bp->reg->adjust_ns);
1534 iowrite32(time_sec, &bp->reg->adjust_sec);
1535
1536 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1537 iowrite32(ctrl, &bp->reg->ctrl);
1538
1539 /* restore clock selection */
1540 iowrite32(select >> 16, &bp->reg->select);
1541 }
1542
1543 static int
ptp_ocp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)1544 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1545 {
1546 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1547 unsigned long flags;
1548
1549 spin_lock_irqsave(&bp->lock, flags);
1550 __ptp_ocp_settime_locked(bp, ts);
1551 spin_unlock_irqrestore(&bp->lock, flags);
1552
1553 return 0;
1554 }
1555
1556 static void
__ptp_ocp_adjtime_locked(struct ptp_ocp * bp,u32 adj_val)1557 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1558 {
1559 u32 select, ctrl;
1560
1561 select = ioread32(&bp->reg->select);
1562 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1563
1564 iowrite32(adj_val, &bp->reg->offset_ns);
1565 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1566
1567 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1568 iowrite32(ctrl, &bp->reg->ctrl);
1569
1570 /* restore clock selection */
1571 iowrite32(select >> 16, &bp->reg->select);
1572 }
1573
1574 static void
ptp_ocp_adjtime_coarse(struct ptp_ocp * bp,s64 delta_ns)1575 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1576 {
1577 struct timespec64 ts;
1578 unsigned long flags;
1579 int err;
1580
1581 spin_lock_irqsave(&bp->lock, flags);
1582 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1583 if (likely(!err)) {
1584 set_normalized_timespec64(&ts, ts.tv_sec,
1585 ts.tv_nsec + delta_ns);
1586 __ptp_ocp_settime_locked(bp, &ts);
1587 }
1588 spin_unlock_irqrestore(&bp->lock, flags);
1589 }
1590
1591 static int
ptp_ocp_adjtime(struct ptp_clock_info * ptp_info,s64 delta_ns)1592 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1593 {
1594 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1595 unsigned long flags;
1596 u32 adj_ns, sign;
1597
1598 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1599 ptp_ocp_adjtime_coarse(bp, delta_ns);
1600 return 0;
1601 }
1602
1603 sign = delta_ns < 0 ? BIT(31) : 0;
1604 adj_ns = sign ? -delta_ns : delta_ns;
1605
1606 spin_lock_irqsave(&bp->lock, flags);
1607 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1608 spin_unlock_irqrestore(&bp->lock, flags);
1609
1610 return 0;
1611 }
1612
1613 static int
ptp_ocp_null_adjfine(struct ptp_clock_info * ptp_info,long scaled_ppm)1614 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1615 {
1616 if (scaled_ppm == 0)
1617 return 0;
1618
1619 return -EOPNOTSUPP;
1620 }
1621
1622 static s32
ptp_ocp_null_getmaxphase(struct ptp_clock_info * ptp_info)1623 ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
1624 {
1625 return 0;
1626 }
1627
1628 static int
ptp_ocp_null_adjphase(struct ptp_clock_info * ptp_info,s32 phase_ns)1629 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1630 {
1631 return -EOPNOTSUPP;
1632 }
1633
1634 static int
ptp_ocp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)1635 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1636 int on)
1637 {
1638 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1639 struct ptp_ocp_ext_src *ext = NULL;
1640 u32 req;
1641 int err;
1642
1643 switch (rq->type) {
1644 case PTP_CLK_REQ_EXTTS:
1645 req = OCP_REQ_TIMESTAMP;
1646 switch (rq->extts.index) {
1647 case 0:
1648 ext = bp->ts0;
1649 break;
1650 case 1:
1651 ext = bp->ts1;
1652 break;
1653 case 2:
1654 ext = bp->ts2;
1655 break;
1656 case 3:
1657 ext = bp->ts3;
1658 break;
1659 case 4:
1660 ext = bp->ts4;
1661 break;
1662 case 5:
1663 ext = bp->pps;
1664 break;
1665 }
1666 break;
1667 case PTP_CLK_REQ_PPS:
1668 req = OCP_REQ_PPS;
1669 ext = bp->pps;
1670 break;
1671 case PTP_CLK_REQ_PEROUT:
1672 switch (rq->perout.index) {
1673 case 0:
1674 /* This is a request for 1PPS on an output SMA.
1675 * Allow, but assume manual configuration.
1676 */
1677 if (on && (rq->perout.period.sec != 1 ||
1678 rq->perout.period.nsec != 0))
1679 return -EINVAL;
1680 return 0;
1681 case 1:
1682 case 2:
1683 case 3:
1684 case 4:
1685 req = rq->perout.index - 1;
1686 ext = bp->signal_out[req];
1687 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1688 if (err)
1689 return err;
1690 break;
1691 }
1692 break;
1693 default:
1694 return -EOPNOTSUPP;
1695 }
1696
1697 err = -ENXIO;
1698 if (ext)
1699 err = ext->info->enable(ext, req, on);
1700
1701 return err;
1702 }
1703
1704 static int
ptp_ocp_verify(struct ptp_clock_info * ptp_info,unsigned pin,enum ptp_pin_function func,unsigned chan)1705 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1706 enum ptp_pin_function func, unsigned chan)
1707 {
1708 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1709 char buf[16];
1710
1711 switch (func) {
1712 case PTP_PF_NONE:
1713 snprintf(buf, sizeof(buf), "IN: None");
1714 break;
1715 case PTP_PF_EXTTS:
1716 /* Allow timestamps, but require sysfs configuration. */
1717 return 0;
1718 case PTP_PF_PEROUT:
1719 /* channel 0 is 1PPS from PHC.
1720 * channels 1..4 are the frequency generators.
1721 */
1722 if (chan)
1723 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1724 else
1725 snprintf(buf, sizeof(buf), "OUT: PHC");
1726 break;
1727 default:
1728 return -EOPNOTSUPP;
1729 }
1730
1731 return ptp_ocp_sma_store(bp, buf, pin + 1);
1732 }
1733
1734 static const struct ptp_clock_info ptp_ocp_clock_info = {
1735 .owner = THIS_MODULE,
1736 .name = KBUILD_MODNAME,
1737 .max_adj = 100000000,
1738 .gettimex64 = ptp_ocp_gettimex,
1739 .settime64 = ptp_ocp_settime,
1740 .adjtime = ptp_ocp_adjtime,
1741 .adjfine = ptp_ocp_null_adjfine,
1742 .adjphase = ptp_ocp_null_adjphase,
1743 .getmaxphase = ptp_ocp_null_getmaxphase,
1744 .enable = ptp_ocp_enable,
1745 .verify = ptp_ocp_verify,
1746 .pps = true,
1747 .n_ext_ts = 6,
1748 .n_per_out = 5,
1749 .supported_extts_flags = PTP_STRICT_FLAGS | PTP_RISING_EDGE,
1750 .supported_perout_flags = PTP_PEROUT_DUTY_CYCLE | PTP_PEROUT_PHASE,
1751 };
1752
1753 static void
__ptp_ocp_clear_drift_locked(struct ptp_ocp * bp)1754 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1755 {
1756 u32 ctrl, select;
1757
1758 select = ioread32(&bp->reg->select);
1759 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1760
1761 iowrite32(0, &bp->reg->drift_ns);
1762
1763 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1764 iowrite32(ctrl, &bp->reg->ctrl);
1765
1766 /* restore clock selection */
1767 iowrite32(select >> 16, &bp->reg->select);
1768 }
1769
1770 static void
ptp_ocp_utc_distribute(struct ptp_ocp * bp,u32 val)1771 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1772 {
1773 unsigned long flags;
1774
1775 spin_lock_irqsave(&bp->lock, flags);
1776
1777 bp->utc_tai_offset = val;
1778
1779 if (bp->irig_out)
1780 iowrite32(val, &bp->irig_out->adj_sec);
1781 if (bp->dcf_out)
1782 iowrite32(val, &bp->dcf_out->adj_sec);
1783 if (bp->nmea_out)
1784 iowrite32(val, &bp->nmea_out->adj_sec);
1785
1786 spin_unlock_irqrestore(&bp->lock, flags);
1787 }
1788
1789 static void
ptp_ocp_watchdog(struct timer_list * t)1790 ptp_ocp_watchdog(struct timer_list *t)
1791 {
1792 struct ptp_ocp *bp = timer_container_of(bp, t, watchdog);
1793 unsigned long flags;
1794 u32 status, utc_offset;
1795
1796 status = ioread32(&bp->pps_to_clk->status);
1797
1798 if (status & PPS_STATUS_SUPERV_ERR) {
1799 iowrite32(status, &bp->pps_to_clk->status);
1800 if (!bp->gnss_lost) {
1801 spin_lock_irqsave(&bp->lock, flags);
1802 __ptp_ocp_clear_drift_locked(bp);
1803 spin_unlock_irqrestore(&bp->lock, flags);
1804 bp->gnss_lost = ktime_get_real_seconds();
1805 }
1806
1807 } else if (bp->gnss_lost) {
1808 bp->gnss_lost = 0;
1809 }
1810
1811 /* if GNSS provides correct data we can rely on
1812 * it to get leap second information
1813 */
1814 if (bp->tod) {
1815 status = ioread32(&bp->tod->utc_status);
1816 utc_offset = status & TOD_STATUS_UTC_MASK;
1817 if (status & TOD_STATUS_UTC_VALID &&
1818 utc_offset != bp->utc_tai_offset)
1819 ptp_ocp_utc_distribute(bp, utc_offset);
1820 }
1821
1822 mod_timer(&bp->watchdog, jiffies + HZ);
1823 }
1824
1825 static void
ptp_ocp_estimate_pci_timing(struct ptp_ocp * bp)1826 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1827 {
1828 ktime_t start, end, delay = U64_MAX;
1829 u32 ctrl;
1830 int i;
1831
1832 for (i = 0; i < 3; i++) {
1833 ctrl = ioread32(&bp->reg->ctrl);
1834 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1835
1836 iowrite32(ctrl, &bp->reg->ctrl);
1837
1838 start = ktime_get_raw_ns();
1839
1840 ctrl = ioread32(&bp->reg->ctrl);
1841
1842 end = ktime_get_raw_ns();
1843
1844 delay = min(delay, end - start);
1845 }
1846 bp->ts_window_adjust = (delay >> 5) * 3;
1847 }
1848
1849 static int
ptp_ocp_init_clock(struct ptp_ocp * bp,struct ptp_ocp_servo_conf * servo_conf)1850 ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf)
1851 {
1852 struct timespec64 ts;
1853 u32 ctrl;
1854
1855 ctrl = OCP_CTRL_ENABLE;
1856 iowrite32(ctrl, &bp->reg->ctrl);
1857
1858 /* servo configuration */
1859 iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p);
1860 iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i);
1861 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p);
1862 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i);
1863
1864 /* latch servo values */
1865 ctrl |= OCP_CTRL_ADJUST_SERVO;
1866 iowrite32(ctrl, &bp->reg->ctrl);
1867
1868 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1869 dev_err(&bp->pdev->dev, "clock not enabled\n");
1870 return -ENODEV;
1871 }
1872
1873 ptp_ocp_estimate_pci_timing(bp);
1874
1875 bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1876 if (!bp->sync) {
1877 ktime_get_clocktai_ts64(&ts);
1878 ptp_ocp_settime(&bp->ptp_info, &ts);
1879 }
1880
1881 /* If there is a clock supervisor, then enable the watchdog */
1882 if (bp->pps_to_clk) {
1883 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1884 mod_timer(&bp->watchdog, jiffies + HZ);
1885 }
1886
1887 return 0;
1888 }
1889
1890 static void
ptp_ocp_tod_init(struct ptp_ocp * bp)1891 ptp_ocp_tod_init(struct ptp_ocp *bp)
1892 {
1893 u32 ctrl, reg;
1894
1895 ctrl = ioread32(&bp->tod->ctrl);
1896 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1897 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1898 iowrite32(ctrl, &bp->tod->ctrl);
1899
1900 reg = ioread32(&bp->tod->utc_status);
1901 if (reg & TOD_STATUS_UTC_VALID)
1902 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1903 }
1904
1905 static const char *
ptp_ocp_tod_proto_name(const int idx)1906 ptp_ocp_tod_proto_name(const int idx)
1907 {
1908 static const char * const proto_name[] = {
1909 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1910 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1911 };
1912 return proto_name[idx];
1913 }
1914
1915 static const char *
ptp_ocp_tod_gnss_name(int idx)1916 ptp_ocp_tod_gnss_name(int idx)
1917 {
1918 static const char * const gnss_name[] = {
1919 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1920 "Unknown"
1921 };
1922 if (idx >= ARRAY_SIZE(gnss_name))
1923 idx = ARRAY_SIZE(gnss_name) - 1;
1924 return gnss_name[idx];
1925 }
1926
1927 static const char *
ptp_ocp_tty_port_name(int idx)1928 ptp_ocp_tty_port_name(int idx)
1929 {
1930 static const char * const tty_name[] = {
1931 "GNSS", "GNSS2", "MAC", "NMEA"
1932 };
1933 return tty_name[idx];
1934 }
1935
1936 struct ptp_ocp_nvmem_match_info {
1937 struct ptp_ocp *bp;
1938 const void * const tag;
1939 };
1940
1941 static int
ptp_ocp_nvmem_match(struct device * dev,const void * data)1942 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1943 {
1944 const struct ptp_ocp_nvmem_match_info *info = data;
1945
1946 dev = dev->parent;
1947 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1948 return 0;
1949
1950 while ((dev = dev->parent))
1951 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1952 return info->bp == dev_get_drvdata(dev);
1953 return 0;
1954 }
1955
1956 static inline struct nvmem_device *
ptp_ocp_nvmem_device_get(struct ptp_ocp * bp,const void * const tag)1957 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1958 {
1959 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1960
1961 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1962 }
1963
1964 static inline void
ptp_ocp_nvmem_device_put(struct nvmem_device ** nvmemp)1965 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1966 {
1967 if (!IS_ERR_OR_NULL(*nvmemp))
1968 nvmem_device_put(*nvmemp);
1969 *nvmemp = NULL;
1970 }
1971
1972 static void
ptp_ocp_read_eeprom(struct ptp_ocp * bp)1973 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1974 {
1975 const struct ptp_ocp_eeprom_map *map;
1976 struct nvmem_device *nvmem;
1977 const void *tag;
1978 int ret;
1979
1980 if (!bp->i2c_ctrl)
1981 return;
1982
1983 tag = NULL;
1984 nvmem = NULL;
1985
1986 for (map = bp->eeprom_map; map->len; map++) {
1987 if (map->tag != tag) {
1988 tag = map->tag;
1989 ptp_ocp_nvmem_device_put(&nvmem);
1990 }
1991 if (!nvmem) {
1992 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1993 if (IS_ERR(nvmem)) {
1994 ret = PTR_ERR(nvmem);
1995 goto fail;
1996 }
1997 }
1998 ret = nvmem_device_read(nvmem, map->off, map->len,
1999 BP_MAP_ENTRY_ADDR(bp, map));
2000 if (ret != map->len)
2001 goto fail;
2002 }
2003
2004 bp->has_eeprom_data = true;
2005
2006 out:
2007 ptp_ocp_nvmem_device_put(&nvmem);
2008 return;
2009
2010 fail:
2011 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
2012 goto out;
2013 }
2014
2015 static struct device *
ptp_ocp_find_flash(struct ptp_ocp * bp)2016 ptp_ocp_find_flash(struct ptp_ocp *bp)
2017 {
2018 struct device *dev, *last;
2019
2020 last = NULL;
2021 dev = &bp->spi_flash->dev;
2022
2023 while ((dev = device_find_any_child(dev))) {
2024 if (!strcmp("mtd", dev_bus_name(dev)))
2025 break;
2026 put_device(last);
2027 last = dev;
2028 }
2029 put_device(last);
2030
2031 return dev;
2032 }
2033
2034 static int
ptp_ocp_devlink_fw_image(struct devlink * devlink,const struct firmware * fw,const u8 ** data,size_t * size)2035 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
2036 const u8 **data, size_t *size)
2037 {
2038 struct ptp_ocp *bp = devlink_priv(devlink);
2039 const struct ptp_ocp_firmware_header *hdr;
2040 size_t offset, length;
2041 u16 crc;
2042
2043 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
2044 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
2045 devlink_flash_update_status_notify(devlink,
2046 "No firmware header found, cancel firmware upgrade",
2047 NULL, 0, 0);
2048 return -EINVAL;
2049 }
2050
2051 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
2052 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
2053 devlink_flash_update_status_notify(devlink,
2054 "Firmware image compatibility check failed",
2055 NULL, 0, 0);
2056 return -EINVAL;
2057 }
2058
2059 offset = sizeof(*hdr);
2060 length = be32_to_cpu(hdr->image_size);
2061 if (length != (fw->size - offset)) {
2062 devlink_flash_update_status_notify(devlink,
2063 "Firmware image size check failed",
2064 NULL, 0, 0);
2065 return -EINVAL;
2066 }
2067
2068 crc = crc16(0xffff, &fw->data[offset], length);
2069 if (be16_to_cpu(hdr->crc) != crc) {
2070 devlink_flash_update_status_notify(devlink,
2071 "Firmware image CRC check failed",
2072 NULL, 0, 0);
2073 return -EINVAL;
2074 }
2075
2076 *data = &fw->data[offset];
2077 *size = length;
2078
2079 return 0;
2080 }
2081
2082 static int
ptp_ocp_devlink_flash(struct devlink * devlink,struct device * dev,const struct firmware * fw)2083 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
2084 const struct firmware *fw)
2085 {
2086 struct mtd_info *mtd = dev_get_drvdata(dev);
2087 struct ptp_ocp *bp = devlink_priv(devlink);
2088 size_t off, len, size, resid, wrote;
2089 struct erase_info erase;
2090 size_t base, blksz;
2091 const u8 *data;
2092 int err;
2093
2094 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
2095 if (err)
2096 goto out;
2097
2098 off = 0;
2099 base = bp->flash_start;
2100 blksz = 4096;
2101 resid = size;
2102
2103 while (resid) {
2104 devlink_flash_update_status_notify(devlink, "Flashing",
2105 NULL, off, size);
2106
2107 len = min_t(size_t, resid, blksz);
2108 erase.addr = base + off;
2109 erase.len = blksz;
2110
2111 err = mtd_erase(mtd, &erase);
2112 if (err)
2113 goto out;
2114
2115 err = mtd_write(mtd, base + off, len, &wrote, data + off);
2116 if (err)
2117 goto out;
2118
2119 off += blksz;
2120 resid -= len;
2121 }
2122 out:
2123 return err;
2124 }
2125
2126 static int
ptp_ocp_devlink_flash_update(struct devlink * devlink,struct devlink_flash_update_params * params,struct netlink_ext_ack * extack)2127 ptp_ocp_devlink_flash_update(struct devlink *devlink,
2128 struct devlink_flash_update_params *params,
2129 struct netlink_ext_ack *extack)
2130 {
2131 struct ptp_ocp *bp = devlink_priv(devlink);
2132 struct device *dev;
2133 const char *msg;
2134 int err;
2135
2136 dev = ptp_ocp_find_flash(bp);
2137 if (!dev) {
2138 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
2139 return -ENODEV;
2140 }
2141
2142 devlink_flash_update_status_notify(devlink, "Preparing to flash",
2143 NULL, 0, 0);
2144
2145 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
2146
2147 msg = err ? "Flash error" : "Flash complete";
2148 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
2149
2150 put_device(dev);
2151 return err;
2152 }
2153
2154 static int
ptp_ocp_devlink_info_get(struct devlink * devlink,struct devlink_info_req * req,struct netlink_ext_ack * extack)2155 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
2156 struct netlink_ext_ack *extack)
2157 {
2158 struct ptp_ocp *bp = devlink_priv(devlink);
2159 const char *fw_image;
2160 char buf[32];
2161 int err;
2162
2163 fw_image = bp->fw_loader ? "loader" : "fw";
2164 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
2165 err = devlink_info_version_running_put(req, fw_image, buf);
2166 if (err)
2167 return err;
2168
2169 if (!bp->has_eeprom_data) {
2170 ptp_ocp_read_eeprom(bp);
2171 if (!bp->has_eeprom_data)
2172 return 0;
2173 }
2174
2175 sprintf(buf, "%pM", bp->serial);
2176 err = devlink_info_serial_number_put(req, buf);
2177 if (err)
2178 return err;
2179
2180 snprintf(buf, sizeof(buf), "%.*s", OCP_BOARD_ID_LEN,
2181 (const char *)bp->board_id);
2182 err = devlink_info_version_fixed_put(req,
2183 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
2184 buf);
2185 if (err)
2186 return err;
2187
2188 return 0;
2189 }
2190
2191 static const struct devlink_ops ptp_ocp_devlink_ops = {
2192 .flash_update = ptp_ocp_devlink_flash_update,
2193 .info_get = ptp_ocp_devlink_info_get,
2194 };
2195
2196 static void __iomem *
__ptp_ocp_get_mem(struct ptp_ocp * bp,resource_size_t start,int size)2197 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
2198 {
2199 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
2200
2201 return devm_ioremap_resource(&bp->pdev->dev, &res);
2202 }
2203
2204 static void __iomem *
ptp_ocp_get_mem(struct ptp_ocp * bp,struct ocp_resource * r)2205 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2206 {
2207 resource_size_t start;
2208
2209 start = pci_resource_start(bp->pdev, 0) + r->offset;
2210 return __ptp_ocp_get_mem(bp, start, r->size);
2211 }
2212
2213 static int
ptp_ocp_register_spi(struct ptp_ocp * bp,struct ocp_resource * r)2214 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
2215 {
2216 struct ptp_ocp_flash_info *info;
2217 struct pci_dev *pdev = bp->pdev;
2218 struct platform_device *p;
2219 struct resource res[2];
2220 resource_size_t start;
2221 int id;
2222
2223 start = pci_resource_start(pdev, 0) + r->offset;
2224 res[0] = DEFINE_RES_MEM(start, r->size);
2225 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
2226
2227 info = r->extra;
2228 id = pci_dev_id(pdev) << 1;
2229 id += info->pci_offset;
2230
2231 p = platform_device_register_resndata(&pdev->dev, info->name, id,
2232 res, ARRAY_SIZE(res), info->data,
2233 info->data_size);
2234 if (IS_ERR(p))
2235 return PTR_ERR(p);
2236
2237 bp_assign_entry(bp, r, p);
2238
2239 return 0;
2240 }
2241
2242 static struct platform_device *
ptp_ocp_i2c_bus(struct pci_dev * pdev,struct ocp_resource * r,int id)2243 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
2244 {
2245 struct ptp_ocp_i2c_info *info;
2246 struct resource res[2];
2247 resource_size_t start;
2248
2249 info = r->extra;
2250 start = pci_resource_start(pdev, 0) + r->offset;
2251 res[0] = DEFINE_RES_MEM(start, r->size);
2252 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
2253
2254 return platform_device_register_resndata(&pdev->dev, info->name,
2255 id, res, ARRAY_SIZE(res),
2256 info->data, info->data_size);
2257 }
2258
2259 static int
ptp_ocp_register_i2c(struct ptp_ocp * bp,struct ocp_resource * r)2260 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
2261 {
2262 struct pci_dev *pdev = bp->pdev;
2263 struct ptp_ocp_i2c_info *info;
2264 struct platform_device *p;
2265 struct clk_hw *clk;
2266 char buf[32];
2267 int id;
2268
2269 info = r->extra;
2270 id = pci_dev_id(bp->pdev);
2271
2272 sprintf(buf, "AXI.%d", id);
2273 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
2274 info->fixed_rate);
2275 if (IS_ERR(clk))
2276 return PTR_ERR(clk);
2277 bp->i2c_clk = clk;
2278
2279 sprintf(buf, "%s.%d", info->name, id);
2280 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
2281 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
2282 if (IS_ERR(p))
2283 return PTR_ERR(p);
2284
2285 bp_assign_entry(bp, r, p);
2286
2287 return 0;
2288 }
2289
2290 /* The expectation is that this is triggered only on error. */
2291 static irqreturn_t
ptp_ocp_signal_irq(int irq,void * priv)2292 ptp_ocp_signal_irq(int irq, void *priv)
2293 {
2294 struct ptp_ocp_ext_src *ext = priv;
2295 struct signal_reg __iomem *reg = ext->mem;
2296 struct ptp_ocp *bp = ext->bp;
2297 u32 enable, status;
2298 int gen;
2299
2300 gen = ext->info->index - 1;
2301
2302 enable = ioread32(®->enable);
2303 status = ioread32(®->status);
2304
2305 /* disable generator on error */
2306 if (status || !enable) {
2307 iowrite32(0, ®->intr_mask);
2308 iowrite32(0, ®->enable);
2309 bp->signal[gen].running = false;
2310 }
2311
2312 iowrite32(0, ®->intr); /* ack interrupt */
2313
2314 return IRQ_HANDLED;
2315 }
2316
2317 static int
ptp_ocp_signal_set(struct ptp_ocp * bp,int gen,struct ptp_ocp_signal * s)2318 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
2319 {
2320 struct ptp_system_timestamp sts;
2321 struct timespec64 ts;
2322 ktime_t start_ns;
2323 int err;
2324
2325 if (!s->period)
2326 return 0;
2327
2328 if (!s->pulse)
2329 s->pulse = ktime_divns(s->period * s->duty, 100);
2330
2331 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
2332 if (err)
2333 return err;
2334
2335 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
2336 if (!s->start) {
2337 /* roundup() does not work on 32-bit systems */
2338 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
2339 s->start *= s->period;
2340 s->start = ktime_add(s->start, s->phase);
2341 }
2342
2343 if (s->duty < 1 || s->duty > 99)
2344 return -EINVAL;
2345
2346 if (s->pulse < 1 || s->pulse > s->period)
2347 return -EINVAL;
2348
2349 if (s->start < start_ns)
2350 return -EINVAL;
2351
2352 bp->signal[gen] = *s;
2353
2354 return 0;
2355 }
2356
2357 static int
ptp_ocp_signal_from_perout(struct ptp_ocp * bp,int gen,struct ptp_perout_request * req)2358 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
2359 struct ptp_perout_request *req)
2360 {
2361 struct ptp_ocp_signal s = { };
2362
2363 s.polarity = bp->signal[gen].polarity;
2364 s.period = ktime_set(req->period.sec, req->period.nsec);
2365 if (!s.period)
2366 return 0;
2367
2368 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
2369 s.pulse = ktime_set(req->on.sec, req->on.nsec);
2370 s.duty = ktime_divns(s.pulse * 100, s.period);
2371 }
2372
2373 if (req->flags & PTP_PEROUT_PHASE)
2374 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
2375 else
2376 s.start = ktime_set(req->start.sec, req->start.nsec);
2377
2378 return ptp_ocp_signal_set(bp, gen, &s);
2379 }
2380
2381 static int
ptp_ocp_signal_enable(void * priv,u32 req,bool enable)2382 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
2383 {
2384 struct ptp_ocp_ext_src *ext = priv;
2385 struct signal_reg __iomem *reg = ext->mem;
2386 struct ptp_ocp *bp = ext->bp;
2387 struct timespec64 ts;
2388 int gen;
2389
2390 gen = ext->info->index - 1;
2391
2392 iowrite32(0, ®->intr_mask);
2393 iowrite32(0, ®->enable);
2394 bp->signal[gen].running = false;
2395 if (!enable)
2396 return 0;
2397
2398 ts = ktime_to_timespec64(bp->signal[gen].start);
2399 iowrite32(ts.tv_sec, ®->start_sec);
2400 iowrite32(ts.tv_nsec, ®->start_ns);
2401
2402 ts = ktime_to_timespec64(bp->signal[gen].period);
2403 iowrite32(ts.tv_sec, ®->period_sec);
2404 iowrite32(ts.tv_nsec, ®->period_ns);
2405
2406 ts = ktime_to_timespec64(bp->signal[gen].pulse);
2407 iowrite32(ts.tv_sec, ®->pulse_sec);
2408 iowrite32(ts.tv_nsec, ®->pulse_ns);
2409
2410 iowrite32(bp->signal[gen].polarity, ®->polarity);
2411 iowrite32(0, ®->repeat_count);
2412
2413 iowrite32(0, ®->intr); /* clear interrupt state */
2414 iowrite32(1, ®->intr_mask); /* enable interrupt */
2415 iowrite32(3, ®->enable); /* valid & enable */
2416
2417 bp->signal[gen].running = true;
2418
2419 return 0;
2420 }
2421
2422 static irqreturn_t
ptp_ocp_ts_irq(int irq,void * priv)2423 ptp_ocp_ts_irq(int irq, void *priv)
2424 {
2425 struct ptp_ocp_ext_src *ext = priv;
2426 struct ts_reg __iomem *reg = ext->mem;
2427 struct ptp_clock_event ev;
2428 u32 sec, nsec;
2429
2430 if (ext == ext->bp->pps) {
2431 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
2432 ev.type = PTP_CLOCK_PPS;
2433 ptp_clock_event(ext->bp->ptp, &ev);
2434 }
2435
2436 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
2437 goto out;
2438 }
2439
2440 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
2441 sec = ioread32(®->time_sec);
2442 nsec = ioread32(®->time_ns);
2443
2444 ev.type = PTP_CLOCK_EXTTS;
2445 ev.index = ext->info->index;
2446 ev.timestamp = sec * NSEC_PER_SEC + nsec;
2447
2448 ptp_clock_event(ext->bp->ptp, &ev);
2449
2450 out:
2451 iowrite32(1, ®->intr); /* write 1 to ack */
2452
2453 return IRQ_HANDLED;
2454 }
2455
2456 static int
ptp_ocp_ts_enable(void * priv,u32 req,bool enable)2457 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
2458 {
2459 struct ptp_ocp_ext_src *ext = priv;
2460 struct ts_reg __iomem *reg = ext->mem;
2461 struct ptp_ocp *bp = ext->bp;
2462
2463 if (ext == bp->pps) {
2464 u32 old_map = bp->pps_req_map;
2465
2466 if (enable)
2467 bp->pps_req_map |= req;
2468 else
2469 bp->pps_req_map &= ~req;
2470
2471 /* if no state change, just return */
2472 if ((!!old_map ^ !!bp->pps_req_map) == 0)
2473 return 0;
2474 }
2475
2476 if (enable) {
2477 iowrite32(1, ®->enable);
2478 iowrite32(1, ®->intr_mask);
2479 iowrite32(1, ®->intr);
2480 } else {
2481 int irq_vec = pci_irq_vector(bp->pdev, ext->irq_vec);
2482
2483 iowrite32(0, ®->intr_mask);
2484 iowrite32(0, ®->enable);
2485 ioread32(®->intr_mask);
2486 if (irq_vec > 0)
2487 synchronize_irq(irq_vec);
2488 }
2489
2490 return 0;
2491 }
2492
2493 static void
ptp_ocp_unregister_ext(struct ptp_ocp_ext_src * ext)2494 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
2495 {
2496 if (!ext)
2497 return;
2498
2499 ext->info->enable(ext, ~0, false);
2500 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
2501 kfree(ext);
2502 }
2503
2504 static int
ptp_ocp_register_ext(struct ptp_ocp * bp,struct ocp_resource * r)2505 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2506 {
2507 struct pci_dev *pdev = bp->pdev;
2508 struct ptp_ocp_ext_src *ext;
2509 int err;
2510
2511 ext = kzalloc_obj(*ext);
2512 if (!ext)
2513 return -ENOMEM;
2514
2515 ext->mem = ptp_ocp_get_mem(bp, r);
2516 if (IS_ERR(ext->mem)) {
2517 err = PTR_ERR(ext->mem);
2518 goto out;
2519 }
2520
2521 ext->bp = bp;
2522 ext->info = r->extra;
2523 ext->irq_vec = r->irq_vec;
2524
2525 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2526 ext, "ocp%d.%s", bp->id, r->name);
2527 if (err) {
2528 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2529 goto out;
2530 }
2531
2532 bp_assign_entry(bp, r, ext);
2533
2534 return 0;
2535
2536 out:
2537 kfree(ext);
2538 return err;
2539 }
2540
2541 static int
ptp_ocp_serial_line(struct ptp_ocp * bp,struct ocp_resource * r)2542 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2543 {
2544 struct pci_dev *pdev = bp->pdev;
2545 struct uart_8250_port uart;
2546
2547 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2548 * the serial port device claim and release the pci resource.
2549 */
2550 memset(&uart, 0, sizeof(uart));
2551 uart.port.dev = &pdev->dev;
2552 uart.port.iotype = UPIO_MEM;
2553 uart.port.regshift = 2;
2554 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2555 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2556 uart.port.uartclk = 50000000;
2557 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2558 uart.port.type = PORT_16550A;
2559
2560 return serial8250_register_8250_port(&uart);
2561 }
2562
2563 static int
ptp_ocp_register_serial(struct ptp_ocp * bp,struct ocp_resource * r)2564 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2565 {
2566 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2567 struct ptp_ocp_serial_port port = {};
2568
2569 port.line = ptp_ocp_serial_line(bp, r);
2570 if (port.line < 0)
2571 return port.line;
2572
2573 if (p)
2574 port.baud = p->baud;
2575
2576 bp_assign_entry(bp, r, port);
2577
2578 return 0;
2579 }
2580
2581 static int
ptp_ocp_register_mem(struct ptp_ocp * bp,struct ocp_resource * r)2582 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2583 {
2584 void __iomem *mem;
2585
2586 mem = ptp_ocp_get_mem(bp, r);
2587 if (IS_ERR(mem))
2588 return PTR_ERR(mem);
2589
2590 bp_assign_entry(bp, r, mem);
2591
2592 return 0;
2593 }
2594
2595 static void
ptp_ocp_nmea_out_init(struct ptp_ocp * bp)2596 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2597 {
2598 if (!bp->nmea_out)
2599 return;
2600
2601 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2602 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2603 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2604 }
2605
2606 static void
_ptp_ocp_signal_init(struct ptp_ocp_signal * s,struct signal_reg __iomem * reg)2607 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2608 {
2609 u32 val;
2610
2611 iowrite32(0, ®->enable); /* disable */
2612
2613 val = ioread32(®->polarity);
2614 s->polarity = val ? true : false;
2615 s->duty = 50;
2616 }
2617
2618 static void
ptp_ocp_signal_init(struct ptp_ocp * bp)2619 ptp_ocp_signal_init(struct ptp_ocp *bp)
2620 {
2621 int i;
2622
2623 for (i = 0; i < 4; i++)
2624 if (bp->signal_out[i])
2625 _ptp_ocp_signal_init(&bp->signal[i],
2626 bp->signal_out[i]->mem);
2627 }
2628
2629 static void
ptp_ocp_attr_group_del(struct ptp_ocp * bp)2630 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2631 {
2632 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2633 kfree(bp->attr_group);
2634 }
2635
2636 static int
ptp_ocp_attr_group_add(struct ptp_ocp * bp,const struct ocp_attr_group * attr_tbl)2637 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2638 const struct ocp_attr_group *attr_tbl)
2639 {
2640 int count, i;
2641 int err;
2642
2643 count = 0;
2644 for (i = 0; attr_tbl[i].cap; i++)
2645 if (attr_tbl[i].cap & bp->fw_cap)
2646 count++;
2647
2648 bp->attr_group = kzalloc_objs(*bp->attr_group, count + 1);
2649 if (!bp->attr_group)
2650 return -ENOMEM;
2651
2652 count = 0;
2653 for (i = 0; attr_tbl[i].cap; i++)
2654 if (attr_tbl[i].cap & bp->fw_cap)
2655 bp->attr_group[count++] = attr_tbl[i].group;
2656
2657 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2658 if (err)
2659 bp->attr_group[0] = NULL;
2660
2661 return err;
2662 }
2663
2664 static void
ptp_ocp_enable_fpga(u32 __iomem * reg,u32 bit,bool enable)2665 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2666 {
2667 u32 ctrl;
2668 bool on;
2669
2670 ctrl = ioread32(reg);
2671 on = ctrl & bit;
2672 if (on ^ enable) {
2673 ctrl &= ~bit;
2674 ctrl |= enable ? bit : 0;
2675 iowrite32(ctrl, reg);
2676 }
2677 }
2678
2679 static void
ptp_ocp_irig_out(struct ptp_ocp * bp,bool enable)2680 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2681 {
2682 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2683 IRIG_M_CTRL_ENABLE, enable);
2684 }
2685
2686 static void
ptp_ocp_irig_in(struct ptp_ocp * bp,bool enable)2687 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2688 {
2689 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2690 IRIG_S_CTRL_ENABLE, enable);
2691 }
2692
2693 static void
ptp_ocp_dcf_out(struct ptp_ocp * bp,bool enable)2694 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2695 {
2696 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2697 DCF_M_CTRL_ENABLE, enable);
2698 }
2699
2700 static void
ptp_ocp_dcf_in(struct ptp_ocp * bp,bool enable)2701 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2702 {
2703 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2704 DCF_S_CTRL_ENABLE, enable);
2705 }
2706
2707 static void
__handle_signal_outputs(struct ptp_ocp * bp,u32 val)2708 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2709 {
2710 ptp_ocp_irig_out(bp, val & 0x00100010);
2711 ptp_ocp_dcf_out(bp, val & 0x00200020);
2712 }
2713
2714 static void
__handle_signal_inputs(struct ptp_ocp * bp,u32 val)2715 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2716 {
2717 ptp_ocp_irig_in(bp, val & 0x00100010);
2718 ptp_ocp_dcf_in(bp, val & 0x00200020);
2719 }
2720
2721 static u32
ptp_ocp_sma_fb_get(struct ptp_ocp * bp,int sma_nr)2722 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2723 {
2724 u32 __iomem *gpio;
2725 u32 shift;
2726
2727 if (bp->sma[sma_nr - 1].fixed_fcn)
2728 return (sma_nr - 1) & 1;
2729
2730 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2731 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2732 else
2733 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2734 shift = sma_nr & 1 ? 0 : 16;
2735
2736 return (ioread32(gpio) >> shift) & 0xffff;
2737 }
2738
2739 static int
ptp_ocp_sma_fb_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2740 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2741 {
2742 u32 reg, mask, shift;
2743 unsigned long flags;
2744 u32 __iomem *gpio;
2745
2746 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2747 shift = sma_nr & 1 ? 0 : 16;
2748
2749 mask = 0xffff << (16 - shift);
2750
2751 spin_lock_irqsave(&bp->lock, flags);
2752
2753 reg = ioread32(gpio);
2754 reg = (reg & mask) | (val << shift);
2755
2756 __handle_signal_outputs(bp, reg);
2757
2758 iowrite32(reg, gpio);
2759
2760 spin_unlock_irqrestore(&bp->lock, flags);
2761
2762 return 0;
2763 }
2764
2765 static int
ptp_ocp_sma_fb_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2766 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2767 {
2768 u32 reg, mask, shift;
2769 unsigned long flags;
2770 u32 __iomem *gpio;
2771
2772 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2773 shift = sma_nr & 1 ? 0 : 16;
2774
2775 mask = 0xffff << (16 - shift);
2776
2777 spin_lock_irqsave(&bp->lock, flags);
2778
2779 reg = ioread32(gpio);
2780 reg = (reg & mask) | (val << shift);
2781
2782 __handle_signal_inputs(bp, reg);
2783
2784 iowrite32(reg, gpio);
2785
2786 spin_unlock_irqrestore(&bp->lock, flags);
2787
2788 return 0;
2789 }
2790
2791 static void
ptp_ocp_sma_fb_init(struct ptp_ocp * bp)2792 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2793 {
2794 struct dpll_pin_properties prop = {
2795 .board_label = NULL,
2796 .type = DPLL_PIN_TYPE_EXT,
2797 .capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,
2798 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2799 .freq_supported = ptp_ocp_sma_freq,
2800
2801 };
2802 u32 reg;
2803 int i;
2804
2805 /* defaults */
2806 for (i = 0; i < OCP_SMA_NUM; i++) {
2807 bp->sma[i].default_fcn = i & 1;
2808 bp->sma[i].dpll_prop = prop;
2809 bp->sma[i].dpll_prop.board_label =
2810 bp->ptp_info.pin_config[i].name;
2811 }
2812 bp->sma[0].mode = SMA_MODE_IN;
2813 bp->sma[1].mode = SMA_MODE_IN;
2814 bp->sma[2].mode = SMA_MODE_OUT;
2815 bp->sma[3].mode = SMA_MODE_OUT;
2816 /* If no SMA1 map, the pin functions and directions are fixed. */
2817 if (!bp->sma_map1) {
2818 for (i = 0; i < OCP_SMA_NUM; i++) {
2819 bp->sma[i].fixed_fcn = true;
2820 bp->sma[i].fixed_dir = true;
2821 bp->sma[i].dpll_prop.capabilities &=
2822 ~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2823 }
2824 return;
2825 }
2826
2827 /* If SMA2 GPIO output map is all 1, it is not present.
2828 * This indicates the firmware has fixed direction SMA pins.
2829 */
2830 reg = ioread32(&bp->sma_map2->gpio2);
2831 if (reg == 0xffffffff) {
2832 for (i = 0; i < OCP_SMA_NUM; i++)
2833 bp->sma[i].fixed_dir = true;
2834 } else {
2835 reg = ioread32(&bp->sma_map1->gpio1);
2836 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2837 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2838
2839 reg = ioread32(&bp->sma_map1->gpio2);
2840 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2841 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2842 }
2843 }
2844
2845 static const struct ocp_sma_op ocp_fb_sma_op = {
2846 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2847 .init = ptp_ocp_sma_fb_init,
2848 .get = ptp_ocp_sma_fb_get,
2849 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2850 .set_output = ptp_ocp_sma_fb_set_output,
2851 };
2852
2853 static int
ptp_ocp_sma_adva_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2854 ptp_ocp_sma_adva_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2855 {
2856 u32 reg, mask, shift;
2857 unsigned long flags;
2858 u32 __iomem *gpio;
2859
2860 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2861 shift = sma_nr & 1 ? 0 : 16;
2862
2863 mask = 0xffff << (16 - shift);
2864
2865 spin_lock_irqsave(&bp->lock, flags);
2866
2867 reg = ioread32(gpio);
2868 reg = (reg & mask) | (val << shift);
2869
2870 iowrite32(reg, gpio);
2871
2872 spin_unlock_irqrestore(&bp->lock, flags);
2873
2874 return 0;
2875 }
2876
2877 static int
ptp_ocp_sma_adva_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2878 ptp_ocp_sma_adva_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2879 {
2880 u32 reg, mask, shift;
2881 unsigned long flags;
2882 u32 __iomem *gpio;
2883
2884 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2885 shift = sma_nr & 1 ? 0 : 16;
2886
2887 mask = 0xffff << (16 - shift);
2888
2889 spin_lock_irqsave(&bp->lock, flags);
2890
2891 reg = ioread32(gpio);
2892 reg = (reg & mask) | (val << shift);
2893
2894 iowrite32(reg, gpio);
2895
2896 spin_unlock_irqrestore(&bp->lock, flags);
2897
2898 return 0;
2899 }
2900
2901 static const struct ocp_sma_op ocp_adva_sma_op = {
2902 .tbl = { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out },
2903 .init = ptp_ocp_sma_fb_init,
2904 .get = ptp_ocp_sma_fb_get,
2905 .set_inputs = ptp_ocp_sma_adva_set_inputs,
2906 .set_output = ptp_ocp_sma_adva_set_output,
2907 };
2908
2909 static const struct ocp_sma_op ocp_adva_x1_sma_op = {
2910 .tbl = { ptp_ocp_adva_x1_sma_in, ptp_ocp_adva_x1_sma_out },
2911 .init = ptp_ocp_sma_fb_init,
2912 .get = ptp_ocp_sma_fb_get,
2913 .set_inputs = ptp_ocp_sma_adva_set_inputs,
2914 .set_output = ptp_ocp_sma_adva_set_output,
2915 };
2916
2917 static int
ptp_ocp_set_pins(struct ptp_ocp * bp)2918 ptp_ocp_set_pins(struct ptp_ocp *bp)
2919 {
2920 struct ptp_pin_desc *config;
2921 int i;
2922
2923 config = kzalloc_objs(*config, 4);
2924 if (!config)
2925 return -ENOMEM;
2926
2927 for (i = 0; i < 4; i++) {
2928 sprintf(config[i].name, "sma%d", i + 1);
2929 config[i].index = i;
2930 }
2931
2932 bp->ptp_info.n_pins = 4;
2933 bp->ptp_info.pin_config = config;
2934
2935 return 0;
2936 }
2937
2938 static void
ptp_ocp_fb_set_version(struct ptp_ocp * bp)2939 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2940 {
2941 u64 cap = OCP_CAP_BASIC;
2942 u32 version;
2943
2944 version = ioread32(&bp->image->version);
2945
2946 /* if lower 16 bits are empty, this is the fw loader. */
2947 if ((version & 0xffff) == 0) {
2948 version = version >> 16;
2949 bp->fw_loader = true;
2950 }
2951
2952 bp->fw_tag = version >> 15;
2953 bp->fw_version = version & 0x7fff;
2954
2955 if (bp->fw_tag) {
2956 /* FPGA firmware */
2957 if (version >= 5)
2958 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2959 } else {
2960 /* SOM firmware */
2961 if (version >= 19)
2962 cap |= OCP_CAP_SIGNAL;
2963 if (version >= 20)
2964 cap |= OCP_CAP_FREQ;
2965 }
2966
2967 bp->fw_cap = cap;
2968 }
2969
2970 /* FB specific board initializers; last "resource" registered. */
2971 static int
ptp_ocp_fb_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2972 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2973 {
2974 int err;
2975
2976 bp->flash_start = 1024 * 4096;
2977 bp->eeprom_map = fb_eeprom_map;
2978 bp->fw_version = ioread32(&bp->image->version);
2979 bp->sma_op = &ocp_fb_sma_op;
2980 bp->signals_nr = 4;
2981 bp->freq_in_nr = 4;
2982
2983 ptp_ocp_fb_set_version(bp);
2984
2985 ptp_ocp_tod_init(bp);
2986 ptp_ocp_nmea_out_init(bp);
2987 ptp_ocp_signal_init(bp);
2988
2989 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2990 if (err)
2991 return err;
2992
2993 err = ptp_ocp_set_pins(bp);
2994 if (err)
2995 return err;
2996 ptp_ocp_sma_init(bp);
2997
2998 return ptp_ocp_init_clock(bp, r->extra);
2999 }
3000
3001 static bool
ptp_ocp_allow_irq(struct ptp_ocp * bp,struct ocp_resource * r)3002 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
3003 {
3004 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
3005
3006 if (!allow)
3007 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
3008 r->irq_vec, r->name);
3009 return allow;
3010 }
3011
3012 static int
ptp_ocp_register_resources(struct ptp_ocp * bp,kernel_ulong_t driver_data)3013 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
3014 {
3015 struct ocp_resource *r, *table;
3016 int err = 0;
3017
3018 table = (struct ocp_resource *)driver_data;
3019 for (r = table; r->setup; r++) {
3020 if (!ptp_ocp_allow_irq(bp, r))
3021 continue;
3022 err = r->setup(bp, r);
3023 if (err) {
3024 dev_err(&bp->pdev->dev,
3025 "Could not register %s: err %d\n",
3026 r->name, err);
3027 break;
3028 }
3029 }
3030 return err;
3031 }
3032
3033 static void
ptp_ocp_art_sma_init(struct ptp_ocp * bp)3034 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
3035 {
3036 struct dpll_pin_properties prop = {
3037 .board_label = NULL,
3038 .type = DPLL_PIN_TYPE_EXT,
3039 .capabilities = 0,
3040 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
3041 .freq_supported = ptp_ocp_sma_freq,
3042
3043 };
3044 u32 reg;
3045 int i;
3046
3047 /* defaults */
3048 bp->sma[0].mode = SMA_MODE_IN;
3049 bp->sma[1].mode = SMA_MODE_IN;
3050 bp->sma[2].mode = SMA_MODE_OUT;
3051 bp->sma[3].mode = SMA_MODE_OUT;
3052
3053 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
3054 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
3055 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
3056 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
3057
3058 for (i = 0; i < OCP_SMA_NUM; i++) {
3059 /* If no SMA map, the pin functions and directions are fixed. */
3060 bp->sma[i].dpll_prop = prop;
3061 bp->sma[i].dpll_prop.board_label =
3062 bp->ptp_info.pin_config[i].name;
3063 if (!bp->art_sma) {
3064 bp->sma[i].fixed_fcn = true;
3065 bp->sma[i].fixed_dir = true;
3066 continue;
3067 }
3068 reg = ioread32(&bp->art_sma->map[i].gpio);
3069
3070 switch (reg & 0xff) {
3071 case 0:
3072 bp->sma[i].fixed_fcn = true;
3073 bp->sma[i].fixed_dir = true;
3074 break;
3075 case 1:
3076 case 8:
3077 bp->sma[i].mode = SMA_MODE_IN;
3078 bp->sma[i].dpll_prop.capabilities =
3079 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
3080 break;
3081 default:
3082 bp->sma[i].mode = SMA_MODE_OUT;
3083 bp->sma[i].dpll_prop.capabilities =
3084 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
3085 break;
3086 }
3087 }
3088 }
3089
3090 static u32
ptp_ocp_art_sma_get(struct ptp_ocp * bp,int sma_nr)3091 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
3092 {
3093 if (bp->sma[sma_nr - 1].fixed_fcn)
3094 return bp->sma[sma_nr - 1].default_fcn;
3095
3096 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
3097 }
3098
3099 /* note: store 0 is considered invalid. */
3100 static int
ptp_ocp_art_sma_set(struct ptp_ocp * bp,int sma_nr,u32 val)3101 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
3102 {
3103 unsigned long flags;
3104 u32 __iomem *gpio;
3105 int err = 0;
3106 u32 reg;
3107
3108 val &= SMA_SELECT_MASK;
3109 if (hweight32(val) > 1)
3110 return -EINVAL;
3111
3112 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
3113
3114 spin_lock_irqsave(&bp->lock, flags);
3115 reg = ioread32(gpio);
3116 if (((reg >> 16) & val) == 0) {
3117 err = -EOPNOTSUPP;
3118 } else {
3119 reg = (reg & 0xff00) | (val & 0xff);
3120 iowrite32(reg, gpio);
3121 }
3122 spin_unlock_irqrestore(&bp->lock, flags);
3123
3124 return err;
3125 }
3126
3127 static const struct ocp_sma_op ocp_art_sma_op = {
3128 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
3129 .init = ptp_ocp_art_sma_init,
3130 .get = ptp_ocp_art_sma_get,
3131 .set_inputs = ptp_ocp_art_sma_set,
3132 .set_output = ptp_ocp_art_sma_set,
3133 };
3134
3135 /* ART specific board initializers; last "resource" registered. */
3136 static int
ptp_ocp_art_board_init(struct ptp_ocp * bp,struct ocp_resource * r)3137 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
3138 {
3139 int err;
3140
3141 bp->flash_start = 0x1000000;
3142 bp->eeprom_map = art_eeprom_map;
3143 bp->fw_cap = OCP_CAP_BASIC;
3144 bp->fw_version = ioread32(&bp->reg->version);
3145 bp->fw_tag = 2;
3146 bp->sma_op = &ocp_art_sma_op;
3147 bp->signals_nr = 4;
3148 bp->freq_in_nr = 4;
3149
3150 /* Enable MAC serial port during initialisation */
3151 iowrite32(1, &bp->board_config->mro50_serial_activate);
3152
3153 err = ptp_ocp_set_pins(bp);
3154 if (err)
3155 return err;
3156 ptp_ocp_sma_init(bp);
3157
3158 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
3159 if (err)
3160 return err;
3161
3162 return ptp_ocp_init_clock(bp, r->extra);
3163 }
3164
3165 /* ADVA board initializer; variant differences come from r->extra. */
3166 static int
ptp_ocp_adva_board_init(struct ptp_ocp * bp,struct ocp_resource * r)3167 ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
3168 {
3169 struct ptp_ocp_adva_info *info = r->extra;
3170 u32 version;
3171 int err;
3172
3173 bp->flash_start = info->flash_start;
3174 bp->eeprom_map = fb_eeprom_map;
3175 bp->sma_op = info->sma_op;
3176 bp->signals_nr = info->signals_nr;
3177 bp->freq_in_nr = info->freq_in_nr;
3178
3179 version = ioread32(&bp->image->version);
3180 /* if lower 16 bits are empty, this is the fw loader. */
3181 if ((version & 0xffff) == 0) {
3182 version = version >> 16;
3183 bp->fw_loader = true;
3184 }
3185 bp->fw_tag = 3;
3186 bp->fw_version = version & 0xffff;
3187 bp->fw_cap = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ;
3188
3189 ptp_ocp_tod_init(bp);
3190 ptp_ocp_nmea_out_init(bp);
3191 ptp_ocp_signal_init(bp);
3192
3193 err = ptp_ocp_attr_group_add(bp, info->attr_groups);
3194 if (err)
3195 return err;
3196
3197 err = ptp_ocp_set_pins(bp);
3198 if (err)
3199 return err;
3200 ptp_ocp_sma_init(bp);
3201
3202 return ptp_ocp_init_clock(bp, &info->servo);
3203 }
3204
3205 static ssize_t
ptp_ocp_show_output(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)3206 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
3207 int def_val)
3208 {
3209 const char *name;
3210 ssize_t count;
3211
3212 count = sysfs_emit(buf, "OUT: ");
3213 name = ptp_ocp_select_name_from_val(tbl, val);
3214 if (!name)
3215 name = ptp_ocp_select_name_from_val(tbl, def_val);
3216 count += sysfs_emit_at(buf, count, "%s\n", name);
3217 return count;
3218 }
3219
3220 static ssize_t
ptp_ocp_show_inputs(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)3221 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
3222 int def_val)
3223 {
3224 const char *name;
3225 ssize_t count;
3226 int i;
3227
3228 count = sysfs_emit(buf, "IN: ");
3229 for (i = 0; tbl[i].name; i++) {
3230 if (val & tbl[i].value) {
3231 name = tbl[i].name;
3232 count += sysfs_emit_at(buf, count, "%s ", name);
3233 }
3234 }
3235 if (!val && def_val >= 0) {
3236 name = ptp_ocp_select_name_from_val(tbl, def_val);
3237 count += sysfs_emit_at(buf, count, "%s ", name);
3238 }
3239 if (count)
3240 count--;
3241 count += sysfs_emit_at(buf, count, "\n");
3242 return count;
3243 }
3244
3245 static int
sma_parse_inputs(const struct ocp_selector * const tbl[],const char * buf,enum ptp_ocp_sma_mode * mode)3246 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
3247 enum ptp_ocp_sma_mode *mode)
3248 {
3249 int idx, count, dir;
3250 char **argv;
3251 int ret;
3252
3253 argv = argv_split(GFP_KERNEL, buf, &count);
3254 if (!argv)
3255 return -ENOMEM;
3256
3257 ret = -EINVAL;
3258 if (!count)
3259 goto out;
3260
3261 idx = 0;
3262 dir = *mode == SMA_MODE_IN ? 0 : 1;
3263 if (!strcasecmp("IN:", argv[0])) {
3264 dir = 0;
3265 idx++;
3266 }
3267 if (!strcasecmp("OUT:", argv[0])) {
3268 dir = 1;
3269 idx++;
3270 }
3271 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
3272
3273 ret = 0;
3274 for (; idx < count; idx++)
3275 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
3276 if (ret < 0)
3277 ret = -EINVAL;
3278
3279 out:
3280 argv_free(argv);
3281 return ret;
3282 }
3283
3284 static ssize_t
ptp_ocp_sma_show(struct ptp_ocp * bp,int sma_nr,char * buf,int default_in_val,int default_out_val)3285 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
3286 int default_in_val, int default_out_val)
3287 {
3288 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3289 const struct ocp_selector * const *tbl;
3290 u32 val;
3291
3292 tbl = bp->sma_op->tbl;
3293 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
3294
3295 if (sma->mode == SMA_MODE_IN) {
3296 if (sma->disabled)
3297 val = SMA_DISABLE;
3298 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
3299 }
3300
3301 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
3302 }
3303
3304 static ssize_t
sma1_show(struct device * dev,struct device_attribute * attr,char * buf)3305 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
3306 {
3307 struct ptp_ocp *bp = dev_get_drvdata(dev);
3308
3309 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
3310 }
3311
3312 static ssize_t
sma2_show(struct device * dev,struct device_attribute * attr,char * buf)3313 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
3314 {
3315 struct ptp_ocp *bp = dev_get_drvdata(dev);
3316
3317 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
3318 }
3319
3320 static ssize_t
sma3_show(struct device * dev,struct device_attribute * attr,char * buf)3321 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
3322 {
3323 struct ptp_ocp *bp = dev_get_drvdata(dev);
3324
3325 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
3326 }
3327
3328 static ssize_t
sma4_show(struct device * dev,struct device_attribute * attr,char * buf)3329 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
3330 {
3331 struct ptp_ocp *bp = dev_get_drvdata(dev);
3332
3333 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
3334 }
3335
3336 static int
ptp_ocp_sma_store_val(struct ptp_ocp * bp,int val,enum ptp_ocp_sma_mode mode,int sma_nr)3337 ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)
3338 {
3339 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3340
3341 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
3342 return -EOPNOTSUPP;
3343
3344 if (sma->fixed_fcn) {
3345 if (val != sma->default_fcn)
3346 return -EOPNOTSUPP;
3347 return 0;
3348 }
3349
3350 sma->disabled = !!(val & SMA_DISABLE);
3351
3352 if (mode != sma->mode) {
3353 if (mode == SMA_MODE_IN)
3354 ptp_ocp_sma_set_output(bp, sma_nr, 0);
3355 else
3356 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
3357 sma->mode = mode;
3358 }
3359
3360 if (!sma->fixed_dir)
3361 val |= SMA_ENABLE; /* add enable bit */
3362
3363 if (sma->disabled)
3364 val = 0;
3365
3366 if (mode == SMA_MODE_IN)
3367 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
3368 else
3369 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
3370
3371 return val;
3372 }
3373
3374 static int
ptp_ocp_sma_store(struct ptp_ocp * bp,const char * buf,int sma_nr)3375 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
3376 {
3377 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3378 enum ptp_ocp_sma_mode mode;
3379 int val;
3380
3381 mode = sma->mode;
3382 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
3383 if (val < 0)
3384 return val;
3385 return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);
3386 }
3387
3388 static ssize_t
sma1_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3389 sma1_store(struct device *dev, struct device_attribute *attr,
3390 const char *buf, size_t count)
3391 {
3392 struct ptp_ocp *bp = dev_get_drvdata(dev);
3393 int err;
3394
3395 err = ptp_ocp_sma_store(bp, buf, 1);
3396 return err ? err : count;
3397 }
3398
3399 static ssize_t
sma2_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3400 sma2_store(struct device *dev, struct device_attribute *attr,
3401 const char *buf, size_t count)
3402 {
3403 struct ptp_ocp *bp = dev_get_drvdata(dev);
3404 int err;
3405
3406 err = ptp_ocp_sma_store(bp, buf, 2);
3407 return err ? err : count;
3408 }
3409
3410 static ssize_t
sma3_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3411 sma3_store(struct device *dev, struct device_attribute *attr,
3412 const char *buf, size_t count)
3413 {
3414 struct ptp_ocp *bp = dev_get_drvdata(dev);
3415 int err;
3416
3417 err = ptp_ocp_sma_store(bp, buf, 3);
3418 return err ? err : count;
3419 }
3420
3421 static ssize_t
sma4_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3422 sma4_store(struct device *dev, struct device_attribute *attr,
3423 const char *buf, size_t count)
3424 {
3425 struct ptp_ocp *bp = dev_get_drvdata(dev);
3426 int err;
3427
3428 err = ptp_ocp_sma_store(bp, buf, 4);
3429 return err ? err : count;
3430 }
3431 static DEVICE_ATTR_RW(sma1);
3432 static DEVICE_ATTR_RW(sma2);
3433 static DEVICE_ATTR_RW(sma3);
3434 static DEVICE_ATTR_RW(sma4);
3435
3436 static ssize_t
available_sma_inputs_show(struct device * dev,struct device_attribute * attr,char * buf)3437 available_sma_inputs_show(struct device *dev,
3438 struct device_attribute *attr, char *buf)
3439 {
3440 struct ptp_ocp *bp = dev_get_drvdata(dev);
3441
3442 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
3443 }
3444 static DEVICE_ATTR_RO(available_sma_inputs);
3445
3446 static ssize_t
available_sma_outputs_show(struct device * dev,struct device_attribute * attr,char * buf)3447 available_sma_outputs_show(struct device *dev,
3448 struct device_attribute *attr, char *buf)
3449 {
3450 struct ptp_ocp *bp = dev_get_drvdata(dev);
3451
3452 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
3453 }
3454 static DEVICE_ATTR_RO(available_sma_outputs);
3455
3456 #define EXT_ATTR_RO(_group, _name, _val) \
3457 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3458 { __ATTR_RO(_name), (void *)_val }
3459 #define EXT_ATTR_RW(_group, _name, _val) \
3460 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3461 { __ATTR_RW(_name), (void *)_val }
3462 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
3463
3464 /* period [duty [phase [polarity]]] */
3465 static ssize_t
signal_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3466 signal_store(struct device *dev, struct device_attribute *attr,
3467 const char *buf, size_t count)
3468 {
3469 struct dev_ext_attribute *ea = to_ext_attr(attr);
3470 struct ptp_ocp *bp = dev_get_drvdata(dev);
3471 struct ptp_ocp_signal s = { };
3472 int gen = (uintptr_t)ea->var;
3473 int argc, err;
3474 char **argv;
3475
3476 argv = argv_split(GFP_KERNEL, buf, &argc);
3477 if (!argv)
3478 return -ENOMEM;
3479
3480 err = -EINVAL;
3481 s.duty = bp->signal[gen].duty;
3482 s.phase = bp->signal[gen].phase;
3483 s.period = bp->signal[gen].period;
3484 s.polarity = bp->signal[gen].polarity;
3485
3486 switch (argc) {
3487 case 4:
3488 argc--;
3489 err = kstrtobool(argv[argc], &s.polarity);
3490 if (err)
3491 goto out;
3492 fallthrough;
3493 case 3:
3494 argc--;
3495 err = kstrtou64(argv[argc], 0, &s.phase);
3496 if (err)
3497 goto out;
3498 fallthrough;
3499 case 2:
3500 argc--;
3501 err = kstrtoint(argv[argc], 0, &s.duty);
3502 if (err)
3503 goto out;
3504 fallthrough;
3505 case 1:
3506 argc--;
3507 err = kstrtou64(argv[argc], 0, &s.period);
3508 if (err)
3509 goto out;
3510 break;
3511 default:
3512 goto out;
3513 }
3514
3515 err = ptp_ocp_signal_set(bp, gen, &s);
3516 if (err)
3517 goto out;
3518
3519 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
3520
3521 out:
3522 argv_free(argv);
3523 return err ? err : count;
3524 }
3525
3526 static ssize_t
signal_show(struct device * dev,struct device_attribute * attr,char * buf)3527 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
3528 {
3529 struct dev_ext_attribute *ea = to_ext_attr(attr);
3530 struct ptp_ocp *bp = dev_get_drvdata(dev);
3531 struct ptp_ocp_signal *signal;
3532 int gen = (uintptr_t)ea->var;
3533 struct timespec64 ts;
3534
3535 signal = &bp->signal[gen];
3536
3537 ts = ktime_to_timespec64(signal->start);
3538
3539 return sysfs_emit(buf, "%llu %d %llu %d %ptT TAI\n",
3540 signal->period, signal->duty, signal->phase, signal->polarity,
3541 &ts.tv_sec);
3542 }
3543 static EXT_ATTR_RW(signal, signal, 0);
3544 static EXT_ATTR_RW(signal, signal, 1);
3545 static EXT_ATTR_RW(signal, signal, 2);
3546 static EXT_ATTR_RW(signal, signal, 3);
3547
3548 static ssize_t
duty_show(struct device * dev,struct device_attribute * attr,char * buf)3549 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
3550 {
3551 struct dev_ext_attribute *ea = to_ext_attr(attr);
3552 struct ptp_ocp *bp = dev_get_drvdata(dev);
3553 int i = (uintptr_t)ea->var;
3554
3555 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
3556 }
3557 static EXT_ATTR_RO(signal, duty, 0);
3558 static EXT_ATTR_RO(signal, duty, 1);
3559 static EXT_ATTR_RO(signal, duty, 2);
3560 static EXT_ATTR_RO(signal, duty, 3);
3561
3562 static ssize_t
period_show(struct device * dev,struct device_attribute * attr,char * buf)3563 period_show(struct device *dev, struct device_attribute *attr, char *buf)
3564 {
3565 struct dev_ext_attribute *ea = to_ext_attr(attr);
3566 struct ptp_ocp *bp = dev_get_drvdata(dev);
3567 int i = (uintptr_t)ea->var;
3568
3569 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
3570 }
3571 static EXT_ATTR_RO(signal, period, 0);
3572 static EXT_ATTR_RO(signal, period, 1);
3573 static EXT_ATTR_RO(signal, period, 2);
3574 static EXT_ATTR_RO(signal, period, 3);
3575
3576 static ssize_t
phase_show(struct device * dev,struct device_attribute * attr,char * buf)3577 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
3578 {
3579 struct dev_ext_attribute *ea = to_ext_attr(attr);
3580 struct ptp_ocp *bp = dev_get_drvdata(dev);
3581 int i = (uintptr_t)ea->var;
3582
3583 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
3584 }
3585 static EXT_ATTR_RO(signal, phase, 0);
3586 static EXT_ATTR_RO(signal, phase, 1);
3587 static EXT_ATTR_RO(signal, phase, 2);
3588 static EXT_ATTR_RO(signal, phase, 3);
3589
3590 static ssize_t
polarity_show(struct device * dev,struct device_attribute * attr,char * buf)3591 polarity_show(struct device *dev, struct device_attribute *attr,
3592 char *buf)
3593 {
3594 struct dev_ext_attribute *ea = to_ext_attr(attr);
3595 struct ptp_ocp *bp = dev_get_drvdata(dev);
3596 int i = (uintptr_t)ea->var;
3597
3598 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
3599 }
3600 static EXT_ATTR_RO(signal, polarity, 0);
3601 static EXT_ATTR_RO(signal, polarity, 1);
3602 static EXT_ATTR_RO(signal, polarity, 2);
3603 static EXT_ATTR_RO(signal, polarity, 3);
3604
3605 static ssize_t
running_show(struct device * dev,struct device_attribute * attr,char * buf)3606 running_show(struct device *dev, struct device_attribute *attr, char *buf)
3607 {
3608 struct dev_ext_attribute *ea = to_ext_attr(attr);
3609 struct ptp_ocp *bp = dev_get_drvdata(dev);
3610 int i = (uintptr_t)ea->var;
3611
3612 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
3613 }
3614 static EXT_ATTR_RO(signal, running, 0);
3615 static EXT_ATTR_RO(signal, running, 1);
3616 static EXT_ATTR_RO(signal, running, 2);
3617 static EXT_ATTR_RO(signal, running, 3);
3618
3619 static ssize_t
start_show(struct device * dev,struct device_attribute * attr,char * buf)3620 start_show(struct device *dev, struct device_attribute *attr, char *buf)
3621 {
3622 struct dev_ext_attribute *ea = to_ext_attr(attr);
3623 struct ptp_ocp *bp = dev_get_drvdata(dev);
3624 int i = (uintptr_t)ea->var;
3625 struct timespec64 ts;
3626
3627 ts = ktime_to_timespec64(bp->signal[i].start);
3628 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
3629 }
3630 static EXT_ATTR_RO(signal, start, 0);
3631 static EXT_ATTR_RO(signal, start, 1);
3632 static EXT_ATTR_RO(signal, start, 2);
3633 static EXT_ATTR_RO(signal, start, 3);
3634
3635 static ssize_t
seconds_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3636 seconds_store(struct device *dev, struct device_attribute *attr,
3637 const char *buf, size_t count)
3638 {
3639 struct dev_ext_attribute *ea = to_ext_attr(attr);
3640 struct ptp_ocp *bp = dev_get_drvdata(dev);
3641 int idx = (uintptr_t)ea->var;
3642 u32 val;
3643 int err;
3644
3645 err = kstrtou32(buf, 0, &val);
3646 if (err)
3647 return err;
3648 if (val > 0xff)
3649 return -EINVAL;
3650
3651 if (val)
3652 val = (val << 8) | 0x1;
3653
3654 iowrite32(val, &bp->freq_in[idx]->ctrl);
3655
3656 return count;
3657 }
3658
3659 static ssize_t
seconds_show(struct device * dev,struct device_attribute * attr,char * buf)3660 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3661 {
3662 struct dev_ext_attribute *ea = to_ext_attr(attr);
3663 struct ptp_ocp *bp = dev_get_drvdata(dev);
3664 int idx = (uintptr_t)ea->var;
3665 u32 val;
3666
3667 val = ioread32(&bp->freq_in[idx]->ctrl);
3668 if (val & 1)
3669 val = (val >> 8) & 0xff;
3670 else
3671 val = 0;
3672
3673 return sysfs_emit(buf, "%u\n", val);
3674 }
3675 static EXT_ATTR_RW(freq, seconds, 0);
3676 static EXT_ATTR_RW(freq, seconds, 1);
3677 static EXT_ATTR_RW(freq, seconds, 2);
3678 static EXT_ATTR_RW(freq, seconds, 3);
3679
3680 static ssize_t
frequency_show(struct device * dev,struct device_attribute * attr,char * buf)3681 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3682 {
3683 struct dev_ext_attribute *ea = to_ext_attr(attr);
3684 struct ptp_ocp *bp = dev_get_drvdata(dev);
3685 int idx = (uintptr_t)ea->var;
3686 u32 val;
3687
3688 val = ioread32(&bp->freq_in[idx]->status);
3689 if (val & FREQ_STATUS_ERROR)
3690 return sysfs_emit(buf, "error\n");
3691 if (val & FREQ_STATUS_OVERRUN)
3692 return sysfs_emit(buf, "overrun\n");
3693 if (val & FREQ_STATUS_VALID)
3694 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3695 return 0;
3696 }
3697 static EXT_ATTR_RO(freq, frequency, 0);
3698 static EXT_ATTR_RO(freq, frequency, 1);
3699 static EXT_ATTR_RO(freq, frequency, 2);
3700 static EXT_ATTR_RO(freq, frequency, 3);
3701
3702 static ssize_t
ptp_ocp_tty_show(struct device * dev,struct device_attribute * attr,char * buf)3703 ptp_ocp_tty_show(struct device *dev, struct device_attribute *attr, char *buf)
3704 {
3705 struct dev_ext_attribute *ea = to_ext_attr(attr);
3706 struct ptp_ocp *bp = dev_get_drvdata(dev);
3707
3708 /*
3709 * NOTE: This output does not include a trailing newline for backward
3710 * compatibility. Existing userspace software uses this value directly
3711 * as a device path (e.g., "/dev/ttyS4"), and adding a newline would
3712 * break those applications. Do not add a newline to this output.
3713 */
3714 return sysfs_emit(buf, "ttyS%d", bp->port[(uintptr_t)ea->var].line);
3715 }
3716
3717 static umode_t
ptp_ocp_timecard_tty_is_visible(struct kobject * kobj,struct attribute * attr,int n)3718 ptp_ocp_timecard_tty_is_visible(struct kobject *kobj, struct attribute *attr, int n)
3719 {
3720 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3721 struct ptp_ocp_serial_port *port;
3722 struct device_attribute *dattr;
3723 struct dev_ext_attribute *ea;
3724
3725 if (strncmp(attr->name, "tty", 3))
3726 return attr->mode;
3727
3728 dattr = container_of(attr, struct device_attribute, attr);
3729 ea = container_of(dattr, struct dev_ext_attribute, attr);
3730 port = &bp->port[(uintptr_t)ea->var];
3731 return port->line == -1 ? 0 : 0444;
3732 }
3733
3734 #define EXT_TTY_ATTR_RO(_name, _val) \
3735 struct dev_ext_attribute dev_attr_tty##_name = \
3736 { __ATTR(tty##_name, 0444, ptp_ocp_tty_show, NULL), (void *)_val }
3737
3738 static EXT_TTY_ATTR_RO(GNSS, PORT_GNSS);
3739 static EXT_TTY_ATTR_RO(GNSS2, PORT_GNSS2);
3740 static EXT_TTY_ATTR_RO(MAC, PORT_MAC);
3741 static EXT_TTY_ATTR_RO(NMEA, PORT_NMEA);
3742 static struct attribute *ptp_ocp_timecard_tty_attrs[] = {
3743 &dev_attr_ttyGNSS.attr.attr,
3744 &dev_attr_ttyGNSS2.attr.attr,
3745 &dev_attr_ttyMAC.attr.attr,
3746 &dev_attr_ttyNMEA.attr.attr,
3747 NULL,
3748 };
3749
3750 static const struct attribute_group ptp_ocp_timecard_tty_group = {
3751 .name = "tty",
3752 .attrs = ptp_ocp_timecard_tty_attrs,
3753 .is_visible = ptp_ocp_timecard_tty_is_visible,
3754 };
3755
3756 static ssize_t
serialnum_show(struct device * dev,struct device_attribute * attr,char * buf)3757 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3758 {
3759 struct ptp_ocp *bp = dev_get_drvdata(dev);
3760
3761 if (!bp->has_eeprom_data)
3762 ptp_ocp_read_eeprom(bp);
3763
3764 return sysfs_emit(buf, "%pM\n", bp->serial);
3765 }
3766 static DEVICE_ATTR_RO(serialnum);
3767
3768 static ssize_t
gnss_sync_show(struct device * dev,struct device_attribute * attr,char * buf)3769 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3770 {
3771 struct ptp_ocp *bp = dev_get_drvdata(dev);
3772 ssize_t ret;
3773
3774 if (bp->gnss_lost)
3775 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3776 else
3777 ret = sysfs_emit(buf, "SYNC\n");
3778
3779 return ret;
3780 }
3781 static DEVICE_ATTR_RO(gnss_sync);
3782
3783 static ssize_t
utc_tai_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3784 utc_tai_offset_show(struct device *dev,
3785 struct device_attribute *attr, char *buf)
3786 {
3787 struct ptp_ocp *bp = dev_get_drvdata(dev);
3788
3789 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3790 }
3791
3792 static ssize_t
utc_tai_offset_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3793 utc_tai_offset_store(struct device *dev,
3794 struct device_attribute *attr,
3795 const char *buf, size_t count)
3796 {
3797 struct ptp_ocp *bp = dev_get_drvdata(dev);
3798 int err;
3799 u32 val;
3800
3801 err = kstrtou32(buf, 0, &val);
3802 if (err)
3803 return err;
3804
3805 ptp_ocp_utc_distribute(bp, val);
3806
3807 return count;
3808 }
3809 static DEVICE_ATTR_RW(utc_tai_offset);
3810
3811 static ssize_t
ts_window_adjust_show(struct device * dev,struct device_attribute * attr,char * buf)3812 ts_window_adjust_show(struct device *dev,
3813 struct device_attribute *attr, char *buf)
3814 {
3815 struct ptp_ocp *bp = dev_get_drvdata(dev);
3816
3817 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3818 }
3819
3820 static ssize_t
ts_window_adjust_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3821 ts_window_adjust_store(struct device *dev,
3822 struct device_attribute *attr,
3823 const char *buf, size_t count)
3824 {
3825 struct ptp_ocp *bp = dev_get_drvdata(dev);
3826 int err;
3827 u32 val;
3828
3829 err = kstrtou32(buf, 0, &val);
3830 if (err)
3831 return err;
3832
3833 bp->ts_window_adjust = val;
3834
3835 return count;
3836 }
3837 static DEVICE_ATTR_RW(ts_window_adjust);
3838
3839 static ssize_t
irig_b_mode_show(struct device * dev,struct device_attribute * attr,char * buf)3840 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3841 {
3842 struct ptp_ocp *bp = dev_get_drvdata(dev);
3843 u32 val;
3844
3845 val = ioread32(&bp->irig_out->ctrl);
3846 val = (val >> 16) & 0x07;
3847 return sysfs_emit(buf, "%d\n", val);
3848 }
3849
3850 static ssize_t
irig_b_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3851 irig_b_mode_store(struct device *dev,
3852 struct device_attribute *attr,
3853 const char *buf, size_t count)
3854 {
3855 struct ptp_ocp *bp = dev_get_drvdata(dev);
3856 unsigned long flags;
3857 int err;
3858 u32 reg;
3859 u8 val;
3860
3861 err = kstrtou8(buf, 0, &val);
3862 if (err)
3863 return err;
3864 if (val > 7)
3865 return -EINVAL;
3866
3867 reg = ((val & 0x7) << 16);
3868
3869 spin_lock_irqsave(&bp->lock, flags);
3870 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3871 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3872 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3873 spin_unlock_irqrestore(&bp->lock, flags);
3874
3875 return count;
3876 }
3877 static DEVICE_ATTR_RW(irig_b_mode);
3878
3879 static ssize_t
clock_source_show(struct device * dev,struct device_attribute * attr,char * buf)3880 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3881 {
3882 struct ptp_ocp *bp = dev_get_drvdata(dev);
3883 const char *p;
3884 u32 select;
3885
3886 select = ioread32(&bp->reg->select);
3887 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3888
3889 return sysfs_emit(buf, "%s\n", p);
3890 }
3891
3892 static ssize_t
clock_source_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3893 clock_source_store(struct device *dev, struct device_attribute *attr,
3894 const char *buf, size_t count)
3895 {
3896 struct ptp_ocp *bp = dev_get_drvdata(dev);
3897 unsigned long flags;
3898 int val;
3899
3900 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3901 if (val < 0)
3902 return val;
3903
3904 spin_lock_irqsave(&bp->lock, flags);
3905 iowrite32(val, &bp->reg->select);
3906 spin_unlock_irqrestore(&bp->lock, flags);
3907
3908 return count;
3909 }
3910 static DEVICE_ATTR_RW(clock_source);
3911
3912 static ssize_t
available_clock_sources_show(struct device * dev,struct device_attribute * attr,char * buf)3913 available_clock_sources_show(struct device *dev,
3914 struct device_attribute *attr, char *buf)
3915 {
3916 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3917 }
3918 static DEVICE_ATTR_RO(available_clock_sources);
3919
3920 static ssize_t
clock_status_drift_show(struct device * dev,struct device_attribute * attr,char * buf)3921 clock_status_drift_show(struct device *dev,
3922 struct device_attribute *attr, char *buf)
3923 {
3924 struct ptp_ocp *bp = dev_get_drvdata(dev);
3925 u32 val;
3926 int res;
3927
3928 val = ioread32(&bp->reg->status_drift);
3929 res = (val & ~INT_MAX) ? -1 : 1;
3930 res *= (val & INT_MAX);
3931 return sysfs_emit(buf, "%d\n", res);
3932 }
3933 static DEVICE_ATTR_RO(clock_status_drift);
3934
3935 static ssize_t
clock_status_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3936 clock_status_offset_show(struct device *dev,
3937 struct device_attribute *attr, char *buf)
3938 {
3939 struct ptp_ocp *bp = dev_get_drvdata(dev);
3940 u32 val;
3941 int res;
3942
3943 val = ioread32(&bp->reg->status_offset);
3944 res = (val & ~INT_MAX) ? -1 : 1;
3945 res *= (val & INT_MAX);
3946 return sysfs_emit(buf, "%d\n", res);
3947 }
3948 static DEVICE_ATTR_RO(clock_status_offset);
3949
3950 static ssize_t
tod_correction_show(struct device * dev,struct device_attribute * attr,char * buf)3951 tod_correction_show(struct device *dev,
3952 struct device_attribute *attr, char *buf)
3953 {
3954 struct ptp_ocp *bp = dev_get_drvdata(dev);
3955 u32 val;
3956 int res;
3957
3958 val = ioread32(&bp->tod->adj_sec);
3959 res = (val & ~INT_MAX) ? -1 : 1;
3960 res *= (val & INT_MAX);
3961 return sysfs_emit(buf, "%d\n", res);
3962 }
3963
3964 static ssize_t
tod_correction_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3965 tod_correction_store(struct device *dev, struct device_attribute *attr,
3966 const char *buf, size_t count)
3967 {
3968 struct ptp_ocp *bp = dev_get_drvdata(dev);
3969 unsigned long flags;
3970 int err, res;
3971 u32 val = 0;
3972
3973 err = kstrtos32(buf, 0, &res);
3974 if (err)
3975 return err;
3976 if (res < 0) {
3977 res *= -1;
3978 val |= BIT(31);
3979 }
3980 val |= res;
3981
3982 spin_lock_irqsave(&bp->lock, flags);
3983 iowrite32(val, &bp->tod->adj_sec);
3984 spin_unlock_irqrestore(&bp->lock, flags);
3985
3986 return count;
3987 }
3988 static DEVICE_ATTR_RW(tod_correction);
3989
3990 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3991 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3992 &dev_attr_signal##_nr##_signal.attr.attr, \
3993 &dev_attr_signal##_nr##_duty.attr.attr, \
3994 &dev_attr_signal##_nr##_phase.attr.attr, \
3995 &dev_attr_signal##_nr##_period.attr.attr, \
3996 &dev_attr_signal##_nr##_polarity.attr.attr, \
3997 &dev_attr_signal##_nr##_running.attr.attr, \
3998 &dev_attr_signal##_nr##_start.attr.attr, \
3999 NULL, \
4000 }
4001
4002 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
4003 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
4004 static const struct attribute_group \
4005 fb_timecard_signal##_nr##_group = { \
4006 .name = #_name, \
4007 .attrs = fb_timecard_signal##_nr##_attrs, \
4008 }
4009
4010 DEVICE_SIGNAL_GROUP(gen1, 0);
4011 DEVICE_SIGNAL_GROUP(gen2, 1);
4012 DEVICE_SIGNAL_GROUP(gen3, 2);
4013 DEVICE_SIGNAL_GROUP(gen4, 3);
4014
4015 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
4016 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
4017 &dev_attr_freq##_nr##_seconds.attr.attr, \
4018 &dev_attr_freq##_nr##_frequency.attr.attr, \
4019 NULL, \
4020 }
4021
4022 #define DEVICE_FREQ_GROUP(_name, _nr) \
4023 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
4024 static const struct attribute_group \
4025 fb_timecard_freq##_nr##_group = { \
4026 .name = #_name, \
4027 .attrs = fb_timecard_freq##_nr##_attrs, \
4028 }
4029
4030 DEVICE_FREQ_GROUP(freq1, 0);
4031 DEVICE_FREQ_GROUP(freq2, 1);
4032 DEVICE_FREQ_GROUP(freq3, 2);
4033 DEVICE_FREQ_GROUP(freq4, 3);
4034
4035 static ssize_t
disciplining_config_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)4036 disciplining_config_read(struct file *filp, struct kobject *kobj,
4037 const struct bin_attribute *bin_attr, char *buf,
4038 loff_t off, size_t count)
4039 {
4040 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4041 size_t size = OCP_ART_CONFIG_SIZE;
4042 struct nvmem_device *nvmem;
4043 ssize_t err;
4044
4045 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4046 if (IS_ERR(nvmem))
4047 return PTR_ERR(nvmem);
4048
4049 if (off > size) {
4050 err = 0;
4051 goto out;
4052 }
4053
4054 if (off + count > size)
4055 count = size - off;
4056
4057 // the configuration is in the very beginning of the EEPROM
4058 err = nvmem_device_read(nvmem, off, count, buf);
4059 if (err != count) {
4060 err = -EFAULT;
4061 goto out;
4062 }
4063
4064 out:
4065 ptp_ocp_nvmem_device_put(&nvmem);
4066
4067 return err;
4068 }
4069
4070 static ssize_t
disciplining_config_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)4071 disciplining_config_write(struct file *filp, struct kobject *kobj,
4072 const struct bin_attribute *bin_attr, char *buf,
4073 loff_t off, size_t count)
4074 {
4075 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4076 struct nvmem_device *nvmem;
4077 ssize_t err;
4078
4079 /* Allow write of the whole area only */
4080 if (off || count != OCP_ART_CONFIG_SIZE)
4081 return -EFAULT;
4082
4083 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4084 if (IS_ERR(nvmem))
4085 return PTR_ERR(nvmem);
4086
4087 err = nvmem_device_write(nvmem, 0x00, count, buf);
4088 if (err != count)
4089 err = -EFAULT;
4090
4091 ptp_ocp_nvmem_device_put(&nvmem);
4092
4093 return err;
4094 }
4095 static const BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
4096
4097 static ssize_t
temperature_table_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)4098 temperature_table_read(struct file *filp, struct kobject *kobj,
4099 const struct bin_attribute *bin_attr, char *buf,
4100 loff_t off, size_t count)
4101 {
4102 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4103 size_t size = OCP_ART_TEMP_TABLE_SIZE;
4104 struct nvmem_device *nvmem;
4105 ssize_t err;
4106
4107 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4108 if (IS_ERR(nvmem))
4109 return PTR_ERR(nvmem);
4110
4111 if (off > size) {
4112 err = 0;
4113 goto out;
4114 }
4115
4116 if (off + count > size)
4117 count = size - off;
4118
4119 // the configuration is in the very beginning of the EEPROM
4120 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
4121 if (err != count) {
4122 err = -EFAULT;
4123 goto out;
4124 }
4125
4126 out:
4127 ptp_ocp_nvmem_device_put(&nvmem);
4128
4129 return err;
4130 }
4131
4132 static ssize_t
temperature_table_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)4133 temperature_table_write(struct file *filp, struct kobject *kobj,
4134 const struct bin_attribute *bin_attr, char *buf,
4135 loff_t off, size_t count)
4136 {
4137 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4138 struct nvmem_device *nvmem;
4139 ssize_t err;
4140
4141 /* Allow write of the whole area only */
4142 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
4143 return -EFAULT;
4144
4145 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4146 if (IS_ERR(nvmem))
4147 return PTR_ERR(nvmem);
4148
4149 err = nvmem_device_write(nvmem, 0x90, count, buf);
4150 if (err != count)
4151 err = -EFAULT;
4152
4153 ptp_ocp_nvmem_device_put(&nvmem);
4154
4155 return err;
4156 }
4157 static const BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
4158
4159 static struct attribute *fb_timecard_attrs[] = {
4160 &dev_attr_serialnum.attr,
4161 &dev_attr_gnss_sync.attr,
4162 &dev_attr_clock_source.attr,
4163 &dev_attr_available_clock_sources.attr,
4164 &dev_attr_sma1.attr,
4165 &dev_attr_sma2.attr,
4166 &dev_attr_sma3.attr,
4167 &dev_attr_sma4.attr,
4168 &dev_attr_available_sma_inputs.attr,
4169 &dev_attr_available_sma_outputs.attr,
4170 &dev_attr_clock_status_drift.attr,
4171 &dev_attr_clock_status_offset.attr,
4172 &dev_attr_irig_b_mode.attr,
4173 &dev_attr_utc_tai_offset.attr,
4174 &dev_attr_ts_window_adjust.attr,
4175 &dev_attr_tod_correction.attr,
4176 NULL,
4177 };
4178
4179 static const struct attribute_group fb_timecard_group = {
4180 .attrs = fb_timecard_attrs,
4181 };
4182
4183 static const struct ocp_attr_group fb_timecard_groups[] = {
4184 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
4185 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
4186 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
4187 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
4188 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
4189 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
4190 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
4191 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
4192 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
4193 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
4194 { },
4195 };
4196
4197 static struct attribute *art_timecard_attrs[] = {
4198 &dev_attr_serialnum.attr,
4199 &dev_attr_clock_source.attr,
4200 &dev_attr_available_clock_sources.attr,
4201 &dev_attr_utc_tai_offset.attr,
4202 &dev_attr_ts_window_adjust.attr,
4203 &dev_attr_sma1.attr,
4204 &dev_attr_sma2.attr,
4205 &dev_attr_sma3.attr,
4206 &dev_attr_sma4.attr,
4207 &dev_attr_available_sma_inputs.attr,
4208 &dev_attr_available_sma_outputs.attr,
4209 NULL,
4210 };
4211
4212 static const struct bin_attribute *const bin_art_timecard_attrs[] = {
4213 &bin_attr_disciplining_config,
4214 &bin_attr_temperature_table,
4215 NULL,
4216 };
4217
4218 static const struct attribute_group art_timecard_group = {
4219 .attrs = art_timecard_attrs,
4220 .bin_attrs = bin_art_timecard_attrs,
4221 };
4222
4223 static const struct ocp_attr_group art_timecard_groups[] = {
4224 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
4225 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
4226 { },
4227 };
4228
4229 static struct attribute *adva_timecard_attrs[] = {
4230 &dev_attr_serialnum.attr,
4231 &dev_attr_gnss_sync.attr,
4232 &dev_attr_clock_source.attr,
4233 &dev_attr_available_clock_sources.attr,
4234 &dev_attr_sma1.attr,
4235 &dev_attr_sma2.attr,
4236 &dev_attr_sma3.attr,
4237 &dev_attr_sma4.attr,
4238 &dev_attr_available_sma_inputs.attr,
4239 &dev_attr_available_sma_outputs.attr,
4240 &dev_attr_clock_status_drift.attr,
4241 &dev_attr_clock_status_offset.attr,
4242 &dev_attr_ts_window_adjust.attr,
4243 &dev_attr_tod_correction.attr,
4244 NULL,
4245 };
4246
4247 static const struct attribute_group adva_timecard_group = {
4248 .attrs = adva_timecard_attrs,
4249 };
4250
4251 static const struct ocp_attr_group adva_timecard_groups[] = {
4252 { .cap = OCP_CAP_BASIC, .group = &adva_timecard_group },
4253 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
4254 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
4255 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
4256 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
4257 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
4258 { },
4259 };
4260
4261 static struct attribute *adva_timecard_x1_attrs[] = {
4262 &dev_attr_serialnum.attr,
4263 &dev_attr_gnss_sync.attr,
4264 &dev_attr_clock_source.attr,
4265 &dev_attr_available_clock_sources.attr,
4266 &dev_attr_sma1.attr,
4267 &dev_attr_sma2.attr,
4268 &dev_attr_sma3.attr,
4269 &dev_attr_sma4.attr,
4270 &dev_attr_available_sma_inputs.attr,
4271 &dev_attr_available_sma_outputs.attr,
4272 &dev_attr_clock_status_drift.attr,
4273 &dev_attr_clock_status_offset.attr,
4274 &dev_attr_ts_window_adjust.attr,
4275 &dev_attr_utc_tai_offset.attr,
4276 &dev_attr_tod_correction.attr,
4277 NULL,
4278 };
4279
4280 static const struct attribute_group adva_timecard_x1_group = {
4281 .attrs = adva_timecard_x1_attrs,
4282 };
4283
4284 static const struct ocp_attr_group adva_timecard_x1_groups[] = {
4285 { .cap = OCP_CAP_BASIC, .group = &adva_timecard_x1_group },
4286 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
4287 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
4288 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
4289 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
4290 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
4291 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
4292 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
4293 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
4294 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
4295 { },
4296 };
4297
4298 static void
gpio_input_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit,const char * def)4299 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
4300 const char *def)
4301 {
4302 int i;
4303
4304 for (i = 0; i < 4; i++) {
4305 if (bp->sma[i].mode != SMA_MODE_IN)
4306 continue;
4307 if (map[i][0] & (1 << bit)) {
4308 sprintf(buf, "sma%d", i + 1);
4309 return;
4310 }
4311 }
4312 if (!def)
4313 def = "----";
4314 strcpy(buf, def);
4315 }
4316
4317 static void
gpio_output_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit)4318 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
4319 {
4320 char *ans = buf;
4321 int i;
4322
4323 strcpy(ans, "----");
4324 for (i = 0; i < 4; i++) {
4325 if (bp->sma[i].mode != SMA_MODE_OUT)
4326 continue;
4327 if (map[i][1] & (1 << bit))
4328 ans += sprintf(ans, "sma%d ", i + 1);
4329 }
4330 }
4331
4332 static void
_signal_summary_show(struct seq_file * s,struct ptp_ocp * bp,int nr)4333 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
4334 {
4335 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
4336 struct ptp_ocp_signal *signal = &bp->signal[nr];
4337 char label[16];
4338 bool on;
4339 u32 val;
4340
4341 on = signal->running;
4342 sprintf(label, "GEN%d", nr + 1);
4343 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
4344 label, on ? " ON" : "OFF",
4345 signal->period, signal->duty, signal->phase,
4346 signal->polarity);
4347
4348 val = ioread32(®->enable);
4349 seq_printf(s, " [%x", val);
4350 val = ioread32(®->status);
4351 seq_printf(s, " %x]", val);
4352
4353 seq_printf(s, " start:%llu\n", signal->start);
4354 }
4355
4356 static void
_frequency_summary_show(struct seq_file * s,int nr,struct frequency_reg __iomem * reg)4357 _frequency_summary_show(struct seq_file *s, int nr,
4358 struct frequency_reg __iomem *reg)
4359 {
4360 char label[16];
4361 bool on;
4362 u32 val;
4363
4364 if (!reg)
4365 return;
4366
4367 sprintf(label, "FREQ%d", nr + 1);
4368 val = ioread32(®->ctrl);
4369 on = val & 1;
4370 val = (val >> 8) & 0xff;
4371 seq_printf(s, "%7s: %s, sec:%u",
4372 label,
4373 on ? " ON" : "OFF",
4374 val);
4375
4376 val = ioread32(®->status);
4377 if (val & FREQ_STATUS_ERROR)
4378 seq_printf(s, ", error");
4379 if (val & FREQ_STATUS_OVERRUN)
4380 seq_printf(s, ", overrun");
4381 if (val & FREQ_STATUS_VALID)
4382 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
4383 seq_printf(s, " reg:%x\n", val);
4384 }
4385
4386 static int
ptp_ocp_summary_show(struct seq_file * s,void * data)4387 ptp_ocp_summary_show(struct seq_file *s, void *data)
4388 {
4389 struct device *dev = s->private;
4390 struct ptp_system_timestamp sts;
4391 struct ts_reg __iomem *ts_reg;
4392 char *buf, *src, *mac_src;
4393 struct timespec64 ts;
4394 struct ptp_ocp *bp;
4395 u16 sma_val[4][2];
4396 u32 ctrl, val;
4397 bool on, map;
4398 int i;
4399
4400 buf = (char *)__get_free_page(GFP_KERNEL);
4401 if (!buf)
4402 return -ENOMEM;
4403
4404 bp = dev_get_drvdata(dev);
4405
4406 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
4407 for (i = 0; i < __PORT_COUNT; i++) {
4408 if (bp->port[i].line != -1)
4409 seq_printf(s, "%7s: /dev/ttyS%d\n", ptp_ocp_tty_port_name(i),
4410 bp->port[i].line);
4411 }
4412
4413 memset(sma_val, 0xff, sizeof(sma_val));
4414 if (bp->sma_map1) {
4415 u32 reg;
4416
4417 reg = ioread32(&bp->sma_map1->gpio1);
4418 sma_val[0][0] = reg & 0xffff;
4419 sma_val[1][0] = reg >> 16;
4420
4421 reg = ioread32(&bp->sma_map1->gpio2);
4422 sma_val[2][1] = reg & 0xffff;
4423 sma_val[3][1] = reg >> 16;
4424
4425 reg = ioread32(&bp->sma_map2->gpio1);
4426 sma_val[2][0] = reg & 0xffff;
4427 sma_val[3][0] = reg >> 16;
4428
4429 reg = ioread32(&bp->sma_map2->gpio2);
4430 sma_val[0][1] = reg & 0xffff;
4431 sma_val[1][1] = reg >> 16;
4432 }
4433
4434 sma1_show(dev, NULL, buf);
4435 seq_printf(s, " sma1: %04x,%04x %s",
4436 sma_val[0][0], sma_val[0][1], buf);
4437
4438 sma2_show(dev, NULL, buf);
4439 seq_printf(s, " sma2: %04x,%04x %s",
4440 sma_val[1][0], sma_val[1][1], buf);
4441
4442 sma3_show(dev, NULL, buf);
4443 seq_printf(s, " sma3: %04x,%04x %s",
4444 sma_val[2][0], sma_val[2][1], buf);
4445
4446 sma4_show(dev, NULL, buf);
4447 seq_printf(s, " sma4: %04x,%04x %s",
4448 sma_val[3][0], sma_val[3][1], buf);
4449
4450 if (bp->ts0) {
4451 ts_reg = bp->ts0->mem;
4452 on = ioread32(&ts_reg->enable);
4453 src = "GNSS1";
4454 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
4455 on ? " ON" : "OFF", src);
4456 }
4457
4458 if (bp->ts1) {
4459 ts_reg = bp->ts1->mem;
4460 on = ioread32(&ts_reg->enable);
4461 gpio_input_map(buf, bp, sma_val, 2, NULL);
4462 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
4463 on ? " ON" : "OFF", buf);
4464 }
4465
4466 if (bp->ts2) {
4467 ts_reg = bp->ts2->mem;
4468 on = ioread32(&ts_reg->enable);
4469 gpio_input_map(buf, bp, sma_val, 3, NULL);
4470 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
4471 on ? " ON" : "OFF", buf);
4472 }
4473
4474 if (bp->ts3) {
4475 ts_reg = bp->ts3->mem;
4476 on = ioread32(&ts_reg->enable);
4477 gpio_input_map(buf, bp, sma_val, 6, NULL);
4478 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
4479 on ? " ON" : "OFF", buf);
4480 }
4481
4482 if (bp->ts4) {
4483 ts_reg = bp->ts4->mem;
4484 on = ioread32(&ts_reg->enable);
4485 gpio_input_map(buf, bp, sma_val, 7, NULL);
4486 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
4487 on ? " ON" : "OFF", buf);
4488 }
4489
4490 if (bp->pps) {
4491 ts_reg = bp->pps->mem;
4492 src = "PHC";
4493 on = ioread32(&ts_reg->enable);
4494 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
4495 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
4496 on && map ? " ON" : "OFF", src);
4497
4498 map = !!(bp->pps_req_map & OCP_REQ_PPS);
4499 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
4500 on && map ? " ON" : "OFF", src);
4501 }
4502
4503 if (bp->fw_cap & OCP_CAP_SIGNAL)
4504 for (i = 0; i < bp->signals_nr; i++)
4505 _signal_summary_show(s, bp, i);
4506
4507 if (bp->fw_cap & OCP_CAP_FREQ)
4508 for (i = 0; i < bp->freq_in_nr; i++)
4509 _frequency_summary_show(s, i, bp->freq_in[i]);
4510
4511 if (bp->irig_out) {
4512 ctrl = ioread32(&bp->irig_out->ctrl);
4513 on = ctrl & IRIG_M_CTRL_ENABLE;
4514 val = ioread32(&bp->irig_out->status);
4515 gpio_output_map(buf, bp, sma_val, 4);
4516 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
4517 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
4518 }
4519
4520 if (bp->irig_in) {
4521 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
4522 val = ioread32(&bp->irig_in->status);
4523 gpio_input_map(buf, bp, sma_val, 4, NULL);
4524 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
4525 on ? " ON" : "OFF", val, buf);
4526 }
4527
4528 if (bp->dcf_out) {
4529 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
4530 val = ioread32(&bp->dcf_out->status);
4531 gpio_output_map(buf, bp, sma_val, 5);
4532 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
4533 on ? " ON" : "OFF", val, buf);
4534 }
4535
4536 if (bp->dcf_in) {
4537 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
4538 val = ioread32(&bp->dcf_in->status);
4539 gpio_input_map(buf, bp, sma_val, 5, NULL);
4540 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
4541 on ? " ON" : "OFF", val, buf);
4542 }
4543
4544 if (bp->nmea_out) {
4545 on = ioread32(&bp->nmea_out->ctrl) & 1;
4546 val = ioread32(&bp->nmea_out->status);
4547 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
4548 on ? " ON" : "OFF", val);
4549 }
4550
4551 /* compute src for PPS1, used below. */
4552 if (bp->pps_select) {
4553 val = ioread32(&bp->pps_select->gpio1);
4554 src = &buf[80];
4555 mac_src = "GNSS1";
4556 if (val & 0x01) {
4557 gpio_input_map(src, bp, sma_val, 0, NULL);
4558 mac_src = src;
4559 } else if (val & 0x02) {
4560 src = "MAC";
4561 } else if (val & 0x04) {
4562 src = "GNSS1";
4563 } else {
4564 src = "----";
4565 mac_src = src;
4566 }
4567 } else {
4568 src = "?";
4569 mac_src = src;
4570 }
4571 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
4572
4573 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
4574 seq_printf(s, "MAC PPS2 src: %s\n", buf);
4575
4576 /* assumes automatic switchover/selection */
4577 val = ioread32(&bp->reg->select);
4578 switch (val >> 16) {
4579 case 0:
4580 sprintf(buf, "----");
4581 break;
4582 case 2:
4583 sprintf(buf, "IRIG");
4584 break;
4585 case 3:
4586 sprintf(buf, "%s via PPS1", src);
4587 break;
4588 case 6:
4589 sprintf(buf, "DCF");
4590 break;
4591 default:
4592 strcpy(buf, "unknown");
4593 break;
4594 }
4595 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
4596 bp->sync ? "sync" : "unsynced");
4597
4598 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
4599 struct timespec64 sys_ts;
4600 s64 pre_ns, post_ns, ns;
4601
4602 pre_ns = ktime_to_ns(sts.pre_sts.systime);
4603 post_ns = ktime_to_ns(sts.post_sts.systime);
4604 ns = (pre_ns + post_ns) / 2;
4605 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
4606 sys_ts = ns_to_timespec64(ns);
4607
4608 seq_printf(s, "%7s: %ptSp == %ptS TAI\n", "PHC", &ts, &ts);
4609 seq_printf(s, "%7s: %ptSp == %ptS UTC offset %d\n", "SYS",
4610 &sys_ts, &sys_ts, bp->utc_tai_offset);
4611 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
4612 timespec64_to_ns(&ts) - ns,
4613 post_ns - pre_ns);
4614 }
4615
4616 free_page((unsigned long)buf);
4617 return 0;
4618 }
4619 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
4620
4621 static int
ptp_ocp_tod_status_show(struct seq_file * s,void * data)4622 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
4623 {
4624 struct device *dev = s->private;
4625 struct ptp_ocp *bp;
4626 u32 val;
4627 int idx;
4628
4629 bp = dev_get_drvdata(dev);
4630
4631 val = ioread32(&bp->tod->ctrl);
4632 if (!(val & TOD_CTRL_ENABLE)) {
4633 seq_printf(s, "TOD Slave disabled\n");
4634 return 0;
4635 }
4636 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
4637
4638 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
4639 idx += (val >> 16) & 3;
4640 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
4641
4642 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
4643 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
4644
4645 val = ioread32(&bp->tod->version);
4646 seq_printf(s, "TOD Version %d.%d.%d\n",
4647 val >> 24, (val >> 16) & 0xff, val & 0xffff);
4648
4649 val = ioread32(&bp->tod->status);
4650 seq_printf(s, "Status register: 0x%08X\n", val);
4651
4652 val = ioread32(&bp->tod->adj_sec);
4653 idx = (val & ~INT_MAX) ? -1 : 1;
4654 idx *= (val & INT_MAX);
4655 seq_printf(s, "Correction seconds: %d\n", idx);
4656
4657 val = ioread32(&bp->tod->utc_status);
4658 seq_printf(s, "UTC status register: 0x%08X\n", val);
4659 seq_printf(s, "UTC offset: %ld valid:%d\n",
4660 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
4661 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
4662 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
4663 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
4664
4665 val = ioread32(&bp->tod->leap);
4666 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
4667
4668 return 0;
4669 }
4670 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
4671
4672 static struct dentry *ptp_ocp_debugfs_root;
4673
4674 static void
ptp_ocp_debugfs_add_device(struct ptp_ocp * bp)4675 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
4676 {
4677 struct dentry *d;
4678
4679 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
4680 bp->debug_root = d;
4681 debugfs_create_file("summary", 0444, bp->debug_root,
4682 &bp->dev, &ptp_ocp_summary_fops);
4683 if (bp->tod)
4684 debugfs_create_file("tod_status", 0444, bp->debug_root,
4685 &bp->dev, &ptp_ocp_tod_status_fops);
4686 }
4687
4688 static void
ptp_ocp_debugfs_remove_device(struct ptp_ocp * bp)4689 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
4690 {
4691 debugfs_remove_recursive(bp->debug_root);
4692 }
4693
4694 static void
ptp_ocp_debugfs_init(void)4695 ptp_ocp_debugfs_init(void)
4696 {
4697 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
4698 }
4699
4700 static void
ptp_ocp_debugfs_fini(void)4701 ptp_ocp_debugfs_fini(void)
4702 {
4703 debugfs_remove_recursive(ptp_ocp_debugfs_root);
4704 }
4705
4706 static void
ptp_ocp_dev_release(struct device * dev)4707 ptp_ocp_dev_release(struct device *dev)
4708 {
4709 struct ptp_ocp *bp = dev_get_drvdata(dev);
4710
4711 mutex_lock(&ptp_ocp_lock);
4712 idr_remove(&ptp_ocp_idr, bp->id);
4713 mutex_unlock(&ptp_ocp_lock);
4714 }
4715
4716 static int
ptp_ocp_device_init(struct ptp_ocp * bp,struct pci_dev * pdev)4717 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
4718 {
4719 int i, err;
4720
4721 mutex_lock(&ptp_ocp_lock);
4722 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
4723 mutex_unlock(&ptp_ocp_lock);
4724 if (err < 0) {
4725 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
4726 return err;
4727 }
4728 bp->id = err;
4729
4730 bp->ptp_info = ptp_ocp_clock_info;
4731 spin_lock_init(&bp->lock);
4732
4733 for (i = 0; i < __PORT_COUNT; i++)
4734 bp->port[i].line = -1;
4735
4736 bp->pdev = pdev;
4737
4738 device_initialize(&bp->dev);
4739 dev_set_name(&bp->dev, "ocp%d", bp->id);
4740 bp->dev.class = &timecard_class;
4741 bp->dev.parent = &pdev->dev;
4742 bp->dev.release = ptp_ocp_dev_release;
4743 dev_set_drvdata(&bp->dev, bp);
4744
4745 err = device_add(&bp->dev);
4746 if (err) {
4747 dev_err(&bp->dev, "device add failed: %d\n", err);
4748 goto out;
4749 }
4750
4751 pci_set_drvdata(pdev, bp);
4752
4753 return 0;
4754
4755 out:
4756 put_device(&bp->dev);
4757 return err;
4758 }
4759
4760 static void
ptp_ocp_symlink(struct ptp_ocp * bp,struct device * child,const char * link)4761 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4762 {
4763 struct device *dev = &bp->dev;
4764
4765 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4766 dev_err(dev, "%s symlink failed\n", link);
4767 }
4768
4769 static void
ptp_ocp_link_child(struct ptp_ocp * bp,const char * name,const char * link)4770 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4771 {
4772 struct device *dev, *child;
4773
4774 dev = &bp->pdev->dev;
4775
4776 child = device_find_child_by_name(dev, name);
4777 if (!child) {
4778 dev_err(dev, "Could not find device %s\n", name);
4779 return;
4780 }
4781
4782 ptp_ocp_symlink(bp, child, link);
4783 put_device(child);
4784 }
4785
4786 static int
ptp_ocp_complete(struct ptp_ocp * bp)4787 ptp_ocp_complete(struct ptp_ocp *bp)
4788 {
4789 struct pps_device *pps;
4790 char buf[32];
4791
4792 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4793 ptp_ocp_link_child(bp, buf, "ptp");
4794
4795 pps = pps_lookup_dev(bp->ptp);
4796 if (pps)
4797 ptp_ocp_symlink(bp, &pps->dev, "pps");
4798
4799 ptp_ocp_debugfs_add_device(bp);
4800
4801 return 0;
4802 }
4803
4804 static void
ptp_ocp_phc_info(struct ptp_ocp * bp)4805 ptp_ocp_phc_info(struct ptp_ocp *bp)
4806 {
4807 struct timespec64 ts;
4808 u32 version, select;
4809
4810 version = ioread32(&bp->reg->version);
4811 select = ioread32(&bp->reg->select);
4812 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4813 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4814 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4815 ptp_clock_index(bp->ptp));
4816
4817 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4818 dev_info(&bp->pdev->dev, "Time: %ptSp, %s\n",
4819 &ts, bp->sync ? "in-sync" : "UNSYNCED");
4820 }
4821
4822 static void
ptp_ocp_serial_info(struct device * dev,const char * name,int port,int baud)4823 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4824 {
4825 if (port != -1)
4826 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4827 }
4828
4829 static void
ptp_ocp_info(struct ptp_ocp * bp)4830 ptp_ocp_info(struct ptp_ocp *bp)
4831 {
4832 static int nmea_baud[] = {
4833 1200, 2400, 4800, 9600, 19200, 38400,
4834 57600, 115200, 230400, 460800, 921600,
4835 1000000, 2000000
4836 };
4837 struct device *dev = &bp->pdev->dev;
4838 u32 reg;
4839 int i;
4840
4841 ptp_ocp_phc_info(bp);
4842
4843 for (i = 0; i < __PORT_COUNT; i++) {
4844 if (i == PORT_NMEA && bp->nmea_out && bp->port[PORT_NMEA].line != -1) {
4845 bp->port[PORT_NMEA].baud = -1;
4846
4847 reg = ioread32(&bp->nmea_out->uart_baud);
4848 if (reg < ARRAY_SIZE(nmea_baud))
4849 bp->port[PORT_NMEA].baud = nmea_baud[reg];
4850 }
4851 ptp_ocp_serial_info(dev, ptp_ocp_tty_port_name(i), bp->port[i].line,
4852 bp->port[i].baud);
4853 }
4854 }
4855
4856 static void
ptp_ocp_detach_sysfs(struct ptp_ocp * bp)4857 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4858 {
4859 struct device *dev = &bp->dev;
4860
4861 sysfs_remove_link(&dev->kobj, "ptp");
4862 sysfs_remove_link(&dev->kobj, "pps");
4863 }
4864
4865 static void
ptp_ocp_detach(struct ptp_ocp * bp)4866 ptp_ocp_detach(struct ptp_ocp *bp)
4867 {
4868 int i;
4869
4870 ptp_ocp_debugfs_remove_device(bp);
4871 ptp_ocp_detach_sysfs(bp);
4872 ptp_ocp_attr_group_del(bp);
4873 timer_delete_sync(&bp->watchdog);
4874 /* Disable interrupts on all timestampers */
4875 if (bp->ts0)
4876 ptp_ocp_ts_enable(bp->ts0, 0, false);
4877 if (bp->ts1)
4878 ptp_ocp_ts_enable(bp->ts1, 0, false);
4879 if (bp->ts2)
4880 ptp_ocp_ts_enable(bp->ts2, 0, false);
4881 if (bp->ts3)
4882 ptp_ocp_ts_enable(bp->ts3, 0, false);
4883 if (bp->ts4)
4884 ptp_ocp_ts_enable(bp->ts4, 0, false);
4885 if (bp->pps)
4886 ptp_ocp_ts_enable(bp->pps, ~0, false);
4887 if (bp->ptp)
4888 ptp_clock_unregister(bp->ptp);
4889 kfree(bp->ptp_info.pin_config);
4890 ptp_ocp_unregister_ext(bp->ts0);
4891 ptp_ocp_unregister_ext(bp->ts1);
4892 ptp_ocp_unregister_ext(bp->ts2);
4893 ptp_ocp_unregister_ext(bp->ts3);
4894 ptp_ocp_unregister_ext(bp->ts4);
4895 ptp_ocp_unregister_ext(bp->pps);
4896 for (i = 0; i < 4; i++)
4897 ptp_ocp_unregister_ext(bp->signal_out[i]);
4898 for (i = 0; i < __PORT_COUNT; i++)
4899 if (bp->port[i].line != -1)
4900 serial8250_unregister_port(bp->port[i].line);
4901 platform_device_unregister(bp->spi_flash);
4902 platform_device_unregister(bp->i2c_ctrl);
4903 if (bp->i2c_clk)
4904 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4905 if (bp->n_irqs)
4906 pci_free_irq_vectors(bp->pdev);
4907 device_unregister(&bp->dev);
4908 }
4909
4910 static int
ptp_ocp_dpll_lock_status_get(const struct dpll_device * dpll,void * priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack)4911 ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,
4912 enum dpll_lock_status *status,
4913 enum dpll_lock_status_error *status_error,
4914 struct netlink_ext_ack *extack)
4915 {
4916 struct ptp_ocp *bp = priv;
4917
4918 *status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;
4919
4920 return 0;
4921 }
4922
ptp_ocp_dpll_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack)4923 static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,
4924 const struct dpll_device *dpll, void *priv,
4925 enum dpll_pin_state *state,
4926 struct netlink_ext_ack *extack)
4927 {
4928 struct ptp_ocp *bp = priv;
4929 int idx;
4930
4931 if (bp->pps_select) {
4932 idx = ioread32(&bp->pps_select->gpio1);
4933 *state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :
4934 DPLL_PIN_STATE_SELECTABLE;
4935 return 0;
4936 }
4937 NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");
4938 return -EINVAL;
4939 }
4940
ptp_ocp_dpll_mode_get(const struct dpll_device * dpll,void * priv,enum dpll_mode * mode,struct netlink_ext_ack * extack)4941 static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,
4942 enum dpll_mode *mode, struct netlink_ext_ack *extack)
4943 {
4944 *mode = DPLL_MODE_AUTOMATIC;
4945 return 0;
4946 }
4947
ptp_ocp_dpll_direction_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack)4948 static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,
4949 void *pin_priv,
4950 const struct dpll_device *dpll,
4951 void *priv,
4952 enum dpll_pin_direction *direction,
4953 struct netlink_ext_ack *extack)
4954 {
4955 struct ptp_ocp_sma_connector *sma = pin_priv;
4956
4957 *direction = sma->mode == SMA_MODE_IN ?
4958 DPLL_PIN_DIRECTION_INPUT :
4959 DPLL_PIN_DIRECTION_OUTPUT;
4960 return 0;
4961 }
4962
ptp_ocp_dpll_direction_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction direction,struct netlink_ext_ack * extack)4963 static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,
4964 void *pin_priv,
4965 const struct dpll_device *dpll,
4966 void *dpll_priv,
4967 enum dpll_pin_direction direction,
4968 struct netlink_ext_ack *extack)
4969 {
4970 struct ptp_ocp_sma_connector *sma = pin_priv;
4971 struct ptp_ocp *bp = dpll_priv;
4972 enum ptp_ocp_sma_mode mode;
4973 int sma_nr = (sma - bp->sma);
4974
4975 if (sma->fixed_dir)
4976 return -EOPNOTSUPP;
4977 mode = direction == DPLL_PIN_DIRECTION_INPUT ?
4978 SMA_MODE_IN : SMA_MODE_OUT;
4979 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1);
4980 }
4981
ptp_ocp_dpll_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack)4982 static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,
4983 void *pin_priv,
4984 const struct dpll_device *dpll,
4985 void *dpll_priv, u64 frequency,
4986 struct netlink_ext_ack *extack)
4987 {
4988 struct ptp_ocp_sma_connector *sma = pin_priv;
4989 struct ptp_ocp *bp = dpll_priv;
4990 const struct ocp_selector *tbl;
4991 int sma_nr = (sma - bp->sma);
4992 int i;
4993
4994 if (sma->fixed_fcn)
4995 return -EOPNOTSUPP;
4996
4997 tbl = bp->sma_op->tbl[sma->mode];
4998 for (i = 0; tbl[i].name; i++)
4999 if (tbl[i].frequency == frequency)
5000 return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr + 1);
5001 return -EINVAL;
5002 }
5003
ptp_ocp_dpll_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack)5004 static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,
5005 void *pin_priv,
5006 const struct dpll_device *dpll,
5007 void *dpll_priv, u64 *frequency,
5008 struct netlink_ext_ack *extack)
5009 {
5010 struct ptp_ocp_sma_connector *sma = pin_priv;
5011 struct ptp_ocp *bp = dpll_priv;
5012 const struct ocp_selector *tbl;
5013 int sma_nr = (sma - bp->sma);
5014 u32 val;
5015 int i;
5016
5017 val = bp->sma_op->get(bp, sma_nr + 1);
5018 tbl = bp->sma_op->tbl[sma->mode];
5019 for (i = 0; tbl[i].name; i++)
5020 if (val == tbl[i].value) {
5021 *frequency = tbl[i].frequency;
5022 return 0;
5023 }
5024
5025 return -EINVAL;
5026 }
5027
5028 static const struct dpll_device_ops dpll_ops = {
5029 .lock_status_get = ptp_ocp_dpll_lock_status_get,
5030 .mode_get = ptp_ocp_dpll_mode_get,
5031 };
5032
5033 static const struct dpll_pin_ops dpll_pins_ops = {
5034 .frequency_get = ptp_ocp_dpll_frequency_get,
5035 .frequency_set = ptp_ocp_dpll_frequency_set,
5036 .direction_get = ptp_ocp_dpll_direction_get,
5037 .direction_set = ptp_ocp_dpll_direction_set,
5038 .state_on_dpll_get = ptp_ocp_dpll_state_get,
5039 };
5040
5041 static void
ptp_ocp_sync_work(struct work_struct * work)5042 ptp_ocp_sync_work(struct work_struct *work)
5043 {
5044 struct ptp_ocp *bp;
5045 bool sync;
5046
5047 bp = container_of(work, struct ptp_ocp, sync_work.work);
5048 sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);
5049
5050 if (bp->sync != sync)
5051 dpll_device_change_ntf(bp->dpll);
5052
5053 bp->sync = sync;
5054
5055 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
5056 }
5057
5058 static int
ptp_ocp_probe(struct pci_dev * pdev,const struct pci_device_id * id)5059 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
5060 {
5061 struct devlink *devlink;
5062 struct ptp_ocp *bp;
5063 int err, i;
5064 u64 clkid;
5065
5066 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
5067 if (!devlink) {
5068 dev_err(&pdev->dev, "devlink_alloc failed\n");
5069 return -ENOMEM;
5070 }
5071
5072 err = pci_enable_device(pdev);
5073 if (err) {
5074 dev_err(&pdev->dev, "pci_enable_device\n");
5075 goto out_free;
5076 }
5077
5078 bp = devlink_priv(devlink);
5079 err = ptp_ocp_device_init(bp, pdev);
5080 if (err)
5081 goto out_disable;
5082
5083 INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);
5084
5085 /* compat mode.
5086 * Older FPGA firmware only returns 2 irq's.
5087 * allow this - if not all of the IRQ's are returned, skip the
5088 * extra devices and just register the clock.
5089 */
5090 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
5091 if (err < 0) {
5092 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
5093 goto out;
5094 }
5095 bp->n_irqs = err;
5096 pci_set_master(pdev);
5097
5098 err = ptp_ocp_register_resources(bp, id->driver_data);
5099 if (err)
5100 goto out;
5101
5102 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
5103 if (IS_ERR(bp->ptp)) {
5104 err = PTR_ERR(bp->ptp);
5105 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
5106 bp->ptp = NULL;
5107 goto out;
5108 }
5109
5110 err = ptp_ocp_complete(bp);
5111 if (err)
5112 goto out;
5113
5114 ptp_ocp_info(bp);
5115 devlink_register(devlink);
5116
5117 clkid = pci_get_dsn(pdev);
5118 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE, &bp->tracker);
5119 if (IS_ERR(bp->dpll)) {
5120 err = PTR_ERR(bp->dpll);
5121 dev_err(&pdev->dev, "dpll_device_alloc failed\n");
5122 goto out;
5123 }
5124
5125 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
5126 if (err)
5127 goto out;
5128
5129 for (i = 0; i < OCP_SMA_NUM; i++) {
5130 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE,
5131 &bp->sma[i].dpll_prop,
5132 &bp->sma[i].tracker);
5133 if (IS_ERR(bp->sma[i].dpll_pin)) {
5134 err = PTR_ERR(bp->sma[i].dpll_pin);
5135 goto out_dpll;
5136 }
5137
5138 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
5139 &bp->sma[i]);
5140 if (err) {
5141 dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
5142 goto out_dpll;
5143 }
5144 }
5145 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
5146
5147 return 0;
5148 out_dpll:
5149 while (i--) {
5150 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
5151 dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
5152 }
5153 dpll_device_put(bp->dpll, &bp->tracker);
5154 out:
5155 ptp_ocp_detach(bp);
5156 out_disable:
5157 pci_disable_device(pdev);
5158 out_free:
5159 devlink_free(devlink);
5160 return err;
5161 }
5162
5163 static void
ptp_ocp_remove(struct pci_dev * pdev)5164 ptp_ocp_remove(struct pci_dev *pdev)
5165 {
5166 struct ptp_ocp *bp = pci_get_drvdata(pdev);
5167 struct devlink *devlink = priv_to_devlink(bp);
5168 int i;
5169
5170 cancel_delayed_work_sync(&bp->sync_work);
5171 for (i = 0; i < OCP_SMA_NUM; i++) {
5172 if (bp->sma[i].dpll_pin) {
5173 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
5174 dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
5175 }
5176 }
5177 dpll_device_unregister(bp->dpll, &dpll_ops, bp);
5178 dpll_device_put(bp->dpll, &bp->tracker);
5179 devlink_unregister(devlink);
5180 ptp_ocp_detach(bp);
5181 pci_disable_device(pdev);
5182
5183 devlink_free(devlink);
5184 }
5185
5186 static struct pci_driver ptp_ocp_driver = {
5187 .name = KBUILD_MODNAME,
5188 .id_table = ptp_ocp_pcidev_id,
5189 .probe = ptp_ocp_probe,
5190 .remove = ptp_ocp_remove,
5191 .shutdown = ptp_ocp_remove,
5192 };
5193
5194 static int
ptp_ocp_i2c_notifier_call(struct notifier_block * nb,unsigned long action,void * data)5195 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
5196 unsigned long action, void *data)
5197 {
5198 struct device *dev, *child = data;
5199 struct ptp_ocp *bp;
5200 bool add;
5201
5202 switch (action) {
5203 case BUS_NOTIFY_ADD_DEVICE:
5204 case BUS_NOTIFY_DEL_DEVICE:
5205 add = action == BUS_NOTIFY_ADD_DEVICE;
5206 break;
5207 default:
5208 return 0;
5209 }
5210
5211 if (!i2c_verify_adapter(child))
5212 return 0;
5213
5214 dev = child;
5215 while ((dev = dev->parent))
5216 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
5217 goto found;
5218 return 0;
5219
5220 found:
5221 bp = dev_get_drvdata(dev);
5222 if (add)
5223 ptp_ocp_symlink(bp, child, "i2c");
5224 else
5225 sysfs_remove_link(&bp->dev.kobj, "i2c");
5226
5227 return 0;
5228 }
5229
5230 static struct notifier_block ptp_ocp_i2c_notifier = {
5231 .notifier_call = ptp_ocp_i2c_notifier_call,
5232 };
5233
5234 static int __init
ptp_ocp_init(void)5235 ptp_ocp_init(void)
5236 {
5237 const char *what;
5238 int err;
5239
5240 ptp_ocp_debugfs_init();
5241
5242 what = "timecard class";
5243 err = class_register(&timecard_class);
5244 if (err)
5245 goto out;
5246
5247 what = "i2c notifier";
5248 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
5249 if (err)
5250 goto out_notifier;
5251
5252 what = "ptp_ocp driver";
5253 err = pci_register_driver(&ptp_ocp_driver);
5254 if (err)
5255 goto out_register;
5256
5257 return 0;
5258
5259 out_register:
5260 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
5261 out_notifier:
5262 class_unregister(&timecard_class);
5263 out:
5264 ptp_ocp_debugfs_fini();
5265 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
5266 return err;
5267 }
5268
5269 static void __exit
ptp_ocp_fini(void)5270 ptp_ocp_fini(void)
5271 {
5272 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
5273 pci_unregister_driver(&ptp_ocp_driver);
5274 class_unregister(&timecard_class);
5275 ptp_ocp_debugfs_fini();
5276 }
5277
5278 module_init(ptp_ocp_init);
5279 module_exit(ptp_ocp_fini);
5280
5281 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
5282 MODULE_LICENSE("GPL v2");
5283