1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "timing_generator.h"
29 #include "hw_sequencer.h"
30 #include "hw_sequencer_private.h"
31 #include "basics/dc_common.h"
32 #include "resource.h"
33 #include "dc_dmub_srv.h"
34 #include "dc_state_priv.h"
35
36 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
37
38 /* used as index in array of black_color_format */
39 enum black_color_format {
40 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
41 BLACK_COLOR_FORMAT_RGB_LIMITED,
42 BLACK_COLOR_FORMAT_YUV_TV,
43 BLACK_COLOR_FORMAT_YUV_CV,
44 BLACK_COLOR_FORMAT_YUV_SUPER_AA,
45 BLACK_COLOR_FORMAT_DEBUG,
46 };
47
48 enum dc_color_space_type {
49 COLOR_SPACE_RGB_TYPE,
50 COLOR_SPACE_RGB_LIMITED_TYPE,
51 COLOR_SPACE_YCBCR601_TYPE,
52 COLOR_SPACE_YCBCR709_TYPE,
53 COLOR_SPACE_YCBCR2020_TYPE,
54 COLOR_SPACE_YCBCR601_LIMITED_TYPE,
55 COLOR_SPACE_YCBCR709_LIMITED_TYPE,
56 COLOR_SPACE_YCBCR709_BLACK_TYPE,
57 };
58
59 static const struct tg_color black_color_format[] = {
60 /* BlackColorFormat_RGB_FullRange */
61 {0, 0, 0},
62 /* BlackColorFormat_RGB_Limited */
63 {0x40, 0x40, 0x40},
64 /* BlackColorFormat_YUV_TV */
65 {0x200, 0x40, 0x200},
66 /* BlackColorFormat_YUV_CV */
67 {0x1f4, 0x40, 0x1f4},
68 /* BlackColorFormat_YUV_SuperAA */
69 {0x1a2, 0x20, 0x1a2},
70 /* visual confirm debug */
71 {0xff, 0xff, 0},
72 };
73
74 struct out_csc_color_matrix_type {
75 enum dc_color_space_type color_space_type;
76 uint16_t regval[12];
77 };
78
79 static const struct out_csc_color_matrix_type output_csc_matrix[] = {
80 { COLOR_SPACE_RGB_TYPE,
81 { 0x2000, 0, 0, 0,
82 0, 0x2000, 0, 0,
83 0, 0, 0x2000, 0} },
84 { COLOR_SPACE_RGB_LIMITED_TYPE,
85 { 0x1B67, 0, 0, 0x201,
86 0, 0x1B67, 0, 0x201,
87 0, 0, 0x1B67, 0x201} },
88 { COLOR_SPACE_YCBCR601_TYPE,
89 { 0xE04, 0xF444, 0xFDB9, 0x1004,
90 0x831, 0x1016, 0x320, 0x201,
91 0xFB45, 0xF6B7, 0xE04, 0x1004} },
92 { COLOR_SPACE_YCBCR709_TYPE,
93 { 0xE04, 0xF345, 0xFEB7, 0x1004,
94 0x5D3, 0x1399, 0x1FA, 0x201,
95 0xFCCA, 0xF533, 0xE04, 0x1004} },
96 /* TODO: correct values below */
97 { COLOR_SPACE_YCBCR601_LIMITED_TYPE,
98 { 0xE00, 0xF447, 0xFDB9, 0x1000,
99 0x991, 0x12C9, 0x3A6, 0x200,
100 0xFB47, 0xF6B9, 0xE00, 0x1000} },
101 { COLOR_SPACE_YCBCR709_LIMITED_TYPE,
102 { 0xE00, 0xF349, 0xFEB7, 0x1000,
103 0x6CE, 0x16E3, 0x24F, 0x200,
104 0xFCCB, 0xF535, 0xE00, 0x1000} },
105 { COLOR_SPACE_YCBCR2020_TYPE,
106 { 0x1000, 0xF149, 0xFEB7, 0x1004,
107 0x0868, 0x15B2, 0x01E6, 0x201,
108 0xFB88, 0xF478, 0x1000, 0x1004} },
109 { COLOR_SPACE_YCBCR709_BLACK_TYPE,
110 { 0x0000, 0x0000, 0x0000, 0x1000,
111 0x0000, 0x0000, 0x0000, 0x0200,
112 0x0000, 0x0000, 0x0000, 0x1000} },
113 };
114
is_rgb_type(enum dc_color_space color_space)115 static bool is_rgb_type(
116 enum dc_color_space color_space)
117 {
118 bool ret = false;
119
120 if (color_space == COLOR_SPACE_SRGB ||
121 color_space == COLOR_SPACE_XR_RGB ||
122 color_space == COLOR_SPACE_MSREF_SCRGB ||
123 color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
124 color_space == COLOR_SPACE_ADOBERGB ||
125 color_space == COLOR_SPACE_DCIP3 ||
126 color_space == COLOR_SPACE_DOLBYVISION)
127 ret = true;
128 return ret;
129 }
130
is_rgb_limited_type(enum dc_color_space color_space)131 static bool is_rgb_limited_type(
132 enum dc_color_space color_space)
133 {
134 bool ret = false;
135
136 if (color_space == COLOR_SPACE_SRGB_LIMITED ||
137 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
138 ret = true;
139 return ret;
140 }
141
is_ycbcr601_type(enum dc_color_space color_space)142 static bool is_ycbcr601_type(
143 enum dc_color_space color_space)
144 {
145 bool ret = false;
146
147 if (color_space == COLOR_SPACE_YCBCR601 ||
148 color_space == COLOR_SPACE_XV_YCC_601)
149 ret = true;
150 return ret;
151 }
152
is_ycbcr601_limited_type(enum dc_color_space color_space)153 static bool is_ycbcr601_limited_type(
154 enum dc_color_space color_space)
155 {
156 bool ret = false;
157
158 if (color_space == COLOR_SPACE_YCBCR601_LIMITED)
159 ret = true;
160 return ret;
161 }
162
is_ycbcr709_type(enum dc_color_space color_space)163 static bool is_ycbcr709_type(
164 enum dc_color_space color_space)
165 {
166 bool ret = false;
167
168 if (color_space == COLOR_SPACE_YCBCR709 ||
169 color_space == COLOR_SPACE_XV_YCC_709)
170 ret = true;
171 return ret;
172 }
173
is_ycbcr2020_type(enum dc_color_space color_space)174 static bool is_ycbcr2020_type(
175 enum dc_color_space color_space)
176 {
177 bool ret = false;
178
179 if (color_space == COLOR_SPACE_2020_YCBCR)
180 ret = true;
181 return ret;
182 }
183
is_ycbcr709_limited_type(enum dc_color_space color_space)184 static bool is_ycbcr709_limited_type(
185 enum dc_color_space color_space)
186 {
187 bool ret = false;
188
189 if (color_space == COLOR_SPACE_YCBCR709_LIMITED)
190 ret = true;
191 return ret;
192 }
193
get_color_space_type(enum dc_color_space color_space)194 static enum dc_color_space_type get_color_space_type(enum dc_color_space color_space)
195 {
196 enum dc_color_space_type type = COLOR_SPACE_RGB_TYPE;
197
198 if (is_rgb_type(color_space))
199 type = COLOR_SPACE_RGB_TYPE;
200 else if (is_rgb_limited_type(color_space))
201 type = COLOR_SPACE_RGB_LIMITED_TYPE;
202 else if (is_ycbcr601_type(color_space))
203 type = COLOR_SPACE_YCBCR601_TYPE;
204 else if (is_ycbcr709_type(color_space))
205 type = COLOR_SPACE_YCBCR709_TYPE;
206 else if (is_ycbcr601_limited_type(color_space))
207 type = COLOR_SPACE_YCBCR601_LIMITED_TYPE;
208 else if (is_ycbcr709_limited_type(color_space))
209 type = COLOR_SPACE_YCBCR709_LIMITED_TYPE;
210 else if (is_ycbcr2020_type(color_space))
211 type = COLOR_SPACE_YCBCR2020_TYPE;
212 else if (color_space == COLOR_SPACE_YCBCR709)
213 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
214 else if (color_space == COLOR_SPACE_YCBCR709_BLACK)
215 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
216 return type;
217 }
218
find_color_matrix(enum dc_color_space color_space,uint32_t * array_size)219 const uint16_t *find_color_matrix(enum dc_color_space color_space,
220 uint32_t *array_size)
221 {
222 int i;
223 enum dc_color_space_type type;
224 const uint16_t *val = NULL;
225 int arr_size = NUM_ELEMENTS(output_csc_matrix);
226
227 type = get_color_space_type(color_space);
228 for (i = 0; i < arr_size; i++)
229 if (output_csc_matrix[i].color_space_type == type) {
230 val = output_csc_matrix[i].regval;
231 *array_size = 12;
232 break;
233 }
234
235 return val;
236 }
237
238
color_space_to_black_color(const struct dc * dc,enum dc_color_space colorspace,struct tg_color * black_color)239 void color_space_to_black_color(
240 const struct dc *dc,
241 enum dc_color_space colorspace,
242 struct tg_color *black_color)
243 {
244 switch (colorspace) {
245 case COLOR_SPACE_YCBCR601:
246 case COLOR_SPACE_YCBCR709:
247 case COLOR_SPACE_YCBCR709_BLACK:
248 case COLOR_SPACE_YCBCR601_LIMITED:
249 case COLOR_SPACE_YCBCR709_LIMITED:
250 case COLOR_SPACE_2020_YCBCR:
251 *black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
252 break;
253
254 case COLOR_SPACE_SRGB_LIMITED:
255 *black_color =
256 black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
257 break;
258
259 /**
260 * Remove default and add case for all color space
261 * so when we forget to add new color space
262 * compiler will give a warning
263 */
264 case COLOR_SPACE_UNKNOWN:
265 case COLOR_SPACE_SRGB:
266 case COLOR_SPACE_XR_RGB:
267 case COLOR_SPACE_MSREF_SCRGB:
268 case COLOR_SPACE_XV_YCC_709:
269 case COLOR_SPACE_XV_YCC_601:
270 case COLOR_SPACE_2020_RGB_FULLRANGE:
271 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
272 case COLOR_SPACE_ADOBERGB:
273 case COLOR_SPACE_DCIP3:
274 case COLOR_SPACE_DISPLAYNATIVE:
275 case COLOR_SPACE_DOLBYVISION:
276 case COLOR_SPACE_APPCTRL:
277 case COLOR_SPACE_CUSTOMPOINTS:
278 /* fefault is sRGB black (full range). */
279 *black_color =
280 black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
281 /* default is sRGB black 0. */
282 break;
283 }
284 }
285
hwss_wait_for_blank_complete(struct timing_generator * tg)286 bool hwss_wait_for_blank_complete(
287 struct timing_generator *tg)
288 {
289 int counter;
290
291 /* Not applicable if the pipe is not primary, save 300ms of boot time */
292 if (!tg->funcs->is_blanked)
293 return true;
294 for (counter = 0; counter < 100; counter++) {
295 if (tg->funcs->is_blanked(tg))
296 break;
297
298 msleep(1);
299 }
300
301 if (counter == 100) {
302 dm_error("DC: failed to blank crtc!\n");
303 return false;
304 }
305
306 return true;
307 }
308
get_mpctree_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)309 void get_mpctree_visual_confirm_color(
310 struct pipe_ctx *pipe_ctx,
311 struct tg_color *color)
312 {
313 const struct tg_color pipe_colors[6] = {
314 {MAX_TG_COLOR_VALUE, 0, 0}, /* red */
315 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, /* orange */
316 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
317 {0, MAX_TG_COLOR_VALUE, 0}, /* green */
318 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */
319 {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, /* purple */
320 };
321
322 struct pipe_ctx *top_pipe = pipe_ctx;
323
324 while (top_pipe->top_pipe)
325 top_pipe = top_pipe->top_pipe;
326
327 *color = pipe_colors[top_pipe->pipe_idx];
328 }
329
get_surface_visual_confirm_color(const struct pipe_ctx * pipe_ctx,struct tg_color * color)330 void get_surface_visual_confirm_color(
331 const struct pipe_ctx *pipe_ctx,
332 struct tg_color *color)
333 {
334 uint32_t color_value = MAX_TG_COLOR_VALUE;
335
336 switch (pipe_ctx->plane_res.scl_data.format) {
337 case PIXEL_FORMAT_ARGB8888:
338 /* set border color to red */
339 color->color_r_cr = color_value;
340 if (pipe_ctx->plane_state->layer_index > 0) {
341 /* set border color to pink */
342 color->color_b_cb = color_value;
343 color->color_g_y = color_value * 0.5;
344 }
345 break;
346
347 case PIXEL_FORMAT_ARGB2101010:
348 /* set border color to blue */
349 color->color_b_cb = color_value;
350 if (pipe_ctx->plane_state->layer_index > 0) {
351 /* set border color to cyan */
352 color->color_g_y = color_value;
353 }
354 break;
355 case PIXEL_FORMAT_420BPP8:
356 /* set border color to green */
357 color->color_g_y = color_value;
358 break;
359 case PIXEL_FORMAT_420BPP10:
360 /* set border color to yellow */
361 color->color_g_y = color_value;
362 color->color_r_cr = color_value;
363 break;
364 case PIXEL_FORMAT_FP16:
365 /* set border color to white */
366 color->color_r_cr = color_value;
367 color->color_b_cb = color_value;
368 color->color_g_y = color_value;
369 if (pipe_ctx->plane_state->layer_index > 0) {
370 /* set border color to orange */
371 color->color_g_y = 0.22 * color_value;
372 color->color_b_cb = 0;
373 }
374 break;
375 default:
376 break;
377 }
378 }
379
get_hdr_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)380 void get_hdr_visual_confirm_color(
381 struct pipe_ctx *pipe_ctx,
382 struct tg_color *color)
383 {
384 uint32_t color_value = MAX_TG_COLOR_VALUE;
385 bool is_sdr = false;
386
387 /* Determine the overscan color based on the top-most (desktop) plane's context */
388 struct pipe_ctx *top_pipe_ctx = pipe_ctx;
389
390 while (top_pipe_ctx->top_pipe != NULL)
391 top_pipe_ctx = top_pipe_ctx->top_pipe;
392
393 switch (top_pipe_ctx->plane_res.scl_data.format) {
394 case PIXEL_FORMAT_ARGB2101010:
395 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
396 /* HDR10, ARGB2101010 - set border color to red */
397 color->color_r_cr = color_value;
398 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
399 /* FreeSync 2 ARGB2101010 - set border color to pink */
400 color->color_r_cr = color_value;
401 color->color_b_cb = color_value;
402 } else
403 is_sdr = true;
404 break;
405 case PIXEL_FORMAT_FP16:
406 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
407 /* HDR10, FP16 - set border color to blue */
408 color->color_b_cb = color_value;
409 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
410 /* FreeSync 2 HDR - set border color to green */
411 color->color_g_y = color_value;
412 } else
413 is_sdr = true;
414 break;
415 default:
416 is_sdr = true;
417 break;
418 }
419
420 if (is_sdr) {
421 /* SDR - set border color to Gray */
422 color->color_r_cr = color_value/2;
423 color->color_b_cb = color_value/2;
424 color->color_g_y = color_value/2;
425 }
426 }
427
get_subvp_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)428 void get_subvp_visual_confirm_color(
429 struct pipe_ctx *pipe_ctx,
430 struct tg_color *color)
431 {
432 uint32_t color_value = MAX_TG_COLOR_VALUE;
433 if (pipe_ctx) {
434 switch (pipe_ctx->p_state_type) {
435 case P_STATE_SUB_VP:
436 color->color_r_cr = color_value;
437 color->color_g_y = 0;
438 color->color_b_cb = 0;
439 break;
440 case P_STATE_DRR_SUB_VP:
441 color->color_r_cr = 0;
442 color->color_g_y = color_value;
443 color->color_b_cb = 0;
444 break;
445 case P_STATE_V_BLANK_SUB_VP:
446 color->color_r_cr = 0;
447 color->color_g_y = 0;
448 color->color_b_cb = color_value;
449 break;
450 default:
451 break;
452 }
453 }
454 }
455
get_mclk_switch_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)456 void get_mclk_switch_visual_confirm_color(
457 struct pipe_ctx *pipe_ctx,
458 struct tg_color *color)
459 {
460 uint32_t color_value = MAX_TG_COLOR_VALUE;
461
462 if (pipe_ctx) {
463 switch (pipe_ctx->p_state_type) {
464 case P_STATE_V_BLANK:
465 color->color_r_cr = color_value;
466 color->color_g_y = color_value;
467 color->color_b_cb = 0;
468 break;
469 case P_STATE_FPO:
470 color->color_r_cr = 0;
471 color->color_g_y = color_value;
472 color->color_b_cb = color_value;
473 break;
474 case P_STATE_V_ACTIVE:
475 color->color_r_cr = color_value;
476 color->color_g_y = 0;
477 color->color_b_cb = color_value;
478 break;
479 case P_STATE_SUB_VP:
480 color->color_r_cr = color_value;
481 color->color_g_y = 0;
482 color->color_b_cb = 0;
483 break;
484 case P_STATE_DRR_SUB_VP:
485 color->color_r_cr = 0;
486 color->color_g_y = color_value;
487 color->color_b_cb = 0;
488 break;
489 case P_STATE_V_BLANK_SUB_VP:
490 color->color_r_cr = 0;
491 color->color_g_y = 0;
492 color->color_b_cb = color_value;
493 break;
494 default:
495 break;
496 }
497 }
498 }
499
set_p_state_switch_method(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)500 void set_p_state_switch_method(
501 struct dc *dc,
502 struct dc_state *context,
503 struct pipe_ctx *pipe_ctx)
504 {
505 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
506 bool enable_subvp;
507
508 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)
509 return;
510
511 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] !=
512 dm_dram_clock_change_unsupported) {
513 /* MCLK switching is supported */
514 if (!pipe_ctx->has_vactive_margin) {
515 /* In Vblank - yellow */
516 pipe_ctx->p_state_type = P_STATE_V_BLANK;
517
518 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
519 /* FPO + Vblank - cyan */
520 pipe_ctx->p_state_type = P_STATE_FPO;
521 }
522 } else {
523 /* In Vactive - pink */
524 pipe_ctx->p_state_type = P_STATE_V_ACTIVE;
525 }
526
527 /* SubVP */
528 enable_subvp = false;
529
530 for (int i = 0; i < dc->res_pool->pipe_count; i++) {
531 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
532
533 if (pipe->stream && dc_state_get_paired_subvp_stream(context, pipe->stream) &&
534 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {
535 /* SubVP enable - red */
536 pipe_ctx->p_state_type = P_STATE_SUB_VP;
537 enable_subvp = true;
538
539 if (pipe_ctx->stream == pipe->stream)
540 return;
541 break;
542 }
543 }
544
545 if (enable_subvp && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) {
546 if (pipe_ctx->stream->allow_freesync == 1) {
547 /* SubVP enable and DRR on - green */
548 pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;
549 } else {
550 /* SubVP enable and No DRR - blue */
551 pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;
552 }
553 }
554 }
555 }
556
get_fams2_visual_confirm_color(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx,struct tg_color * color)557 void get_fams2_visual_confirm_color(
558 struct dc *dc,
559 struct dc_state *context,
560 struct pipe_ctx *pipe_ctx,
561 struct tg_color *color)
562 {
563 uint32_t color_value = MAX_TG_COLOR_VALUE;
564
565 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)
566 return;
567
568 /* driver only handles visual confirm when FAMS2 is disabled */
569 if (!dc_state_is_fams2_in_use(dc, context)) {
570 /* when FAMS2 is disabled, all pipes are grey */
571 color->color_g_y = color_value / 2;
572 color->color_b_cb = color_value / 2;
573 color->color_r_cr = color_value / 2;
574 }
575 }
576
hwss_build_fast_sequence(struct dc * dc,struct dc_dmub_cmd * dc_dmub_cmd,unsigned int dmub_cmd_count,struct block_sequence block_sequence[],unsigned int * num_steps,struct pipe_ctx * pipe_ctx,struct dc_stream_status * stream_status,struct dc_state * context)577 void hwss_build_fast_sequence(struct dc *dc,
578 struct dc_dmub_cmd *dc_dmub_cmd,
579 unsigned int dmub_cmd_count,
580 struct block_sequence block_sequence[],
581 unsigned int *num_steps,
582 struct pipe_ctx *pipe_ctx,
583 struct dc_stream_status *stream_status,
584 struct dc_state *context)
585 {
586 struct dc_plane_state *plane = pipe_ctx->plane_state;
587 struct dc_stream_state *stream = pipe_ctx->stream;
588 struct dce_hwseq *hws = dc->hwseq;
589 struct pipe_ctx *current_pipe = NULL;
590 struct pipe_ctx *current_mpc_pipe = NULL;
591 unsigned int i = 0;
592
593 *num_steps = 0; // Initialize to 0
594
595 if (!plane || !stream)
596 return;
597
598 if (dc->hwss.wait_for_dcc_meta_propagation) {
599 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;
600 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;
601 block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;
602 (*num_steps)++;
603 }
604 if (dc->hwss.subvp_pipe_control_lock_fast) {
605 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
606 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;
607 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
608 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
609 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
610 (*num_steps)++;
611 }
612 if (dc->hwss.fams2_global_control_lock_fast) {
613 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;
614 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = true;
615 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
616 block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST;
617 (*num_steps)++;
618 }
619 if (dc->hwss.pipe_control_lock) {
620 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
621 block_sequence[*num_steps].params.pipe_control_lock_params.lock = true;
622 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
623 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
624 (*num_steps)++;
625 }
626
627 for (i = 0; i < dmub_cmd_count; i++) {
628 block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx;
629 block_sequence[*num_steps].params.send_dmcub_cmd_params.cmd = &(dc_dmub_cmd[i].dmub_cmd);
630 block_sequence[*num_steps].params.send_dmcub_cmd_params.wait_type = dc_dmub_cmd[i].wait_type;
631 block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD;
632 (*num_steps)++;
633 }
634
635 current_pipe = pipe_ctx;
636 while (current_pipe) {
637 current_mpc_pipe = current_pipe;
638 while (current_mpc_pipe) {
639 if (current_mpc_pipe->plane_state) {
640 if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) {
641 block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe;
642 block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;
643 block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
644 (*num_steps)++;
645 }
646 if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {
647 block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;
648 block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;
649 block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;
650 block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
651 (*num_steps)++;
652 }
653 if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {
654 if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) &&
655 stream_status->mall_stream_config.type == SUBVP_MAIN) {
656 block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;
657 block_sequence[*num_steps].params.subvp_save_surf_addr.addr = ¤t_mpc_pipe->plane_state->address;
658 block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index;
659 block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
660 (*num_steps)++;
661 }
662
663 block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;
664 block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;
665 block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;
666 (*num_steps)++;
667 }
668
669 if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {
670 block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
671 block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;
672 block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;
673 block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
674 (*num_steps)++;
675 }
676
677 if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {
678 block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;
679 block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
680 (*num_steps)++;
681 }
682 if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) {
683 block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;
684 block_sequence[*num_steps].func = DPP_SETUP_DPP;
685 (*num_steps)++;
686 }
687 if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) {
688 block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;
689 block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
690 (*num_steps)++;
691 }
692 }
693 if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
694 block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
695 block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;
696 block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream;
697 block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
698 (*num_steps)++;
699 }
700
701 if (current_mpc_pipe->stream->update_flags.bits.out_csc) {
702 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;
703 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
704 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
705 block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
706 (*num_steps)++;
707
708 if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {
709 block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
710 block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
711 block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;
712 block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
713 block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;
714 (*num_steps)++;
715 } else {
716 block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;
717 block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
718 block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;
719 block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
720 block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;
721 (*num_steps)++;
722 }
723 }
724 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
725 }
726 current_pipe = current_pipe->next_odm_pipe;
727 }
728
729 if (dc->hwss.pipe_control_lock) {
730 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
731 block_sequence[*num_steps].params.pipe_control_lock_params.lock = false;
732 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
733 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
734 (*num_steps)++;
735 }
736 if (dc->hwss.subvp_pipe_control_lock_fast) {
737 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
738 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false;
739 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
740 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
741 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
742 (*num_steps)++;
743 }
744 if (dc->hwss.fams2_global_control_lock_fast) {
745 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;
746 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = false;
747 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
748 block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST;
749 (*num_steps)++;
750 }
751
752 current_pipe = pipe_ctx;
753 while (current_pipe) {
754 current_mpc_pipe = current_pipe;
755
756 while (current_mpc_pipe) {
757 if (!current_mpc_pipe->bottom_pipe && !current_mpc_pipe->next_odm_pipe &&
758 current_mpc_pipe->stream && current_mpc_pipe->plane_state &&
759 current_mpc_pipe->plane_state->update_flags.bits.addr_update &&
760 !current_mpc_pipe->plane_state->skip_manual_trigger) {
761 block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;
762 block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;
763 (*num_steps)++;
764 }
765 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
766 }
767 current_pipe = current_pipe->next_odm_pipe;
768 }
769 }
770
hwss_execute_sequence(struct dc * dc,struct block_sequence block_sequence[],int num_steps)771 void hwss_execute_sequence(struct dc *dc,
772 struct block_sequence block_sequence[],
773 int num_steps)
774 {
775 unsigned int i;
776 union block_sequence_params *params;
777 struct dce_hwseq *hws = dc->hwseq;
778
779 for (i = 0; i < num_steps; i++) {
780 params = &(block_sequence[i].params);
781 switch (block_sequence[i].func) {
782
783 case DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST:
784 dc->hwss.subvp_pipe_control_lock_fast(params);
785 break;
786 case OPTC_PIPE_CONTROL_LOCK:
787 dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc,
788 params->pipe_control_lock_params.pipe_ctx,
789 params->pipe_control_lock_params.lock);
790 break;
791 case HUBP_SET_FLIP_CONTROL_GSL:
792 dc->hwss.set_flip_control_gsl(params->set_flip_control_gsl_params.pipe_ctx,
793 params->set_flip_control_gsl_params.flip_immediate);
794 break;
795 case HUBP_PROGRAM_TRIPLEBUFFER:
796 dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc,
797 params->program_triplebuffer_params.pipe_ctx,
798 params->program_triplebuffer_params.enableTripleBuffer);
799 break;
800 case HUBP_UPDATE_PLANE_ADDR:
801 dc->hwss.update_plane_addr(params->update_plane_addr_params.dc,
802 params->update_plane_addr_params.pipe_ctx);
803 break;
804 case DPP_SET_INPUT_TRANSFER_FUNC:
805 hws->funcs.set_input_transfer_func(params->set_input_transfer_func_params.dc,
806 params->set_input_transfer_func_params.pipe_ctx,
807 params->set_input_transfer_func_params.plane_state);
808 break;
809 case DPP_PROGRAM_GAMUT_REMAP:
810 dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);
811 break;
812 case DPP_SETUP_DPP:
813 hwss_setup_dpp(params);
814 break;
815 case DPP_PROGRAM_BIAS_AND_SCALE:
816 hwss_program_bias_and_scale(params);
817 break;
818 case OPTC_PROGRAM_MANUAL_TRIGGER:
819 hwss_program_manual_trigger(params);
820 break;
821 case DPP_SET_OUTPUT_TRANSFER_FUNC:
822 hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc,
823 params->set_output_transfer_func_params.pipe_ctx,
824 params->set_output_transfer_func_params.stream);
825 break;
826 case MPC_UPDATE_VISUAL_CONFIRM:
827 dc->hwss.update_visual_confirm_color(params->update_visual_confirm_params.dc,
828 params->update_visual_confirm_params.pipe_ctx,
829 params->update_visual_confirm_params.mpcc_id);
830 break;
831 case MPC_POWER_ON_MPC_MEM_PWR:
832 hwss_power_on_mpc_mem_pwr(params);
833 break;
834 case MPC_SET_OUTPUT_CSC:
835 hwss_set_output_csc(params);
836 break;
837 case MPC_SET_OCSC_DEFAULT:
838 hwss_set_ocsc_default(params);
839 break;
840 case DMUB_SEND_DMCUB_CMD:
841 hwss_send_dmcub_cmd(params);
842 break;
843 case DMUB_SUBVP_SAVE_SURF_ADDR:
844 hwss_subvp_save_surf_addr(params);
845 break;
846 case HUBP_WAIT_FOR_DCC_META_PROP:
847 dc->hwss.wait_for_dcc_meta_propagation(
848 params->wait_for_dcc_meta_propagation_params.dc,
849 params->wait_for_dcc_meta_propagation_params.top_pipe_to_program);
850 break;
851 case DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST:
852 dc->hwss.fams2_global_control_lock_fast(params);
853 break;
854 default:
855 ASSERT(false);
856 break;
857 }
858 }
859 }
860
hwss_send_dmcub_cmd(union block_sequence_params * params)861 void hwss_send_dmcub_cmd(union block_sequence_params *params)
862 {
863 struct dc_context *ctx = params->send_dmcub_cmd_params.ctx;
864 union dmub_rb_cmd *cmd = params->send_dmcub_cmd_params.cmd;
865 enum dm_dmub_wait_type wait_type = params->send_dmcub_cmd_params.wait_type;
866
867 dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type);
868 }
869
hwss_program_manual_trigger(union block_sequence_params * params)870 void hwss_program_manual_trigger(union block_sequence_params *params)
871 {
872 struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx;
873
874 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
875 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
876 }
877
hwss_setup_dpp(union block_sequence_params * params)878 void hwss_setup_dpp(union block_sequence_params *params)
879 {
880 struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx;
881 struct dpp *dpp = pipe_ctx->plane_res.dpp;
882 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
883
884 if (dpp && dpp->funcs->dpp_setup) {
885 // program the input csc
886 dpp->funcs->dpp_setup(dpp,
887 plane_state->format,
888 EXPANSION_MODE_ZERO,
889 plane_state->input_csc_color_matrix,
890 plane_state->color_space,
891 NULL);
892 }
893
894 if (dpp && dpp->funcs->set_cursor_matrix) {
895 dpp->funcs->set_cursor_matrix(dpp,
896 plane_state->color_space,
897 plane_state->cursor_csc_color_matrix);
898 }
899 }
900
hwss_program_bias_and_scale(union block_sequence_params * params)901 void hwss_program_bias_and_scale(union block_sequence_params *params)
902 {
903 struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx;
904 struct dpp *dpp = pipe_ctx->plane_res.dpp;
905 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
906 struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;
907
908 //TODO :for CNVC set scale and bias registers if necessary
909 if (dpp->funcs->dpp_program_bias_and_scale) {
910 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
911 }
912 }
913
hwss_power_on_mpc_mem_pwr(union block_sequence_params * params)914 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
915 {
916 struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;
917 int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id;
918 bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
919
920 if (mpc->funcs->power_on_mpc_mem_pwr)
921 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
922 }
923
hwss_set_output_csc(union block_sequence_params * params)924 void hwss_set_output_csc(union block_sequence_params *params)
925 {
926 struct mpc *mpc = params->set_output_csc_params.mpc;
927 int opp_id = params->set_output_csc_params.opp_id;
928 const uint16_t *matrix = params->set_output_csc_params.regval;
929 enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode;
930
931 if (mpc->funcs->set_output_csc != NULL)
932 mpc->funcs->set_output_csc(mpc,
933 opp_id,
934 matrix,
935 ocsc_mode);
936 }
937
hwss_set_ocsc_default(union block_sequence_params * params)938 void hwss_set_ocsc_default(union block_sequence_params *params)
939 {
940 struct mpc *mpc = params->set_ocsc_default_params.mpc;
941 int opp_id = params->set_ocsc_default_params.opp_id;
942 enum dc_color_space colorspace = params->set_ocsc_default_params.color_space;
943 enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode;
944
945 if (mpc->funcs->set_ocsc_default != NULL)
946 mpc->funcs->set_ocsc_default(mpc,
947 opp_id,
948 colorspace,
949 ocsc_mode);
950 }
951
hwss_subvp_save_surf_addr(union block_sequence_params * params)952 void hwss_subvp_save_surf_addr(union block_sequence_params *params)
953 {
954 struct dc_dmub_srv *dc_dmub_srv = params->subvp_save_surf_addr.dc_dmub_srv;
955 const struct dc_plane_address *addr = params->subvp_save_surf_addr.addr;
956 uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index;
957
958 dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index);
959 }
960
get_surface_tile_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)961 void get_surface_tile_visual_confirm_color(
962 struct pipe_ctx *pipe_ctx,
963 struct tg_color *color)
964 {
965 uint32_t color_value = MAX_TG_COLOR_VALUE;
966 /* Determine the overscan color based on the bottom-most plane's context */
967 struct pipe_ctx *bottom_pipe_ctx = pipe_ctx;
968
969 while (bottom_pipe_ctx->bottom_pipe != NULL)
970 bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;
971
972 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
973 case DC_SW_LINEAR:
974 /* LINEAR Surface - set border color to red */
975 color->color_r_cr = color_value;
976 break;
977 default:
978 break;
979 }
980 }
981
982 /**
983 * hwss_wait_for_all_blank_complete - wait for all active OPPs to finish pending blank
984 * pattern updates
985 *
986 * @dc: [in] dc reference
987 * @context: [in] hardware context in use
988 */
hwss_wait_for_all_blank_complete(struct dc * dc,struct dc_state * context)989 void hwss_wait_for_all_blank_complete(struct dc *dc,
990 struct dc_state *context)
991 {
992 struct pipe_ctx *opp_head;
993 struct dce_hwseq *hws = dc->hwseq;
994 int i;
995
996 if (!hws->funcs.wait_for_blank_complete)
997 return;
998
999 for (i = 0; i < MAX_PIPES; i++) {
1000 opp_head = &context->res_ctx.pipe_ctx[i];
1001
1002 if (!resource_is_pipe_type(opp_head, OPP_HEAD) ||
1003 dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM)
1004 continue;
1005
1006 hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp);
1007 }
1008 }
1009
hwss_wait_for_odm_update_pending_complete(struct dc * dc,struct dc_state * context)1010 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)
1011 {
1012 struct pipe_ctx *otg_master;
1013 struct timing_generator *tg;
1014 int i;
1015
1016 for (i = 0; i < MAX_PIPES; i++) {
1017 otg_master = &context->res_ctx.pipe_ctx[i];
1018 if (!resource_is_pipe_type(otg_master, OTG_MASTER) ||
1019 dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM)
1020 continue;
1021 tg = otg_master->stream_res.tg;
1022 if (tg->funcs->wait_odm_doublebuffer_pending_clear)
1023 tg->funcs->wait_odm_doublebuffer_pending_clear(tg);
1024 }
1025
1026 /* ODM update may require to reprogram blank pattern for each OPP */
1027 hwss_wait_for_all_blank_complete(dc, context);
1028 }
1029
hwss_wait_for_no_pipes_pending(struct dc * dc,struct dc_state * context)1030 void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1031 {
1032 int i;
1033 for (i = 0; i < MAX_PIPES; i++) {
1034 int count = 0;
1035 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1036
1037 if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
1038 continue;
1039
1040 /* Timeout 100 ms */
1041 while (count < 100000) {
1042 /* Must set to false to start with, due to OR in update function */
1043 pipe->plane_state->status.is_flip_pending = false;
1044 dc->hwss.update_pending_status(pipe);
1045 if (!pipe->plane_state->status.is_flip_pending)
1046 break;
1047 udelay(1);
1048 count++;
1049 }
1050 ASSERT(!pipe->plane_state->status.is_flip_pending);
1051 }
1052 }
1053
hwss_wait_for_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)1054 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
1055 {
1056 /*
1057 * This function calls HWSS to wait for any potentially double buffered
1058 * operations to complete. It should be invoked as a pre-amble prior
1059 * to full update programming before asserting any HW locks.
1060 */
1061 int pipe_idx;
1062 int opp_inst;
1063 int opp_count = dc->res_pool->res_cap->num_opp;
1064 struct hubp *hubp;
1065 int mpcc_inst;
1066 const struct pipe_ctx *pipe_ctx;
1067
1068 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
1069 pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];
1070
1071 if (!pipe_ctx->stream)
1072 continue;
1073
1074 if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
1075 pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
1076
1077 hubp = pipe_ctx->plane_res.hubp;
1078 if (!hubp)
1079 continue;
1080
1081 mpcc_inst = hubp->inst;
1082 // MPCC inst is equal to pipe index in practice
1083 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1084 if ((dc->res_pool->opps[opp_inst] != NULL) &&
1085 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {
1086 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1087 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1088 break;
1089 }
1090 }
1091 }
1092 hwss_wait_for_odm_update_pending_complete(dc, dc_context);
1093 }
1094
hwss_process_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)1095 void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
1096 {
1097 /* wait for outstanding updates */
1098 hwss_wait_for_outstanding_hw_updates(dc, dc_context);
1099
1100 /* perform outstanding post update programming */
1101 if (dc->hwss.program_outstanding_updates)
1102 dc->hwss.program_outstanding_updates(dc, dc_context);
1103 }
1104