1 /*
2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/kernfs.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_discovery.h"
29 #include "soc15_hw_ip.h"
30 #include "discovery.h"
31 #include "amdgpu_ras.h"
32
33 #include "soc15.h"
34 #include "gfx_v9_0.h"
35 #include "gfx_v9_4_3.h"
36 #include "gmc_v9_0.h"
37 #include "df_v1_7.h"
38 #include "df_v3_6.h"
39 #include "df_v4_3.h"
40 #include "df_v4_6_2.h"
41 #include "df_v4_15.h"
42 #include "nbio_v6_1.h"
43 #include "nbio_v7_0.h"
44 #include "nbio_v7_4.h"
45 #include "nbio_v7_9.h"
46 #include "nbio_v7_11.h"
47 #include "hdp_v4_0.h"
48 #include "vega10_ih.h"
49 #include "vega20_ih.h"
50 #include "sdma_v4_0.h"
51 #include "sdma_v4_4_2.h"
52 #include "uvd_v7_0.h"
53 #include "vce_v4_0.h"
54 #include "vcn_v1_0.h"
55 #include "vcn_v2_5.h"
56 #include "jpeg_v2_5.h"
57 #include "smuio_v9_0.h"
58 #include "gmc_v10_0.h"
59 #include "gmc_v11_0.h"
60 #include "gmc_v12_0.h"
61 #include "gfxhub_v2_0.h"
62 #include "mmhub_v2_0.h"
63 #include "nbio_v2_3.h"
64 #include "nbio_v4_3.h"
65 #include "nbio_v7_2.h"
66 #include "nbio_v7_7.h"
67 #include "nbif_v6_3_1.h"
68 #include "nbio_v6_3_2.h"
69 #include "hdp_v5_0.h"
70 #include "hdp_v5_2.h"
71 #include "hdp_v6_0.h"
72 #include "hdp_v7_0.h"
73 #include "nv.h"
74 #include "soc21.h"
75 #include "soc24.h"
76 #include "soc_v1_0.h"
77 #include "navi10_ih.h"
78 #include "ih_v6_0.h"
79 #include "ih_v6_1.h"
80 #include "ih_v7_0.h"
81 #include "gfx_v10_0.h"
82 #include "gfx_v11_0.h"
83 #include "gfx_v12_0.h"
84 #include "gfx_v12_1.h"
85 #include "sdma_v5_0.h"
86 #include "sdma_v5_2.h"
87 #include "sdma_v6_0.h"
88 #include "sdma_v7_0.h"
89 #include "sdma_v7_1.h"
90 #include "lsdma_v6_0.h"
91 #include "lsdma_v7_0.h"
92 #include "lsdma_v7_1.h"
93 #include "vcn_v2_0.h"
94 #include "jpeg_v2_0.h"
95 #include "vcn_v3_0.h"
96 #include "jpeg_v3_0.h"
97 #include "vcn_v4_0.h"
98 #include "jpeg_v4_0.h"
99 #include "vcn_v4_0_3.h"
100 #include "jpeg_v4_0_3.h"
101 #include "vcn_v4_0_5.h"
102 #include "jpeg_v4_0_5.h"
103 #include "amdgpu_vkms.h"
104 #include "mes_v11_0.h"
105 #include "mes_v12_0.h"
106 #include "mes_v12_1.h"
107 #include "smuio_v11_0.h"
108 #include "smuio_v11_0_6.h"
109 #include "smuio_v13_0.h"
110 #include "smuio_v13_0_3.h"
111 #include "smuio_v13_0_6.h"
112 #include "smuio_v14_0_2.h"
113 #include "smuio_v15_0_0.h"
114 #include "smuio_v15_0_8.h"
115 #include "vcn_v5_0_0.h"
116 #include "vcn_v5_0_1.h"
117 #include "vcn_v5_0_2.h"
118 #include "jpeg_v5_0_0.h"
119 #include "jpeg_v5_0_1.h"
120 #include "jpeg_v5_0_2.h"
121 #include "jpeg_v5_3_0.h"
122
123 #include "amdgpu_ras_mgr.h"
124
125 #include "amdgpu_vpe.h"
126 #if defined(CONFIG_DRM_AMD_ISP)
127 #include "amdgpu_isp.h"
128 #endif
129
130 MODULE_FIRMWARE("amdgpu/ip_discovery.bin");
131 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin");
132 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin");
133 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin");
134 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin");
135 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin");
136 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin");
137 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin");
138 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin");
139
140 /* Note: These registers are consistent across all the SOCs */
141 #define mmIP_DISCOVERY_VERSION 0x16A00
142 #define mmRCC_CONFIG_MEMSIZE 0xde3
143 #define mmMP0_SMN_C2PMSG_33 0x16061
144 #define mmMM_INDEX 0x0
145 #define mmMM_INDEX_HI 0x6
146 #define mmMM_DATA 0x1
147
148 #define mmDRIVER_SCRATCH_0 0x94
149 #define mmDRIVER_SCRATCH_1 0x95
150 #define mmDRIVER_SCRATCH_2 0x96
151
152 struct ip_discovery_top {
153 struct kobject kobj;
154 struct kset die_kset;
155 struct pci_dev *pdev;
156 struct amdgpu_device *adev;
157 uint8_t *discovery_bin;
158 uint32_t bin_size;
159 bool standalone_mode;
160 };
161
162 /* List to track early-initialized ip_discovery_top entries */
163 struct early_ip_discovery {
164 struct list_head list;
165 struct pci_dev *pdev;
166 struct ip_discovery_top *ip_top;
167 };
168
169 static LIST_HEAD(early_ip_discovery_list);
170 static DEFINE_MUTEX(early_ip_discovery_mutex);
171
172 static const char *hw_id_names[HW_ID_MAX] = {
173 [MP1_HWID] = "MP1",
174 [MP2_HWID] = "MP2",
175 [THM_HWID] = "THM",
176 [SMUIO_HWID] = "SMUIO",
177 [FUSE_HWID] = "FUSE",
178 [CLKA_HWID] = "CLKA",
179 [PWR_HWID] = "PWR",
180 [GC_HWID] = "GC",
181 [UVD_HWID] = "UVD",
182 [AUDIO_AZ_HWID] = "AUDIO_AZ",
183 [ACP_HWID] = "ACP",
184 [DCI_HWID] = "DCI",
185 [DMU_HWID] = "DMU",
186 [DCO_HWID] = "DCO",
187 [DIO_HWID] = "DIO",
188 [XDMA_HWID] = "XDMA",
189 [DCEAZ_HWID] = "DCEAZ",
190 [DAZ_HWID] = "DAZ",
191 [SDPMUX_HWID] = "SDPMUX",
192 [NTB_HWID] = "NTB",
193 [IOHC_HWID] = "IOHC",
194 [L2IMU_HWID] = "L2IMU",
195 [VCE_HWID] = "VCE",
196 [MMHUB_HWID] = "MMHUB",
197 [ATHUB_HWID] = "ATHUB",
198 [DBGU_NBIO_HWID] = "DBGU_NBIO",
199 [DFX_HWID] = "DFX",
200 [DBGU0_HWID] = "DBGU0",
201 [DBGU1_HWID] = "DBGU1",
202 [OSSSYS_HWID] = "OSSSYS",
203 [HDP_HWID] = "HDP",
204 [SDMA0_HWID] = "SDMA0",
205 [SDMA1_HWID] = "SDMA1",
206 [SDMA2_HWID] = "SDMA2",
207 [SDMA3_HWID] = "SDMA3",
208 [LSDMA_HWID] = "LSDMA",
209 [ISP_HWID] = "ISP",
210 [DBGU_IO_HWID] = "DBGU_IO",
211 [DF_HWID] = "DF",
212 [CLKB_HWID] = "CLKB",
213 [FCH_HWID] = "FCH",
214 [DFX_DAP_HWID] = "DFX_DAP",
215 [L1IMU_PCIE_HWID] = "L1IMU_PCIE",
216 [L1IMU_NBIF_HWID] = "L1IMU_NBIF",
217 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
218 [L1IMU3_HWID] = "L1IMU3",
219 [L1IMU4_HWID] = "L1IMU4",
220 [L1IMU5_HWID] = "L1IMU5",
221 [L1IMU6_HWID] = "L1IMU6",
222 [L1IMU7_HWID] = "L1IMU7",
223 [L1IMU8_HWID] = "L1IMU8",
224 [L1IMU9_HWID] = "L1IMU9",
225 [L1IMU10_HWID] = "L1IMU10",
226 [L1IMU11_HWID] = "L1IMU11",
227 [L1IMU12_HWID] = "L1IMU12",
228 [L1IMU13_HWID] = "L1IMU13",
229 [L1IMU14_HWID] = "L1IMU14",
230 [L1IMU15_HWID] = "L1IMU15",
231 [WAFLC_HWID] = "WAFLC",
232 [FCH_USB_PD_HWID] = "FCH_USB_PD",
233 [PCIE_HWID] = "PCIE",
234 [PCS_HWID] = "PCS",
235 [DDCL_HWID] = "DDCL",
236 [SST_HWID] = "SST",
237 [IOAGR_HWID] = "IOAGR",
238 [NBIF_HWID] = "NBIF",
239 [IOAPIC_HWID] = "IOAPIC",
240 [SYSTEMHUB_HWID] = "SYSTEMHUB",
241 [NTBCCP_HWID] = "NTBCCP",
242 [UMC_HWID] = "UMC",
243 [SATA_HWID] = "SATA",
244 [USB_HWID] = "USB",
245 [CCXSEC_HWID] = "CCXSEC",
246 [XGMI_HWID] = "XGMI",
247 [XGBE_HWID] = "XGBE",
248 [MP0_HWID] = "MP0",
249 [VPE_HWID] = "VPE",
250 [UMSCH_HWID] = "UMSCH",
251 [ATU_HWID] = "ATU",
252 [AIGC_HWID] = "AIGC",
253 };
254
255 static int hw_id_map[MAX_HWIP] = {
256 [GC_HWIP] = GC_HWID,
257 [HDP_HWIP] = HDP_HWID,
258 [SDMA0_HWIP] = SDMA0_HWID,
259 [SDMA1_HWIP] = SDMA1_HWID,
260 [SDMA2_HWIP] = SDMA2_HWID,
261 [SDMA3_HWIP] = SDMA3_HWID,
262 [LSDMA_HWIP] = LSDMA_HWID,
263 [MMHUB_HWIP] = MMHUB_HWID,
264 [ATHUB_HWIP] = ATHUB_HWID,
265 [NBIO_HWIP] = NBIF_HWID,
266 [MP0_HWIP] = MP0_HWID,
267 [MP1_HWIP] = MP1_HWID,
268 [UVD_HWIP] = UVD_HWID,
269 [VCE_HWIP] = VCE_HWID,
270 [DF_HWIP] = DF_HWID,
271 [DCE_HWIP] = DMU_HWID,
272 [OSSSYS_HWIP] = OSSSYS_HWID,
273 [SMUIO_HWIP] = SMUIO_HWID,
274 [PWR_HWIP] = PWR_HWID,
275 [NBIF_HWIP] = NBIF_HWID,
276 [THM_HWIP] = THM_HWID,
277 [CLK_HWIP] = CLKA_HWID,
278 [UMC_HWIP] = UMC_HWID,
279 [XGMI_HWIP] = XGMI_HWID,
280 [DCI_HWIP] = DCI_HWID,
281 [PCIE_HWIP] = PCIE_HWID,
282 [VPE_HWIP] = VPE_HWID,
283 [UMSCH_HWIP] = UMSCH_HWID,
284 [ISP_HWIP] = ISP_HWID,
285 [ATU_HWIP] = ATU_HWID,
286 };
287
amdgpu_discovery_get_tmr_info(struct amdgpu_device * adev,bool * is_tmr_in_sysmem)288 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev,
289 bool *is_tmr_in_sysmem)
290 {
291 u64 vram_size, tmr_offset, tmr_size;
292 u32 msg, tmr_offset_lo, tmr_offset_hi;
293 int i, ret;
294
295 if (!amdgpu_sriov_vf(adev)) {
296 /* It can take up to two second for IFWI init to complete on some dGPUs,
297 * but generally it should be in the 60-100ms range. Normally this starts
298 * as soon as the device gets power so by the time the OS loads this has long
299 * completed. However, when a card is hotplugged via e.g., USB4, we need to
300 * wait for this to complete. Once the C2PMSG is updated, we can
301 * continue.
302 */
303
304 for (i = 0; i < 2000; i++) {
305 msg = RREG32(mmMP0_SMN_C2PMSG_33);
306 if (msg & 0x80000000)
307 break;
308 msleep(1);
309 }
310 }
311
312 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE);
313 if (vram_size == U32_MAX)
314 return -ENXIO;
315 else if (!vram_size)
316 *is_tmr_in_sysmem = true;
317 else
318 *is_tmr_in_sysmem = false;
319
320 /* init the default tmr size and offset */
321 adev->discovery.size = DISCOVERY_TMR_SIZE;
322 if (vram_size)
323 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET;
324
325 if (amdgpu_sriov_vf(adev)) {
326 if (adev->virt.is_dynamic_crit_regn_enabled) {
327 adev->discovery.offset =
328 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset;
329 adev->discovery.size =
330 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10;
331 if (!adev->discovery.size)
332 return -EINVAL;
333 } else {
334 goto out;
335 }
336 } else {
337 if (adev->discovery.offset) {
338 u32 signature;
339
340 /* If VRAM holds a valid discovery signature at the default
341 * discovery offset, use it as-is.
342 */
343 amdgpu_device_vram_access(adev, adev->discovery.offset,
344 &signature, sizeof(signature),
345 false);
346 if (le32_to_cpu(signature) == BINARY_SIGNATURE)
347 goto out;
348 }
349
350 tmr_size = RREG32(mmDRIVER_SCRATCH_2);
351 if (tmr_size) {
352 /* It's preferred to transition to PSP mailbox reg interface
353 * for both bare-metal and passthrough if available */
354 adev->discovery.size = (u32)tmr_size;
355 tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0);
356 tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1);
357 adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 |
358 le32_to_cpu(tmr_offset_lo));
359 } else if (!vram_size) {
360 /* fall back to apci approach to query tmr offset if vram_size is 0 */
361 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size);
362 if (ret)
363 return ret;
364 adev->discovery.size = DISCOVERY_TMR_SIZE;
365 adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET;
366 }
367 }
368 out:
369 adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL);
370 if (!adev->discovery.bin)
371 return -ENOMEM;
372 adev->discovery.debugfs_blob.data = adev->discovery.bin;
373 adev->discovery.debugfs_blob.size = adev->discovery.size;
374
375 return 0;
376 }
377
amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device * adev,uint8_t * binary)378 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary)
379 {
380 void *discv_regn;
381
382 /* This region is read-only and reserved from system use */
383 discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC);
384 if (discv_regn) {
385 memcpy(binary, discv_regn, adev->discovery.size);
386 memunmap(discv_regn);
387 return 0;
388 }
389
390 return -ENOENT;
391 }
392
393 #define IP_DISCOVERY_V2 2
394 #define IP_DISCOVERY_V4 4
395
amdgpu_discovery_read_binary_from_mem(struct amdgpu_device * adev,uint8_t * binary,bool is_tmr_in_sysmem)396 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
397 uint8_t *binary,
398 bool is_tmr_in_sysmem)
399 {
400 int ret = 0;
401
402 if (!is_tmr_in_sysmem) {
403 if (amdgpu_sriov_vf(adev) &&
404 amdgpu_sriov_xgmi_connected_to_cpu(adev)) {
405 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
406 } else {
407 amdgpu_device_vram_access(adev, adev->discovery.offset,
408 (uint32_t *)binary,
409 adev->discovery.size, false);
410 adev->discovery.reserve_tmr = true;
411 }
412 } else {
413 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
414 }
415
416 return ret;
417 }
418
amdgpu_discovery_read_binary_from_file(struct amdgpu_device * adev,uint8_t * binary,const char * fw_name)419 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev,
420 uint8_t *binary,
421 const char *fw_name)
422 {
423 const struct firmware *fw;
424 int r;
425
426 r = firmware_request_nowarn(&fw, fw_name, adev->dev);
427 if (r) {
428 if (amdgpu_discovery == 2)
429 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name);
430 else
431 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name);
432 return r;
433 }
434
435 if (fw->size > adev->discovery.size) {
436 dev_err(adev->dev,
437 "ip discovery firmware \"%s\" too large (%zu > %u)\n",
438 fw_name, fw->size, adev->discovery.size);
439 release_firmware(fw);
440 return -EINVAL;
441 }
442
443 /* Ensure the firmware is at least large enough to contain the
444 * binary header fields.
445 */
446 if (fw->size < offsetof(struct binary_header, binary_size) +
447 sizeof(((struct binary_header *)0)->binary_size)) {
448 dev_err(adev->dev,
449 "ip discovery firmware \"%s\" too small (%zu)\n",
450 fw_name, fw->size);
451 release_firmware(fw);
452 return -EINVAL;
453 }
454
455 memcpy((u8 *)binary, (u8 *)fw->data, fw->size);
456 release_firmware(fw);
457
458 return 0;
459 }
460
amdgpu_discovery_calculate_checksum(uint8_t * data,uint32_t size)461 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
462 {
463 uint16_t checksum = 0;
464 int i;
465
466 for (i = 0; i < size; i++)
467 checksum += data[i];
468
469 return checksum;
470 }
471
amdgpu_discovery_verify_checksum(struct amdgpu_device * adev,uint8_t * data,uint32_t size,uint16_t expected)472 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev,
473 uint8_t *data, uint32_t size,
474 uint16_t expected)
475 {
476 uint16_t calculated;
477
478 calculated = amdgpu_discovery_calculate_checksum(data, size);
479
480 if (calculated != expected) {
481 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n",
482 calculated, expected, size);
483 return false;
484 }
485
486 return true;
487 }
488
amdgpu_discovery_verify_binary_signature(uint8_t * binary)489 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
490 {
491 struct binary_header *bhdr;
492 bhdr = (struct binary_header *)binary;
493
494 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
495 }
496
amdgpu_discovery_harvest_config_quirk(struct amdgpu_device * adev)497 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
498 {
499 /*
500 * So far, apply this quirk only on those Navy Flounder boards which
501 * have a bad harvest table of VCN config.
502 */
503 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) &&
504 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) {
505 switch (adev->pdev->revision) {
506 case 0xC1:
507 case 0xC2:
508 case 0xC3:
509 case 0xC5:
510 case 0xC7:
511 case 0xCF:
512 case 0xDF:
513 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
514 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1;
515 break;
516 default:
517 break;
518 }
519 }
520 }
521
amdgpu_discovery_verify_npsinfo(struct amdgpu_device * adev,struct table_info * info)522 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev,
523 struct table_info *info)
524 {
525 uint8_t *discovery_bin = adev->discovery.bin;
526 uint16_t checksum;
527 uint16_t offset;
528
529 offset = le16_to_cpu(info->offset);
530 checksum = le16_to_cpu(info->checksum);
531
532 struct nps_info_header *nhdr =
533 (struct nps_info_header *)(discovery_bin + offset);
534
535 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) {
536 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n");
537 return -EINVAL;
538 }
539
540 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset,
541 le32_to_cpu(nhdr->size_bytes),
542 checksum)) {
543 dev_dbg(adev->dev, "invalid nps info data table checksum\n");
544 return -EINVAL;
545 }
546
547 return 0;
548 }
549
amdgpu_discovery_get_fw_name(struct amdgpu_device * adev)550 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev)
551 {
552 if (amdgpu_discovery == 2) {
553 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */
554 adev->discovery.reserve_tmr = true;
555 return "amdgpu/ip_discovery.bin";
556 }
557
558 switch (adev->asic_type) {
559 case CHIP_VEGA10:
560 return "amdgpu/vega10_ip_discovery.bin";
561 case CHIP_VEGA12:
562 return "amdgpu/vega12_ip_discovery.bin";
563 case CHIP_RAVEN:
564 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
565 return "amdgpu/raven2_ip_discovery.bin";
566 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
567 return "amdgpu/picasso_ip_discovery.bin";
568 else
569 return "amdgpu/raven_ip_discovery.bin";
570 case CHIP_VEGA20:
571 return "amdgpu/vega20_ip_discovery.bin";
572 case CHIP_ARCTURUS:
573 return "amdgpu/arcturus_ip_discovery.bin";
574 case CHIP_ALDEBARAN:
575 return "amdgpu/aldebaran_ip_discovery.bin";
576 default:
577 return NULL;
578 }
579 }
580
581 static struct table_info *
amdgpu_discovery_get_table_info_from_bin(uint8_t * discovery_bin,uint16_t table_id)582 amdgpu_discovery_get_table_info_from_bin(uint8_t *discovery_bin,
583 uint16_t table_id)
584 {
585 struct binary_header *bhdr = (struct binary_header *)discovery_bin;
586 struct binary_header_v2 *bhdrv2;
587
588 switch (bhdr->version_major) {
589 case 2:
590 bhdrv2 = (struct binary_header_v2 *)discovery_bin;
591 return &bhdrv2->table_list[table_id];
592 case 1:
593 case 0:
594 return &bhdr->table_list[table_id];
595 default:
596 return NULL;
597 }
598 }
599
amdgpu_discovery_get_table_info(struct amdgpu_device * adev,struct table_info ** info,uint16_t table_id)600 static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev,
601 struct table_info **info,
602 uint16_t table_id)
603 {
604 struct binary_header *bhdr =
605 (struct binary_header *)adev->discovery.bin;
606
607 *info = amdgpu_discovery_get_table_info_from_bin(adev->discovery.bin,
608 table_id);
609 if (!*info) {
610 dev_err(adev->dev, "Invalid ip discovery table version %d\n",
611 bhdr->version_major);
612 return -EINVAL;
613 }
614
615 return 0;
616 }
617
amdgpu_discovery_table_check(struct amdgpu_device * adev,uint8_t * discovery_bin,uint16_t table_id)618 static int amdgpu_discovery_table_check(struct amdgpu_device *adev,
619 uint8_t *discovery_bin,
620 uint16_t table_id)
621 {
622 int r, act_val, exp_val, table_size;
623 uint16_t offset, checksum;
624 struct table_info *info;
625 bool check_table = true;
626 char *table_name;
627
628 r = amdgpu_discovery_get_table_info(adev, &info, table_id);
629 if (r)
630 return r;
631 offset = le16_to_cpu(info->offset);
632 checksum = le16_to_cpu(info->checksum);
633
634 switch (table_id) {
635 case IP_DISCOVERY: {
636 struct ip_discovery_header *ihdr =
637 (struct ip_discovery_header *)(discovery_bin + offset);
638 act_val = le32_to_cpu(ihdr->signature);
639 exp_val = DISCOVERY_TABLE_SIGNATURE;
640 table_size = le16_to_cpu(ihdr->size);
641 table_name = "data table";
642 break;
643 }
644 case GC: {
645 struct gpu_info_header *ghdr =
646 (struct gpu_info_header *)(discovery_bin + offset);
647 act_val = le32_to_cpu(ghdr->table_id);
648 exp_val = GC_TABLE_ID;
649 table_size = le16_to_cpu(ghdr->size);
650 table_name = "gc table";
651 break;
652 }
653 case HARVEST_INFO: {
654 struct harvest_info_header *hhdr =
655 (struct harvest_info_header *)(discovery_bin + offset);
656 act_val = le32_to_cpu(hhdr->signature);
657 exp_val = HARVEST_TABLE_SIGNATURE;
658 table_size = sizeof(struct harvest_table);
659 table_name = "harvest table";
660 break;
661 }
662 case VCN_INFO: {
663 struct vcn_info_header *vhdr =
664 (struct vcn_info_header *)(discovery_bin + offset);
665 act_val = le32_to_cpu(vhdr->table_id);
666 exp_val = VCN_INFO_TABLE_ID;
667 table_size = le32_to_cpu(vhdr->size_bytes);
668 table_name = "vcn table";
669 break;
670 }
671 case MALL_INFO: {
672 struct mall_info_header *mhdr =
673 (struct mall_info_header *)(discovery_bin + offset);
674 act_val = le32_to_cpu(mhdr->table_id);
675 exp_val = MALL_INFO_TABLE_ID;
676 table_size = le32_to_cpu(mhdr->size_bytes);
677 table_name = "mall table";
678 check_table = false;
679 break;
680 }
681 default:
682 dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id);
683 check_table = false;
684 break;
685 }
686
687 if (check_table && offset) {
688 if (act_val != exp_val) {
689 dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name);
690 return -EINVAL;
691 }
692
693 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset,
694 table_size, checksum)) {
695 dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name);
696 return -EINVAL;
697 }
698 }
699
700 return 0;
701 }
702
amdgpu_discovery_init(struct amdgpu_device * adev)703 static int amdgpu_discovery_init(struct amdgpu_device *adev)
704 {
705 struct binary_header *bhdr;
706 uint8_t *discovery_bin;
707 const char *fw_name;
708 uint16_t offset;
709 uint16_t size;
710 uint16_t checksum;
711 uint16_t table_id;
712 bool is_tmr_in_sysmem;
713 int r;
714
715 r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem);
716 if (r)
717 return r;
718
719 discovery_bin = adev->discovery.bin;
720 /* Read from file if it is the preferred option */
721 fw_name = amdgpu_discovery_get_fw_name(adev);
722 if (fw_name != NULL) {
723 drm_dbg(&adev->ddev, "use ip discovery information from file");
724 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin,
725 fw_name);
726 if (r)
727 goto out;
728 } else {
729 drm_dbg(&adev->ddev, "use ip discovery information from memory");
730 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin,
731 is_tmr_in_sysmem);
732 if (r)
733 goto out;
734 }
735
736 /* check the ip discovery binary signature */
737 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) {
738 dev_err(adev->dev,
739 "get invalid ip discovery binary signature\n");
740 r = -EINVAL;
741 goto out;
742 }
743
744 bhdr = (struct binary_header *)discovery_bin;
745
746 offset = offsetof(struct binary_header, binary_checksum) +
747 sizeof(bhdr->binary_checksum);
748 size = le16_to_cpu(bhdr->binary_size) - offset;
749 checksum = le16_to_cpu(bhdr->binary_checksum);
750
751 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size,
752 checksum)) {
753 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
754 r = -EINVAL;
755 goto out;
756 }
757
758 for (table_id = 0; table_id <= MALL_INFO; table_id++) {
759 r = amdgpu_discovery_table_check(adev, discovery_bin, table_id);
760 if (r)
761 goto out;
762 }
763
764 return 0;
765
766 out:
767 kfree(adev->discovery.bin);
768 adev->discovery.bin = NULL;
769 if ((amdgpu_discovery != 2) &&
770 (RREG32(mmIP_DISCOVERY_VERSION) == 4))
771 amdgpu_ras_query_boot_status(adev, 4);
772 return r;
773 }
774
amdgpu_discovery_fini(struct amdgpu_device * adev)775 void amdgpu_discovery_fini(struct amdgpu_device *adev)
776 {
777 if (adev->discovery.ip_top && !adev->discovery.ip_top->standalone_mode)
778 amdgpu_discovery_sysfs_fini(adev);
779
780 kfree(adev->discovery.bin);
781 adev->discovery.bin = NULL;
782 }
783
amdgpu_discovery_validate_ip(struct amdgpu_device * adev,uint8_t instance,uint16_t hw_id)784 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev,
785 uint8_t instance, uint16_t hw_id)
786 {
787 if (instance >= HWIP_MAX_INSTANCE) {
788 if (adev)
789 dev_err(adev->dev,
790 "Unexpected instance_number (%d) from ip discovery blob\n",
791 instance);
792 return -EINVAL;
793 }
794 if (hw_id >= HW_ID_MAX) {
795 if (adev)
796 dev_err(adev->dev,
797 "Unexpected hw_id (%d) from ip discovery blob\n",
798 hw_id);
799 return -EINVAL;
800 }
801
802 return 0;
803 }
804
amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device * adev,uint32_t * vcn_harvest_count)805 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
806 uint32_t *vcn_harvest_count)
807 {
808 uint8_t *discovery_bin = adev->discovery.bin;
809 struct binary_header *bhdr;
810 struct ip_discovery_header *ihdr;
811 struct die_header *dhdr;
812 struct ip *ip;
813 uint16_t die_offset, ip_offset, num_dies, num_ips;
814 uint16_t hw_id;
815 uint8_t inst;
816 int i, j;
817
818 bhdr = (struct binary_header *)discovery_bin;
819 ihdr = (struct ip_discovery_header
820 *)(discovery_bin +
821 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
822 num_dies = le16_to_cpu(ihdr->num_dies);
823
824 /* scan harvest bit of all IP data structures */
825 for (i = 0; i < num_dies; i++) {
826 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
827 dhdr = (struct die_header *)(discovery_bin + die_offset);
828 num_ips = le16_to_cpu(dhdr->num_ips);
829 ip_offset = die_offset + sizeof(*dhdr);
830
831 for (j = 0; j < num_ips; j++) {
832 ip = (struct ip *)(discovery_bin + ip_offset);
833 inst = ip->number_instance;
834 hw_id = le16_to_cpu(ip->hw_id);
835 if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
836 goto next_ip;
837
838 if (ip->harvest == 1) {
839 switch (hw_id) {
840 case VCN_HWID:
841 (*vcn_harvest_count)++;
842 if (inst == 0) {
843 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
844 adev->vcn.inst_mask &=
845 ~AMDGPU_VCN_HARVEST_VCN0;
846 adev->jpeg.inst_mask &=
847 ~AMDGPU_VCN_HARVEST_VCN0;
848 } else {
849 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
850 adev->vcn.inst_mask &=
851 ~AMDGPU_VCN_HARVEST_VCN1;
852 adev->jpeg.inst_mask &=
853 ~AMDGPU_VCN_HARVEST_VCN1;
854 }
855 break;
856 case DMU_HWID:
857 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
858 break;
859 default:
860 break;
861 }
862 }
863 next_ip:
864 ip_offset += struct_size(ip, base_address,
865 ip->num_base_address);
866 }
867 }
868 }
869
amdgpu_discovery_read_from_harvest_table(struct amdgpu_device * adev,uint32_t * vcn_harvest_count,uint32_t * umc_harvest_count)870 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
871 uint32_t *vcn_harvest_count,
872 uint32_t *umc_harvest_count)
873 {
874 uint8_t *discovery_bin = adev->discovery.bin;
875 struct table_info *info;
876 struct harvest_table *harvest_info;
877 u16 offset;
878 int i;
879 u64 umc_harvest_config = 0;
880
881 if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO))
882 return;
883 offset = le16_to_cpu(info->offset);
884
885 if (!offset) {
886 dev_err(adev->dev, "invalid harvest table offset\n");
887 return;
888 }
889
890 harvest_info = (struct harvest_table *)(discovery_bin + offset);
891
892 for (i = 0; i < 32; i++) {
893 u16 hw_id = le16_to_cpu(harvest_info->list[i].hw_id);
894 u8 inst = harvest_info->list[i].number_instance;
895
896 if (hw_id == 0)
897 break;
898
899 if (inst >= 32) {
900 dev_warn(adev->dev,
901 "bogus harvest instance %u for hw_id %u\n",
902 inst, hw_id);
903 continue;
904 }
905
906 switch (hw_id) {
907 case VCN_HWID:
908 (*vcn_harvest_count)++;
909 adev->vcn.harvest_config |= BIT(inst);
910 adev->jpeg.harvest_config |= BIT(inst);
911
912 adev->vcn.inst_mask &= ~BIT(inst);
913 adev->jpeg.inst_mask &= ~BIT(inst);
914 break;
915 case DMU_HWID:
916 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
917 break;
918 case UMC_HWID:
919 umc_harvest_config |= BIT_ULL(inst);
920 (*umc_harvest_count)++;
921 break;
922 case GC_HWID:
923 adev->gfx.xcc_mask &= ~BIT(inst);
924 break;
925 case SDMA0_HWID:
926 adev->sdma.sdma_mask &= ~BIT(inst);
927 break;
928 #if defined(CONFIG_DRM_AMD_ISP)
929 case ISP_HWID:
930 adev->isp.harvest_config |= ~BIT(inst);
931 break;
932 #endif
933 default:
934 break;
935 }
936 }
937
938 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) &
939 ~umc_harvest_config;
940 }
941
942 /* ================================================== */
943
944 struct ip_hw_instance {
945 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
946
947 int hw_id;
948 u8 num_instance;
949 u8 major, minor, revision;
950 u8 harvest;
951
952 int num_base_addresses;
953 u32 base_addr[] __counted_by(num_base_addresses);
954 };
955
956 struct ip_hw_id {
957 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
958 int hw_id;
959 };
960
961 struct ip_die_entry {
962 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */
963 u16 num_ips;
964 };
965
966 /* -------------------------------------------------- */
967
968 struct ip_hw_instance_attr {
969 struct attribute attr;
970 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
971 };
972
hw_id_show(struct ip_hw_instance * ip_hw_instance,char * buf)973 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
974 {
975 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
976 }
977
num_instance_show(struct ip_hw_instance * ip_hw_instance,char * buf)978 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
979 {
980 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
981 }
982
major_show(struct ip_hw_instance * ip_hw_instance,char * buf)983 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
984 {
985 return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
986 }
987
minor_show(struct ip_hw_instance * ip_hw_instance,char * buf)988 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
989 {
990 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
991 }
992
revision_show(struct ip_hw_instance * ip_hw_instance,char * buf)993 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
994 {
995 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
996 }
997
harvest_show(struct ip_hw_instance * ip_hw_instance,char * buf)998 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
999 {
1000 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
1001 }
1002
num_base_addresses_show(struct ip_hw_instance * ip_hw_instance,char * buf)1003 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
1004 {
1005 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
1006 }
1007
base_addr_show(struct ip_hw_instance * ip_hw_instance,char * buf)1008 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
1009 {
1010 ssize_t at;
1011 int ii;
1012
1013 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
1014 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
1015 */
1016 if (at + 12 > PAGE_SIZE)
1017 break;
1018 at += sysfs_emit_at(buf, at, "0x%08X\n",
1019 ip_hw_instance->base_addr[ii]);
1020 }
1021
1022 return at;
1023 }
1024
1025 static struct ip_hw_instance_attr ip_hw_attr[] = {
1026 __ATTR_RO(hw_id),
1027 __ATTR_RO(num_instance),
1028 __ATTR_RO(major),
1029 __ATTR_RO(minor),
1030 __ATTR_RO(revision),
1031 __ATTR_RO(harvest),
1032 __ATTR_RO(num_base_addresses),
1033 __ATTR_RO(base_addr),
1034 };
1035
1036 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
1037 ATTRIBUTE_GROUPS(ip_hw_instance);
1038
1039 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
1040 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
1041
ip_hw_instance_attr_show(struct kobject * kobj,struct attribute * attr,char * buf)1042 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
1043 struct attribute *attr,
1044 char *buf)
1045 {
1046 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
1047 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
1048
1049 if (!ip_hw_attr->show)
1050 return -EIO;
1051
1052 return ip_hw_attr->show(ip_hw_instance, buf);
1053 }
1054
1055 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
1056 .show = ip_hw_instance_attr_show,
1057 };
1058
ip_hw_instance_release(struct kobject * kobj)1059 static void ip_hw_instance_release(struct kobject *kobj)
1060 {
1061 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
1062
1063 kfree(ip_hw_instance);
1064 }
1065
1066 static const struct kobj_type ip_hw_instance_ktype = {
1067 .release = ip_hw_instance_release,
1068 .sysfs_ops = &ip_hw_instance_sysfs_ops,
1069 .default_groups = ip_hw_instance_groups,
1070 };
1071
1072 /* -------------------------------------------------- */
1073
1074 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
1075
ip_hw_id_release(struct kobject * kobj)1076 static void ip_hw_id_release(struct kobject *kobj)
1077 {
1078 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
1079
1080 if (!list_empty(&ip_hw_id->hw_id_kset.list))
1081 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
1082 kfree(ip_hw_id);
1083 }
1084
1085 static const struct kobj_type ip_hw_id_ktype = {
1086 .release = ip_hw_id_release,
1087 .sysfs_ops = &kobj_sysfs_ops,
1088 };
1089
1090 /* -------------------------------------------------- */
1091
1092 static void die_kobj_release(struct kobject *kobj);
1093 static void ip_disc_release(struct kobject *kobj);
1094
1095 struct ip_die_entry_attribute {
1096 struct attribute attr;
1097 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
1098 };
1099
1100 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr)
1101
num_ips_show(struct ip_die_entry * ip_die_entry,char * buf)1102 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
1103 {
1104 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
1105 }
1106
1107 /* If there are more ip_die_entry attrs, other than the number of IPs,
1108 * we can make this intro an array of attrs, and then initialize
1109 * ip_die_entry_attrs in a loop.
1110 */
1111 static struct ip_die_entry_attribute num_ips_attr =
1112 __ATTR_RO(num_ips);
1113
1114 static struct attribute *ip_die_entry_attrs[] = {
1115 &num_ips_attr.attr,
1116 NULL,
1117 };
1118 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
1119
1120 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
1121
ip_die_entry_attr_show(struct kobject * kobj,struct attribute * attr,char * buf)1122 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
1123 struct attribute *attr,
1124 char *buf)
1125 {
1126 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
1127 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
1128
1129 if (!ip_die_entry_attr->show)
1130 return -EIO;
1131
1132 return ip_die_entry_attr->show(ip_die_entry, buf);
1133 }
1134
ip_die_entry_release(struct kobject * kobj)1135 static void ip_die_entry_release(struct kobject *kobj)
1136 {
1137 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
1138
1139 if (!list_empty(&ip_die_entry->ip_kset.list))
1140 DRM_ERROR("ip_die_entry->ip_kset is not empty");
1141 kfree(ip_die_entry);
1142 }
1143
1144 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
1145 .show = ip_die_entry_attr_show,
1146 };
1147
1148 static const struct kobj_type ip_die_entry_ktype = {
1149 .release = ip_die_entry_release,
1150 .sysfs_ops = &ip_die_entry_sysfs_ops,
1151 .default_groups = ip_die_entry_groups,
1152 };
1153
1154 static const struct kobj_type die_kobj_ktype = {
1155 .release = die_kobj_release,
1156 .sysfs_ops = &kobj_sysfs_ops,
1157 };
1158
1159 static const struct kobj_type ip_discovery_ktype = {
1160 .release = ip_disc_release,
1161 .sysfs_ops = &kobj_sysfs_ops,
1162 };
1163
die_kobj_release(struct kobject * kobj)1164 static void die_kobj_release(struct kobject *kobj)
1165 {
1166 struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
1167 struct ip_discovery_top,
1168 die_kset);
1169 if (!list_empty(&ip_top->die_kset.list))
1170 DRM_ERROR("ip_top->die_kset is not empty");
1171 }
1172
ip_disc_release(struct kobject * kobj)1173 static void ip_disc_release(struct kobject *kobj)
1174 {
1175 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
1176 kobj);
1177 struct amdgpu_device *adev = ip_top->adev;
1178
1179 /* In standalone mode, discovery_bin is managed by devm and will be
1180 * freed automatically when the PCI device is removed. Do not manually
1181 * free it here to avoid double-free.
1182 */
1183
1184 kfree(ip_top);
1185 if (adev)
1186 adev->discovery.ip_top = NULL;
1187 }
1188
amdgpu_discovery_get_harvest_info(struct amdgpu_device * adev,uint16_t hw_id,uint8_t inst)1189 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,
1190 uint16_t hw_id, uint8_t inst)
1191 {
1192 uint8_t harvest = 0;
1193
1194 /* In early init mode (adev == NULL), harvest info is not available */
1195 if (!adev)
1196 return 0;
1197
1198 /* Until a uniform way is figured, get mask based on hwid */
1199 switch (hw_id) {
1200 case VCN_HWID:
1201 /* VCN vs UVD+VCE */
1202 if (!amdgpu_ip_version(adev, VCE_HWIP, 0))
1203 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;
1204 break;
1205 case DMU_HWID:
1206 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
1207 harvest = 0x1;
1208 break;
1209 case UMC_HWID:
1210 /* TODO: It needs another parsing; for now, ignore.*/
1211 break;
1212 case GC_HWID:
1213 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;
1214 break;
1215 case SDMA0_HWID:
1216 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0;
1217 break;
1218 default:
1219 break;
1220 }
1221
1222 return harvest;
1223 }
1224
amdgpu_discovery_sysfs_ips(struct amdgpu_device * adev,struct ip_discovery_top * ip_top,struct ip_die_entry * ip_die_entry,const size_t _ip_offset,const int num_ips,bool reg_base_64)1225 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
1226 struct ip_discovery_top *ip_top,
1227 struct ip_die_entry *ip_die_entry,
1228 const size_t _ip_offset, const int num_ips,
1229 bool reg_base_64)
1230 {
1231 uint8_t *discovery_bin = ip_top->standalone_mode ?
1232 ip_top->discovery_bin :
1233 adev->discovery.bin;
1234 int ii, jj, kk, res;
1235 uint16_t hw_id;
1236 uint8_t inst;
1237
1238 DRM_DEBUG("num_ips:%d", num_ips);
1239
1240 /* Find all IPs of a given HW ID, and add their instance to
1241 * #die/#hw_id/#instance/<attributes>
1242 */
1243 for (ii = 0; ii < HW_ID_MAX; ii++) {
1244 struct ip_hw_id *ip_hw_id = NULL;
1245 size_t ip_offset = _ip_offset;
1246
1247 for (jj = 0; jj < num_ips; jj++) {
1248 struct ip_v4 *ip;
1249 struct ip_hw_instance *ip_hw_instance;
1250
1251 ip = (struct ip_v4 *)(discovery_bin + ip_offset);
1252 inst = ip->instance_number;
1253 hw_id = le16_to_cpu(ip->hw_id);
1254 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) ||
1255 hw_id != ii)
1256 goto next_ip;
1257
1258 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
1259
1260 /* We have a hw_id match; register the hw
1261 * block if not yet registered.
1262 */
1263 if (!ip_hw_id) {
1264 ip_hw_id = kzalloc_obj(*ip_hw_id);
1265 if (!ip_hw_id)
1266 return -ENOMEM;
1267 ip_hw_id->hw_id = ii;
1268
1269 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
1270 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
1271 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
1272 res = kset_register(&ip_hw_id->hw_id_kset);
1273 if (res) {
1274 DRM_ERROR("Couldn't register ip_hw_id kset");
1275 kfree(ip_hw_id);
1276 return res;
1277 }
1278 if (hw_id_names[ii]) {
1279 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
1280 &ip_hw_id->hw_id_kset.kobj,
1281 hw_id_names[ii]);
1282 if (res) {
1283 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
1284 hw_id_names[ii],
1285 kobject_name(&ip_die_entry->ip_kset.kobj));
1286 }
1287 }
1288 }
1289
1290 /* Now register its instance.
1291 */
1292 ip_hw_instance = kzalloc_flex(*ip_hw_instance,
1293 base_addr,
1294 ip->num_base_address);
1295 if (!ip_hw_instance) {
1296 DRM_ERROR("no memory for ip_hw_instance");
1297 return -ENOMEM;
1298 }
1299 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
1300 ip_hw_instance->num_instance = ip->instance_number;
1301 ip_hw_instance->major = ip->major;
1302 ip_hw_instance->minor = ip->minor;
1303 ip_hw_instance->revision = ip->revision;
1304 ip_hw_instance->harvest =
1305 amdgpu_discovery_get_harvest_info(
1306 adev, ip_hw_instance->hw_id,
1307 ip_hw_instance->num_instance);
1308 ip_hw_instance->num_base_addresses = ip->num_base_address;
1309
1310 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) {
1311 /*
1312 * Standalone mode uses a raw copy of the discovery
1313 * binary; decode 64-bit addresses here. The shared
1314 * bin is already collapsed to 32-bit in place.
1315 */
1316 if (reg_base_64 && ip_top->standalone_mode)
1317 ip_hw_instance->base_addr[kk] =
1318 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF;
1319 else
1320 ip_hw_instance->base_addr[kk] =
1321 le32_to_cpu(ip->base_address[kk]);
1322 }
1323
1324 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
1325 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
1326 res = kobject_add(&ip_hw_instance->kobj, NULL,
1327 "%d", ip_hw_instance->num_instance);
1328 if (res)
1329 kobject_put(&ip_hw_instance->kobj);
1330 next_ip:
1331 if (reg_base_64)
1332 ip_offset += struct_size(ip, base_address_64,
1333 ip->num_base_address);
1334 else
1335 ip_offset += struct_size(ip, base_address,
1336 ip->num_base_address);
1337 }
1338 }
1339
1340 return 0;
1341 }
1342
amdgpu_discovery_sysfs_recurse(struct amdgpu_device * adev,struct ip_discovery_top * ip_top)1343 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev,
1344 struct ip_discovery_top *ip_top)
1345 {
1346 uint8_t *discovery_bin = ip_top->standalone_mode ?
1347 ip_top->discovery_bin :
1348 adev->discovery.bin;
1349 struct table_info *info;
1350 struct ip_discovery_header *ihdr;
1351 struct die_header *dhdr;
1352 struct kset *die_kset = &ip_top->die_kset;
1353 u16 num_dies, die_offset, num_ips;
1354 size_t ip_offset;
1355 int ii, res;
1356
1357 info = amdgpu_discovery_get_table_info_from_bin(discovery_bin,
1358 IP_DISCOVERY);
1359 if (!info)
1360 return -EINVAL;
1361 ihdr = (struct ip_discovery_header
1362 *)(discovery_bin +
1363 le16_to_cpu(info->offset));
1364 num_dies = le16_to_cpu(ihdr->num_dies);
1365
1366 DRM_DEBUG("number of dies: %d\n", num_dies);
1367
1368 for (ii = 0; ii < num_dies; ii++) {
1369 struct ip_die_entry *ip_die_entry;
1370
1371 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
1372 dhdr = (struct die_header *)(discovery_bin + die_offset);
1373 num_ips = le16_to_cpu(dhdr->num_ips);
1374 ip_offset = die_offset + sizeof(*dhdr);
1375
1376 /* Add the die to the kset.
1377 *
1378 * dhdr->die_id == ii, which was checked in
1379 * amdgpu_discovery_reg_base_init().
1380 */
1381
1382 ip_die_entry = kzalloc_obj(*ip_die_entry);
1383 if (!ip_die_entry)
1384 return -ENOMEM;
1385
1386 ip_die_entry->num_ips = num_ips;
1387
1388 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
1389 ip_die_entry->ip_kset.kobj.kset = die_kset;
1390 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
1391 res = kset_register(&ip_die_entry->ip_kset);
1392 if (res) {
1393 DRM_ERROR("Couldn't register ip_die_entry kset");
1394 kfree(ip_die_entry);
1395 return res;
1396 }
1397
1398 amdgpu_discovery_sysfs_ips(adev, ip_top, ip_die_entry, ip_offset,
1399 num_ips, !!ihdr->base_addr_64_bit);
1400 }
1401
1402 return 0;
1403 }
1404
amdgpu_discovery_sysfs_init(struct amdgpu_device * adev)1405 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
1406 {
1407 uint8_t *discovery_bin = adev->discovery.bin;
1408 struct ip_discovery_top *ip_top;
1409 struct kset *die_kset;
1410 int res, ii;
1411
1412 if (!discovery_bin)
1413 return -EINVAL;
1414
1415 /* If early init already created sysfs in standalone mode, skip normal init */
1416 if (adev->discovery.ip_top && adev->discovery.ip_top->standalone_mode)
1417 return 0;
1418
1419 ip_top = kzalloc_obj(*ip_top);
1420 if (!ip_top)
1421 return -ENOMEM;
1422
1423 ip_top->adev = adev;
1424
1425 /* Check if ip_discovery already exists before creating.
1426 * This shouldn't normally happen but handle it gracefully.
1427 */
1428 if (adev->dev->kobj.sd) {
1429 struct kernfs_node *existing;
1430
1431 existing = kernfs_find_and_get(adev->dev->kobj.sd, "ip_discovery");
1432 if (existing) {
1433 kernfs_put(existing);
1434 kfree(ip_top);
1435 return 0;
1436 }
1437 }
1438
1439 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype,
1440 &adev->dev->kobj, "ip_discovery");
1441 if (res) {
1442 DRM_ERROR("Couldn't init and add ip_discovery/");
1443 goto Err;
1444 }
1445
1446 adev->discovery.ip_top = ip_top;
1447
1448 die_kset = &ip_top->die_kset;
1449 kobject_set_name(&die_kset->kobj, "%s", "die");
1450 die_kset->kobj.parent = &ip_top->kobj;
1451 die_kset->kobj.ktype = &die_kobj_ktype;
1452 res = kset_register(&ip_top->die_kset);
1453 if (res) {
1454 DRM_ERROR("Couldn't register die_kset");
1455 goto Err;
1456 }
1457
1458 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1459 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1460 ip_hw_instance_attrs[ii] = NULL;
1461
1462 res = amdgpu_discovery_sysfs_recurse(adev, ip_top);
1463
1464 return res;
1465 Err:
1466 kobject_put(&ip_top->kobj);
1467 return res;
1468 }
1469
1470 /* -------------------------------------------------- */
1471
1472 #define list_to_kobj(el) container_of(el, struct kobject, entry)
1473
amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id * ip_hw_id)1474 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
1475 {
1476 struct list_head *el, *tmp;
1477 struct kset *hw_id_kset;
1478
1479 hw_id_kset = &ip_hw_id->hw_id_kset;
1480 spin_lock(&hw_id_kset->list_lock);
1481 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
1482 list_del_init(el);
1483 spin_unlock(&hw_id_kset->list_lock);
1484 /* kobject is embedded in ip_hw_instance */
1485 kobject_put(list_to_kobj(el));
1486 spin_lock(&hw_id_kset->list_lock);
1487 }
1488 spin_unlock(&hw_id_kset->list_lock);
1489 kobject_put(&ip_hw_id->hw_id_kset.kobj);
1490 }
1491
amdgpu_discovery_sysfs_die_free(struct ip_die_entry * ip_die_entry)1492 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
1493 {
1494 struct list_head *el, *tmp;
1495 struct kset *ip_kset;
1496
1497 ip_kset = &ip_die_entry->ip_kset;
1498 spin_lock(&ip_kset->list_lock);
1499 list_for_each_prev_safe(el, tmp, &ip_kset->list) {
1500 list_del_init(el);
1501 spin_unlock(&ip_kset->list_lock);
1502 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
1503 spin_lock(&ip_kset->list_lock);
1504 }
1505 spin_unlock(&ip_kset->list_lock);
1506 kobject_put(&ip_die_entry->ip_kset.kobj);
1507 }
1508
amdgpu_discovery_sysfs_fini(struct amdgpu_device * adev)1509 void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
1510 {
1511 struct ip_discovery_top *ip_top = adev->discovery.ip_top;
1512 struct list_head *el, *tmp;
1513 struct kset *die_kset;
1514
1515 if (!ip_top)
1516 return;
1517
1518 /*
1519 * In standalone mode the sysfs hierarchy is tied to the PCI device
1520 * lifetime and is torn down by amdgpu_discovery_sysfs_early_fini().
1521 * Freeing it here would leave a dangling pointer in the early
1522 * discovery list, causing a use-after-free on driver unbind.
1523 */
1524 if (ip_top->standalone_mode)
1525 return;
1526
1527 adev->discovery.ip_top = NULL;
1528 die_kset = &ip_top->die_kset;
1529 spin_lock(&die_kset->list_lock);
1530 list_for_each_prev_safe(el, tmp, &die_kset->list) {
1531 list_del_init(el);
1532 spin_unlock(&die_kset->list_lock);
1533 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1534 spin_lock(&die_kset->list_lock);
1535 }
1536 spin_unlock(&die_kset->list_lock);
1537 kobject_put(&ip_top->die_kset.kobj);
1538 kobject_put(&ip_top->kobj);
1539 }
1540
1541 /* devcoredump support */
amdgpu_discovery_dump(struct amdgpu_device * adev,struct drm_printer * p)1542 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p)
1543 {
1544 struct ip_discovery_top *ip_top = adev->discovery.ip_top;
1545 struct ip_die_entry *ip_die_entry;
1546 struct list_head *el_die, *el_hw_id, *el_hw_inst;
1547 struct ip_hw_id *hw_id;
1548 struct kset *die_kset;
1549 struct ip_hw_instance *ip_inst;
1550 int i = 0, j;
1551
1552 if (!ip_top)
1553 return;
1554
1555 die_kset = &ip_top->die_kset;
1556
1557 drm_printf(p, "\nHW IP Discovery\n");
1558
1559 spin_lock(&die_kset->list_lock);
1560 list_for_each(el_die, &die_kset->list) {
1561 drm_printf(p, "die %d\n", i++);
1562 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die));
1563
1564 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) {
1565 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id));
1566 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]);
1567
1568 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) {
1569 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst));
1570 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance);
1571 drm_printf(p, "\tmajor %d\n", ip_inst->major);
1572 drm_printf(p, "\tminor %d\n", ip_inst->minor);
1573 drm_printf(p, "\trevision %d\n", ip_inst->revision);
1574 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest);
1575 drm_printf(p, "\tnum_base_addresses %d\n",
1576 ip_inst->num_base_addresses);
1577 for (j = 0; j < ip_inst->num_base_addresses; j++)
1578 drm_printf(p, "\tbase_addr[%d] 0x%08X\n",
1579 j, ip_inst->base_addr[j]);
1580 }
1581 }
1582 }
1583 spin_unlock(&die_kset->list_lock);
1584 }
1585
amdgpu_discovery_sysfs_early_init(struct amdgpu_device * adev,struct pci_dev * pdev)1586 int amdgpu_discovery_sysfs_early_init(struct amdgpu_device *adev, struct pci_dev *pdev)
1587 {
1588 struct ip_discovery_top *ip_top;
1589 struct early_ip_discovery *early_entry, *tmp;
1590 struct kset *die_kset;
1591 uint8_t *discovery_bin;
1592 int res, ii;
1593
1594 if (!adev || !adev->discovery.bin)
1595 return -EINVAL;
1596
1597 if (adev->discovery.ip_top)
1598 return 0;
1599
1600 mutex_lock(&early_ip_discovery_mutex);
1601 list_for_each_entry_safe(early_entry, tmp, &early_ip_discovery_list, list) {
1602 if (early_entry->pdev == pdev) {
1603 adev->discovery.ip_top = early_entry->ip_top;
1604 early_entry->ip_top->adev = adev;
1605 mutex_unlock(&early_ip_discovery_mutex);
1606 return 0;
1607 }
1608 }
1609 mutex_unlock(&early_ip_discovery_mutex);
1610
1611 discovery_bin = adev->discovery.bin;
1612
1613 early_entry = kzalloc_obj(*early_entry);
1614 if (!early_entry)
1615 return -ENOMEM;
1616
1617 ip_top = kzalloc_obj(*ip_top);
1618 if (!ip_top) {
1619 kfree(early_entry);
1620 return -ENOMEM;
1621 }
1622
1623 ip_top->discovery_bin = devm_kmemdup(&pdev->dev, discovery_bin,
1624 DISCOVERY_TMR_SIZE, GFP_KERNEL);
1625 if (!ip_top->discovery_bin) {
1626 kfree(ip_top);
1627 kfree(early_entry);
1628 return -ENOMEM;
1629 }
1630
1631 ip_top->bin_size = DISCOVERY_TMR_SIZE;
1632 ip_top->pdev = pdev;
1633 ip_top->adev = adev;
1634 ip_top->standalone_mode = true;
1635
1636 /* Check if ip_discovery already exists (from previous probe attempt).
1637 * This can happen if the module was unloaded and reloaded but the
1638 * sysfs persisted (tied to PCI device lifetime).
1639 */
1640 if (pdev->dev.kobj.sd) {
1641 struct kernfs_node *existing;
1642
1643 existing = kernfs_find_and_get(pdev->dev.kobj.sd, "ip_discovery");
1644 if (existing) {
1645 kernfs_put(existing);
1646 kfree(ip_top);
1647 kfree(early_entry);
1648 return 0;
1649 }
1650 }
1651
1652 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype,
1653 &pdev->dev.kobj, "ip_discovery");
1654 if (res)
1655 goto err_put_kobj;
1656
1657 adev->discovery.ip_top = ip_top;
1658
1659 die_kset = &ip_top->die_kset;
1660 kobject_set_name(&die_kset->kobj, "%s", "die");
1661 die_kset->kobj.parent = &ip_top->kobj;
1662 die_kset->kobj.ktype = &die_kobj_ktype;
1663 res = kset_register(&ip_top->die_kset);
1664 if (res)
1665 goto err_put_die_kset;
1666
1667 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1668 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1669 ip_hw_instance_attrs[ii] = NULL;
1670
1671 res = amdgpu_discovery_sysfs_recurse(NULL, ip_top);
1672 if (res)
1673 goto err_put_die_kset;
1674
1675 early_entry->pdev = pdev;
1676 early_entry->ip_top = ip_top;
1677 mutex_lock(&early_ip_discovery_mutex);
1678 list_add(&early_entry->list, &early_ip_discovery_list);
1679 mutex_unlock(&early_ip_discovery_mutex);
1680
1681 return 0;
1682
1683 err_put_die_kset:
1684 kobject_put(&ip_top->die_kset.kobj);
1685 err_put_kobj:
1686 kobject_put(&ip_top->kobj);
1687 kfree(early_entry);
1688 adev->discovery.ip_top = NULL;
1689 return res;
1690 }
1691
amdgpu_discovery_sysfs_early_fini(struct pci_dev * pdev)1692 void amdgpu_discovery_sysfs_early_fini(struct pci_dev *pdev)
1693 {
1694 struct early_ip_discovery *entry, *tmp_entry;
1695 struct ip_discovery_top *ip_top = NULL;
1696 struct list_head *el, *tmp;
1697 struct kset *die_kset;
1698
1699 /* Find the entry in our tracking list */
1700 mutex_lock(&early_ip_discovery_mutex);
1701 list_for_each_entry_safe(entry, tmp_entry, &early_ip_discovery_list, list) {
1702 if (entry->pdev == pdev) {
1703 ip_top = entry->ip_top;
1704 list_del(&entry->list);
1705 kfree(entry);
1706 break;
1707 }
1708 }
1709 mutex_unlock(&early_ip_discovery_mutex);
1710
1711 if (!ip_top)
1712 return;
1713
1714 /* Clean up sysfs hierarchy */
1715 die_kset = &ip_top->die_kset;
1716
1717 spin_lock(&die_kset->list_lock);
1718 list_for_each_prev_safe(el, tmp, &die_kset->list) {
1719 list_del_init(el);
1720 spin_unlock(&die_kset->list_lock);
1721 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1722 spin_lock(&die_kset->list_lock);
1723 }
1724 spin_unlock(&die_kset->list_lock);
1725
1726 kobject_put(&ip_top->die_kset.kobj);
1727 kobject_put(&ip_top->kobj);
1728 /* ip_top itself will be freed by kobject_put via ip_disc_release */
1729 }
1730
1731 /* ================================================== */
1732
amdgpu_discovery_reg_base_init(struct amdgpu_device * adev)1733 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
1734 {
1735 uint8_t num_base_address, subrev, variant;
1736 struct table_info *info;
1737 struct ip_discovery_header *ihdr;
1738 struct die_header *dhdr;
1739 uint8_t *discovery_bin;
1740 struct ip_v4 *ip;
1741 uint16_t die_offset;
1742 uint16_t ip_offset;
1743 uint16_t num_dies;
1744 uint32_t wafl_ver;
1745 uint16_t num_ips;
1746 uint16_t hw_id;
1747 uint8_t inst;
1748 int hw_ip;
1749 int i, j, k;
1750 int r;
1751
1752 r = amdgpu_discovery_init(adev);
1753 if (r)
1754 return r;
1755
1756 amdgpu_discovery_sysfs_early_init(adev, adev->pdev);
1757
1758 discovery_bin = adev->discovery.bin;
1759 wafl_ver = 0;
1760 adev->gfx.xcc_mask = 0;
1761 adev->sdma.sdma_mask = 0;
1762 adev->vcn.inst_mask = 0;
1763 adev->jpeg.inst_mask = 0;
1764 r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY);
1765 if (r)
1766 return r;
1767 ihdr = (struct ip_discovery_header
1768 *)(discovery_bin +
1769 le16_to_cpu(info->offset));
1770 num_dies = le16_to_cpu(ihdr->num_dies);
1771
1772 DRM_DEBUG("number of dies: %d\n", num_dies);
1773
1774 for (i = 0; i < num_dies; i++) {
1775 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1776 dhdr = (struct die_header *)(discovery_bin + die_offset);
1777 num_ips = le16_to_cpu(dhdr->num_ips);
1778 ip_offset = die_offset + sizeof(*dhdr);
1779
1780 if (le16_to_cpu(dhdr->die_id) != i) {
1781 DRM_ERROR("invalid die id %d, expected %d\n",
1782 le16_to_cpu(dhdr->die_id), i);
1783 return -EINVAL;
1784 }
1785
1786 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1787 le16_to_cpu(dhdr->die_id), num_ips);
1788
1789 for (j = 0; j < num_ips; j++) {
1790 ip = (struct ip_v4 *)(discovery_bin + ip_offset);
1791
1792 inst = ip->instance_number;
1793 hw_id = le16_to_cpu(ip->hw_id);
1794 if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
1795 goto next_ip;
1796
1797 num_base_address = ip->num_base_address;
1798
1799 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1800 hw_id_names[le16_to_cpu(ip->hw_id)],
1801 le16_to_cpu(ip->hw_id),
1802 ip->instance_number,
1803 ip->major, ip->minor,
1804 ip->revision);
1805
1806 if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1807 /* Bit [5:0]: original revision value
1808 * Bit [7:6]: en/decode capability:
1809 * 0b00 : VCN function normally
1810 * 0b10 : encode is disabled
1811 * 0b01 : decode is disabled
1812 */
1813 if (adev->vcn.num_vcn_inst <
1814 AMDGPU_MAX_VCN_INSTANCES) {
1815 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =
1816 ip->revision & 0xc0;
1817 adev->vcn.num_vcn_inst++;
1818 adev->vcn.inst_mask |=
1819 (1U << ip->instance_number);
1820 adev->jpeg.inst_mask |=
1821 (1U << ip->instance_number);
1822 } else {
1823 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n",
1824 adev->vcn.num_vcn_inst + 1,
1825 AMDGPU_MAX_VCN_INSTANCES);
1826 }
1827 ip->revision &= ~0xc0;
1828 }
1829 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1830 le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1831 le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1832 le16_to_cpu(ip->hw_id) == SDMA3_HWID) {
1833 if (adev->sdma.num_instances <
1834 AMDGPU_MAX_SDMA_INSTANCES) {
1835 adev->sdma.num_instances++;
1836 adev->sdma.sdma_mask |=
1837 (1U << ip->instance_number);
1838 } else {
1839 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n",
1840 adev->sdma.num_instances + 1,
1841 AMDGPU_MAX_SDMA_INSTANCES);
1842 }
1843 }
1844
1845 if (le16_to_cpu(ip->hw_id) == VPE_HWID) {
1846 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES)
1847 adev->vpe.num_instances++;
1848 else
1849 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n",
1850 adev->vpe.num_instances + 1,
1851 AMDGPU_MAX_VPE_INSTANCES);
1852 }
1853
1854 if (le16_to_cpu(ip->hw_id) == UMC_HWID) {
1855 adev->gmc.num_umc++;
1856 adev->umc.node_inst_num++;
1857 }
1858
1859 if (le16_to_cpu(ip->hw_id) == GC_HWID)
1860 adev->gfx.xcc_mask |=
1861 (1U << ip->instance_number);
1862
1863 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID)
1864 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor,
1865 ip->revision, 0, 0);
1866
1867 for (k = 0; k < num_base_address; k++) {
1868 /*
1869 * convert the endianness of base addresses in place,
1870 * so that we don't need to convert them when accessing adev->reg_offset.
1871 */
1872 if (ihdr->base_addr_64_bit)
1873 /* Truncate the 64bit base address from ip discovery
1874 * and only store lower 32bit ip base in reg_offset[].
1875 * Bits > 32 follows ASIC specific format, thus just
1876 * discard them and handle it within specific ASIC.
1877 * By this way reg_offset[] and related helpers can
1878 * stay unchanged.
1879 * The base address is in dwords, thus clear the
1880 * highest 2 bits to store.
1881 */
1882 ip->base_address[k] =
1883 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
1884 else
1885 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1886 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1887 }
1888
1889 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1890 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) &&
1891 hw_id_map[hw_ip] != 0) {
1892 DRM_DEBUG("set register base offset for %s\n",
1893 hw_id_names[le16_to_cpu(ip->hw_id)]);
1894 adev->reg_offset[hw_ip][ip->instance_number] =
1895 ip->base_address;
1896 /* Instance support is somewhat inconsistent.
1897 * SDMA is a good example. Sienna cichlid has 4 total
1898 * SDMA instances, each enumerated separately (HWIDs
1899 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances,
1900 * but they are enumerated as multiple instances of the
1901 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another
1902 * example. On most chips there are multiple instances
1903 * with the same HWID.
1904 */
1905
1906 if (ihdr->version < 3) {
1907 subrev = 0;
1908 variant = 0;
1909 } else {
1910 subrev = ip->sub_revision;
1911 variant = ip->variant;
1912 }
1913
1914 adev->ip_versions[hw_ip]
1915 [ip->instance_number] =
1916 IP_VERSION_FULL(ip->major,
1917 ip->minor,
1918 ip->revision,
1919 variant,
1920 subrev);
1921 }
1922 }
1923
1924 next_ip:
1925 if (ihdr->base_addr_64_bit)
1926 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
1927 else
1928 ip_offset += struct_size(ip, base_address, ip->num_base_address);
1929 }
1930 }
1931
1932 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0])
1933 adev->ip_versions[XGMI_HWIP][0] = wafl_ver;
1934
1935 return 0;
1936 }
1937
amdgpu_discovery_harvest_ip(struct amdgpu_device * adev)1938 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1939 {
1940 uint8_t *discovery_bin = adev->discovery.bin;
1941 struct ip_discovery_header *ihdr;
1942 struct table_info *info;
1943 int vcn_harvest_count = 0;
1944 int umc_harvest_count = 0;
1945 uint16_t ihdr_ver;
1946
1947 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY))
1948 return;
1949 ihdr = (struct ip_discovery_header *)(discovery_bin +
1950 le16_to_cpu(info->offset));
1951 ihdr_ver = le16_to_cpu(ihdr->version);
1952 /*
1953 * Harvest table does not fit Navi1x and legacy GPUs,
1954 * so read harvest bit per IP data structure to set
1955 * harvest configuration.
1956 */
1957 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) &&
1958 ihdr_ver <= 2) {
1959 if ((adev->pdev->device == 0x731E &&
1960 (adev->pdev->revision == 0xC6 ||
1961 adev->pdev->revision == 0xC7)) ||
1962 (adev->pdev->device == 0x7340 &&
1963 adev->pdev->revision == 0xC9) ||
1964 (adev->pdev->device == 0x7360 &&
1965 adev->pdev->revision == 0xC7))
1966 amdgpu_discovery_read_harvest_bit_per_ip(adev,
1967 &vcn_harvest_count);
1968 } else {
1969 amdgpu_discovery_read_from_harvest_table(adev,
1970 &vcn_harvest_count,
1971 &umc_harvest_count);
1972 }
1973
1974 amdgpu_discovery_harvest_config_quirk(adev);
1975
1976 if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1977 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1978 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1979 }
1980
1981 if (umc_harvest_count < adev->gmc.num_umc) {
1982 adev->gmc.num_umc -= umc_harvest_count;
1983 }
1984 }
1985
1986 union gc_info {
1987 struct gc_info_v1_0 v1;
1988 struct gc_info_v1_1 v1_1;
1989 struct gc_info_v1_2 v1_2;
1990 struct gc_info_v1_3 v1_3;
1991 struct gc_info_v2_0 v2;
1992 struct gc_info_v2_1 v2_1;
1993 };
1994
amdgpu_discovery_get_gfx_info(struct amdgpu_device * adev)1995 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1996 {
1997 uint8_t *discovery_bin = adev->discovery.bin;
1998 struct table_info *info;
1999 union gc_info *gc_info;
2000 u16 offset;
2001
2002 if (!discovery_bin) {
2003 DRM_ERROR("ip discovery uninitialized\n");
2004 return -EINVAL;
2005 }
2006
2007 if (amdgpu_discovery_get_table_info(adev, &info, GC))
2008 return -EINVAL;
2009 offset = le16_to_cpu(info->offset);
2010
2011 if (!offset)
2012 return 0;
2013
2014 gc_info = (union gc_info *)(discovery_bin + offset);
2015
2016 switch (le16_to_cpu(gc_info->v1.header.version_major)) {
2017 case 1:
2018 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
2019 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
2020 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
2021 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
2022 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
2023 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
2024 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
2025 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
2026 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
2027 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
2028 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
2029 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
2030 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
2031 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
2032 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
2033 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
2034 le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
2035 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
2036 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) {
2037 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
2038 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
2039 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
2040 }
2041 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) {
2042 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
2043 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
2044 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
2045 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
2046 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
2047 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
2048 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
2049 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
2050 }
2051 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) {
2052 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu);
2053 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size);
2054 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc);
2055 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size);
2056 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc);
2057 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size);
2058 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size);
2059 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size);
2060 }
2061 break;
2062 case 2:
2063 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
2064 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
2065 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
2066 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
2067 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
2068 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
2069 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
2070 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
2071 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
2072 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
2073 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
2074 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
2075 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
2076 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
2077 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
2078 le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
2079 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
2080 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) {
2081 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh);
2082 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu);
2083 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */
2084 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc);
2085 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc);
2086 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc);
2087 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */
2088 }
2089 break;
2090 default:
2091 dev_err(adev->dev,
2092 "Unhandled GC info table %d.%d\n",
2093 le16_to_cpu(gc_info->v1.header.version_major),
2094 le16_to_cpu(gc_info->v1.header.version_minor));
2095 return -EINVAL;
2096 }
2097 return 0;
2098 }
2099
2100 union mall_info {
2101 struct mall_info_v1_0 v1;
2102 struct mall_info_v2_0 v2;
2103 };
2104
amdgpu_discovery_get_mall_info(struct amdgpu_device * adev)2105 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
2106 {
2107 uint8_t *discovery_bin = adev->discovery.bin;
2108 struct table_info *info;
2109 union mall_info *mall_info;
2110 u32 u, mall_size_per_umc, m_s_present, half_use;
2111 u64 mall_size;
2112 u16 offset;
2113
2114 if (!discovery_bin) {
2115 DRM_ERROR("ip discovery uninitialized\n");
2116 return -EINVAL;
2117 }
2118
2119 if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO))
2120 return -EINVAL;
2121 offset = le16_to_cpu(info->offset);
2122
2123 if (!offset)
2124 return 0;
2125
2126 mall_info = (union mall_info *)(discovery_bin + offset);
2127
2128 switch (le16_to_cpu(mall_info->v1.header.version_major)) {
2129 case 1:
2130 mall_size = 0;
2131 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
2132 m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
2133 half_use = le32_to_cpu(mall_info->v1.m_half_use);
2134 for (u = 0; u < adev->gmc.num_umc; u++) {
2135 if (m_s_present & (1 << u))
2136 mall_size += mall_size_per_umc * 2;
2137 else if (half_use & (1 << u))
2138 mall_size += mall_size_per_umc / 2;
2139 else
2140 mall_size += mall_size_per_umc;
2141 }
2142 adev->gmc.mall_size = mall_size;
2143 adev->gmc.m_half_use = half_use;
2144 break;
2145 case 2:
2146 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc);
2147 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc;
2148 break;
2149 default:
2150 dev_err(adev->dev,
2151 "Unhandled MALL info table %d.%d\n",
2152 le16_to_cpu(mall_info->v1.header.version_major),
2153 le16_to_cpu(mall_info->v1.header.version_minor));
2154 return -EINVAL;
2155 }
2156 return 0;
2157 }
2158
2159 union vcn_info {
2160 struct vcn_info_v1_0 v1;
2161 };
2162
amdgpu_discovery_get_vcn_info(struct amdgpu_device * adev)2163 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
2164 {
2165 uint8_t *discovery_bin = adev->discovery.bin;
2166 struct table_info *info;
2167 union vcn_info *vcn_info;
2168 u16 offset;
2169 int v;
2170
2171 if (!discovery_bin) {
2172 DRM_ERROR("ip discovery uninitialized\n");
2173 return -EINVAL;
2174 }
2175
2176 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
2177 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES
2178 * but that may change in the future with new GPUs so keep this
2179 * check for defensive purposes.
2180 */
2181 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
2182 dev_err(adev->dev, "invalid vcn instances\n");
2183 return -EINVAL;
2184 }
2185
2186 if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO))
2187 return -EINVAL;
2188 offset = le16_to_cpu(info->offset);
2189
2190 if (!offset)
2191 return 0;
2192
2193 vcn_info = (union vcn_info *)(discovery_bin + offset);
2194
2195 switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
2196 case 1:
2197 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
2198 * so this won't overflow.
2199 */
2200 for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
2201 adev->vcn.inst[v].vcn_codec_disable_mask =
2202 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
2203 }
2204 break;
2205 default:
2206 dev_err(adev->dev,
2207 "Unhandled VCN info table %d.%d\n",
2208 le16_to_cpu(vcn_info->v1.header.version_major),
2209 le16_to_cpu(vcn_info->v1.header.version_minor));
2210 return -EINVAL;
2211 }
2212 return 0;
2213 }
2214
2215 union nps_info {
2216 struct nps_info_v1_0 v1;
2217 };
2218
amdgpu_discovery_refresh_nps_info(struct amdgpu_device * adev,union nps_info * nps_data)2219 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev,
2220 union nps_info *nps_data)
2221 {
2222 uint64_t vram_size, pos, offset;
2223 struct nps_info_header *nhdr;
2224 struct binary_header bhdr;
2225 struct binary_header_v2 bhdrv2;
2226 uint16_t checksum;
2227
2228 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
2229 pos = vram_size - DISCOVERY_TMR_OFFSET;
2230 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false);
2231
2232 switch (bhdr.version_major) {
2233 case 2:
2234 amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false);
2235 offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset);
2236 checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum);
2237 break;
2238 case 1:
2239 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset);
2240 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum);
2241 break;
2242 default:
2243 return -EINVAL;
2244 }
2245
2246 amdgpu_device_vram_access(adev, (pos + offset), nps_data,
2247 sizeof(*nps_data), false);
2248
2249 nhdr = (struct nps_info_header *)(nps_data);
2250 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data,
2251 le32_to_cpu(nhdr->size_bytes),
2252 checksum)) {
2253 dev_err(adev->dev, "nps data refresh, checksum mismatch\n");
2254 return -EINVAL;
2255 }
2256
2257 return 0;
2258 }
2259
amdgpu_discovery_get_nps_info(struct amdgpu_device * adev,uint32_t * nps_type,struct amdgpu_gmc_memrange * ranges,int * range_cnt,bool refresh)2260 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev,
2261 uint32_t *nps_type,
2262 struct amdgpu_gmc_memrange *ranges,
2263 int *range_cnt, bool refresh)
2264 {
2265 uint8_t *discovery_bin = adev->discovery.bin;
2266 struct table_info *info;
2267 union nps_info *nps_info;
2268 union nps_info nps_data;
2269 u16 offset;
2270 int i, r;
2271
2272 if (!nps_type || !range_cnt || !ranges)
2273 return -EINVAL;
2274
2275 if (refresh) {
2276 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data);
2277 if (r)
2278 return r;
2279 nps_info = &nps_data;
2280 } else {
2281 if (!discovery_bin) {
2282 dev_err(adev->dev,
2283 "fetch mem range failed, ip discovery uninitialized\n");
2284 return -EINVAL;
2285 }
2286
2287 if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO))
2288 return -EINVAL;
2289 offset = le16_to_cpu(info->offset);
2290
2291 if (!offset)
2292 return -ENOENT;
2293
2294 /* If verification fails, return as if NPS table doesn't exist */
2295 if (amdgpu_discovery_verify_npsinfo(adev, info))
2296 return -ENOENT;
2297
2298 nps_info = (union nps_info *)(discovery_bin + offset);
2299 }
2300
2301 switch (le16_to_cpu(nps_info->v1.header.version_major)) {
2302 case 1:
2303 *nps_type = nps_info->v1.nps_type;
2304 if (*range_cnt < nps_info->v1.count) {
2305 dev_dbg(adev->dev,
2306 "not enough space for nps ranges: %d < %d\n",
2307 *range_cnt, nps_info->v1.count);
2308 return -ENOSPC;
2309 }
2310 *range_cnt = nps_info->v1.count;
2311 for (i = 0; i < *range_cnt; i++) {
2312 ranges[i].base_address =
2313 nps_info->v1.instance_info[i].base_address;
2314 ranges[i].limit_address =
2315 nps_info->v1.instance_info[i].limit_address;
2316 ranges[i].nid_mask = -1;
2317 ranges[i].flags = 0;
2318 }
2319 break;
2320 default:
2321 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n",
2322 le16_to_cpu(nps_info->v1.header.version_major),
2323 le16_to_cpu(nps_info->v1.header.version_minor));
2324 return -EINVAL;
2325 }
2326
2327 return 0;
2328 }
2329
amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device * adev)2330 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
2331 {
2332 /* what IP to use for this? */
2333 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2334 case IP_VERSION(9, 0, 1):
2335 case IP_VERSION(9, 1, 0):
2336 case IP_VERSION(9, 2, 1):
2337 case IP_VERSION(9, 2, 2):
2338 case IP_VERSION(9, 3, 0):
2339 case IP_VERSION(9, 4, 0):
2340 case IP_VERSION(9, 4, 1):
2341 case IP_VERSION(9, 4, 2):
2342 case IP_VERSION(9, 4, 3):
2343 case IP_VERSION(9, 4, 4):
2344 case IP_VERSION(9, 5, 0):
2345 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
2346 break;
2347 case IP_VERSION(10, 1, 10):
2348 case IP_VERSION(10, 1, 1):
2349 case IP_VERSION(10, 1, 2):
2350 case IP_VERSION(10, 1, 3):
2351 case IP_VERSION(10, 1, 4):
2352 case IP_VERSION(10, 3, 0):
2353 case IP_VERSION(10, 3, 1):
2354 case IP_VERSION(10, 3, 2):
2355 case IP_VERSION(10, 3, 3):
2356 case IP_VERSION(10, 3, 4):
2357 case IP_VERSION(10, 3, 5):
2358 case IP_VERSION(10, 3, 6):
2359 case IP_VERSION(10, 3, 7):
2360 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
2361 break;
2362 case IP_VERSION(11, 0, 0):
2363 case IP_VERSION(11, 0, 1):
2364 case IP_VERSION(11, 0, 2):
2365 case IP_VERSION(11, 0, 3):
2366 case IP_VERSION(11, 0, 4):
2367 case IP_VERSION(11, 5, 0):
2368 case IP_VERSION(11, 5, 1):
2369 case IP_VERSION(11, 5, 2):
2370 case IP_VERSION(11, 5, 3):
2371 case IP_VERSION(11, 5, 4):
2372 case IP_VERSION(11, 5, 6):
2373 case IP_VERSION(11, 7, 0):
2374 case IP_VERSION(11, 7, 1):
2375 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
2376 break;
2377 case IP_VERSION(12, 0, 0):
2378 case IP_VERSION(12, 0, 1):
2379 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block);
2380 break;
2381 case IP_VERSION(12, 1, 0):
2382 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block);
2383 break;
2384 default:
2385 dev_err(adev->dev,
2386 "Failed to add common ip block(GC_HWIP:0x%x)\n",
2387 amdgpu_ip_version(adev, GC_HWIP, 0));
2388 return -EINVAL;
2389 }
2390 return 0;
2391 }
2392
amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device * adev)2393 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
2394 {
2395 /* use GC or MMHUB IP version */
2396 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2397 case IP_VERSION(9, 0, 1):
2398 case IP_VERSION(9, 1, 0):
2399 case IP_VERSION(9, 2, 1):
2400 case IP_VERSION(9, 2, 2):
2401 case IP_VERSION(9, 3, 0):
2402 case IP_VERSION(9, 4, 0):
2403 case IP_VERSION(9, 4, 1):
2404 case IP_VERSION(9, 4, 2):
2405 case IP_VERSION(9, 4, 3):
2406 case IP_VERSION(9, 4, 4):
2407 case IP_VERSION(9, 5, 0):
2408 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2409 break;
2410 case IP_VERSION(10, 1, 10):
2411 case IP_VERSION(10, 1, 1):
2412 case IP_VERSION(10, 1, 2):
2413 case IP_VERSION(10, 1, 3):
2414 case IP_VERSION(10, 1, 4):
2415 case IP_VERSION(10, 3, 0):
2416 case IP_VERSION(10, 3, 1):
2417 case IP_VERSION(10, 3, 2):
2418 case IP_VERSION(10, 3, 3):
2419 case IP_VERSION(10, 3, 4):
2420 case IP_VERSION(10, 3, 5):
2421 case IP_VERSION(10, 3, 6):
2422 case IP_VERSION(10, 3, 7):
2423 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
2424 break;
2425 case IP_VERSION(11, 0, 0):
2426 case IP_VERSION(11, 0, 1):
2427 case IP_VERSION(11, 0, 2):
2428 case IP_VERSION(11, 0, 3):
2429 case IP_VERSION(11, 0, 4):
2430 case IP_VERSION(11, 5, 0):
2431 case IP_VERSION(11, 5, 1):
2432 case IP_VERSION(11, 5, 2):
2433 case IP_VERSION(11, 5, 3):
2434 case IP_VERSION(11, 5, 4):
2435 case IP_VERSION(11, 5, 6):
2436 case IP_VERSION(11, 7, 0):
2437 case IP_VERSION(11, 7, 1):
2438 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
2439 break;
2440 case IP_VERSION(12, 0, 0):
2441 case IP_VERSION(12, 0, 1):
2442 case IP_VERSION(12, 1, 0):
2443 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block);
2444 break;
2445 default:
2446 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
2447 amdgpu_ip_version(adev, GC_HWIP, 0));
2448 return -EINVAL;
2449 }
2450 return 0;
2451 }
2452
amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device * adev)2453 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
2454 {
2455 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) {
2456 case IP_VERSION(4, 0, 0):
2457 case IP_VERSION(4, 0, 1):
2458 case IP_VERSION(4, 1, 0):
2459 case IP_VERSION(4, 1, 1):
2460 case IP_VERSION(4, 3, 0):
2461 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
2462 break;
2463 case IP_VERSION(4, 2, 0):
2464 case IP_VERSION(4, 2, 1):
2465 case IP_VERSION(4, 4, 0):
2466 case IP_VERSION(4, 4, 2):
2467 case IP_VERSION(4, 4, 5):
2468 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
2469 break;
2470 case IP_VERSION(5, 0, 0):
2471 case IP_VERSION(5, 0, 1):
2472 case IP_VERSION(5, 0, 2):
2473 case IP_VERSION(5, 0, 3):
2474 case IP_VERSION(5, 2, 0):
2475 case IP_VERSION(5, 2, 1):
2476 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
2477 break;
2478 case IP_VERSION(6, 0, 0):
2479 case IP_VERSION(6, 0, 1):
2480 case IP_VERSION(6, 0, 2):
2481 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block);
2482 break;
2483 case IP_VERSION(6, 1, 0):
2484 case IP_VERSION(6, 1, 1):
2485 case IP_VERSION(6, 4, 0):
2486 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block);
2487 break;
2488 case IP_VERSION(7, 0, 0):
2489 case IP_VERSION(7, 1, 0):
2490 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block);
2491 break;
2492 default:
2493 dev_err(adev->dev,
2494 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
2495 amdgpu_ip_version(adev, OSSSYS_HWIP, 0));
2496 return -EINVAL;
2497 }
2498 return 0;
2499 }
2500
amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device * adev)2501 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
2502 {
2503 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2504 case IP_VERSION(9, 0, 0):
2505 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
2506 break;
2507 case IP_VERSION(10, 0, 0):
2508 case IP_VERSION(10, 0, 1):
2509 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
2510 break;
2511 case IP_VERSION(11, 0, 0):
2512 case IP_VERSION(11, 0, 2):
2513 case IP_VERSION(11, 0, 4):
2514 case IP_VERSION(11, 0, 5):
2515 case IP_VERSION(11, 0, 9):
2516 case IP_VERSION(11, 0, 7):
2517 case IP_VERSION(11, 0, 11):
2518 case IP_VERSION(11, 0, 12):
2519 case IP_VERSION(11, 0, 13):
2520 case IP_VERSION(11, 5, 0):
2521 case IP_VERSION(11, 5, 2):
2522 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
2523 break;
2524 case IP_VERSION(11, 0, 8):
2525 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
2526 break;
2527 case IP_VERSION(11, 0, 3):
2528 case IP_VERSION(12, 0, 1):
2529 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
2530 break;
2531 case IP_VERSION(13, 0, 0):
2532 case IP_VERSION(13, 0, 1):
2533 case IP_VERSION(13, 0, 2):
2534 case IP_VERSION(13, 0, 3):
2535 case IP_VERSION(13, 0, 5):
2536 case IP_VERSION(13, 0, 6):
2537 case IP_VERSION(13, 0, 7):
2538 case IP_VERSION(13, 0, 8):
2539 case IP_VERSION(13, 0, 10):
2540 case IP_VERSION(13, 0, 11):
2541 case IP_VERSION(13, 0, 12):
2542 case IP_VERSION(13, 0, 14):
2543 case IP_VERSION(13, 0, 15):
2544 case IP_VERSION(14, 0, 0):
2545 case IP_VERSION(14, 0, 1):
2546 case IP_VERSION(14, 0, 4):
2547 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
2548 break;
2549 case IP_VERSION(13, 0, 4):
2550 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block);
2551 break;
2552 case IP_VERSION(14, 0, 2):
2553 case IP_VERSION(14, 0, 3):
2554 case IP_VERSION(14, 0, 5):
2555 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block);
2556 break;
2557 case IP_VERSION(15, 0, 0):
2558 case IP_VERSION(15, 0, 5):
2559 case IP_VERSION(15, 0, 9):
2560 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block);
2561 break;
2562 case IP_VERSION(15, 0, 8):
2563 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block);
2564 break;
2565 default:
2566 dev_err(adev->dev,
2567 "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
2568 amdgpu_ip_version(adev, MP0_HWIP, 0));
2569 return -EINVAL;
2570 }
2571 return 0;
2572 }
2573
amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device * adev)2574 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
2575 {
2576 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2577 case IP_VERSION(9, 0, 0):
2578 case IP_VERSION(10, 0, 0):
2579 case IP_VERSION(10, 0, 1):
2580 case IP_VERSION(11, 0, 2):
2581 if (adev->asic_type == CHIP_ARCTURUS)
2582 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2583 else
2584 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2585 break;
2586 case IP_VERSION(11, 0, 0):
2587 case IP_VERSION(11, 0, 5):
2588 case IP_VERSION(11, 0, 9):
2589 case IP_VERSION(11, 0, 7):
2590 case IP_VERSION(11, 0, 11):
2591 case IP_VERSION(11, 0, 12):
2592 case IP_VERSION(11, 0, 13):
2593 case IP_VERSION(11, 5, 0):
2594 case IP_VERSION(11, 5, 2):
2595 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2596 break;
2597 case IP_VERSION(11, 0, 8):
2598 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
2599 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2600 break;
2601 case IP_VERSION(12, 0, 0):
2602 case IP_VERSION(12, 0, 1):
2603 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
2604 break;
2605 case IP_VERSION(13, 0, 0):
2606 case IP_VERSION(13, 0, 1):
2607 case IP_VERSION(13, 0, 2):
2608 case IP_VERSION(13, 0, 3):
2609 case IP_VERSION(13, 0, 4):
2610 case IP_VERSION(13, 0, 5):
2611 case IP_VERSION(13, 0, 6):
2612 case IP_VERSION(13, 0, 7):
2613 case IP_VERSION(13, 0, 8):
2614 case IP_VERSION(13, 0, 10):
2615 case IP_VERSION(13, 0, 11):
2616 case IP_VERSION(13, 0, 14):
2617 case IP_VERSION(13, 0, 12):
2618 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
2619 break;
2620 case IP_VERSION(14, 0, 0):
2621 case IP_VERSION(14, 0, 1):
2622 case IP_VERSION(14, 0, 2):
2623 case IP_VERSION(14, 0, 3):
2624 case IP_VERSION(14, 0, 4):
2625 case IP_VERSION(14, 0, 5):
2626 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block);
2627 break;
2628 case IP_VERSION(15, 0, 0):
2629 case IP_VERSION(15, 0, 5):
2630 case IP_VERSION(15, 0, 8):
2631 case IP_VERSION(15, 0, 9):
2632 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block);
2633 break;
2634 default:
2635 dev_err(adev->dev,
2636 "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
2637 amdgpu_ip_version(adev, MP1_HWIP, 0));
2638 return -EINVAL;
2639 }
2640 return 0;
2641 }
2642
2643 #if defined(CONFIG_DRM_AMD_DC)
amdgpu_discovery_set_sriov_display(struct amdgpu_device * adev)2644 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev)
2645 {
2646 amdgpu_device_set_sriov_virtual_display(adev);
2647 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2648 }
2649 #endif
2650
amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device * adev)2651 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
2652 {
2653 if (adev->enable_virtual_display) {
2654 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2655 return 0;
2656 }
2657
2658 if (!amdgpu_device_has_dc_support(adev))
2659 return 0;
2660
2661 #if defined(CONFIG_DRM_AMD_DC)
2662 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2663 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2664 case IP_VERSION(1, 0, 0):
2665 case IP_VERSION(1, 0, 1):
2666 case IP_VERSION(2, 0, 2):
2667 case IP_VERSION(2, 0, 0):
2668 case IP_VERSION(2, 0, 3):
2669 case IP_VERSION(2, 1, 0):
2670 case IP_VERSION(3, 0, 0):
2671 case IP_VERSION(3, 0, 2):
2672 case IP_VERSION(3, 0, 3):
2673 case IP_VERSION(3, 0, 1):
2674 case IP_VERSION(3, 1, 2):
2675 case IP_VERSION(3, 1, 3):
2676 case IP_VERSION(3, 1, 4):
2677 case IP_VERSION(3, 1, 5):
2678 case IP_VERSION(3, 1, 6):
2679 case IP_VERSION(3, 2, 0):
2680 case IP_VERSION(3, 2, 1):
2681 case IP_VERSION(3, 5, 0):
2682 case IP_VERSION(3, 5, 1):
2683 case IP_VERSION(3, 6, 0):
2684 case IP_VERSION(4, 1, 0):
2685 case IP_VERSION(4, 2, 0):
2686 case IP_VERSION(4, 2, 1):
2687 case IP_VERSION(6, 0, 0):
2688 /* TODO: Fix IP version. DC code expects version 4.0.1 */
2689 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0))
2690 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1);
2691
2692 if (amdgpu_sriov_vf(adev))
2693 amdgpu_discovery_set_sriov_display(adev);
2694 else
2695 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2696 break;
2697 default:
2698 dev_err(adev->dev,
2699 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
2700 amdgpu_ip_version(adev, DCE_HWIP, 0));
2701 return -EINVAL;
2702 }
2703 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2704 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2705 case IP_VERSION(12, 0, 0):
2706 case IP_VERSION(12, 0, 1):
2707 case IP_VERSION(12, 1, 0):
2708 if (amdgpu_sriov_vf(adev))
2709 amdgpu_discovery_set_sriov_display(adev);
2710 else
2711 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2712 break;
2713 default:
2714 dev_err(adev->dev,
2715 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
2716 amdgpu_ip_version(adev, DCI_HWIP, 0));
2717 return -EINVAL;
2718 }
2719 }
2720 #endif
2721 return 0;
2722 }
2723
amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device * adev)2724 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
2725 {
2726 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2727 case IP_VERSION(9, 0, 1):
2728 case IP_VERSION(9, 1, 0):
2729 case IP_VERSION(9, 2, 1):
2730 case IP_VERSION(9, 2, 2):
2731 case IP_VERSION(9, 3, 0):
2732 case IP_VERSION(9, 4, 0):
2733 case IP_VERSION(9, 4, 1):
2734 case IP_VERSION(9, 4, 2):
2735 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
2736 break;
2737 case IP_VERSION(9, 4, 3):
2738 case IP_VERSION(9, 4, 4):
2739 case IP_VERSION(9, 5, 0):
2740 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block);
2741 break;
2742 case IP_VERSION(10, 1, 10):
2743 case IP_VERSION(10, 1, 2):
2744 case IP_VERSION(10, 1, 1):
2745 case IP_VERSION(10, 1, 3):
2746 case IP_VERSION(10, 1, 4):
2747 case IP_VERSION(10, 3, 0):
2748 case IP_VERSION(10, 3, 2):
2749 case IP_VERSION(10, 3, 1):
2750 case IP_VERSION(10, 3, 4):
2751 case IP_VERSION(10, 3, 5):
2752 case IP_VERSION(10, 3, 6):
2753 case IP_VERSION(10, 3, 3):
2754 case IP_VERSION(10, 3, 7):
2755 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
2756 break;
2757 case IP_VERSION(11, 0, 0):
2758 case IP_VERSION(11, 0, 1):
2759 case IP_VERSION(11, 0, 2):
2760 case IP_VERSION(11, 0, 3):
2761 case IP_VERSION(11, 0, 4):
2762 case IP_VERSION(11, 5, 0):
2763 case IP_VERSION(11, 5, 1):
2764 case IP_VERSION(11, 5, 2):
2765 case IP_VERSION(11, 5, 3):
2766 case IP_VERSION(11, 5, 4):
2767 case IP_VERSION(11, 5, 6):
2768 case IP_VERSION(11, 7, 0):
2769 case IP_VERSION(11, 7, 1):
2770 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
2771 break;
2772 case IP_VERSION(12, 0, 0):
2773 case IP_VERSION(12, 0, 1):
2774 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block);
2775 break;
2776 case IP_VERSION(12, 1, 0):
2777 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block);
2778 break;
2779 default:
2780 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
2781 amdgpu_ip_version(adev, GC_HWIP, 0));
2782 return -EINVAL;
2783 }
2784 return 0;
2785 }
2786
amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device * adev)2787 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
2788 {
2789 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
2790 case IP_VERSION(4, 0, 0):
2791 case IP_VERSION(4, 0, 1):
2792 case IP_VERSION(4, 1, 0):
2793 case IP_VERSION(4, 1, 1):
2794 case IP_VERSION(4, 1, 2):
2795 case IP_VERSION(4, 2, 0):
2796 case IP_VERSION(4, 2, 2):
2797 case IP_VERSION(4, 4, 0):
2798 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
2799 break;
2800 case IP_VERSION(4, 4, 2):
2801 case IP_VERSION(4, 4, 5):
2802 case IP_VERSION(4, 4, 4):
2803 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block);
2804 break;
2805 case IP_VERSION(5, 0, 0):
2806 case IP_VERSION(5, 0, 1):
2807 case IP_VERSION(5, 0, 2):
2808 case IP_VERSION(5, 0, 5):
2809 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
2810 break;
2811 case IP_VERSION(5, 2, 0):
2812 case IP_VERSION(5, 2, 2):
2813 case IP_VERSION(5, 2, 4):
2814 case IP_VERSION(5, 2, 5):
2815 case IP_VERSION(5, 2, 6):
2816 case IP_VERSION(5, 2, 3):
2817 case IP_VERSION(5, 2, 1):
2818 case IP_VERSION(5, 2, 7):
2819 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
2820 break;
2821 case IP_VERSION(6, 0, 0):
2822 case IP_VERSION(6, 0, 1):
2823 case IP_VERSION(6, 0, 2):
2824 case IP_VERSION(6, 0, 3):
2825 case IP_VERSION(6, 1, 0):
2826 case IP_VERSION(6, 1, 1):
2827 case IP_VERSION(6, 1, 2):
2828 case IP_VERSION(6, 1, 3):
2829 case IP_VERSION(6, 1, 4):
2830 case IP_VERSION(6, 4, 0):
2831 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
2832 break;
2833 case IP_VERSION(7, 0, 0):
2834 case IP_VERSION(7, 0, 1):
2835 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block);
2836 break;
2837 case IP_VERSION(7, 1, 0):
2838 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block);
2839 break;
2840 default:
2841 dev_err(adev->dev,
2842 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
2843 amdgpu_ip_version(adev, SDMA0_HWIP, 0));
2844 return -EINVAL;
2845 }
2846
2847 return 0;
2848 }
2849
amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device * adev)2850 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev)
2851 {
2852 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2853 case IP_VERSION(13, 0, 6):
2854 case IP_VERSION(13, 0, 12):
2855 case IP_VERSION(13, 0, 14):
2856 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block);
2857 break;
2858 default:
2859 break;
2860 }
2861 return 0;
2862 }
2863
amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device * adev)2864 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
2865 {
2866 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2867 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
2868 case IP_VERSION(7, 0, 0):
2869 case IP_VERSION(7, 2, 0):
2870 /* UVD is not supported on vega20 SR-IOV */
2871 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2872 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
2873 break;
2874 default:
2875 dev_err(adev->dev,
2876 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
2877 amdgpu_ip_version(adev, UVD_HWIP, 0));
2878 return -EINVAL;
2879 }
2880 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2881 case IP_VERSION(4, 0, 0):
2882 case IP_VERSION(4, 1, 0):
2883 /* VCE is not supported on vega20 SR-IOV */
2884 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2885 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
2886 break;
2887 default:
2888 dev_err(adev->dev,
2889 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
2890 amdgpu_ip_version(adev, VCE_HWIP, 0));
2891 return -EINVAL;
2892 }
2893 } else {
2894 uint32_t vcn_version = amdgpu_ip_version(adev, UVD_HWIP, 0);
2895
2896 /* no VCN discovered; nothing to add */
2897 if (!vcn_version)
2898 return 0;
2899 switch (vcn_version) {
2900 case IP_VERSION(1, 0, 0):
2901 case IP_VERSION(1, 0, 1):
2902 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
2903 break;
2904 case IP_VERSION(2, 0, 0):
2905 case IP_VERSION(2, 0, 2):
2906 case IP_VERSION(2, 2, 0):
2907 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
2908 if (!amdgpu_sriov_vf(adev))
2909 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
2910 break;
2911 case IP_VERSION(2, 0, 3):
2912 break;
2913 case IP_VERSION(2, 5, 0):
2914 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
2915 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
2916 break;
2917 case IP_VERSION(2, 6, 0):
2918 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
2919 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
2920 break;
2921 case IP_VERSION(3, 0, 0):
2922 case IP_VERSION(3, 0, 16):
2923 case IP_VERSION(3, 1, 1):
2924 case IP_VERSION(3, 1, 2):
2925 case IP_VERSION(3, 0, 2):
2926 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2927 if (!amdgpu_sriov_vf(adev))
2928 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
2929 break;
2930 case IP_VERSION(3, 0, 33):
2931 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2932 break;
2933 case IP_VERSION(4, 0, 0):
2934 case IP_VERSION(4, 0, 2):
2935 case IP_VERSION(4, 0, 4):
2936 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
2937 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
2938 break;
2939 case IP_VERSION(4, 0, 3):
2940 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
2941 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
2942 break;
2943 case IP_VERSION(4, 0, 5):
2944 case IP_VERSION(4, 0, 6):
2945 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
2946 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
2947 break;
2948 case IP_VERSION(5, 0, 0):
2949 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
2950 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block);
2951 break;
2952 case IP_VERSION(5, 3, 0):
2953 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
2954 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block);
2955 break;
2956 case IP_VERSION(5, 0, 1):
2957 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block);
2958 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block);
2959 break;
2960 case IP_VERSION(5, 0, 2):
2961 amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block);
2962 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_2_ip_block);
2963 break;
2964 default:
2965 dev_err(adev->dev,
2966 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
2967 vcn_version);
2968 return -EINVAL;
2969 }
2970 }
2971 return 0;
2972 }
2973
amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device * adev)2974 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
2975 {
2976 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2977 case IP_VERSION(11, 0, 0):
2978 case IP_VERSION(11, 0, 1):
2979 case IP_VERSION(11, 0, 2):
2980 case IP_VERSION(11, 0, 3):
2981 case IP_VERSION(11, 0, 4):
2982 case IP_VERSION(11, 5, 0):
2983 case IP_VERSION(11, 5, 1):
2984 case IP_VERSION(11, 5, 2):
2985 case IP_VERSION(11, 5, 3):
2986 case IP_VERSION(11, 5, 4):
2987 case IP_VERSION(11, 5, 6):
2988 case IP_VERSION(11, 7, 0):
2989 case IP_VERSION(11, 7, 1):
2990 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
2991 adev->enable_mes = true;
2992 adev->enable_mes_kiq = true;
2993 break;
2994 case IP_VERSION(12, 0, 0):
2995 case IP_VERSION(12, 0, 1):
2996 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block);
2997 adev->enable_mes = true;
2998 adev->enable_mes_kiq = true;
2999 if (amdgpu_uni_mes)
3000 adev->enable_uni_mes = true;
3001 break;
3002 case IP_VERSION(12, 1, 0):
3003 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block);
3004 adev->enable_mes = true;
3005 adev->enable_mes_kiq = true;
3006 if (amdgpu_uni_mes)
3007 adev->enable_uni_mes = true;
3008 break;
3009 default:
3010 break;
3011 }
3012 return 0;
3013 }
3014
amdgpu_discovery_init_soc_config(struct amdgpu_device * adev)3015 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev)
3016 {
3017 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3018 case IP_VERSION(9, 4, 3):
3019 case IP_VERSION(9, 4, 4):
3020 case IP_VERSION(9, 5, 0):
3021 aqua_vanjaram_init_soc_config(adev);
3022 break;
3023 case IP_VERSION(12, 1, 0):
3024 soc_v1_0_init_soc_config(adev);
3025 break;
3026 default:
3027 break;
3028 }
3029 }
3030
amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device * adev)3031 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev)
3032 {
3033 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
3034 case IP_VERSION(6, 1, 0):
3035 case IP_VERSION(6, 1, 1):
3036 case IP_VERSION(6, 1, 3):
3037 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block);
3038 break;
3039 case IP_VERSION(2, 0, 0):
3040 case IP_VERSION(2, 2, 0):
3041 amdgpu_device_ip_block_add(adev, &vpe_v2_0_ip_block);
3042 break;
3043 default:
3044 break;
3045 }
3046
3047 return 0;
3048 }
3049
amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device * adev)3050 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev)
3051 {
3052 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
3053 case IP_VERSION(4, 0, 5):
3054 case IP_VERSION(4, 0, 6):
3055 if (amdgpu_umsch_mm & 0x1) {
3056 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block);
3057 adev->enable_umsch_mm = true;
3058 }
3059 break;
3060 default:
3061 break;
3062 }
3063
3064 return 0;
3065 }
3066
amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device * adev)3067 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev)
3068 {
3069 #if defined(CONFIG_DRM_AMD_ISP)
3070 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) {
3071 case IP_VERSION(4, 1, 0):
3072 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block);
3073 break;
3074 case IP_VERSION(4, 1, 1):
3075 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block);
3076 break;
3077 default:
3078 break;
3079 }
3080 #endif
3081
3082 return 0;
3083 }
3084
amdgpu_discovery_set_ip_blocks(struct amdgpu_device * adev)3085 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
3086 {
3087 int r;
3088
3089 switch (adev->asic_type) {
3090 case CHIP_VEGA10:
3091 /* This is not fatal. We only need the discovery
3092 * binary for sysfs. We don't need it for a
3093 * functional system.
3094 */
3095 amdgpu_discovery_init(adev);
3096 vega10_reg_base_init(adev);
3097 adev->sdma.num_instances = 2;
3098 adev->sdma.sdma_mask = 3;
3099 adev->gmc.num_umc = 4;
3100 adev->gfx.xcc_mask = 1;
3101 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
3102 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
3103 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
3104 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
3105 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
3106 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
3107 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
3108 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
3109 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
3110 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
3111 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
3112 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
3113 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
3114 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
3115 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
3116 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
3117 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
3118 break;
3119 case CHIP_VEGA12:
3120 /* This is not fatal. We only need the discovery
3121 * binary for sysfs. We don't need it for a
3122 * functional system.
3123 */
3124 amdgpu_discovery_init(adev);
3125 vega10_reg_base_init(adev);
3126 adev->sdma.num_instances = 2;
3127 adev->sdma.sdma_mask = 3;
3128 adev->gmc.num_umc = 4;
3129 adev->gfx.xcc_mask = 1;
3130 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
3131 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
3132 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
3133 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
3134 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
3135 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
3136 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
3137 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
3138 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
3139 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
3140 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
3141 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
3142 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
3143 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
3144 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
3145 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
3146 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
3147 break;
3148 case CHIP_RAVEN:
3149 /* This is not fatal. We only need the discovery
3150 * binary for sysfs. We don't need it for a
3151 * functional system.
3152 */
3153 amdgpu_discovery_init(adev);
3154 vega10_reg_base_init(adev);
3155 adev->sdma.num_instances = 1;
3156 adev->sdma.sdma_mask = 1;
3157 adev->vcn.num_vcn_inst = 1;
3158 adev->gmc.num_umc = 2;
3159 adev->gfx.xcc_mask = 1;
3160 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
3161 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
3162 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
3163 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
3164 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
3165 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
3166 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
3167 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
3168 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
3169 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
3170 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
3171 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
3172 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
3173 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
3174 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
3175 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
3176 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);
3177 } else {
3178 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
3179 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
3180 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
3181 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
3182 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
3183 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
3184 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
3185 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
3186 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
3187 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
3188 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
3189 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
3190 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
3191 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
3192 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
3193 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);
3194 }
3195 break;
3196 case CHIP_VEGA20:
3197 /* This is not fatal. We only need the discovery
3198 * binary for sysfs. We don't need it for a
3199 * functional system.
3200 */
3201 amdgpu_discovery_init(adev);
3202 vega20_reg_base_init(adev);
3203 adev->sdma.num_instances = 2;
3204 adev->sdma.sdma_mask = 3;
3205 adev->gmc.num_umc = 8;
3206 adev->gfx.xcc_mask = 1;
3207 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
3208 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
3209 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
3210 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
3211 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
3212 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
3213 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
3214 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
3215 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
3216 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
3217 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
3218 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
3219 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
3220 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
3221 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
3222 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
3223 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
3224 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
3225 break;
3226 case CHIP_ARCTURUS:
3227 /* This is not fatal. We only need the discovery
3228 * binary for sysfs. We don't need it for a
3229 * functional system.
3230 */
3231 amdgpu_discovery_init(adev);
3232 arct_reg_base_init(adev);
3233 adev->sdma.num_instances = 8;
3234 adev->sdma.sdma_mask = 0xff;
3235 adev->vcn.num_vcn_inst = 2;
3236 adev->gmc.num_umc = 8;
3237 adev->gfx.xcc_mask = 1;
3238 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
3239 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
3240 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
3241 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
3242 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
3243 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
3244 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
3245 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
3246 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
3247 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
3248 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
3249 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
3250 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
3251 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
3252 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
3253 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
3254 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
3255 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
3256 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
3257 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
3258 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
3259 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
3260 break;
3261 case CHIP_ALDEBARAN:
3262 /* This is not fatal. We only need the discovery
3263 * binary for sysfs. We don't need it for a
3264 * functional system.
3265 */
3266 amdgpu_discovery_init(adev);
3267 aldebaran_reg_base_init(adev);
3268 adev->sdma.num_instances = 5;
3269 adev->sdma.sdma_mask = 0x1f;
3270 adev->vcn.num_vcn_inst = 2;
3271 adev->gmc.num_umc = 4;
3272 adev->gfx.xcc_mask = 1;
3273 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
3274 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
3275 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
3276 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
3277 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
3278 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
3279 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
3280 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
3281 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
3282 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
3283 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
3284 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
3285 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
3286 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
3287 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
3288 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
3289 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
3290 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
3291 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
3292 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
3293 break;
3294 case CHIP_CYAN_SKILLFISH:
3295 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
3296 r = amdgpu_discovery_reg_base_init(adev);
3297 if (r)
3298 return -EINVAL;
3299
3300 amdgpu_discovery_harvest_ip(adev);
3301 amdgpu_discovery_get_gfx_info(adev);
3302 amdgpu_discovery_get_mall_info(adev);
3303 amdgpu_discovery_get_vcn_info(adev);
3304 } else {
3305 cyan_skillfish_reg_base_init(adev);
3306 adev->sdma.num_instances = 2;
3307 adev->sdma.sdma_mask = 3;
3308 adev->gfx.xcc_mask = 1;
3309 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3);
3310 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3);
3311 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1);
3312 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1);
3313 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1);
3314 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1);
3315 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0);
3316 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1);
3317 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1);
3318 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8);
3319 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8);
3320 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1);
3321 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8);
3322 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3);
3323 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3);
3324 }
3325 break;
3326 default:
3327 r = amdgpu_discovery_reg_base_init(adev);
3328 if (r) {
3329 drm_err(&adev->ddev, "discovery failed: %d\n", r);
3330 return r;
3331 }
3332
3333 amdgpu_discovery_harvest_ip(adev);
3334 amdgpu_discovery_get_gfx_info(adev);
3335 amdgpu_discovery_get_mall_info(adev);
3336 amdgpu_discovery_get_vcn_info(adev);
3337 break;
3338 }
3339
3340 amdgpu_discovery_init_soc_config(adev);
3341 amdgpu_discovery_sysfs_init(adev);
3342
3343 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3344 case IP_VERSION(9, 0, 1):
3345 case IP_VERSION(9, 2, 1):
3346 case IP_VERSION(9, 4, 0):
3347 case IP_VERSION(9, 4, 1):
3348 case IP_VERSION(9, 4, 2):
3349 case IP_VERSION(9, 4, 3):
3350 case IP_VERSION(9, 4, 4):
3351 case IP_VERSION(9, 5, 0):
3352 adev->family = AMDGPU_FAMILY_AI;
3353 break;
3354 case IP_VERSION(9, 1, 0):
3355 case IP_VERSION(9, 2, 2):
3356 case IP_VERSION(9, 3, 0):
3357 adev->family = AMDGPU_FAMILY_RV;
3358 break;
3359 case IP_VERSION(10, 1, 10):
3360 case IP_VERSION(10, 1, 1):
3361 case IP_VERSION(10, 1, 2):
3362 case IP_VERSION(10, 1, 3):
3363 case IP_VERSION(10, 1, 4):
3364 case IP_VERSION(10, 3, 0):
3365 case IP_VERSION(10, 3, 2):
3366 case IP_VERSION(10, 3, 4):
3367 case IP_VERSION(10, 3, 5):
3368 adev->family = AMDGPU_FAMILY_NV;
3369 break;
3370 case IP_VERSION(10, 3, 1):
3371 adev->family = AMDGPU_FAMILY_VGH;
3372 adev->apu_flags |= AMD_APU_IS_VANGOGH;
3373 break;
3374 case IP_VERSION(10, 3, 3):
3375 adev->family = AMDGPU_FAMILY_YC;
3376 break;
3377 case IP_VERSION(10, 3, 6):
3378 adev->family = AMDGPU_FAMILY_GC_10_3_6;
3379 break;
3380 case IP_VERSION(10, 3, 7):
3381 adev->family = AMDGPU_FAMILY_GC_10_3_7;
3382 break;
3383 case IP_VERSION(11, 0, 0):
3384 case IP_VERSION(11, 0, 2):
3385 case IP_VERSION(11, 0, 3):
3386 adev->family = AMDGPU_FAMILY_GC_11_0_0;
3387 break;
3388 case IP_VERSION(11, 0, 1):
3389 case IP_VERSION(11, 0, 4):
3390 adev->family = AMDGPU_FAMILY_GC_11_0_1;
3391 break;
3392 case IP_VERSION(11, 5, 0):
3393 case IP_VERSION(11, 5, 1):
3394 case IP_VERSION(11, 5, 2):
3395 case IP_VERSION(11, 5, 3):
3396 case IP_VERSION(11, 5, 4):
3397 case IP_VERSION(11, 5, 6):
3398 adev->family = AMDGPU_FAMILY_GC_11_5_0;
3399 break;
3400 case IP_VERSION(11, 7, 0):
3401 case IP_VERSION(11, 7, 1):
3402 adev->family = AMDGPU_FAMILY_GC_11_5_4;
3403 break;
3404 case IP_VERSION(12, 0, 0):
3405 case IP_VERSION(12, 0, 1):
3406 case IP_VERSION(12, 1, 0):
3407 adev->family = AMDGPU_FAMILY_GC_12_0_0;
3408 break;
3409 default:
3410 return -EINVAL;
3411 }
3412
3413 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3414 case IP_VERSION(9, 1, 0):
3415 case IP_VERSION(9, 2, 2):
3416 case IP_VERSION(9, 3, 0):
3417 case IP_VERSION(10, 1, 3):
3418 case IP_VERSION(10, 1, 4):
3419 case IP_VERSION(10, 3, 1):
3420 case IP_VERSION(10, 3, 3):
3421 case IP_VERSION(10, 3, 6):
3422 case IP_VERSION(10, 3, 7):
3423 case IP_VERSION(11, 0, 1):
3424 case IP_VERSION(11, 0, 4):
3425 case IP_VERSION(11, 5, 0):
3426 case IP_VERSION(11, 5, 1):
3427 case IP_VERSION(11, 5, 2):
3428 case IP_VERSION(11, 5, 3):
3429 case IP_VERSION(11, 5, 4):
3430 case IP_VERSION(11, 5, 6):
3431 case IP_VERSION(11, 7, 0):
3432 case IP_VERSION(11, 7, 1):
3433 adev->flags |= AMD_IS_APU;
3434 break;
3435 default:
3436 break;
3437 }
3438
3439 /* set NBIO version */
3440 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
3441 case IP_VERSION(6, 1, 0):
3442 case IP_VERSION(6, 2, 0):
3443 adev->nbio.funcs = &nbio_v6_1_funcs;
3444 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
3445 break;
3446 case IP_VERSION(7, 0, 0):
3447 case IP_VERSION(7, 0, 1):
3448 case IP_VERSION(2, 5, 0):
3449 adev->nbio.funcs = &nbio_v7_0_funcs;
3450 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
3451 break;
3452 case IP_VERSION(7, 4, 0):
3453 case IP_VERSION(7, 4, 1):
3454 case IP_VERSION(7, 4, 4):
3455 adev->nbio.funcs = &nbio_v7_4_funcs;
3456 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
3457 break;
3458 case IP_VERSION(7, 9, 0):
3459 case IP_VERSION(7, 9, 1):
3460 adev->nbio.funcs = &nbio_v7_9_funcs;
3461 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg;
3462 break;
3463 case IP_VERSION(7, 11, 0):
3464 case IP_VERSION(7, 11, 1):
3465 case IP_VERSION(7, 11, 2):
3466 case IP_VERSION(7, 11, 3):
3467 adev->nbio.funcs = &nbio_v7_11_funcs;
3468 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg;
3469 break;
3470 case IP_VERSION(7, 2, 0):
3471 case IP_VERSION(7, 2, 1):
3472 case IP_VERSION(7, 3, 0):
3473 case IP_VERSION(7, 5, 0):
3474 case IP_VERSION(7, 5, 1):
3475 adev->nbio.funcs = &nbio_v7_2_funcs;
3476 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
3477 break;
3478 case IP_VERSION(2, 1, 1):
3479 case IP_VERSION(2, 3, 0):
3480 case IP_VERSION(2, 3, 1):
3481 case IP_VERSION(2, 3, 2):
3482 case IP_VERSION(3, 3, 0):
3483 case IP_VERSION(3, 3, 1):
3484 case IP_VERSION(3, 3, 2):
3485 case IP_VERSION(3, 3, 3):
3486 adev->nbio.funcs = &nbio_v2_3_funcs;
3487 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
3488 break;
3489 case IP_VERSION(4, 3, 0):
3490 case IP_VERSION(4, 3, 1):
3491 if (amdgpu_sriov_vf(adev))
3492 adev->nbio.funcs = &nbio_v4_3_sriov_funcs;
3493 else
3494 adev->nbio.funcs = &nbio_v4_3_funcs;
3495 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
3496 break;
3497 case IP_VERSION(7, 7, 0):
3498 case IP_VERSION(7, 7, 1):
3499 adev->nbio.funcs = &nbio_v7_7_funcs;
3500 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
3501 break;
3502 case IP_VERSION(6, 3, 1):
3503 case IP_VERSION(7, 11, 4):
3504 case IP_VERSION(7, 11, 5):
3505 adev->nbio.funcs = &nbif_v6_3_1_funcs;
3506 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg;
3507 break;
3508 case IP_VERSION(6, 3, 2):
3509 adev->nbio.funcs = &nbio_v6_3_2_funcs;
3510 break;
3511 default:
3512 break;
3513 }
3514
3515 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) {
3516 case IP_VERSION(4, 0, 0):
3517 case IP_VERSION(4, 0, 1):
3518 case IP_VERSION(4, 1, 0):
3519 case IP_VERSION(4, 1, 1):
3520 case IP_VERSION(4, 1, 2):
3521 case IP_VERSION(4, 2, 0):
3522 case IP_VERSION(4, 2, 1):
3523 case IP_VERSION(4, 4, 0):
3524 case IP_VERSION(4, 4, 2):
3525 case IP_VERSION(4, 4, 5):
3526 adev->hdp.funcs = &hdp_v4_0_funcs;
3527 break;
3528 case IP_VERSION(5, 0, 0):
3529 case IP_VERSION(5, 0, 1):
3530 case IP_VERSION(5, 0, 2):
3531 case IP_VERSION(5, 0, 3):
3532 case IP_VERSION(5, 0, 4):
3533 case IP_VERSION(5, 2, 0):
3534 adev->hdp.funcs = &hdp_v5_0_funcs;
3535 break;
3536 case IP_VERSION(5, 2, 1):
3537 adev->hdp.funcs = &hdp_v5_2_funcs;
3538 break;
3539 case IP_VERSION(6, 0, 0):
3540 case IP_VERSION(6, 0, 1):
3541 case IP_VERSION(6, 1, 0):
3542 case IP_VERSION(6, 1, 1):
3543 case IP_VERSION(6, 4, 0):
3544 adev->hdp.funcs = &hdp_v6_0_funcs;
3545 break;
3546 case IP_VERSION(7, 0, 0):
3547 adev->hdp.funcs = &hdp_v7_0_funcs;
3548 break;
3549 default:
3550 break;
3551 }
3552
3553 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) {
3554 case IP_VERSION(3, 6, 0):
3555 case IP_VERSION(3, 6, 1):
3556 case IP_VERSION(3, 6, 2):
3557 adev->df.funcs = &df_v3_6_funcs;
3558 break;
3559 case IP_VERSION(2, 1, 0):
3560 case IP_VERSION(2, 1, 1):
3561 case IP_VERSION(2, 5, 0):
3562 case IP_VERSION(3, 5, 1):
3563 case IP_VERSION(3, 5, 2):
3564 adev->df.funcs = &df_v1_7_funcs;
3565 break;
3566 case IP_VERSION(4, 3, 0):
3567 adev->df.funcs = &df_v4_3_funcs;
3568 break;
3569 case IP_VERSION(4, 6, 2):
3570 adev->df.funcs = &df_v4_6_2_funcs;
3571 break;
3572 case IP_VERSION(4, 15, 0):
3573 case IP_VERSION(4, 15, 1):
3574 adev->df.funcs = &df_v4_15_funcs;
3575 break;
3576 default:
3577 break;
3578 }
3579
3580 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) {
3581 case IP_VERSION(9, 0, 0):
3582 case IP_VERSION(9, 0, 1):
3583 case IP_VERSION(10, 0, 0):
3584 case IP_VERSION(10, 0, 1):
3585 case IP_VERSION(10, 0, 2):
3586 adev->smuio.funcs = &smuio_v9_0_funcs;
3587 break;
3588 case IP_VERSION(11, 0, 0):
3589 case IP_VERSION(11, 0, 2):
3590 case IP_VERSION(11, 0, 3):
3591 case IP_VERSION(11, 0, 4):
3592 case IP_VERSION(11, 0, 7):
3593 case IP_VERSION(11, 0, 8):
3594 adev->smuio.funcs = &smuio_v11_0_funcs;
3595 break;
3596 case IP_VERSION(11, 0, 6):
3597 case IP_VERSION(11, 0, 10):
3598 case IP_VERSION(11, 0, 11):
3599 case IP_VERSION(11, 5, 0):
3600 case IP_VERSION(11, 5, 2):
3601 case IP_VERSION(13, 0, 1):
3602 case IP_VERSION(13, 0, 9):
3603 case IP_VERSION(13, 0, 10):
3604 adev->smuio.funcs = &smuio_v11_0_6_funcs;
3605 break;
3606 case IP_VERSION(13, 0, 2):
3607 adev->smuio.funcs = &smuio_v13_0_funcs;
3608 break;
3609 case IP_VERSION(13, 0, 3):
3610 case IP_VERSION(13, 0, 11):
3611 adev->smuio.funcs = &smuio_v13_0_3_funcs;
3612 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) {
3613 adev->flags |= AMD_IS_APU;
3614 }
3615 break;
3616 case IP_VERSION(13, 0, 6):
3617 case IP_VERSION(13, 0, 8):
3618 case IP_VERSION(14, 0, 0):
3619 case IP_VERSION(14, 0, 1):
3620 adev->smuio.funcs = &smuio_v13_0_6_funcs;
3621 break;
3622 case IP_VERSION(14, 0, 2):
3623 adev->smuio.funcs = &smuio_v14_0_2_funcs;
3624 break;
3625 case IP_VERSION(15, 0, 0):
3626 case IP_VERSION(15, 0, 5):
3627 adev->smuio.funcs = &smuio_v15_0_0_funcs;
3628 break;
3629 case IP_VERSION(15, 0, 8):
3630 adev->smuio.funcs = &smuio_v15_0_8_funcs;
3631 break;
3632 default:
3633 break;
3634 }
3635
3636 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
3637 case IP_VERSION(6, 0, 0):
3638 case IP_VERSION(6, 0, 1):
3639 case IP_VERSION(6, 0, 2):
3640 case IP_VERSION(6, 0, 3):
3641 adev->lsdma.funcs = &lsdma_v6_0_funcs;
3642 break;
3643 case IP_VERSION(7, 0, 0):
3644 case IP_VERSION(7, 0, 1):
3645 adev->lsdma.funcs = &lsdma_v7_0_funcs;
3646 break;
3647 case IP_VERSION(7, 1, 0):
3648 adev->lsdma.funcs = &lsdma_v7_1_funcs;
3649 break;
3650 default:
3651 break;
3652 }
3653
3654 r = amdgpu_discovery_set_common_ip_blocks(adev);
3655 if (r)
3656 return r;
3657
3658 r = amdgpu_discovery_set_gmc_ip_blocks(adev);
3659 if (r)
3660 return r;
3661
3662 /* For SR-IOV, PSP needs to be initialized before IH */
3663 if (amdgpu_sriov_vf(adev)) {
3664 r = amdgpu_discovery_set_psp_ip_blocks(adev);
3665 if (r)
3666 return r;
3667 r = amdgpu_discovery_set_ih_ip_blocks(adev);
3668 if (r)
3669 return r;
3670 } else {
3671 r = amdgpu_discovery_set_ih_ip_blocks(adev);
3672 if (r)
3673 return r;
3674
3675 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3676 r = amdgpu_discovery_set_psp_ip_blocks(adev);
3677 if (r)
3678 return r;
3679 }
3680 }
3681
3682 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3683 r = amdgpu_discovery_set_smu_ip_blocks(adev);
3684 if (r)
3685 return r;
3686 }
3687
3688 r = amdgpu_discovery_set_display_ip_blocks(adev);
3689 if (r)
3690 return r;
3691
3692 r = amdgpu_discovery_set_gc_ip_blocks(adev);
3693 if (r)
3694 return r;
3695
3696 r = amdgpu_discovery_set_sdma_ip_blocks(adev);
3697 if (r)
3698 return r;
3699
3700 r = amdgpu_discovery_set_ras_ip_blocks(adev);
3701 if (r)
3702 return r;
3703
3704 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
3705 !amdgpu_sriov_vf(adev) &&
3706 amdgpu_dpm == 1) ||
3707 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO &&
3708 amdgpu_dpm == 1)) {
3709 r = amdgpu_discovery_set_smu_ip_blocks(adev);
3710 if (r)
3711 return r;
3712 }
3713
3714 r = amdgpu_discovery_set_mm_ip_blocks(adev);
3715 if (r)
3716 return r;
3717
3718 r = amdgpu_discovery_set_mes_ip_blocks(adev);
3719 if (r)
3720 return r;
3721
3722 r = amdgpu_discovery_set_vpe_ip_blocks(adev);
3723 if (r)
3724 return r;
3725
3726 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev);
3727 if (r)
3728 return r;
3729
3730 r = amdgpu_discovery_set_isp_ip_blocks(adev);
3731 if (r)
3732 return r;
3733 return 0;
3734 }
3735
amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device * adev,uint16_t * major,uint16_t * minor)3736 int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev,
3737 uint16_t *major, uint16_t *minor)
3738 {
3739 uint8_t *discovery_bin = adev->discovery.bin;
3740 struct table_info *info;
3741 union gc_info *gc_info;
3742 u16 offset;
3743
3744 if (!discovery_bin)
3745 return -EINVAL;
3746 if (amdgpu_discovery_get_table_info(adev, &info, GC))
3747 return -EINVAL;
3748
3749 offset = le16_to_cpu(info->offset);
3750 if (!offset)
3751 return -EINVAL;
3752
3753 gc_info = (union gc_info *)(discovery_bin + offset);
3754
3755 if (major)
3756 *major = le16_to_cpu(gc_info->v1.header.version_major);
3757 if (minor)
3758 *minor = le16_to_cpu(gc_info->v1.header.version_minor);
3759 return 0;
3760 }
3761