1 /* 2 * Copyright 2012-2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn20_hubp.h" 27 28 #include "dm_services.h" 29 #include "dce_calcs.h" 30 #include "reg_helper.h" 31 #include "basics/conversion.h" 32 33 #define DC_LOGGER \ 34 ctx->logger 35 #define DC_LOGGER_INIT(logger) 36 37 #define REG(reg)\ 38 hubp2->hubp_regs->reg 39 40 #define CTX \ 41 hubp2->base.ctx 42 43 #undef FN 44 #define FN(reg_name, field_name) \ 45 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 46 47 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, 48 struct vm_system_aperture_param *apt) 49 { 50 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 51 52 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 53 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 54 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 55 56 // The format of default addr is 48:12 of the 48 bit addr 57 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 58 59 // The format of high/low are 48:18 of the 48 bit addr 60 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 61 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 62 63 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 64 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */ 65 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 66 67 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 68 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 69 70 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 71 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 72 73 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 74 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 75 76 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 77 ENABLE_L1_TLB, 1, 78 SYSTEM_ACCESS_MODE, 0x3); 79 } 80 81 void hubp2_program_deadline( 82 struct hubp *hubp, 83 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 84 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 85 { 86 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 87 88 /* DLG - Per hubp */ 89 REG_SET_2(BLANK_OFFSET_0, 0, 90 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 91 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 92 93 REG_SET(BLANK_OFFSET_1, 0, 94 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 95 96 REG_SET(DST_DIMENSIONS, 0, 97 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 98 99 REG_SET_2(DST_AFTER_SCALER, 0, 100 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 101 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 102 103 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 104 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 105 106 /* DLG - Per luma/chroma */ 107 REG_SET(VBLANK_PARAMETERS_1, 0, 108 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 109 110 if (REG(NOM_PARAMETERS_0)) 111 REG_SET(NOM_PARAMETERS_0, 0, 112 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 113 114 if (REG(NOM_PARAMETERS_1)) 115 REG_SET(NOM_PARAMETERS_1, 0, 116 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 117 118 REG_SET(NOM_PARAMETERS_4, 0, 119 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 120 121 REG_SET(NOM_PARAMETERS_5, 0, 122 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 123 124 REG_SET_2(PER_LINE_DELIVERY, 0, 125 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 126 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 127 128 REG_SET(VBLANK_PARAMETERS_2, 0, 129 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 130 131 if (REG(NOM_PARAMETERS_2)) 132 REG_SET(NOM_PARAMETERS_2, 0, 133 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 134 135 if (REG(NOM_PARAMETERS_3)) 136 REG_SET(NOM_PARAMETERS_3, 0, 137 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 138 139 REG_SET(NOM_PARAMETERS_6, 0, 140 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 141 142 REG_SET(NOM_PARAMETERS_7, 0, 143 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 144 145 /* TTU - per hubp */ 146 REG_SET_2(DCN_TTU_QOS_WM, 0, 147 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 148 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 149 150 /* TTU - per luma/chroma */ 151 /* Assumed surf0 is luma and 1 is chroma */ 152 153 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 154 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 155 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 156 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 157 158 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 159 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 160 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 161 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 162 163 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 164 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 165 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 166 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 167 168 REG_SET(FLIP_PARAMETERS_1, 0, 169 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); 170 } 171 172 void hubp2_vready_at_or_After_vsync(struct hubp *hubp, 173 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 174 { 175 uint32_t value = 0; 176 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 177 /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */ 178 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8); 179 /* 180 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) 181 <= OTG_V_BLANK_END 182 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1 183 else 184 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0 185 */ 186 if (pipe_dest->htotal != 0) { 187 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width 188 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 189 value = 1; 190 } else 191 value = 0; 192 } 193 194 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); 195 } 196 197 static void hubp2_program_requestor(struct hubp *hubp, 198 struct _vcs_dpi_display_rq_regs_st *rq_regs) 199 { 200 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 201 202 REG_UPDATE(HUBPRET_CONTROL, 203 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 204 REG_SET_4(DCN_EXPANSION_MODE, 0, 205 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 206 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 207 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 208 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 209 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 210 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 211 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 212 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 213 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 214 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 215 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 216 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 217 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 218 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 219 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 220 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 221 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 222 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 223 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 224 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 225 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 226 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 227 } 228 229 static void hubp2_setup( 230 struct hubp *hubp, 231 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 232 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 233 struct _vcs_dpi_display_rq_regs_st *rq_regs, 234 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 235 { 236 /* otg is locked when this func is called. Register are double buffered. 237 * disable the requestors is not needed 238 */ 239 240 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 241 hubp2_program_requestor(hubp, rq_regs); 242 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 243 244 } 245 246 void hubp2_setup_interdependent( 247 struct hubp *hubp, 248 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 249 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 250 { 251 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 252 253 REG_SET_2(PREFETCH_SETTINGS, 0, 254 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 255 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 256 257 REG_SET(PREFETCH_SETTINGS_C, 0, 258 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 259 260 REG_SET_2(VBLANK_PARAMETERS_0, 0, 261 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 262 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 263 264 REG_SET_2(FLIP_PARAMETERS_0, 0, 265 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip, 266 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip); 267 268 REG_SET(VBLANK_PARAMETERS_3, 0, 269 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 270 271 REG_SET(VBLANK_PARAMETERS_4, 0, 272 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 273 274 REG_SET(FLIP_PARAMETERS_2, 0, 275 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l); 276 277 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 278 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 279 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 280 281 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 282 REFCYC_PER_REQ_DELIVERY_PRE, 283 ttu_attr->refcyc_per_req_delivery_pre_l); 284 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 285 REFCYC_PER_REQ_DELIVERY_PRE, 286 ttu_attr->refcyc_per_req_delivery_pre_c); 287 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 288 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 289 REG_SET(DCN_CUR1_TTU_CNTL1, 0, 290 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1); 291 292 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 293 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 294 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 295 } 296 297 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used: 298 * NUM_BANKS 299 * NUM_SE 300 * NUM_RB_PER_SE 301 * RB_ALIGNED 302 * Other things can be defaulted, since they never change: 303 * PIPE_ALIGNED = 0 304 * META_LINEAR = 0 305 * In GFX10, only these apply: 306 * PIPE_INTERLEAVE 307 * NUM_PIPES 308 * MAX_COMPRESSED_FRAGS 309 * SW_MODE 310 */ 311 static void hubp2_program_tiling( 312 struct dcn20_hubp *hubp2, 313 const struct dc_tiling_info *info, 314 const enum surface_pixel_format pixel_format) 315 { 316 (void)pixel_format; 317 REG_UPDATE_3(DCSURF_ADDR_CONFIG, 318 NUM_PIPES, log_2(info->gfx9.num_pipes), 319 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 320 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 321 322 REG_UPDATE_4(DCSURF_TILING_CONFIG, 323 SW_MODE, info->gfx9.swizzle, 324 META_LINEAR, 0, 325 RB_ALIGNED, 0, 326 PIPE_ALIGNED, 0); 327 } 328 329 void hubp2_program_size( 330 struct hubp *hubp, 331 enum surface_pixel_format format, 332 const struct plane_size *plane_size, 333 struct dc_plane_dcc_param *dcc) 334 { 335 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 336 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 337 bool use_pitch_c = false; 338 339 /* Program data and meta surface pitch (calculation from addrlib) 340 * 444 or 420 luma 341 */ 342 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 343 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END; 344 use_pitch_c = use_pitch_c 345 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); 346 if (use_pitch_c) { 347 ASSERT(plane_size->chroma_pitch != 0); 348 /* Chroma pitch zero can cause system hang! */ 349 350 pitch = plane_size->surface_pitch - 1; 351 meta_pitch = dcc->meta_pitch - 1; 352 pitch_c = plane_size->chroma_pitch - 1; 353 meta_pitch_c = dcc->meta_pitch_c - 1; 354 } else { 355 pitch = plane_size->surface_pitch - 1; 356 meta_pitch = dcc->meta_pitch - 1; 357 pitch_c = 0; 358 meta_pitch_c = 0; 359 } 360 361 if (!dcc->enable) { 362 meta_pitch = 0; 363 meta_pitch_c = 0; 364 } 365 366 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 367 PITCH, pitch, META_PITCH, meta_pitch); 368 369 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN; 370 use_pitch_c = use_pitch_c 371 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); 372 if (use_pitch_c) 373 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 374 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 375 } 376 377 void hubp2_program_rotation( 378 struct hubp *hubp, 379 enum dc_rotation_angle rotation, 380 bool horizontal_mirror) 381 { 382 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 383 uint32_t mirror; 384 385 386 if (horizontal_mirror) 387 mirror = 1; 388 else 389 mirror = 0; 390 391 /* Program rotation angle and horz mirror - no mirror */ 392 if (rotation == ROTATION_ANGLE_0) 393 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 394 ROTATION_ANGLE, 0, 395 H_MIRROR_EN, mirror); 396 else if (rotation == ROTATION_ANGLE_90) 397 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 398 ROTATION_ANGLE, 1, 399 H_MIRROR_EN, mirror); 400 else if (rotation == ROTATION_ANGLE_180) 401 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 402 ROTATION_ANGLE, 2, 403 H_MIRROR_EN, mirror); 404 else if (rotation == ROTATION_ANGLE_270) 405 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 406 ROTATION_ANGLE, 3, 407 H_MIRROR_EN, mirror); 408 } 409 410 void hubp2_clear_tiling(struct hubp *hubp) 411 { 412 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 413 414 REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0); 415 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); 416 417 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 418 PRIMARY_SURFACE_DCC_EN, 0, 419 PRIMARY_SURFACE_DCC_IND_64B_BLK, 0, 420 SECONDARY_SURFACE_DCC_EN, 0, 421 SECONDARY_SURFACE_DCC_IND_64B_BLK, 0); 422 } 423 424 void hubp2_dcc_control(struct hubp *hubp, bool enable, 425 enum hubp_ind_block_size independent_64b_blks) 426 { 427 uint32_t dcc_en = enable ? 1 : 0; 428 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 429 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 430 431 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 432 PRIMARY_SURFACE_DCC_EN, dcc_en, 433 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 434 SECONDARY_SURFACE_DCC_EN, dcc_en, 435 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 436 } 437 438 void hubp2_program_pixel_format( 439 struct hubp *hubp, 440 enum surface_pixel_format format) 441 { 442 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 443 uint32_t red_bar = 3; 444 uint32_t blue_bar = 2; 445 446 /* swap for ABGR format */ 447 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 448 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 449 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 450 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 451 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 452 red_bar = 2; 453 blue_bar = 3; 454 } 455 456 REG_UPDATE_2(HUBPRET_CONTROL, 457 CROSSBAR_SRC_CB_B, blue_bar, 458 CROSSBAR_SRC_CR_R, red_bar); 459 460 /* Mapping is same as ipp programming (cnvc) */ 461 462 switch (format) { 463 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 464 REG_UPDATE(DCSURF_SURFACE_CONFIG, 465 SURFACE_PIXEL_FORMAT, 1); 466 break; 467 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 468 REG_UPDATE(DCSURF_SURFACE_CONFIG, 469 SURFACE_PIXEL_FORMAT, 3); 470 break; 471 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 472 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 473 REG_UPDATE(DCSURF_SURFACE_CONFIG, 474 SURFACE_PIXEL_FORMAT, 8); 475 break; 476 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 477 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 478 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 479 REG_UPDATE(DCSURF_SURFACE_CONFIG, 480 SURFACE_PIXEL_FORMAT, 10); 481 break; 482 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 483 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ 484 REG_UPDATE(DCSURF_SURFACE_CONFIG, 485 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ 486 break; 487 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 488 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 489 REG_UPDATE(DCSURF_SURFACE_CONFIG, 490 SURFACE_PIXEL_FORMAT, 24); 491 break; 492 493 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 494 REG_UPDATE(DCSURF_SURFACE_CONFIG, 495 SURFACE_PIXEL_FORMAT, 65); 496 break; 497 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 498 REG_UPDATE(DCSURF_SURFACE_CONFIG, 499 SURFACE_PIXEL_FORMAT, 64); 500 break; 501 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 502 REG_UPDATE(DCSURF_SURFACE_CONFIG, 503 SURFACE_PIXEL_FORMAT, 67); 504 break; 505 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 506 REG_UPDATE(DCSURF_SURFACE_CONFIG, 507 SURFACE_PIXEL_FORMAT, 66); 508 break; 509 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 510 REG_UPDATE(DCSURF_SURFACE_CONFIG, 511 SURFACE_PIXEL_FORMAT, 12); 512 break; 513 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 514 REG_UPDATE(DCSURF_SURFACE_CONFIG, 515 SURFACE_PIXEL_FORMAT, 112); 516 break; 517 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 518 REG_UPDATE(DCSURF_SURFACE_CONFIG, 519 SURFACE_PIXEL_FORMAT, 113); 520 break; 521 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 522 REG_UPDATE(DCSURF_SURFACE_CONFIG, 523 SURFACE_PIXEL_FORMAT, 114); 524 break; 525 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 526 REG_UPDATE(DCSURF_SURFACE_CONFIG, 527 SURFACE_PIXEL_FORMAT, 118); 528 break; 529 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 530 REG_UPDATE(DCSURF_SURFACE_CONFIG, 531 SURFACE_PIXEL_FORMAT, 119); 532 break; 533 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 534 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 535 SURFACE_PIXEL_FORMAT, 116, 536 ALPHA_PLANE_EN, 0); 537 break; 538 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 539 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 540 SURFACE_PIXEL_FORMAT, 116, 541 ALPHA_PLANE_EN, 1); 542 break; 543 default: 544 BREAK_TO_DEBUGGER(); 545 break; 546 } 547 548 /* don't see the need of program the xbar in DCN 1.0 */ 549 } 550 551 void hubp2_program_surface_config( 552 struct hubp *hubp, 553 enum surface_pixel_format format, 554 struct dc_tiling_info *tiling_info, 555 struct plane_size *plane_size, 556 enum dc_rotation_angle rotation, 557 struct dc_plane_dcc_param *dcc, 558 bool horizontal_mirror, 559 unsigned int compat_level) 560 { 561 (void)compat_level; 562 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 563 564 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 565 hubp2_program_tiling(hubp2, tiling_info, format); 566 hubp2_program_size(hubp, format, plane_size, dcc); 567 hubp2_program_rotation(hubp, rotation, horizontal_mirror); 568 hubp2_program_pixel_format(hubp, format); 569 } 570 571 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( 572 unsigned int cursor_width, 573 enum dc_cursor_color_format cursor_mode) 574 { 575 enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 576 577 if (cursor_mode == CURSOR_MODE_MONO) 578 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 579 else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND || 580 cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 581 cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { 582 if (cursor_width >= 1 && cursor_width <= 32) 583 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 584 else if (cursor_width >= 33 && cursor_width <= 64) 585 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 586 else if (cursor_width >= 65 && cursor_width <= 128) 587 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 588 else if (cursor_width >= 129 && cursor_width <= 256) 589 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 590 } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED || 591 cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) { 592 if (cursor_width >= 1 && cursor_width <= 16) 593 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 594 else if (cursor_width >= 17 && cursor_width <= 32) 595 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 596 else if (cursor_width >= 33 && cursor_width <= 64) 597 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 598 else if (cursor_width >= 65 && cursor_width <= 128) 599 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 600 else if (cursor_width >= 129 && cursor_width <= 256) 601 line_per_chunk = CURSOR_LINE_PER_CHUNK_1; 602 } 603 604 return line_per_chunk; 605 } 606 607 void hubp2_cursor_set_attributes( 608 struct hubp *hubp, 609 const struct dc_cursor_attributes *attr) 610 { 611 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 612 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 613 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( 614 attr->width, attr->color_format); 615 616 hubp->curs_attr = *attr; 617 618 if (!hubp->cursor_offload) { 619 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 620 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 621 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 622 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 623 624 REG_UPDATE_2(CURSOR_SIZE, 625 CURSOR_WIDTH, attr->width, 626 CURSOR_HEIGHT, attr->height); 627 628 REG_UPDATE_4(CURSOR_CONTROL, 629 CURSOR_MODE, attr->color_format, 630 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, 631 CURSOR_PITCH, hw_pitch, 632 CURSOR_LINES_PER_CHUNK, lpc); 633 634 REG_SET_2(CURSOR_SETTINGS, 0, 635 /* no shift of the cursor HDL schedule */ 636 CURSOR0_DST_Y_OFFSET, 0, 637 /* used to shift the cursor chunk request deadline */ 638 CURSOR0_CHUNK_HDL_ADJUST, 3); 639 } 640 641 hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part; 642 hubp->att.SURFACE_ADDR = attr->address.low_part; 643 hubp->att.size.bits.width = attr->width; 644 hubp->att.size.bits.height = attr->height; 645 hubp->att.cur_ctl.bits.mode = attr->color_format; 646 647 hubp->cur_rect.w = attr->width; 648 hubp->cur_rect.h = attr->height; 649 650 hubp->att.cur_ctl.bits.pitch = hw_pitch; 651 hubp->att.cur_ctl.bits.line_per_chunk = lpc; 652 hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION; 653 hubp->att.settings.bits.dst_y_offset = 0; 654 hubp->att.settings.bits.chunk_hdl_adjust = 3; 655 } 656 657 void hubp2_dmdata_set_attributes( 658 struct hubp *hubp, 659 const struct dc_dmdata_attributes *attr) 660 { 661 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 662 663 if (attr->dmdata_mode == DMDATA_HW_MODE) { 664 /* set to HW mode */ 665 REG_UPDATE(DMDATA_CNTL, 666 DMDATA_MODE, 1); 667 668 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */ 669 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); 670 671 /* toggle DMDATA_UPDATED and set repeat and size */ 672 REG_UPDATE(DMDATA_CNTL, 673 DMDATA_UPDATED, 0); 674 REG_UPDATE_3(DMDATA_CNTL, 675 DMDATA_UPDATED, 1, 676 DMDATA_REPEAT, attr->dmdata_repeat, 677 DMDATA_SIZE, attr->dmdata_size); 678 679 /* set DMDATA address */ 680 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part); 681 REG_UPDATE(DMDATA_ADDRESS_HIGH, 682 DMDATA_ADDRESS_HIGH, attr->address.high_part); 683 684 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); 685 686 } else { 687 /* set to SW mode before loading data */ 688 REG_SET(DMDATA_CNTL, 0, 689 DMDATA_MODE, 0); 690 /* toggle DMDATA_SW_UPDATED to start loading sequence */ 691 REG_UPDATE(DMDATA_SW_CNTL, 692 DMDATA_SW_UPDATED, 0); 693 REG_UPDATE_3(DMDATA_SW_CNTL, 694 DMDATA_SW_UPDATED, 1, 695 DMDATA_SW_REPEAT, attr->dmdata_repeat, 696 DMDATA_SW_SIZE, attr->dmdata_size); 697 /* load data into hubp dmdata buffer */ 698 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data); 699 } 700 701 /* Note that DL_DELTA must be programmed if we want to use TTU mode */ 702 REG_SET_3(DMDATA_QOS_CNTL, 0, 703 DMDATA_QOS_MODE, attr->dmdata_qos_mode, 704 DMDATA_QOS_LEVEL, attr->dmdata_qos_level, 705 DMDATA_DL_DELTA, attr->dmdata_dl_delta); 706 } 707 708 void hubp2_dmdata_load( 709 struct hubp *hubp, 710 uint32_t dmdata_sw_size, 711 const uint32_t *dmdata_sw_data) 712 { 713 int i; 714 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 715 716 /* load dmdata into HUBP buffer in SW mode */ 717 for (i = 0; i < dmdata_sw_size / 4; i++) 718 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]); 719 } 720 721 bool hubp2_dmdata_status_done(struct hubp *hubp) 722 { 723 uint32_t status; 724 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 725 726 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); 727 return (status == 1); 728 } 729 730 bool hubp2_program_surface_flip_and_addr( 731 struct hubp *hubp, 732 const struct dc_plane_address *address, 733 bool flip_immediate) 734 { 735 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 736 737 //program flip type 738 REG_UPDATE(DCSURF_FLIP_CONTROL, 739 SURFACE_FLIP_TYPE, flip_immediate); 740 741 // Program VMID reg 742 REG_UPDATE(VMID_SETTINGS_0, 743 VMID, address->vmid); 744 745 746 /* HW automatically latch rest of address register on write to 747 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 748 * 749 * program high first and then the low addr, order matters! 750 */ 751 switch (address->type) { 752 case PLN_ADDR_TYPE_GRAPHICS: 753 /* DCN1.0 does not support const color 754 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 755 * base on address->grph.dcc_const_color 756 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 757 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 758 */ 759 760 if (address->grph.addr.quad_part == 0) 761 break; 762 763 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 764 PRIMARY_SURFACE_TMZ, address->tmz_surface, 765 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 766 767 if (address->grph.meta_addr.quad_part != 0) { 768 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 769 PRIMARY_META_SURFACE_ADDRESS_HIGH, 770 address->grph.meta_addr.high_part); 771 772 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 773 PRIMARY_META_SURFACE_ADDRESS, 774 address->grph.meta_addr.low_part); 775 } 776 777 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 778 PRIMARY_SURFACE_ADDRESS_HIGH, 779 address->grph.addr.high_part); 780 781 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 782 PRIMARY_SURFACE_ADDRESS, 783 address->grph.addr.low_part); 784 break; 785 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 786 if (address->video_progressive.luma_addr.quad_part == 0 787 || address->video_progressive.chroma_addr.quad_part == 0) 788 break; 789 790 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 791 PRIMARY_SURFACE_TMZ, address->tmz_surface, 792 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 793 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 794 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 795 796 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 797 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 798 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 799 address->video_progressive.chroma_meta_addr.high_part); 800 801 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 802 PRIMARY_META_SURFACE_ADDRESS_C, 803 address->video_progressive.chroma_meta_addr.low_part); 804 805 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 806 PRIMARY_META_SURFACE_ADDRESS_HIGH, 807 address->video_progressive.luma_meta_addr.high_part); 808 809 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 810 PRIMARY_META_SURFACE_ADDRESS, 811 address->video_progressive.luma_meta_addr.low_part); 812 } 813 814 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 815 PRIMARY_SURFACE_ADDRESS_HIGH_C, 816 address->video_progressive.chroma_addr.high_part); 817 818 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 819 PRIMARY_SURFACE_ADDRESS_C, 820 address->video_progressive.chroma_addr.low_part); 821 822 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 823 PRIMARY_SURFACE_ADDRESS_HIGH, 824 address->video_progressive.luma_addr.high_part); 825 826 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 827 PRIMARY_SURFACE_ADDRESS, 828 address->video_progressive.luma_addr.low_part); 829 break; 830 case PLN_ADDR_TYPE_GRPH_STEREO: 831 if (address->grph_stereo.left_addr.quad_part == 0) 832 break; 833 if (address->grph_stereo.right_addr.quad_part == 0) 834 break; 835 836 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 837 PRIMARY_SURFACE_TMZ, address->tmz_surface, 838 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 839 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 840 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 841 SECONDARY_SURFACE_TMZ, address->tmz_surface, 842 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 843 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 844 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 845 846 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 847 848 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 849 SECONDARY_META_SURFACE_ADDRESS_HIGH, 850 address->grph_stereo.right_meta_addr.high_part); 851 852 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 853 SECONDARY_META_SURFACE_ADDRESS, 854 address->grph_stereo.right_meta_addr.low_part); 855 } 856 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 857 858 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 859 PRIMARY_META_SURFACE_ADDRESS_HIGH, 860 address->grph_stereo.left_meta_addr.high_part); 861 862 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 863 PRIMARY_META_SURFACE_ADDRESS, 864 address->grph_stereo.left_meta_addr.low_part); 865 } 866 867 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 868 SECONDARY_SURFACE_ADDRESS_HIGH, 869 address->grph_stereo.right_addr.high_part); 870 871 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 872 SECONDARY_SURFACE_ADDRESS, 873 address->grph_stereo.right_addr.low_part); 874 875 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 876 PRIMARY_SURFACE_ADDRESS_HIGH, 877 address->grph_stereo.left_addr.high_part); 878 879 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 880 PRIMARY_SURFACE_ADDRESS, 881 address->grph_stereo.left_addr.low_part); 882 break; 883 default: 884 BREAK_TO_DEBUGGER(); 885 break; 886 } 887 888 hubp->request_address = *address; 889 890 return true; 891 } 892 893 void hubp2_enable_triplebuffer( 894 struct hubp *hubp, 895 bool enable) 896 { 897 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 898 uint32_t triple_buffer_en = 0; 899 bool tri_buffer_en; 900 901 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 902 tri_buffer_en = (triple_buffer_en == 1); 903 if (tri_buffer_en != enable) { 904 REG_UPDATE(DCSURF_FLIP_CONTROL2, 905 SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE); 906 } 907 } 908 909 bool hubp2_is_triplebuffer_enabled( 910 struct hubp *hubp) 911 { 912 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 913 uint32_t triple_buffer_en = 0; 914 915 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 916 917 return (bool)triple_buffer_en; 918 } 919 920 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable) 921 { 922 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 923 924 REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0); 925 } 926 927 bool hubp2_is_flip_pending(struct hubp *hubp) 928 { 929 uint32_t flip_pending = 0; 930 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 931 struct dc_plane_address earliest_inuse_address; 932 933 if (hubp && hubp->power_gated) 934 return false; 935 936 REG_GET(DCSURF_FLIP_CONTROL, 937 SURFACE_FLIP_PENDING, &flip_pending); 938 939 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 940 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 941 942 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 943 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 944 945 if (flip_pending) 946 return true; 947 948 if (hubp && 949 earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 950 return true; 951 952 return false; 953 } 954 955 void hubp2_set_blank(struct hubp *hubp, bool blank) 956 { 957 hubp2_set_blank_regs(hubp, blank); 958 959 if (blank) { 960 hubp->mpcc_id = 0xf; 961 hubp->opp_id = OPP_ID_INVALID; 962 } 963 } 964 965 void hubp2_set_blank_regs(struct hubp *hubp, bool blank) 966 { 967 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 968 uint32_t blank_en = blank ? 1 : 0; 969 970 if (blank) { 971 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 972 973 if (reg_val) { 974 /* init sequence workaround: in case HUBP is 975 * power gated, this wait would timeout. 976 * 977 * we just wrote reg_val to non-0, if it stay 0 978 * it means HUBP is gated 979 */ 980 REG_WAIT(DCHUBP_CNTL, 981 HUBP_NO_OUTSTANDING_REQ, 1, 982 1, 100000); 983 } 984 } 985 986 REG_UPDATE_2(DCHUBP_CNTL, 987 HUBP_BLANK_EN, blank_en, 988 HUBP_TTU_DISABLE, 0); 989 } 990 991 void hubp2_cursor_set_position( 992 struct hubp *hubp, 993 const struct dc_cursor_position *pos, 994 const struct dc_cursor_mi_param *param) 995 { 996 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 997 int x_pos = pos->x - param->viewport.x; 998 int y_pos = pos->y - param->viewport.y; 999 int x_hotspot = pos->x_hotspot; 1000 int y_hotspot = pos->y_hotspot; 1001 int src_x_offset = x_pos - pos->x_hotspot; 1002 int src_y_offset = y_pos - pos->y_hotspot; 1003 int cursor_height = (int)hubp->curs_attr.height; 1004 int cursor_width = (int)hubp->curs_attr.width; 1005 uint32_t dst_x_offset; 1006 uint32_t cur_en = pos->enable ? 1 : 0; 1007 1008 hubp->curs_pos = *pos; 1009 1010 /* 1011 * Guard aganst cursor_set_position() from being called with invalid 1012 * attributes 1013 * 1014 * TODO: Look at combining cursor_set_position() and 1015 * cursor_set_attributes() into cursor_update() 1016 */ 1017 if (hubp->curs_attr.address.quad_part == 0) 1018 return; 1019 1020 // Transform cursor width / height and hotspots for offset calculations 1021 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 1022 swap(cursor_height, cursor_width); 1023 swap(x_hotspot, y_hotspot); 1024 1025 if (param->rotation == ROTATION_ANGLE_90) { 1026 // hotspot = (-y, x) 1027 src_x_offset = x_pos - (cursor_width - x_hotspot); 1028 src_y_offset = y_pos - y_hotspot; 1029 } else if (param->rotation == ROTATION_ANGLE_270) { 1030 // hotspot = (y, -x) 1031 src_x_offset = x_pos - x_hotspot; 1032 src_y_offset = y_pos - (cursor_height - y_hotspot); 1033 } 1034 } else if (param->rotation == ROTATION_ANGLE_180) { 1035 // hotspot = (-x, -y) 1036 if (!param->mirror) 1037 src_x_offset = x_pos - (cursor_width - x_hotspot); 1038 1039 src_y_offset = y_pos - (cursor_height - y_hotspot); 1040 } 1041 1042 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1043 dst_x_offset *= param->ref_clk_khz; 1044 dst_x_offset /= param->pixel_clk_khz; 1045 1046 ASSERT(param->h_scale_ratio.value); 1047 1048 if (param->h_scale_ratio.value) 1049 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1050 dc_fixpt_from_int(dst_x_offset), 1051 param->h_scale_ratio)); 1052 1053 if (src_x_offset >= (int)param->viewport.width) 1054 cur_en = 0; /* not visible beyond right edge*/ 1055 1056 if (src_x_offset + cursor_width <= 0) 1057 cur_en = 0; /* not visible beyond left edge*/ 1058 1059 if (src_y_offset >= (int)param->viewport.height) 1060 cur_en = 0; /* not visible beyond bottom edge*/ 1061 1062 if (src_y_offset + cursor_height <= 0) 1063 cur_en = 0; /* not visible beyond top edge*/ 1064 1065 if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) { 1066 bool cursor_not_programmed = hubp->att.SURFACE_ADDR == 0 && hubp->att.SURFACE_ADDR_HIGH == 0; 1067 1068 if (cur_en && cursor_not_programmed) 1069 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1070 1071 if (!hubp->cursor_offload) 1072 REG_UPDATE(CURSOR_CONTROL, CURSOR_ENABLE, cur_en); 1073 } 1074 1075 if (!hubp->cursor_offload) { 1076 REG_SET_2(CURSOR_POSITION, 0, 1077 CURSOR_X_POSITION, pos->x, 1078 CURSOR_Y_POSITION, pos->y); 1079 1080 REG_SET_2(CURSOR_HOT_SPOT, 0, 1081 CURSOR_HOT_SPOT_X, pos->x_hotspot, 1082 CURSOR_HOT_SPOT_Y, pos->y_hotspot); 1083 1084 REG_SET(CURSOR_DST_OFFSET, 0, 1085 CURSOR_DST_X_OFFSET, dst_x_offset); 1086 } 1087 1088 /* TODO Handle surface pixel formats other than 4:4:4 */ 1089 /* Cursor Position Register Config */ 1090 hubp->pos.cur_ctl.bits.cur_enable = cur_en; 1091 hubp->pos.position.bits.x_pos = pos->x; 1092 hubp->pos.position.bits.y_pos = pos->y; 1093 hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot; 1094 hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot; 1095 hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset; 1096 /* Cursor Rectangle Cache 1097 * Cursor bitmaps have different hotspot values 1098 * There's a possibility that the above logic returns a negative value, 1099 * so we clamp them to 0 1100 */ 1101 if (src_x_offset < 0) 1102 src_x_offset = 0; 1103 if (src_y_offset < 0) 1104 src_y_offset = 0; 1105 /* Save necessary cursor info x, y position. w, h is saved in attribute func. */ 1106 if (param->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 1107 param->rotation != ROTATION_ANGLE_0) { 1108 hubp->cur_rect.x = 0; 1109 hubp->cur_rect.y = 0; 1110 hubp->cur_rect.w = param->stream->timing.h_addressable; 1111 hubp->cur_rect.h = param->stream->timing.v_addressable; 1112 } else { 1113 hubp->cur_rect.x = src_x_offset + param->viewport.x; 1114 hubp->cur_rect.y = src_y_offset + param->viewport.y; 1115 } 1116 } 1117 1118 void hubp2_clk_cntl(struct hubp *hubp, bool enable) 1119 { 1120 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1121 uint32_t clk_enable = enable ? 1 : 0; 1122 1123 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1124 } 1125 1126 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1127 { 1128 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1129 1130 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1131 } 1132 1133 void hubp2_clear_underflow(struct hubp *hubp) 1134 { 1135 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1136 1137 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 1138 } 1139 1140 void hubp2_read_state_common(struct hubp *hubp) 1141 { 1142 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1143 struct dcn_hubp_state *s = &hubp2->state; 1144 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 1145 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 1146 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1147 1148 /* Requester */ 1149 REG_GET(HUBPRET_CONTROL, 1150 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 1151 REG_GET_4(DCN_EXPANSION_MODE, 1152 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 1153 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 1154 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 1155 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 1156 1157 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 1158 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr); 1159 1160 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 1161 MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr); 1162 1163 /* DLG - Per hubp */ 1164 REG_GET_2(BLANK_OFFSET_0, 1165 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 1166 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 1167 1168 REG_GET(BLANK_OFFSET_1, 1169 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 1170 1171 REG_GET(DST_DIMENSIONS, 1172 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 1173 1174 REG_GET_2(DST_AFTER_SCALER, 1175 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 1176 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 1177 1178 if (REG(PREFETCH_SETTINS)) 1179 REG_GET_2(PREFETCH_SETTINS, 1180 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1181 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1182 else 1183 REG_GET_2(PREFETCH_SETTINGS, 1184 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1185 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1186 1187 REG_GET_2(VBLANK_PARAMETERS_0, 1188 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 1189 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 1190 1191 REG_GET(REF_FREQ_TO_PIX_FREQ, 1192 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 1193 1194 /* DLG - Per luma/chroma */ 1195 REG_GET(VBLANK_PARAMETERS_1, 1196 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 1197 1198 REG_GET(VBLANK_PARAMETERS_3, 1199 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 1200 1201 if (REG(NOM_PARAMETERS_0)) 1202 REG_GET(NOM_PARAMETERS_0, 1203 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 1204 1205 if (REG(NOM_PARAMETERS_1)) 1206 REG_GET(NOM_PARAMETERS_1, 1207 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 1208 1209 REG_GET(NOM_PARAMETERS_4, 1210 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 1211 1212 REG_GET(NOM_PARAMETERS_5, 1213 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 1214 1215 REG_GET_2(PER_LINE_DELIVERY_PRE, 1216 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 1217 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 1218 1219 REG_GET_2(PER_LINE_DELIVERY, 1220 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 1221 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 1222 1223 if (REG(PREFETCH_SETTINS_C)) 1224 REG_GET(PREFETCH_SETTINS_C, 1225 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1226 else 1227 REG_GET(PREFETCH_SETTINGS_C, 1228 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1229 1230 REG_GET(VBLANK_PARAMETERS_2, 1231 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 1232 1233 REG_GET(VBLANK_PARAMETERS_4, 1234 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 1235 1236 if (REG(NOM_PARAMETERS_2)) 1237 REG_GET(NOM_PARAMETERS_2, 1238 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 1239 1240 if (REG(NOM_PARAMETERS_3)) 1241 REG_GET(NOM_PARAMETERS_3, 1242 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 1243 1244 REG_GET(NOM_PARAMETERS_6, 1245 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 1246 1247 REG_GET(NOM_PARAMETERS_7, 1248 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 1249 1250 /* TTU - per hubp */ 1251 REG_GET_2(DCN_TTU_QOS_WM, 1252 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 1253 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 1254 1255 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 1256 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 1257 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 1258 1259 /* TTU - per luma/chroma */ 1260 /* Assumed surf0 is luma and 1 is chroma */ 1261 1262 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1263 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 1264 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 1265 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 1266 1267 REG_GET(DCN_SURF0_TTU_CNTL1, 1268 REFCYC_PER_REQ_DELIVERY_PRE, 1269 &ttu_attr->refcyc_per_req_delivery_pre_l); 1270 1271 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1272 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 1273 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 1274 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 1275 1276 REG_GET(DCN_SURF1_TTU_CNTL1, 1277 REFCYC_PER_REQ_DELIVERY_PRE, 1278 &ttu_attr->refcyc_per_req_delivery_pre_c); 1279 1280 /* Rest of hubp */ 1281 REG_GET(DCSURF_SURFACE_CONFIG, 1282 SURFACE_PIXEL_FORMAT, &s->pixel_format); 1283 1284 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 1285 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 1286 1287 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 1288 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 1289 1290 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 1291 PRI_VIEWPORT_WIDTH, &s->viewport_width, 1292 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 1293 1294 REG_GET_2(DCSURF_SURFACE_CONFIG, 1295 ROTATION_ANGLE, &s->rotation_angle, 1296 H_MIRROR_EN, &s->h_mirror_en); 1297 1298 REG_GET(DCSURF_TILING_CONFIG, 1299 SW_MODE, &s->sw_mode); 1300 1301 REG_GET(DCSURF_SURFACE_CONTROL, 1302 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1303 1304 REG_GET_3(DCHUBP_CNTL, 1305 HUBP_BLANK_EN, &s->blank_en, 1306 HUBP_TTU_DISABLE, &s->ttu_disable, 1307 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1308 1309 REG_GET(HUBP_CLK_CNTL, 1310 HUBP_CLOCK_ENABLE, &s->clock_en); 1311 1312 REG_GET(DCN_GLOBAL_TTU_CNTL, 1313 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1314 1315 REG_GET_2(DCN_TTU_QOS_WM, 1316 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1317 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1318 1319 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, 1320 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); 1321 1322 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 1323 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); 1324 1325 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 1326 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo); 1327 1328 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 1329 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi); 1330 } 1331 1332 void hubp2_read_state(struct hubp *hubp) 1333 { 1334 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1335 struct dcn_hubp_state *s = &hubp2->state; 1336 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1337 1338 hubp2_read_state_common(hubp); 1339 1340 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1341 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1342 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1343 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1344 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1345 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1346 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1347 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1348 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1349 1350 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1351 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1352 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1353 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1354 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1355 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1356 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1357 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1358 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1359 1360 if (REG(DCHUBP_CNTL)) 1361 s->hubp_cntl = REG_READ(DCHUBP_CNTL); 1362 1363 if (REG(DCSURF_FLIP_CONTROL)) 1364 s->flip_control = REG_READ(DCSURF_FLIP_CONTROL); 1365 1366 } 1367 1368 static void hubp2_validate_dml_output(struct hubp *hubp, 1369 struct dc_context *ctx, 1370 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 1371 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 1372 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 1373 { 1374 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1375 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 1376 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 1377 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 1378 DC_LOGGER_INIT(ctx->logger); 1379 DC_LOG_DEBUG("DML Validation | Running Validation"); 1380 1381 /* Requestor Regs */ 1382 REG_GET(HUBPRET_CONTROL, 1383 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 1384 REG_GET_4(DCN_EXPANSION_MODE, 1385 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 1386 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 1387 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 1388 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 1389 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1390 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 1391 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 1392 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 1393 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 1394 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 1395 MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 1396 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 1397 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 1398 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1399 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 1400 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 1401 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 1402 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 1403 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 1404 MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size, 1405 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 1406 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 1407 1408 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 1409 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1410 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 1411 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 1412 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1413 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 1414 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 1415 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1416 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 1417 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 1418 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1419 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 1420 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 1421 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1422 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 1423 1424 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 1425 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 1426 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 1427 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 1428 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 1429 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 1430 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 1431 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1432 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 1433 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 1434 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1435 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 1436 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 1437 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1438 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 1439 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 1440 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1441 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 1442 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 1443 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 1444 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 1445 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 1446 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 1447 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 1448 1449 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 1450 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1451 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 1452 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 1453 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1454 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 1455 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 1456 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1457 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 1458 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 1459 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1460 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 1461 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 1462 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1463 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 1464 if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size) 1465 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1466 dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size); 1467 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 1468 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 1469 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 1470 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 1471 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 1472 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 1473 1474 /* DLG - Per hubp */ 1475 REG_GET_2(BLANK_OFFSET_0, 1476 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 1477 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 1478 REG_GET(BLANK_OFFSET_1, 1479 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 1480 REG_GET(DST_DIMENSIONS, 1481 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 1482 REG_GET_2(DST_AFTER_SCALER, 1483 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 1484 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 1485 REG_GET(REF_FREQ_TO_PIX_FREQ, 1486 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 1487 1488 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 1489 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 1490 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 1491 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 1492 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 1493 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 1494 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 1495 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 1496 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 1497 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 1498 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 1499 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 1500 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 1501 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 1502 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 1503 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 1504 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 1505 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 1506 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 1507 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 1508 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 1509 1510 /* DLG - Per luma/chroma */ 1511 REG_GET(VBLANK_PARAMETERS_1, 1512 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 1513 if (REG(NOM_PARAMETERS_0)) 1514 REG_GET(NOM_PARAMETERS_0, 1515 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 1516 if (REG(NOM_PARAMETERS_1)) 1517 REG_GET(NOM_PARAMETERS_1, 1518 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 1519 REG_GET(NOM_PARAMETERS_4, 1520 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 1521 REG_GET(NOM_PARAMETERS_5, 1522 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 1523 REG_GET_2(PER_LINE_DELIVERY, 1524 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 1525 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 1526 REG_GET_2(PER_LINE_DELIVERY_PRE, 1527 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 1528 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 1529 REG_GET(VBLANK_PARAMETERS_2, 1530 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 1531 if (REG(NOM_PARAMETERS_2)) 1532 REG_GET(NOM_PARAMETERS_2, 1533 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 1534 if (REG(NOM_PARAMETERS_3)) 1535 REG_GET(NOM_PARAMETERS_3, 1536 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 1537 REG_GET(NOM_PARAMETERS_6, 1538 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 1539 REG_GET(NOM_PARAMETERS_7, 1540 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 1541 REG_GET(VBLANK_PARAMETERS_3, 1542 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 1543 REG_GET(VBLANK_PARAMETERS_4, 1544 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 1545 1546 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 1547 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 1548 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 1549 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 1550 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 1551 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 1552 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 1553 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 1554 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 1555 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 1556 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 1557 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 1558 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 1559 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 1560 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 1561 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 1562 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 1563 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 1564 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 1565 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 1566 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 1567 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 1568 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 1569 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 1570 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 1571 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 1572 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 1573 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 1574 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 1575 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 1576 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 1577 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 1578 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 1579 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 1580 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 1581 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 1582 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 1583 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 1584 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 1585 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 1586 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 1587 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 1588 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 1589 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 1590 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 1591 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 1592 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 1593 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 1594 1595 /* TTU - per hubp */ 1596 REG_GET_2(DCN_TTU_QOS_WM, 1597 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 1598 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 1599 1600 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 1601 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 1602 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 1603 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 1604 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 1605 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 1606 1607 /* TTU - per luma/chroma */ 1608 /* Assumed surf0 is luma and 1 is chroma */ 1609 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1610 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 1611 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 1612 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 1613 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1614 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 1615 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 1616 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 1617 REG_GET_3(DCN_CUR0_TTU_CNTL0, 1618 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 1619 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 1620 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 1621 REG_GET(FLIP_PARAMETERS_1, 1622 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 1623 REG_GET(DCN_CUR0_TTU_CNTL1, 1624 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 1625 REG_GET(DCN_CUR1_TTU_CNTL1, 1626 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 1627 REG_GET(DCN_SURF0_TTU_CNTL1, 1628 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 1629 REG_GET(DCN_SURF1_TTU_CNTL1, 1630 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 1631 1632 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 1633 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1634 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 1635 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 1636 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1637 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 1638 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 1639 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1640 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 1641 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 1642 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1643 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 1644 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 1645 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1646 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 1647 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 1648 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1649 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 1650 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 1651 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1652 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 1653 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 1654 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1655 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 1656 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 1657 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1658 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 1659 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 1660 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 1661 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 1662 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 1663 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1664 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 1665 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 1666 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1667 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 1668 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 1669 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1670 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 1671 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 1672 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1673 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 1674 } 1675 1676 static struct hubp_funcs dcn20_hubp_funcs = { 1677 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 1678 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 1679 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 1680 .hubp_program_surface_config = hubp2_program_surface_config, 1681 .hubp_is_flip_pending = hubp2_is_flip_pending, 1682 .hubp_setup = hubp2_setup, 1683 .hubp_setup_interdependent = hubp2_setup_interdependent, 1684 .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings, 1685 .set_blank = hubp2_set_blank, 1686 .set_blank_regs = hubp2_set_blank_regs, 1687 .dcc_control = hubp2_dcc_control, 1688 .hubp_reset = hubp_reset, 1689 .mem_program_viewport = min_set_viewport, 1690 .set_cursor_attributes = hubp2_cursor_set_attributes, 1691 .set_cursor_position = hubp2_cursor_set_position, 1692 .hubp_clk_cntl = hubp2_clk_cntl, 1693 .hubp_vtg_sel = hubp2_vtg_sel, 1694 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 1695 .dmdata_load = hubp2_dmdata_load, 1696 .dmdata_status_done = hubp2_dmdata_status_done, 1697 .hubp_read_state = hubp2_read_state, 1698 .hubp_clear_underflow = hubp2_clear_underflow, 1699 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 1700 .hubp_init = hubp1_init, 1701 .validate_dml_output = hubp2_validate_dml_output, 1702 .hubp_in_blank = hubp1_in_blank, 1703 .hubp_soft_reset = hubp1_soft_reset, 1704 .hubp_set_flip_int = hubp1_set_flip_int, 1705 .hubp_clear_tiling = hubp2_clear_tiling, 1706 }; 1707 1708 1709 bool hubp2_construct( 1710 struct dcn20_hubp *hubp2, 1711 struct dc_context *ctx, 1712 uint32_t inst, 1713 const struct dcn_hubp2_registers *hubp_regs, 1714 const struct dcn_hubp2_shift *hubp_shift, 1715 const struct dcn_hubp2_mask *hubp_mask) 1716 { 1717 hubp2->base.funcs = &dcn20_hubp_funcs; 1718 hubp2->base.ctx = ctx; 1719 hubp2->hubp_regs = hubp_regs; 1720 hubp2->hubp_shift = hubp_shift; 1721 hubp2->hubp_mask = hubp_mask; 1722 hubp2->base.inst = inst; 1723 hubp2->base.opp_id = OPP_ID_INVALID; 1724 hubp2->base.mpcc_id = 0xf; 1725 1726 return true; 1727 } 1728