1 /* 2 * Copyright 2012-2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn20_hubp.h" 27 28 #include "dm_services.h" 29 #include "dce_calcs.h" 30 #include "reg_helper.h" 31 #include "basics/conversion.h" 32 33 #define DC_LOGGER \ 34 ctx->logger 35 #define DC_LOGGER_INIT(logger) 36 37 #define REG(reg)\ 38 hubp2->hubp_regs->reg 39 40 #define CTX \ 41 hubp2->base.ctx 42 43 #undef FN 44 #define FN(reg_name, field_name) \ 45 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 46 47 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, 48 struct vm_system_aperture_param *apt) 49 { 50 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 51 52 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 53 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 54 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 55 56 // The format of default addr is 48:12 of the 48 bit addr 57 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 58 59 // The format of high/low are 48:18 of the 48 bit addr 60 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 61 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 62 63 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 64 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */ 65 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 66 67 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 68 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 69 70 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 71 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 72 73 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 74 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 75 76 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 77 ENABLE_L1_TLB, 1, 78 SYSTEM_ACCESS_MODE, 0x3); 79 } 80 81 void hubp2_program_deadline( 82 struct hubp *hubp, 83 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 84 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 85 { 86 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 87 88 /* DLG - Per hubp */ 89 REG_SET_2(BLANK_OFFSET_0, 0, 90 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 91 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 92 93 REG_SET(BLANK_OFFSET_1, 0, 94 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 95 96 REG_SET(DST_DIMENSIONS, 0, 97 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 98 99 REG_SET_2(DST_AFTER_SCALER, 0, 100 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 101 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 102 103 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 104 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 105 106 /* DLG - Per luma/chroma */ 107 REG_SET(VBLANK_PARAMETERS_1, 0, 108 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 109 110 if (REG(NOM_PARAMETERS_0)) 111 REG_SET(NOM_PARAMETERS_0, 0, 112 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 113 114 if (REG(NOM_PARAMETERS_1)) 115 REG_SET(NOM_PARAMETERS_1, 0, 116 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 117 118 REG_SET(NOM_PARAMETERS_4, 0, 119 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 120 121 REG_SET(NOM_PARAMETERS_5, 0, 122 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 123 124 REG_SET_2(PER_LINE_DELIVERY, 0, 125 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 126 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 127 128 REG_SET(VBLANK_PARAMETERS_2, 0, 129 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 130 131 if (REG(NOM_PARAMETERS_2)) 132 REG_SET(NOM_PARAMETERS_2, 0, 133 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 134 135 if (REG(NOM_PARAMETERS_3)) 136 REG_SET(NOM_PARAMETERS_3, 0, 137 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 138 139 REG_SET(NOM_PARAMETERS_6, 0, 140 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 141 142 REG_SET(NOM_PARAMETERS_7, 0, 143 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 144 145 /* TTU - per hubp */ 146 REG_SET_2(DCN_TTU_QOS_WM, 0, 147 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 148 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 149 150 /* TTU - per luma/chroma */ 151 /* Assumed surf0 is luma and 1 is chroma */ 152 153 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 154 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 155 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 156 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 157 158 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 159 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 160 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 161 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 162 163 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 164 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 165 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 166 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 167 168 REG_SET(FLIP_PARAMETERS_1, 0, 169 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); 170 } 171 172 void hubp2_vready_at_or_After_vsync(struct hubp *hubp, 173 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 174 { 175 uint32_t value = 0; 176 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 177 /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */ 178 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8); 179 /* 180 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) 181 <= OTG_V_BLANK_END 182 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1 183 else 184 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0 185 */ 186 if (pipe_dest->htotal != 0) { 187 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width 188 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 189 value = 1; 190 } else 191 value = 0; 192 } 193 194 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); 195 } 196 197 static void hubp2_program_requestor(struct hubp *hubp, 198 struct _vcs_dpi_display_rq_regs_st *rq_regs) 199 { 200 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 201 202 REG_UPDATE(HUBPRET_CONTROL, 203 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 204 REG_SET_4(DCN_EXPANSION_MODE, 0, 205 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 206 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 207 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 208 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 209 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 210 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 211 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 212 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 213 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 214 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 215 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 216 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 217 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 218 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 219 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 220 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 221 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 222 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 223 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 224 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 225 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 226 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 227 } 228 229 static void hubp2_setup( 230 struct hubp *hubp, 231 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 232 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 233 struct _vcs_dpi_display_rq_regs_st *rq_regs, 234 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 235 { 236 /* otg is locked when this func is called. Register are double buffered. 237 * disable the requestors is not needed 238 */ 239 240 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 241 hubp2_program_requestor(hubp, rq_regs); 242 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 243 244 } 245 246 void hubp2_setup_interdependent( 247 struct hubp *hubp, 248 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 249 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 250 { 251 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 252 253 REG_SET_2(PREFETCH_SETTINGS, 0, 254 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 255 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 256 257 REG_SET(PREFETCH_SETTINGS_C, 0, 258 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 259 260 REG_SET_2(VBLANK_PARAMETERS_0, 0, 261 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 262 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 263 264 REG_SET_2(FLIP_PARAMETERS_0, 0, 265 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip, 266 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip); 267 268 REG_SET(VBLANK_PARAMETERS_3, 0, 269 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 270 271 REG_SET(VBLANK_PARAMETERS_4, 0, 272 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 273 274 REG_SET(FLIP_PARAMETERS_2, 0, 275 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l); 276 277 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 278 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 279 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 280 281 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 282 REFCYC_PER_REQ_DELIVERY_PRE, 283 ttu_attr->refcyc_per_req_delivery_pre_l); 284 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 285 REFCYC_PER_REQ_DELIVERY_PRE, 286 ttu_attr->refcyc_per_req_delivery_pre_c); 287 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 288 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 289 REG_SET(DCN_CUR1_TTU_CNTL1, 0, 290 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1); 291 292 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 293 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 294 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 295 } 296 297 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used: 298 * NUM_BANKS 299 * NUM_SE 300 * NUM_RB_PER_SE 301 * RB_ALIGNED 302 * Other things can be defaulted, since they never change: 303 * PIPE_ALIGNED = 0 304 * META_LINEAR = 0 305 * In GFX10, only these apply: 306 * PIPE_INTERLEAVE 307 * NUM_PIPES 308 * MAX_COMPRESSED_FRAGS 309 * SW_MODE 310 */ 311 static void hubp2_program_tiling( 312 struct dcn20_hubp *hubp2, 313 const struct dc_tiling_info *info, 314 const enum surface_pixel_format pixel_format) 315 { 316 REG_UPDATE_3(DCSURF_ADDR_CONFIG, 317 NUM_PIPES, log_2(info->gfx9.num_pipes), 318 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 319 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 320 321 REG_UPDATE_4(DCSURF_TILING_CONFIG, 322 SW_MODE, info->gfx9.swizzle, 323 META_LINEAR, 0, 324 RB_ALIGNED, 0, 325 PIPE_ALIGNED, 0); 326 } 327 328 void hubp2_program_size( 329 struct hubp *hubp, 330 enum surface_pixel_format format, 331 const struct plane_size *plane_size, 332 struct dc_plane_dcc_param *dcc) 333 { 334 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 335 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 336 bool use_pitch_c = false; 337 338 /* Program data and meta surface pitch (calculation from addrlib) 339 * 444 or 420 luma 340 */ 341 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 342 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END; 343 use_pitch_c = use_pitch_c 344 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); 345 if (use_pitch_c) { 346 ASSERT(plane_size->chroma_pitch != 0); 347 /* Chroma pitch zero can cause system hang! */ 348 349 pitch = plane_size->surface_pitch - 1; 350 meta_pitch = dcc->meta_pitch - 1; 351 pitch_c = plane_size->chroma_pitch - 1; 352 meta_pitch_c = dcc->meta_pitch_c - 1; 353 } else { 354 pitch = plane_size->surface_pitch - 1; 355 meta_pitch = dcc->meta_pitch - 1; 356 pitch_c = 0; 357 meta_pitch_c = 0; 358 } 359 360 if (!dcc->enable) { 361 meta_pitch = 0; 362 meta_pitch_c = 0; 363 } 364 365 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 366 PITCH, pitch, META_PITCH, meta_pitch); 367 368 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN; 369 use_pitch_c = use_pitch_c 370 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); 371 if (use_pitch_c) 372 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 373 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 374 } 375 376 void hubp2_program_rotation( 377 struct hubp *hubp, 378 enum dc_rotation_angle rotation, 379 bool horizontal_mirror) 380 { 381 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 382 uint32_t mirror; 383 384 385 if (horizontal_mirror) 386 mirror = 1; 387 else 388 mirror = 0; 389 390 /* Program rotation angle and horz mirror - no mirror */ 391 if (rotation == ROTATION_ANGLE_0) 392 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 393 ROTATION_ANGLE, 0, 394 H_MIRROR_EN, mirror); 395 else if (rotation == ROTATION_ANGLE_90) 396 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 397 ROTATION_ANGLE, 1, 398 H_MIRROR_EN, mirror); 399 else if (rotation == ROTATION_ANGLE_180) 400 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 401 ROTATION_ANGLE, 2, 402 H_MIRROR_EN, mirror); 403 else if (rotation == ROTATION_ANGLE_270) 404 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 405 ROTATION_ANGLE, 3, 406 H_MIRROR_EN, mirror); 407 } 408 409 void hubp2_clear_tiling(struct hubp *hubp) 410 { 411 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 412 413 REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0); 414 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); 415 416 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 417 PRIMARY_SURFACE_DCC_EN, 0, 418 PRIMARY_SURFACE_DCC_IND_64B_BLK, 0, 419 SECONDARY_SURFACE_DCC_EN, 0, 420 SECONDARY_SURFACE_DCC_IND_64B_BLK, 0); 421 } 422 423 void hubp2_dcc_control(struct hubp *hubp, bool enable, 424 enum hubp_ind_block_size independent_64b_blks) 425 { 426 uint32_t dcc_en = enable ? 1 : 0; 427 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 428 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 429 430 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 431 PRIMARY_SURFACE_DCC_EN, dcc_en, 432 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 433 SECONDARY_SURFACE_DCC_EN, dcc_en, 434 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 435 } 436 437 void hubp2_program_pixel_format( 438 struct hubp *hubp, 439 enum surface_pixel_format format) 440 { 441 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 442 uint32_t red_bar = 3; 443 uint32_t blue_bar = 2; 444 445 /* swap for ABGR format */ 446 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 447 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 448 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 449 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 450 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 451 red_bar = 2; 452 blue_bar = 3; 453 } 454 455 REG_UPDATE_2(HUBPRET_CONTROL, 456 CROSSBAR_SRC_CB_B, blue_bar, 457 CROSSBAR_SRC_CR_R, red_bar); 458 459 /* Mapping is same as ipp programming (cnvc) */ 460 461 switch (format) { 462 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 463 REG_UPDATE(DCSURF_SURFACE_CONFIG, 464 SURFACE_PIXEL_FORMAT, 1); 465 break; 466 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 467 REG_UPDATE(DCSURF_SURFACE_CONFIG, 468 SURFACE_PIXEL_FORMAT, 3); 469 break; 470 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 471 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 472 REG_UPDATE(DCSURF_SURFACE_CONFIG, 473 SURFACE_PIXEL_FORMAT, 8); 474 break; 475 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 476 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 477 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 478 REG_UPDATE(DCSURF_SURFACE_CONFIG, 479 SURFACE_PIXEL_FORMAT, 10); 480 break; 481 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 482 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ 483 REG_UPDATE(DCSURF_SURFACE_CONFIG, 484 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ 485 break; 486 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 487 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 488 REG_UPDATE(DCSURF_SURFACE_CONFIG, 489 SURFACE_PIXEL_FORMAT, 24); 490 break; 491 492 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 493 REG_UPDATE(DCSURF_SURFACE_CONFIG, 494 SURFACE_PIXEL_FORMAT, 65); 495 break; 496 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 497 REG_UPDATE(DCSURF_SURFACE_CONFIG, 498 SURFACE_PIXEL_FORMAT, 64); 499 break; 500 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 501 REG_UPDATE(DCSURF_SURFACE_CONFIG, 502 SURFACE_PIXEL_FORMAT, 67); 503 break; 504 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 505 REG_UPDATE(DCSURF_SURFACE_CONFIG, 506 SURFACE_PIXEL_FORMAT, 66); 507 break; 508 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 509 REG_UPDATE(DCSURF_SURFACE_CONFIG, 510 SURFACE_PIXEL_FORMAT, 12); 511 break; 512 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 513 REG_UPDATE(DCSURF_SURFACE_CONFIG, 514 SURFACE_PIXEL_FORMAT, 112); 515 break; 516 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 517 REG_UPDATE(DCSURF_SURFACE_CONFIG, 518 SURFACE_PIXEL_FORMAT, 113); 519 break; 520 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 521 REG_UPDATE(DCSURF_SURFACE_CONFIG, 522 SURFACE_PIXEL_FORMAT, 114); 523 break; 524 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 525 REG_UPDATE(DCSURF_SURFACE_CONFIG, 526 SURFACE_PIXEL_FORMAT, 118); 527 break; 528 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 529 REG_UPDATE(DCSURF_SURFACE_CONFIG, 530 SURFACE_PIXEL_FORMAT, 119); 531 break; 532 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 533 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 534 SURFACE_PIXEL_FORMAT, 116, 535 ALPHA_PLANE_EN, 0); 536 break; 537 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 538 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 539 SURFACE_PIXEL_FORMAT, 116, 540 ALPHA_PLANE_EN, 1); 541 break; 542 default: 543 BREAK_TO_DEBUGGER(); 544 break; 545 } 546 547 /* don't see the need of program the xbar in DCN 1.0 */ 548 } 549 550 void hubp2_program_surface_config( 551 struct hubp *hubp, 552 enum surface_pixel_format format, 553 struct dc_tiling_info *tiling_info, 554 struct plane_size *plane_size, 555 enum dc_rotation_angle rotation, 556 struct dc_plane_dcc_param *dcc, 557 bool horizontal_mirror, 558 unsigned int compat_level) 559 { 560 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 561 562 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 563 hubp2_program_tiling(hubp2, tiling_info, format); 564 hubp2_program_size(hubp, format, plane_size, dcc); 565 hubp2_program_rotation(hubp, rotation, horizontal_mirror); 566 hubp2_program_pixel_format(hubp, format); 567 } 568 569 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( 570 unsigned int cursor_width, 571 enum dc_cursor_color_format cursor_mode) 572 { 573 enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 574 575 if (cursor_mode == CURSOR_MODE_MONO) 576 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 577 else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND || 578 cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 579 cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { 580 if (cursor_width >= 1 && cursor_width <= 32) 581 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 582 else if (cursor_width >= 33 && cursor_width <= 64) 583 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 584 else if (cursor_width >= 65 && cursor_width <= 128) 585 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 586 else if (cursor_width >= 129 && cursor_width <= 256) 587 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 588 } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED || 589 cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) { 590 if (cursor_width >= 1 && cursor_width <= 16) 591 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 592 else if (cursor_width >= 17 && cursor_width <= 32) 593 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 594 else if (cursor_width >= 33 && cursor_width <= 64) 595 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 596 else if (cursor_width >= 65 && cursor_width <= 128) 597 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 598 else if (cursor_width >= 129 && cursor_width <= 256) 599 line_per_chunk = CURSOR_LINE_PER_CHUNK_1; 600 } 601 602 return line_per_chunk; 603 } 604 605 void hubp2_cursor_set_attributes( 606 struct hubp *hubp, 607 const struct dc_cursor_attributes *attr) 608 { 609 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 610 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 611 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( 612 attr->width, attr->color_format); 613 614 hubp->curs_attr = *attr; 615 616 if (!hubp->cursor_offload) { 617 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 618 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 619 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 620 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 621 622 REG_UPDATE_2(CURSOR_SIZE, 623 CURSOR_WIDTH, attr->width, 624 CURSOR_HEIGHT, attr->height); 625 626 REG_UPDATE_4(CURSOR_CONTROL, 627 CURSOR_MODE, attr->color_format, 628 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, 629 CURSOR_PITCH, hw_pitch, 630 CURSOR_LINES_PER_CHUNK, lpc); 631 632 REG_SET_2(CURSOR_SETTINGS, 0, 633 /* no shift of the cursor HDL schedule */ 634 CURSOR0_DST_Y_OFFSET, 0, 635 /* used to shift the cursor chunk request deadline */ 636 CURSOR0_CHUNK_HDL_ADJUST, 3); 637 } 638 639 hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part; 640 hubp->att.SURFACE_ADDR = attr->address.low_part; 641 hubp->att.size.bits.width = attr->width; 642 hubp->att.size.bits.height = attr->height; 643 hubp->att.cur_ctl.bits.mode = attr->color_format; 644 645 hubp->cur_rect.w = attr->width; 646 hubp->cur_rect.h = attr->height; 647 648 hubp->att.cur_ctl.bits.pitch = hw_pitch; 649 hubp->att.cur_ctl.bits.line_per_chunk = lpc; 650 hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION; 651 hubp->att.settings.bits.dst_y_offset = 0; 652 hubp->att.settings.bits.chunk_hdl_adjust = 3; 653 } 654 655 void hubp2_dmdata_set_attributes( 656 struct hubp *hubp, 657 const struct dc_dmdata_attributes *attr) 658 { 659 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 660 661 if (attr->dmdata_mode == DMDATA_HW_MODE) { 662 /* set to HW mode */ 663 REG_UPDATE(DMDATA_CNTL, 664 DMDATA_MODE, 1); 665 666 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */ 667 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); 668 669 /* toggle DMDATA_UPDATED and set repeat and size */ 670 REG_UPDATE(DMDATA_CNTL, 671 DMDATA_UPDATED, 0); 672 REG_UPDATE_3(DMDATA_CNTL, 673 DMDATA_UPDATED, 1, 674 DMDATA_REPEAT, attr->dmdata_repeat, 675 DMDATA_SIZE, attr->dmdata_size); 676 677 /* set DMDATA address */ 678 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part); 679 REG_UPDATE(DMDATA_ADDRESS_HIGH, 680 DMDATA_ADDRESS_HIGH, attr->address.high_part); 681 682 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); 683 684 } else { 685 /* set to SW mode before loading data */ 686 REG_SET(DMDATA_CNTL, 0, 687 DMDATA_MODE, 0); 688 /* toggle DMDATA_SW_UPDATED to start loading sequence */ 689 REG_UPDATE(DMDATA_SW_CNTL, 690 DMDATA_SW_UPDATED, 0); 691 REG_UPDATE_3(DMDATA_SW_CNTL, 692 DMDATA_SW_UPDATED, 1, 693 DMDATA_SW_REPEAT, attr->dmdata_repeat, 694 DMDATA_SW_SIZE, attr->dmdata_size); 695 /* load data into hubp dmdata buffer */ 696 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data); 697 } 698 699 /* Note that DL_DELTA must be programmed if we want to use TTU mode */ 700 REG_SET_3(DMDATA_QOS_CNTL, 0, 701 DMDATA_QOS_MODE, attr->dmdata_qos_mode, 702 DMDATA_QOS_LEVEL, attr->dmdata_qos_level, 703 DMDATA_DL_DELTA, attr->dmdata_dl_delta); 704 } 705 706 void hubp2_dmdata_load( 707 struct hubp *hubp, 708 uint32_t dmdata_sw_size, 709 const uint32_t *dmdata_sw_data) 710 { 711 int i; 712 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 713 714 /* load dmdata into HUBP buffer in SW mode */ 715 for (i = 0; i < dmdata_sw_size / 4; i++) 716 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]); 717 } 718 719 bool hubp2_dmdata_status_done(struct hubp *hubp) 720 { 721 uint32_t status; 722 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 723 724 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); 725 return (status == 1); 726 } 727 728 bool hubp2_program_surface_flip_and_addr( 729 struct hubp *hubp, 730 const struct dc_plane_address *address, 731 bool flip_immediate) 732 { 733 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 734 735 //program flip type 736 REG_UPDATE(DCSURF_FLIP_CONTROL, 737 SURFACE_FLIP_TYPE, flip_immediate); 738 739 // Program VMID reg 740 REG_UPDATE(VMID_SETTINGS_0, 741 VMID, address->vmid); 742 743 744 /* HW automatically latch rest of address register on write to 745 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 746 * 747 * program high first and then the low addr, order matters! 748 */ 749 switch (address->type) { 750 case PLN_ADDR_TYPE_GRAPHICS: 751 /* DCN1.0 does not support const color 752 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 753 * base on address->grph.dcc_const_color 754 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 755 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 756 */ 757 758 if (address->grph.addr.quad_part == 0) 759 break; 760 761 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 762 PRIMARY_SURFACE_TMZ, address->tmz_surface, 763 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 764 765 if (address->grph.meta_addr.quad_part != 0) { 766 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 767 PRIMARY_META_SURFACE_ADDRESS_HIGH, 768 address->grph.meta_addr.high_part); 769 770 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 771 PRIMARY_META_SURFACE_ADDRESS, 772 address->grph.meta_addr.low_part); 773 } 774 775 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 776 PRIMARY_SURFACE_ADDRESS_HIGH, 777 address->grph.addr.high_part); 778 779 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 780 PRIMARY_SURFACE_ADDRESS, 781 address->grph.addr.low_part); 782 break; 783 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 784 if (address->video_progressive.luma_addr.quad_part == 0 785 || address->video_progressive.chroma_addr.quad_part == 0) 786 break; 787 788 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 789 PRIMARY_SURFACE_TMZ, address->tmz_surface, 790 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 791 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 792 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 793 794 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 795 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 796 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 797 address->video_progressive.chroma_meta_addr.high_part); 798 799 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 800 PRIMARY_META_SURFACE_ADDRESS_C, 801 address->video_progressive.chroma_meta_addr.low_part); 802 803 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 804 PRIMARY_META_SURFACE_ADDRESS_HIGH, 805 address->video_progressive.luma_meta_addr.high_part); 806 807 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 808 PRIMARY_META_SURFACE_ADDRESS, 809 address->video_progressive.luma_meta_addr.low_part); 810 } 811 812 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 813 PRIMARY_SURFACE_ADDRESS_HIGH_C, 814 address->video_progressive.chroma_addr.high_part); 815 816 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 817 PRIMARY_SURFACE_ADDRESS_C, 818 address->video_progressive.chroma_addr.low_part); 819 820 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 821 PRIMARY_SURFACE_ADDRESS_HIGH, 822 address->video_progressive.luma_addr.high_part); 823 824 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 825 PRIMARY_SURFACE_ADDRESS, 826 address->video_progressive.luma_addr.low_part); 827 break; 828 case PLN_ADDR_TYPE_GRPH_STEREO: 829 if (address->grph_stereo.left_addr.quad_part == 0) 830 break; 831 if (address->grph_stereo.right_addr.quad_part == 0) 832 break; 833 834 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 835 PRIMARY_SURFACE_TMZ, address->tmz_surface, 836 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 837 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 838 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 839 SECONDARY_SURFACE_TMZ, address->tmz_surface, 840 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 841 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 842 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 843 844 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 845 846 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 847 SECONDARY_META_SURFACE_ADDRESS_HIGH, 848 address->grph_stereo.right_meta_addr.high_part); 849 850 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 851 SECONDARY_META_SURFACE_ADDRESS, 852 address->grph_stereo.right_meta_addr.low_part); 853 } 854 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 855 856 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 857 PRIMARY_META_SURFACE_ADDRESS_HIGH, 858 address->grph_stereo.left_meta_addr.high_part); 859 860 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 861 PRIMARY_META_SURFACE_ADDRESS, 862 address->grph_stereo.left_meta_addr.low_part); 863 } 864 865 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 866 SECONDARY_SURFACE_ADDRESS_HIGH, 867 address->grph_stereo.right_addr.high_part); 868 869 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 870 SECONDARY_SURFACE_ADDRESS, 871 address->grph_stereo.right_addr.low_part); 872 873 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 874 PRIMARY_SURFACE_ADDRESS_HIGH, 875 address->grph_stereo.left_addr.high_part); 876 877 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 878 PRIMARY_SURFACE_ADDRESS, 879 address->grph_stereo.left_addr.low_part); 880 break; 881 default: 882 BREAK_TO_DEBUGGER(); 883 break; 884 } 885 886 hubp->request_address = *address; 887 888 return true; 889 } 890 891 void hubp2_enable_triplebuffer( 892 struct hubp *hubp, 893 bool enable) 894 { 895 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 896 uint32_t triple_buffer_en = 0; 897 bool tri_buffer_en; 898 899 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 900 tri_buffer_en = (triple_buffer_en == 1); 901 if (tri_buffer_en != enable) { 902 REG_UPDATE(DCSURF_FLIP_CONTROL2, 903 SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE); 904 } 905 } 906 907 bool hubp2_is_triplebuffer_enabled( 908 struct hubp *hubp) 909 { 910 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 911 uint32_t triple_buffer_en = 0; 912 913 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 914 915 return (bool)triple_buffer_en; 916 } 917 918 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable) 919 { 920 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 921 922 REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0); 923 } 924 925 bool hubp2_is_flip_pending(struct hubp *hubp) 926 { 927 uint32_t flip_pending = 0; 928 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 929 struct dc_plane_address earliest_inuse_address; 930 931 if (hubp && hubp->power_gated) 932 return false; 933 934 REG_GET(DCSURF_FLIP_CONTROL, 935 SURFACE_FLIP_PENDING, &flip_pending); 936 937 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 938 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 939 940 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 941 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 942 943 if (flip_pending) 944 return true; 945 946 if (hubp && 947 earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 948 return true; 949 950 return false; 951 } 952 953 void hubp2_set_blank(struct hubp *hubp, bool blank) 954 { 955 hubp2_set_blank_regs(hubp, blank); 956 957 if (blank) { 958 hubp->mpcc_id = 0xf; 959 hubp->opp_id = OPP_ID_INVALID; 960 } 961 } 962 963 void hubp2_set_blank_regs(struct hubp *hubp, bool blank) 964 { 965 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 966 uint32_t blank_en = blank ? 1 : 0; 967 968 if (blank) { 969 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 970 971 if (reg_val) { 972 /* init sequence workaround: in case HUBP is 973 * power gated, this wait would timeout. 974 * 975 * we just wrote reg_val to non-0, if it stay 0 976 * it means HUBP is gated 977 */ 978 REG_WAIT(DCHUBP_CNTL, 979 HUBP_NO_OUTSTANDING_REQ, 1, 980 1, 100000); 981 } 982 } 983 984 REG_UPDATE_2(DCHUBP_CNTL, 985 HUBP_BLANK_EN, blank_en, 986 HUBP_TTU_DISABLE, 0); 987 } 988 989 void hubp2_cursor_set_position( 990 struct hubp *hubp, 991 const struct dc_cursor_position *pos, 992 const struct dc_cursor_mi_param *param) 993 { 994 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 995 int x_pos = pos->x - param->viewport.x; 996 int y_pos = pos->y - param->viewport.y; 997 int x_hotspot = pos->x_hotspot; 998 int y_hotspot = pos->y_hotspot; 999 int src_x_offset = x_pos - pos->x_hotspot; 1000 int src_y_offset = y_pos - pos->y_hotspot; 1001 int cursor_height = (int)hubp->curs_attr.height; 1002 int cursor_width = (int)hubp->curs_attr.width; 1003 uint32_t dst_x_offset; 1004 uint32_t cur_en = pos->enable ? 1 : 0; 1005 1006 hubp->curs_pos = *pos; 1007 1008 /* 1009 * Guard aganst cursor_set_position() from being called with invalid 1010 * attributes 1011 * 1012 * TODO: Look at combining cursor_set_position() and 1013 * cursor_set_attributes() into cursor_update() 1014 */ 1015 if (hubp->curs_attr.address.quad_part == 0) 1016 return; 1017 1018 // Transform cursor width / height and hotspots for offset calculations 1019 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 1020 swap(cursor_height, cursor_width); 1021 swap(x_hotspot, y_hotspot); 1022 1023 if (param->rotation == ROTATION_ANGLE_90) { 1024 // hotspot = (-y, x) 1025 src_x_offset = x_pos - (cursor_width - x_hotspot); 1026 src_y_offset = y_pos - y_hotspot; 1027 } else if (param->rotation == ROTATION_ANGLE_270) { 1028 // hotspot = (y, -x) 1029 src_x_offset = x_pos - x_hotspot; 1030 src_y_offset = y_pos - (cursor_height - y_hotspot); 1031 } 1032 } else if (param->rotation == ROTATION_ANGLE_180) { 1033 // hotspot = (-x, -y) 1034 if (!param->mirror) 1035 src_x_offset = x_pos - (cursor_width - x_hotspot); 1036 1037 src_y_offset = y_pos - (cursor_height - y_hotspot); 1038 } 1039 1040 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1041 dst_x_offset *= param->ref_clk_khz; 1042 dst_x_offset /= param->pixel_clk_khz; 1043 1044 ASSERT(param->h_scale_ratio.value); 1045 1046 if (param->h_scale_ratio.value) 1047 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1048 dc_fixpt_from_int(dst_x_offset), 1049 param->h_scale_ratio)); 1050 1051 if (src_x_offset >= (int)param->viewport.width) 1052 cur_en = 0; /* not visible beyond right edge*/ 1053 1054 if (src_x_offset + cursor_width <= 0) 1055 cur_en = 0; /* not visible beyond left edge*/ 1056 1057 if (src_y_offset >= (int)param->viewport.height) 1058 cur_en = 0; /* not visible beyond bottom edge*/ 1059 1060 if (src_y_offset + cursor_height <= 0) 1061 cur_en = 0; /* not visible beyond top edge*/ 1062 1063 if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) { 1064 bool cursor_not_programmed = hubp->att.SURFACE_ADDR == 0 && hubp->att.SURFACE_ADDR_HIGH == 0; 1065 1066 if (cur_en && cursor_not_programmed) 1067 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1068 1069 if (!hubp->cursor_offload) 1070 REG_UPDATE(CURSOR_CONTROL, CURSOR_ENABLE, cur_en); 1071 } 1072 1073 if (!hubp->cursor_offload) { 1074 REG_SET_2(CURSOR_POSITION, 0, 1075 CURSOR_X_POSITION, pos->x, 1076 CURSOR_Y_POSITION, pos->y); 1077 1078 REG_SET_2(CURSOR_HOT_SPOT, 0, 1079 CURSOR_HOT_SPOT_X, pos->x_hotspot, 1080 CURSOR_HOT_SPOT_Y, pos->y_hotspot); 1081 1082 REG_SET(CURSOR_DST_OFFSET, 0, 1083 CURSOR_DST_X_OFFSET, dst_x_offset); 1084 } 1085 1086 /* TODO Handle surface pixel formats other than 4:4:4 */ 1087 /* Cursor Position Register Config */ 1088 hubp->pos.cur_ctl.bits.cur_enable = cur_en; 1089 hubp->pos.position.bits.x_pos = pos->x; 1090 hubp->pos.position.bits.y_pos = pos->y; 1091 hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot; 1092 hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot; 1093 hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset; 1094 /* Cursor Rectangle Cache 1095 * Cursor bitmaps have different hotspot values 1096 * There's a possibility that the above logic returns a negative value, 1097 * so we clamp them to 0 1098 */ 1099 if (src_x_offset < 0) 1100 src_x_offset = 0; 1101 if (src_y_offset < 0) 1102 src_y_offset = 0; 1103 /* Save necessary cursor info x, y position. w, h is saved in attribute func. */ 1104 if (param->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 1105 param->rotation != ROTATION_ANGLE_0) { 1106 hubp->cur_rect.x = 0; 1107 hubp->cur_rect.y = 0; 1108 hubp->cur_rect.w = param->stream->timing.h_addressable; 1109 hubp->cur_rect.h = param->stream->timing.v_addressable; 1110 } else { 1111 hubp->cur_rect.x = src_x_offset + param->viewport.x; 1112 hubp->cur_rect.y = src_y_offset + param->viewport.y; 1113 } 1114 } 1115 1116 void hubp2_clk_cntl(struct hubp *hubp, bool enable) 1117 { 1118 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1119 uint32_t clk_enable = enable ? 1 : 0; 1120 1121 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1122 } 1123 1124 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1125 { 1126 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1127 1128 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1129 } 1130 1131 void hubp2_clear_underflow(struct hubp *hubp) 1132 { 1133 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1134 1135 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 1136 } 1137 1138 void hubp2_read_state_common(struct hubp *hubp) 1139 { 1140 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1141 struct dcn_hubp_state *s = &hubp2->state; 1142 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 1143 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 1144 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1145 1146 /* Requester */ 1147 REG_GET(HUBPRET_CONTROL, 1148 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 1149 REG_GET_4(DCN_EXPANSION_MODE, 1150 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 1151 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 1152 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 1153 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 1154 1155 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 1156 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr); 1157 1158 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 1159 MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr); 1160 1161 /* DLG - Per hubp */ 1162 REG_GET_2(BLANK_OFFSET_0, 1163 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 1164 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 1165 1166 REG_GET(BLANK_OFFSET_1, 1167 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 1168 1169 REG_GET(DST_DIMENSIONS, 1170 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 1171 1172 REG_GET_2(DST_AFTER_SCALER, 1173 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 1174 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 1175 1176 if (REG(PREFETCH_SETTINS)) 1177 REG_GET_2(PREFETCH_SETTINS, 1178 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1179 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1180 else 1181 REG_GET_2(PREFETCH_SETTINGS, 1182 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1183 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1184 1185 REG_GET_2(VBLANK_PARAMETERS_0, 1186 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 1187 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 1188 1189 REG_GET(REF_FREQ_TO_PIX_FREQ, 1190 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 1191 1192 /* DLG - Per luma/chroma */ 1193 REG_GET(VBLANK_PARAMETERS_1, 1194 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 1195 1196 REG_GET(VBLANK_PARAMETERS_3, 1197 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 1198 1199 if (REG(NOM_PARAMETERS_0)) 1200 REG_GET(NOM_PARAMETERS_0, 1201 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 1202 1203 if (REG(NOM_PARAMETERS_1)) 1204 REG_GET(NOM_PARAMETERS_1, 1205 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 1206 1207 REG_GET(NOM_PARAMETERS_4, 1208 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 1209 1210 REG_GET(NOM_PARAMETERS_5, 1211 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 1212 1213 REG_GET_2(PER_LINE_DELIVERY_PRE, 1214 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 1215 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 1216 1217 REG_GET_2(PER_LINE_DELIVERY, 1218 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 1219 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 1220 1221 if (REG(PREFETCH_SETTINS_C)) 1222 REG_GET(PREFETCH_SETTINS_C, 1223 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1224 else 1225 REG_GET(PREFETCH_SETTINGS_C, 1226 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1227 1228 REG_GET(VBLANK_PARAMETERS_2, 1229 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 1230 1231 REG_GET(VBLANK_PARAMETERS_4, 1232 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 1233 1234 if (REG(NOM_PARAMETERS_2)) 1235 REG_GET(NOM_PARAMETERS_2, 1236 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 1237 1238 if (REG(NOM_PARAMETERS_3)) 1239 REG_GET(NOM_PARAMETERS_3, 1240 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 1241 1242 REG_GET(NOM_PARAMETERS_6, 1243 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 1244 1245 REG_GET(NOM_PARAMETERS_7, 1246 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 1247 1248 /* TTU - per hubp */ 1249 REG_GET_2(DCN_TTU_QOS_WM, 1250 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 1251 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 1252 1253 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 1254 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 1255 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 1256 1257 /* TTU - per luma/chroma */ 1258 /* Assumed surf0 is luma and 1 is chroma */ 1259 1260 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1261 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 1262 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 1263 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 1264 1265 REG_GET(DCN_SURF0_TTU_CNTL1, 1266 REFCYC_PER_REQ_DELIVERY_PRE, 1267 &ttu_attr->refcyc_per_req_delivery_pre_l); 1268 1269 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1270 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 1271 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 1272 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 1273 1274 REG_GET(DCN_SURF1_TTU_CNTL1, 1275 REFCYC_PER_REQ_DELIVERY_PRE, 1276 &ttu_attr->refcyc_per_req_delivery_pre_c); 1277 1278 /* Rest of hubp */ 1279 REG_GET(DCSURF_SURFACE_CONFIG, 1280 SURFACE_PIXEL_FORMAT, &s->pixel_format); 1281 1282 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 1283 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 1284 1285 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 1286 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 1287 1288 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 1289 PRI_VIEWPORT_WIDTH, &s->viewport_width, 1290 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 1291 1292 REG_GET_2(DCSURF_SURFACE_CONFIG, 1293 ROTATION_ANGLE, &s->rotation_angle, 1294 H_MIRROR_EN, &s->h_mirror_en); 1295 1296 REG_GET(DCSURF_TILING_CONFIG, 1297 SW_MODE, &s->sw_mode); 1298 1299 REG_GET(DCSURF_SURFACE_CONTROL, 1300 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1301 1302 REG_GET_3(DCHUBP_CNTL, 1303 HUBP_BLANK_EN, &s->blank_en, 1304 HUBP_TTU_DISABLE, &s->ttu_disable, 1305 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1306 1307 REG_GET(HUBP_CLK_CNTL, 1308 HUBP_CLOCK_ENABLE, &s->clock_en); 1309 1310 REG_GET(DCN_GLOBAL_TTU_CNTL, 1311 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1312 1313 REG_GET_2(DCN_TTU_QOS_WM, 1314 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1315 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1316 1317 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, 1318 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); 1319 1320 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 1321 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); 1322 1323 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 1324 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo); 1325 1326 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 1327 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi); 1328 } 1329 1330 void hubp2_read_state(struct hubp *hubp) 1331 { 1332 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1333 struct dcn_hubp_state *s = &hubp2->state; 1334 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1335 1336 hubp2_read_state_common(hubp); 1337 1338 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1339 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1340 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1341 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1342 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1343 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1344 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1345 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1346 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1347 1348 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1349 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1350 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1351 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1352 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1353 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1354 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1355 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1356 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1357 1358 if (REG(DCHUBP_CNTL)) 1359 s->hubp_cntl = REG_READ(DCHUBP_CNTL); 1360 1361 if (REG(DCSURF_FLIP_CONTROL)) 1362 s->flip_control = REG_READ(DCSURF_FLIP_CONTROL); 1363 1364 } 1365 1366 static void hubp2_validate_dml_output(struct hubp *hubp, 1367 struct dc_context *ctx, 1368 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 1369 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 1370 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 1371 { 1372 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1373 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 1374 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 1375 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 1376 DC_LOGGER_INIT(ctx->logger); 1377 DC_LOG_DEBUG("DML Validation | Running Validation"); 1378 1379 /* Requestor Regs */ 1380 REG_GET(HUBPRET_CONTROL, 1381 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 1382 REG_GET_4(DCN_EXPANSION_MODE, 1383 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 1384 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 1385 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 1386 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 1387 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1388 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 1389 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 1390 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 1391 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 1392 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 1393 MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 1394 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 1395 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 1396 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1397 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 1398 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 1399 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 1400 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 1401 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 1402 MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size, 1403 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 1404 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 1405 1406 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 1407 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1408 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 1409 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 1410 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1411 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 1412 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 1413 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1414 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 1415 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 1416 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1417 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 1418 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 1419 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1420 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 1421 1422 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 1423 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 1424 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 1425 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 1426 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 1427 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 1428 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 1429 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1430 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 1431 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 1432 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1433 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 1434 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 1435 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1436 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 1437 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 1438 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1439 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 1440 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 1441 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 1442 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 1443 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 1444 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 1445 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 1446 1447 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 1448 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1449 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 1450 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 1451 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1452 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 1453 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 1454 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1455 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 1456 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 1457 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1458 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 1459 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 1460 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1461 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 1462 if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size) 1463 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1464 dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size); 1465 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 1466 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 1467 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 1468 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 1469 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 1470 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 1471 1472 /* DLG - Per hubp */ 1473 REG_GET_2(BLANK_OFFSET_0, 1474 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 1475 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 1476 REG_GET(BLANK_OFFSET_1, 1477 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 1478 REG_GET(DST_DIMENSIONS, 1479 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 1480 REG_GET_2(DST_AFTER_SCALER, 1481 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 1482 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 1483 REG_GET(REF_FREQ_TO_PIX_FREQ, 1484 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 1485 1486 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 1487 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 1488 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 1489 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 1490 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 1491 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 1492 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 1493 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 1494 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 1495 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 1496 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 1497 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 1498 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 1499 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 1500 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 1501 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 1502 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 1503 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 1504 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 1505 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 1506 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 1507 1508 /* DLG - Per luma/chroma */ 1509 REG_GET(VBLANK_PARAMETERS_1, 1510 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 1511 if (REG(NOM_PARAMETERS_0)) 1512 REG_GET(NOM_PARAMETERS_0, 1513 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 1514 if (REG(NOM_PARAMETERS_1)) 1515 REG_GET(NOM_PARAMETERS_1, 1516 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 1517 REG_GET(NOM_PARAMETERS_4, 1518 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 1519 REG_GET(NOM_PARAMETERS_5, 1520 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 1521 REG_GET_2(PER_LINE_DELIVERY, 1522 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 1523 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 1524 REG_GET_2(PER_LINE_DELIVERY_PRE, 1525 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 1526 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 1527 REG_GET(VBLANK_PARAMETERS_2, 1528 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 1529 if (REG(NOM_PARAMETERS_2)) 1530 REG_GET(NOM_PARAMETERS_2, 1531 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 1532 if (REG(NOM_PARAMETERS_3)) 1533 REG_GET(NOM_PARAMETERS_3, 1534 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 1535 REG_GET(NOM_PARAMETERS_6, 1536 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 1537 REG_GET(NOM_PARAMETERS_7, 1538 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 1539 REG_GET(VBLANK_PARAMETERS_3, 1540 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 1541 REG_GET(VBLANK_PARAMETERS_4, 1542 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 1543 1544 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 1545 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 1546 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 1547 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 1548 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 1549 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 1550 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 1551 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 1552 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 1553 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 1554 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 1555 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 1556 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 1557 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 1558 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 1559 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 1560 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 1561 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 1562 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 1563 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 1564 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 1565 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 1566 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 1567 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 1568 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 1569 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 1570 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 1571 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 1572 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 1573 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 1574 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 1575 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 1576 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 1577 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 1578 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 1579 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 1580 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 1581 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 1582 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 1583 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 1584 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 1585 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 1586 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 1587 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 1588 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 1589 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 1590 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 1591 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 1592 1593 /* TTU - per hubp */ 1594 REG_GET_2(DCN_TTU_QOS_WM, 1595 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 1596 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 1597 1598 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 1599 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 1600 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 1601 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 1602 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 1603 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 1604 1605 /* TTU - per luma/chroma */ 1606 /* Assumed surf0 is luma and 1 is chroma */ 1607 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1608 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 1609 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 1610 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 1611 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1612 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 1613 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 1614 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 1615 REG_GET_3(DCN_CUR0_TTU_CNTL0, 1616 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 1617 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 1618 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 1619 REG_GET(FLIP_PARAMETERS_1, 1620 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 1621 REG_GET(DCN_CUR0_TTU_CNTL1, 1622 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 1623 REG_GET(DCN_CUR1_TTU_CNTL1, 1624 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 1625 REG_GET(DCN_SURF0_TTU_CNTL1, 1626 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 1627 REG_GET(DCN_SURF1_TTU_CNTL1, 1628 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 1629 1630 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 1631 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1632 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 1633 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 1634 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1635 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 1636 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 1637 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1638 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 1639 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 1640 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1641 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 1642 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 1643 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1644 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 1645 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 1646 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1647 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 1648 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 1649 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1650 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 1651 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 1652 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1653 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 1654 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 1655 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1656 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 1657 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 1658 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 1659 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 1660 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 1661 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1662 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 1663 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 1664 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1665 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 1666 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 1667 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1668 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 1669 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 1670 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1671 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 1672 } 1673 1674 static struct hubp_funcs dcn20_hubp_funcs = { 1675 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 1676 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 1677 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 1678 .hubp_program_surface_config = hubp2_program_surface_config, 1679 .hubp_is_flip_pending = hubp2_is_flip_pending, 1680 .hubp_setup = hubp2_setup, 1681 .hubp_setup_interdependent = hubp2_setup_interdependent, 1682 .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings, 1683 .set_blank = hubp2_set_blank, 1684 .set_blank_regs = hubp2_set_blank_regs, 1685 .dcc_control = hubp2_dcc_control, 1686 .hubp_reset = hubp_reset, 1687 .mem_program_viewport = min_set_viewport, 1688 .set_cursor_attributes = hubp2_cursor_set_attributes, 1689 .set_cursor_position = hubp2_cursor_set_position, 1690 .hubp_clk_cntl = hubp2_clk_cntl, 1691 .hubp_vtg_sel = hubp2_vtg_sel, 1692 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 1693 .dmdata_load = hubp2_dmdata_load, 1694 .dmdata_status_done = hubp2_dmdata_status_done, 1695 .hubp_read_state = hubp2_read_state, 1696 .hubp_clear_underflow = hubp2_clear_underflow, 1697 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 1698 .hubp_init = hubp1_init, 1699 .validate_dml_output = hubp2_validate_dml_output, 1700 .hubp_in_blank = hubp1_in_blank, 1701 .hubp_soft_reset = hubp1_soft_reset, 1702 .hubp_set_flip_int = hubp1_set_flip_int, 1703 .hubp_clear_tiling = hubp2_clear_tiling, 1704 }; 1705 1706 1707 bool hubp2_construct( 1708 struct dcn20_hubp *hubp2, 1709 struct dc_context *ctx, 1710 uint32_t inst, 1711 const struct dcn_hubp2_registers *hubp_regs, 1712 const struct dcn_hubp2_shift *hubp_shift, 1713 const struct dcn_hubp2_mask *hubp_mask) 1714 { 1715 hubp2->base.funcs = &dcn20_hubp_funcs; 1716 hubp2->base.ctx = ctx; 1717 hubp2->hubp_regs = hubp_regs; 1718 hubp2->hubp_shift = hubp_shift; 1719 hubp2->hubp_mask = hubp_mask; 1720 hubp2->base.inst = inst; 1721 hubp2->base.opp_id = OPP_ID_INVALID; 1722 hubp2->base.mpcc_id = 0xf; 1723 1724 return true; 1725 } 1726