1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 #include "dce_calcs.h" 27 #include "reg_helper.h" 28 #include "basics/conversion.h" 29 #include "dcn10_hubp.h" 30 31 #define REG(reg)\ 32 hubp1->hubp_regs->reg 33 34 #define CTX \ 35 hubp1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name 40 41 void hubp1_set_blank(struct hubp *hubp, bool blank) 42 { 43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 44 uint32_t blank_en = blank ? 1 : 0; 45 46 REG_UPDATE_2(DCHUBP_CNTL, 47 HUBP_BLANK_EN, blank_en, 48 HUBP_TTU_DISABLE, blank_en); 49 50 if (blank) { 51 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 52 53 if (reg_val) { 54 /* init sequence workaround: in case HUBP is 55 * power gated, this wait would timeout. 56 * 57 * we just wrote reg_val to non-0, if it stay 0 58 * it means HUBP is gated 59 */ 60 REG_WAIT(DCHUBP_CNTL, 61 HUBP_NO_OUTSTANDING_REQ, 1, 62 1, 200); 63 } 64 65 hubp->mpcc_id = 0xf; 66 hubp->opp_id = OPP_ID_INVALID; 67 } 68 } 69 70 static void hubp1_disconnect(struct hubp *hubp) 71 { 72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 73 74 REG_UPDATE(DCHUBP_CNTL, 75 HUBP_TTU_DISABLE, 1); 76 77 REG_UPDATE(CURSOR_CONTROL, 78 CURSOR_ENABLE, 0); 79 } 80 81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) 82 { 83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 84 uint32_t disable = disable_hubp ? 1 : 0; 85 86 REG_UPDATE(DCHUBP_CNTL, 87 HUBP_DISABLE, disable); 88 } 89 90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp) 91 { 92 uint32_t hubp_underflow = 0; 93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 94 95 REG_GET(DCHUBP_CNTL, 96 HUBP_UNDERFLOW_STATUS, 97 &hubp_underflow); 98 99 return hubp_underflow; 100 } 101 102 103 void hubp1_clear_underflow(struct hubp *hubp) 104 { 105 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 106 107 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 108 } 109 110 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) 111 { 112 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 113 uint32_t blank_en = blank ? 1 : 0; 114 115 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); 116 } 117 118 void hubp1_vready_workaround(struct hubp *hubp, 119 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 120 { 121 uint32_t value = 0; 122 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 123 124 /* set HBUBREQ_DEBUG_DB[12] = 1 */ 125 value = REG_READ(HUBPREQ_DEBUG_DB); 126 127 /* hack mode disable */ 128 value |= 0x100; 129 value &= ~0x1000; 130 131 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width 132 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 133 /* if (eco_fix_needed(otg_global_sync_timing) 134 * set HBUBREQ_DEBUG_DB[12] = 1 */ 135 value |= 0x1000; 136 } 137 138 REG_WRITE(HUBPREQ_DEBUG_DB, value); 139 } 140 141 void hubp1_program_tiling( 142 struct hubp *hubp, 143 const struct dc_tiling_info *info, 144 const enum surface_pixel_format pixel_format) 145 { 146 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 147 148 REG_UPDATE_6(DCSURF_ADDR_CONFIG, 149 NUM_PIPES, log_2(info->gfx9.num_pipes), 150 NUM_BANKS, log_2(info->gfx9.num_banks), 151 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 152 NUM_SE, log_2(info->gfx9.num_shader_engines), 153 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), 154 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 155 156 REG_UPDATE_4(DCSURF_TILING_CONFIG, 157 SW_MODE, info->gfx9.swizzle, 158 META_LINEAR, info->gfx9.meta_linear, 159 RB_ALIGNED, info->gfx9.rb_aligned, 160 PIPE_ALIGNED, info->gfx9.pipe_aligned); 161 } 162 163 void hubp1_program_size( 164 struct hubp *hubp, 165 enum surface_pixel_format format, 166 const struct plane_size *plane_size, 167 struct dc_plane_dcc_param *dcc) 168 { 169 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 170 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 171 172 /* Program data and meta surface pitch (calculation from addrlib) 173 * 444 or 420 luma 174 */ 175 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { 176 ASSERT(plane_size->chroma_pitch != 0); 177 /* Chroma pitch zero can cause system hang! */ 178 179 pitch = plane_size->surface_pitch - 1; 180 meta_pitch = dcc->meta_pitch - 1; 181 pitch_c = plane_size->chroma_pitch - 1; 182 meta_pitch_c = dcc->meta_pitch_c - 1; 183 } else { 184 pitch = plane_size->surface_pitch - 1; 185 meta_pitch = dcc->meta_pitch - 1; 186 pitch_c = 0; 187 meta_pitch_c = 0; 188 } 189 190 if (!dcc->enable) { 191 meta_pitch = 0; 192 meta_pitch_c = 0; 193 } 194 195 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 196 PITCH, pitch, META_PITCH, meta_pitch); 197 198 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 199 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 200 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 201 } 202 203 void hubp1_program_rotation( 204 struct hubp *hubp, 205 enum dc_rotation_angle rotation, 206 bool horizontal_mirror) 207 { 208 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 209 uint32_t mirror; 210 211 212 if (horizontal_mirror) 213 mirror = 1; 214 else 215 mirror = 0; 216 217 /* Program rotation angle and horz mirror - no mirror */ 218 if (rotation == ROTATION_ANGLE_0) 219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 220 ROTATION_ANGLE, 0, 221 H_MIRROR_EN, mirror); 222 else if (rotation == ROTATION_ANGLE_90) 223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 224 ROTATION_ANGLE, 1, 225 H_MIRROR_EN, mirror); 226 else if (rotation == ROTATION_ANGLE_180) 227 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 228 ROTATION_ANGLE, 2, 229 H_MIRROR_EN, mirror); 230 else if (rotation == ROTATION_ANGLE_270) 231 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 232 ROTATION_ANGLE, 3, 233 H_MIRROR_EN, mirror); 234 } 235 236 void hubp1_program_pixel_format( 237 struct hubp *hubp, 238 enum surface_pixel_format format) 239 { 240 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 241 uint32_t red_bar = 3; 242 uint32_t blue_bar = 2; 243 244 /* swap for ABGR format */ 245 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 246 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 247 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 248 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 249 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 250 red_bar = 2; 251 blue_bar = 3; 252 } 253 254 REG_UPDATE_2(HUBPRET_CONTROL, 255 CROSSBAR_SRC_CB_B, blue_bar, 256 CROSSBAR_SRC_CR_R, red_bar); 257 258 /* Mapping is same as ipp programming (cnvc) */ 259 260 switch (format) { 261 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 262 REG_UPDATE(DCSURF_SURFACE_CONFIG, 263 SURFACE_PIXEL_FORMAT, 1); 264 break; 265 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 266 REG_UPDATE(DCSURF_SURFACE_CONFIG, 267 SURFACE_PIXEL_FORMAT, 3); 268 break; 269 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 270 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 271 REG_UPDATE(DCSURF_SURFACE_CONFIG, 272 SURFACE_PIXEL_FORMAT, 8); 273 break; 274 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 275 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 276 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 277 REG_UPDATE(DCSURF_SURFACE_CONFIG, 278 SURFACE_PIXEL_FORMAT, 10); 279 break; 280 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 281 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ 282 REG_UPDATE(DCSURF_SURFACE_CONFIG, 283 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ 284 break; 285 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 286 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 287 REG_UPDATE(DCSURF_SURFACE_CONFIG, 288 SURFACE_PIXEL_FORMAT, 24); 289 break; 290 291 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 292 REG_UPDATE(DCSURF_SURFACE_CONFIG, 293 SURFACE_PIXEL_FORMAT, 65); 294 break; 295 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 296 REG_UPDATE(DCSURF_SURFACE_CONFIG, 297 SURFACE_PIXEL_FORMAT, 64); 298 break; 299 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 300 REG_UPDATE(DCSURF_SURFACE_CONFIG, 301 SURFACE_PIXEL_FORMAT, 67); 302 break; 303 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 304 REG_UPDATE(DCSURF_SURFACE_CONFIG, 305 SURFACE_PIXEL_FORMAT, 66); 306 break; 307 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 308 REG_UPDATE(DCSURF_SURFACE_CONFIG, 309 SURFACE_PIXEL_FORMAT, 12); 310 break; 311 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 312 REG_UPDATE(DCSURF_SURFACE_CONFIG, 313 SURFACE_PIXEL_FORMAT, 112); 314 break; 315 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 316 REG_UPDATE(DCSURF_SURFACE_CONFIG, 317 SURFACE_PIXEL_FORMAT, 113); 318 break; 319 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 320 REG_UPDATE(DCSURF_SURFACE_CONFIG, 321 SURFACE_PIXEL_FORMAT, 114); 322 break; 323 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 324 REG_UPDATE(DCSURF_SURFACE_CONFIG, 325 SURFACE_PIXEL_FORMAT, 118); 326 break; 327 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 328 REG_UPDATE(DCSURF_SURFACE_CONFIG, 329 SURFACE_PIXEL_FORMAT, 119); 330 break; 331 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 332 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 333 SURFACE_PIXEL_FORMAT, 116, 334 ALPHA_PLANE_EN, 0); 335 break; 336 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 337 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 338 SURFACE_PIXEL_FORMAT, 116, 339 ALPHA_PLANE_EN, 1); 340 break; 341 default: 342 BREAK_TO_DEBUGGER(); 343 break; 344 } 345 346 /* don't see the need of program the xbar in DCN 1.0 */ 347 } 348 349 bool hubp1_program_surface_flip_and_addr( 350 struct hubp *hubp, 351 const struct dc_plane_address *address, 352 bool flip_immediate) 353 { 354 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 355 356 357 //program flip type 358 REG_UPDATE(DCSURF_FLIP_CONTROL, 359 SURFACE_FLIP_TYPE, flip_immediate); 360 361 362 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 363 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 364 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 365 366 } else { 367 // turn off stereo if not in stereo 368 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 369 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 370 } 371 372 373 374 /* HW automatically latch rest of address register on write to 375 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 376 * 377 * program high first and then the low addr, order matters! 378 */ 379 switch (address->type) { 380 case PLN_ADDR_TYPE_GRAPHICS: 381 /* DCN1.0 does not support const color 382 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 383 * base on address->grph.dcc_const_color 384 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 385 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 386 */ 387 388 if (address->grph.addr.quad_part == 0) 389 break; 390 391 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 392 PRIMARY_SURFACE_TMZ, address->tmz_surface, 393 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 394 395 if (address->grph.meta_addr.quad_part != 0) { 396 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 397 PRIMARY_META_SURFACE_ADDRESS_HIGH, 398 address->grph.meta_addr.high_part); 399 400 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 401 PRIMARY_META_SURFACE_ADDRESS, 402 address->grph.meta_addr.low_part); 403 } 404 405 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 406 PRIMARY_SURFACE_ADDRESS_HIGH, 407 address->grph.addr.high_part); 408 409 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 410 PRIMARY_SURFACE_ADDRESS, 411 address->grph.addr.low_part); 412 break; 413 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 414 if (address->video_progressive.luma_addr.quad_part == 0 415 || address->video_progressive.chroma_addr.quad_part == 0) 416 break; 417 418 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 419 PRIMARY_SURFACE_TMZ, address->tmz_surface, 420 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 421 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 422 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 423 424 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 425 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 426 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 427 address->video_progressive.chroma_meta_addr.high_part); 428 429 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 430 PRIMARY_META_SURFACE_ADDRESS_C, 431 address->video_progressive.chroma_meta_addr.low_part); 432 433 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 434 PRIMARY_META_SURFACE_ADDRESS_HIGH, 435 address->video_progressive.luma_meta_addr.high_part); 436 437 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 438 PRIMARY_META_SURFACE_ADDRESS, 439 address->video_progressive.luma_meta_addr.low_part); 440 } 441 442 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 443 PRIMARY_SURFACE_ADDRESS_HIGH_C, 444 address->video_progressive.chroma_addr.high_part); 445 446 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 447 PRIMARY_SURFACE_ADDRESS_C, 448 address->video_progressive.chroma_addr.low_part); 449 450 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 451 PRIMARY_SURFACE_ADDRESS_HIGH, 452 address->video_progressive.luma_addr.high_part); 453 454 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 455 PRIMARY_SURFACE_ADDRESS, 456 address->video_progressive.luma_addr.low_part); 457 break; 458 case PLN_ADDR_TYPE_GRPH_STEREO: 459 if (address->grph_stereo.left_addr.quad_part == 0) 460 break; 461 if (address->grph_stereo.right_addr.quad_part == 0) 462 break; 463 464 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 465 PRIMARY_SURFACE_TMZ, address->tmz_surface, 466 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 467 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 468 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 469 SECONDARY_SURFACE_TMZ, address->tmz_surface, 470 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 471 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 472 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 473 474 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 475 476 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 477 SECONDARY_META_SURFACE_ADDRESS_HIGH, 478 address->grph_stereo.right_meta_addr.high_part); 479 480 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 481 SECONDARY_META_SURFACE_ADDRESS, 482 address->grph_stereo.right_meta_addr.low_part); 483 } 484 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 485 486 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 487 PRIMARY_META_SURFACE_ADDRESS_HIGH, 488 address->grph_stereo.left_meta_addr.high_part); 489 490 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 491 PRIMARY_META_SURFACE_ADDRESS, 492 address->grph_stereo.left_meta_addr.low_part); 493 } 494 495 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 496 SECONDARY_SURFACE_ADDRESS_HIGH, 497 address->grph_stereo.right_addr.high_part); 498 499 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 500 SECONDARY_SURFACE_ADDRESS, 501 address->grph_stereo.right_addr.low_part); 502 503 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 504 PRIMARY_SURFACE_ADDRESS_HIGH, 505 address->grph_stereo.left_addr.high_part); 506 507 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 508 PRIMARY_SURFACE_ADDRESS, 509 address->grph_stereo.left_addr.low_part); 510 break; 511 default: 512 BREAK_TO_DEBUGGER(); 513 break; 514 } 515 516 hubp->request_address = *address; 517 518 return true; 519 } 520 521 void hubp1_clear_tiling(struct hubp *hubp) 522 { 523 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 524 525 REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0); 526 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); 527 528 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 529 PRIMARY_SURFACE_DCC_EN, 0, 530 PRIMARY_SURFACE_DCC_IND_64B_BLK, 0, 531 SECONDARY_SURFACE_DCC_EN, 0, 532 SECONDARY_SURFACE_DCC_IND_64B_BLK, 0); 533 } 534 535 void hubp1_dcc_control(struct hubp *hubp, bool enable, 536 enum hubp_ind_block_size independent_64b_blks) 537 { 538 uint32_t dcc_en = enable ? 1 : 0; 539 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 540 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 541 542 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 543 PRIMARY_SURFACE_DCC_EN, dcc_en, 544 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 545 SECONDARY_SURFACE_DCC_EN, dcc_en, 546 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 547 } 548 549 void hubp_reset(struct hubp *hubp) 550 { 551 memset(&hubp->pos, 0, sizeof(hubp->pos)); 552 memset(&hubp->att, 0, sizeof(hubp->att)); 553 hubp->cursor_offload = false; 554 } 555 556 void hubp1_program_surface_config( 557 struct hubp *hubp, 558 enum surface_pixel_format format, 559 struct dc_tiling_info *tiling_info, 560 struct plane_size *plane_size, 561 enum dc_rotation_angle rotation, 562 struct dc_plane_dcc_param *dcc, 563 bool horizontal_mirror, 564 unsigned int compat_level) 565 { 566 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 567 hubp1_program_tiling(hubp, tiling_info, format); 568 hubp1_program_size(hubp, format, plane_size, dcc); 569 hubp1_program_rotation(hubp, rotation, horizontal_mirror); 570 hubp1_program_pixel_format(hubp, format); 571 } 572 573 void hubp1_program_requestor( 574 struct hubp *hubp, 575 struct _vcs_dpi_display_rq_regs_st *rq_regs) 576 { 577 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 578 579 REG_UPDATE(HUBPRET_CONTROL, 580 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 581 REG_SET_4(DCN_EXPANSION_MODE, 0, 582 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 583 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 584 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 585 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 586 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 587 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 588 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 589 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 590 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 591 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 592 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 593 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 594 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 595 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 596 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 597 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 598 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 599 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 600 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 601 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 602 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 603 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 604 } 605 606 607 void hubp1_program_deadline( 608 struct hubp *hubp, 609 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 610 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 611 { 612 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 613 614 /* DLG - Per hubp */ 615 REG_SET_2(BLANK_OFFSET_0, 0, 616 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 617 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 618 619 REG_SET(BLANK_OFFSET_1, 0, 620 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 621 622 REG_SET(DST_DIMENSIONS, 0, 623 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 624 625 REG_SET_2(DST_AFTER_SCALER, 0, 626 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 627 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 628 629 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 630 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 631 632 /* DLG - Per luma/chroma */ 633 REG_SET(VBLANK_PARAMETERS_1, 0, 634 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 635 636 if (REG(NOM_PARAMETERS_0)) 637 REG_SET(NOM_PARAMETERS_0, 0, 638 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 639 640 if (REG(NOM_PARAMETERS_1)) 641 REG_SET(NOM_PARAMETERS_1, 0, 642 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 643 644 REG_SET(NOM_PARAMETERS_4, 0, 645 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 646 647 REG_SET(NOM_PARAMETERS_5, 0, 648 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 649 650 REG_SET_2(PER_LINE_DELIVERY, 0, 651 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 652 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 653 654 REG_SET(VBLANK_PARAMETERS_2, 0, 655 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 656 657 if (REG(NOM_PARAMETERS_2)) 658 REG_SET(NOM_PARAMETERS_2, 0, 659 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 660 661 if (REG(NOM_PARAMETERS_3)) 662 REG_SET(NOM_PARAMETERS_3, 0, 663 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 664 665 REG_SET(NOM_PARAMETERS_6, 0, 666 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 667 668 REG_SET(NOM_PARAMETERS_7, 0, 669 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 670 671 /* TTU - per hubp */ 672 REG_SET_2(DCN_TTU_QOS_WM, 0, 673 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 674 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 675 676 /* TTU - per luma/chroma */ 677 /* Assumed surf0 is luma and 1 is chroma */ 678 679 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 680 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 681 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 682 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 683 684 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 685 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 686 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 687 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 688 689 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 690 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 691 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 692 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 693 } 694 695 static void hubp1_setup( 696 struct hubp *hubp, 697 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 698 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 699 struct _vcs_dpi_display_rq_regs_st *rq_regs, 700 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 701 { 702 /* otg is locked when this func is called. Register are double buffered. 703 * disable the requestors is not needed 704 */ 705 hubp1_program_requestor(hubp, rq_regs); 706 hubp1_program_deadline(hubp, dlg_attr, ttu_attr); 707 hubp1_vready_workaround(hubp, pipe_dest); 708 } 709 710 static void hubp1_setup_interdependent( 711 struct hubp *hubp, 712 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 713 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 714 { 715 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 716 717 REG_SET_2(PREFETCH_SETTINS, 0, 718 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 719 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 720 721 REG_SET(PREFETCH_SETTINS_C, 0, 722 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 723 724 REG_SET_2(VBLANK_PARAMETERS_0, 0, 725 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 726 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 727 728 REG_SET(VBLANK_PARAMETERS_3, 0, 729 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 730 731 REG_SET(VBLANK_PARAMETERS_4, 0, 732 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 733 734 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 735 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 736 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 737 738 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 739 REFCYC_PER_REQ_DELIVERY_PRE, 740 ttu_attr->refcyc_per_req_delivery_pre_l); 741 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 742 REFCYC_PER_REQ_DELIVERY_PRE, 743 ttu_attr->refcyc_per_req_delivery_pre_c); 744 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 745 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 746 747 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 748 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 749 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 750 } 751 752 bool hubp1_is_flip_pending(struct hubp *hubp) 753 { 754 uint32_t flip_pending = 0; 755 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 756 struct dc_plane_address earliest_inuse_address; 757 758 if (hubp && hubp->power_gated) 759 return false; 760 761 REG_GET(DCSURF_FLIP_CONTROL, 762 SURFACE_FLIP_PENDING, &flip_pending); 763 764 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 765 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 766 767 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 768 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 769 770 if (flip_pending) 771 return true; 772 773 if (hubp && 774 earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 775 return true; 776 777 return false; 778 } 779 780 static uint32_t aperture_default_system = 1; 781 static uint32_t context0_default_system; /* = 0;*/ 782 783 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, 784 struct vm_system_aperture_param *apt) 785 { 786 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 787 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 788 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 789 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 790 791 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 792 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; 793 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; 794 795 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 796 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ 797 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 798 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 799 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 800 801 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 802 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); 803 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 804 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); 805 806 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 807 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); 808 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 809 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); 810 } 811 812 static void hubp1_set_vm_context0_settings(struct hubp *hubp, 813 const struct vm_context0_param *vm0) 814 { 815 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 816 /* pte base */ 817 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, 818 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); 819 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, 820 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); 821 822 /* pte start */ 823 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, 824 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); 825 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, 826 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); 827 828 /* pte end */ 829 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, 830 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); 831 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, 832 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); 833 834 /* fault handling */ 835 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 836 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, 837 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); 838 REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 839 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); 840 841 /* control: enable VM PTE*/ 842 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 843 ENABLE_L1_TLB, 1, 844 SYSTEM_ACCESS_MODE, 3); 845 } 846 847 void min_set_viewport( 848 struct hubp *hubp, 849 const struct rect *viewport, 850 const struct rect *viewport_c) 851 { 852 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 853 854 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 855 PRI_VIEWPORT_WIDTH, viewport->width, 856 PRI_VIEWPORT_HEIGHT, viewport->height); 857 858 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 859 PRI_VIEWPORT_X_START, viewport->x, 860 PRI_VIEWPORT_Y_START, viewport->y); 861 862 /*for stereo*/ 863 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 864 SEC_VIEWPORT_WIDTH, viewport->width, 865 SEC_VIEWPORT_HEIGHT, viewport->height); 866 867 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 868 SEC_VIEWPORT_X_START, viewport->x, 869 SEC_VIEWPORT_Y_START, viewport->y); 870 871 /* DC supports NV12 only at the moment */ 872 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 873 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 874 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 875 876 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 877 PRI_VIEWPORT_X_START_C, viewport_c->x, 878 PRI_VIEWPORT_Y_START_C, viewport_c->y); 879 880 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 881 SEC_VIEWPORT_WIDTH_C, viewport_c->width, 882 SEC_VIEWPORT_HEIGHT_C, viewport_c->height); 883 884 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 885 SEC_VIEWPORT_X_START_C, viewport_c->x, 886 SEC_VIEWPORT_Y_START_C, viewport_c->y); 887 } 888 889 void hubp1_read_state_common(struct hubp *hubp) 890 { 891 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 892 struct dcn_hubp_state *s = &hubp1->state; 893 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 894 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 895 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 896 uint32_t aperture_low_msb, aperture_low_lsb; 897 uint32_t aperture_high_msb, aperture_high_lsb; 898 899 /* Requester */ 900 REG_GET(HUBPRET_CONTROL, 901 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 902 REG_GET_4(DCN_EXPANSION_MODE, 903 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 904 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 905 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 906 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 907 908 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 909 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, &aperture_low_msb); 910 911 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 912 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, &aperture_low_lsb); 913 914 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 915 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, &aperture_high_msb); 916 917 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 918 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, &aperture_high_lsb); 919 920 // On DCN1, aperture is broken down into MSB and LSB; only keep bits [47:18] to match later DCN format 921 rq_regs->aperture_low_addr = (aperture_low_msb << 26) | (aperture_low_lsb >> 6); 922 rq_regs->aperture_high_addr = (aperture_high_msb << 26) | (aperture_high_lsb >> 6); 923 924 /* DLG - Per hubp */ 925 REG_GET_2(BLANK_OFFSET_0, 926 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 927 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 928 929 REG_GET(BLANK_OFFSET_1, 930 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 931 932 REG_GET(DST_DIMENSIONS, 933 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 934 935 REG_GET_2(DST_AFTER_SCALER, 936 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 937 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 938 939 if (REG(PREFETCH_SETTINS)) 940 REG_GET_2(PREFETCH_SETTINS, 941 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 942 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 943 else 944 REG_GET_2(PREFETCH_SETTINGS, 945 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 946 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 947 948 REG_GET_2(VBLANK_PARAMETERS_0, 949 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 950 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 951 952 REG_GET(REF_FREQ_TO_PIX_FREQ, 953 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 954 955 /* DLG - Per luma/chroma */ 956 REG_GET(VBLANK_PARAMETERS_1, 957 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 958 959 REG_GET(VBLANK_PARAMETERS_3, 960 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 961 962 if (REG(NOM_PARAMETERS_0)) 963 REG_GET(NOM_PARAMETERS_0, 964 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 965 966 if (REG(NOM_PARAMETERS_1)) 967 REG_GET(NOM_PARAMETERS_1, 968 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 969 970 REG_GET(NOM_PARAMETERS_4, 971 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 972 973 REG_GET(NOM_PARAMETERS_5, 974 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 975 976 REG_GET_2(PER_LINE_DELIVERY_PRE, 977 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 978 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 979 980 REG_GET_2(PER_LINE_DELIVERY, 981 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 982 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 983 984 if (REG(PREFETCH_SETTINS_C)) 985 REG_GET(PREFETCH_SETTINS_C, 986 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 987 else 988 REG_GET(PREFETCH_SETTINGS_C, 989 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 990 991 REG_GET(VBLANK_PARAMETERS_2, 992 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 993 994 REG_GET(VBLANK_PARAMETERS_4, 995 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 996 997 if (REG(NOM_PARAMETERS_2)) 998 REG_GET(NOM_PARAMETERS_2, 999 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 1000 1001 if (REG(NOM_PARAMETERS_3)) 1002 REG_GET(NOM_PARAMETERS_3, 1003 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 1004 1005 REG_GET(NOM_PARAMETERS_6, 1006 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 1007 1008 REG_GET(NOM_PARAMETERS_7, 1009 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 1010 1011 /* TTU - per hubp */ 1012 REG_GET_2(DCN_TTU_QOS_WM, 1013 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 1014 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 1015 1016 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 1017 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 1018 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 1019 1020 /* TTU - per luma/chroma */ 1021 /* Assumed surf0 is luma and 1 is chroma */ 1022 1023 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1024 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 1025 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 1026 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 1027 1028 REG_GET(DCN_SURF0_TTU_CNTL1, 1029 REFCYC_PER_REQ_DELIVERY_PRE, 1030 &ttu_attr->refcyc_per_req_delivery_pre_l); 1031 1032 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1033 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 1034 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 1035 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 1036 1037 REG_GET(DCN_SURF1_TTU_CNTL1, 1038 REFCYC_PER_REQ_DELIVERY_PRE, 1039 &ttu_attr->refcyc_per_req_delivery_pre_c); 1040 1041 /* Rest of hubp */ 1042 REG_GET(DCSURF_SURFACE_CONFIG, 1043 SURFACE_PIXEL_FORMAT, &s->pixel_format); 1044 1045 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 1046 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 1047 1048 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 1049 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 1050 1051 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 1052 PRI_VIEWPORT_WIDTH, &s->viewport_width, 1053 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 1054 1055 REG_GET_2(DCSURF_SURFACE_CONFIG, 1056 ROTATION_ANGLE, &s->rotation_angle, 1057 H_MIRROR_EN, &s->h_mirror_en); 1058 1059 REG_GET(DCSURF_TILING_CONFIG, 1060 SW_MODE, &s->sw_mode); 1061 1062 REG_GET(DCSURF_SURFACE_CONTROL, 1063 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1064 1065 REG_GET_3(DCHUBP_CNTL, 1066 HUBP_BLANK_EN, &s->blank_en, 1067 HUBP_TTU_DISABLE, &s->ttu_disable, 1068 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1069 1070 REG_GET(HUBP_CLK_CNTL, 1071 HUBP_CLOCK_ENABLE, &s->clock_en); 1072 1073 REG_GET(DCN_GLOBAL_TTU_CNTL, 1074 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1075 1076 REG_GET_2(DCN_TTU_QOS_WM, 1077 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1078 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1079 1080 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, 1081 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); 1082 1083 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 1084 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); 1085 1086 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 1087 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo); 1088 1089 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 1090 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi); 1091 } 1092 1093 void hubp1_read_state(struct hubp *hubp) 1094 { 1095 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1096 struct dcn_hubp_state *s = &hubp1->state; 1097 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1098 1099 hubp1_read_state_common(hubp); 1100 1101 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1102 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1103 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1104 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1105 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1106 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1107 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1108 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1109 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1110 1111 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1112 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1113 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1114 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1115 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1116 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1117 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1118 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1119 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1120 1121 } 1122 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) 1123 { 1124 enum cursor_pitch hw_pitch; 1125 1126 switch (pitch) { 1127 case 64: 1128 hw_pitch = CURSOR_PITCH_64_PIXELS; 1129 break; 1130 case 128: 1131 hw_pitch = CURSOR_PITCH_128_PIXELS; 1132 break; 1133 case 256: 1134 hw_pitch = CURSOR_PITCH_256_PIXELS; 1135 break; 1136 default: 1137 DC_ERR("Invalid cursor pitch of %d. " 1138 "Only 64/128/256 is supported on DCN.\n", pitch); 1139 hw_pitch = CURSOR_PITCH_64_PIXELS; 1140 break; 1141 } 1142 return hw_pitch; 1143 } 1144 1145 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( 1146 unsigned int cur_width, 1147 enum dc_cursor_color_format format) 1148 { 1149 enum cursor_lines_per_chunk line_per_chunk; 1150 1151 if (format == CURSOR_MODE_MONO) 1152 /* impl B. expansion in CUR Buffer reader */ 1153 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1154 else if (cur_width <= 32) 1155 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 1156 else if (cur_width <= 64) 1157 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 1158 else if (cur_width <= 128) 1159 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 1160 else 1161 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 1162 1163 return line_per_chunk; 1164 } 1165 1166 void hubp1_cursor_set_attributes( 1167 struct hubp *hubp, 1168 const struct dc_cursor_attributes *attr) 1169 { 1170 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1171 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 1172 enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( 1173 attr->width, attr->color_format); 1174 1175 hubp->curs_attr = *attr; 1176 1177 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 1178 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 1179 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 1180 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 1181 1182 REG_UPDATE_2(CURSOR_SIZE, 1183 CURSOR_WIDTH, attr->width, 1184 CURSOR_HEIGHT, attr->height); 1185 1186 REG_UPDATE_3(CURSOR_CONTROL, 1187 CURSOR_MODE, attr->color_format, 1188 CURSOR_PITCH, hw_pitch, 1189 CURSOR_LINES_PER_CHUNK, lpc); 1190 1191 REG_SET_2(CURSOR_SETTINS, 0, 1192 /* no shift of the cursor HDL schedule */ 1193 CURSOR0_DST_Y_OFFSET, 0, 1194 /* used to shift the cursor chunk request deadline */ 1195 CURSOR0_CHUNK_HDL_ADJUST, 3); 1196 } 1197 1198 void hubp1_cursor_set_position( 1199 struct hubp *hubp, 1200 const struct dc_cursor_position *pos, 1201 const struct dc_cursor_mi_param *param) 1202 { 1203 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1204 int x_pos = pos->x - param->viewport.x; 1205 int y_pos = pos->y - param->viewport.y; 1206 int x_hotspot = pos->x_hotspot; 1207 int y_hotspot = pos->y_hotspot; 1208 int src_x_offset = x_pos - pos->x_hotspot; 1209 int src_y_offset = y_pos - pos->y_hotspot; 1210 int cursor_height = (int)hubp->curs_attr.height; 1211 int cursor_width = (int)hubp->curs_attr.width; 1212 uint32_t dst_x_offset; 1213 uint32_t cur_en = pos->enable ? 1 : 0; 1214 1215 hubp->curs_pos = *pos; 1216 1217 /* 1218 * Guard aganst cursor_set_position() from being called with invalid 1219 * attributes 1220 * 1221 * TODO: Look at combining cursor_set_position() and 1222 * cursor_set_attributes() into cursor_update() 1223 */ 1224 if (hubp->curs_attr.address.quad_part == 0) 1225 return; 1226 1227 // Transform cursor width / height and hotspots for offset calculations 1228 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 1229 swap(cursor_height, cursor_width); 1230 swap(x_hotspot, y_hotspot); 1231 1232 if (param->rotation == ROTATION_ANGLE_90) { 1233 // hotspot = (-y, x) 1234 src_x_offset = x_pos - (cursor_width - x_hotspot); 1235 src_y_offset = y_pos - y_hotspot; 1236 } else if (param->rotation == ROTATION_ANGLE_270) { 1237 // hotspot = (y, -x) 1238 src_x_offset = x_pos - x_hotspot; 1239 src_y_offset = y_pos - (cursor_height - y_hotspot); 1240 } 1241 } else if (param->rotation == ROTATION_ANGLE_180) { 1242 // hotspot = (-x, -y) 1243 if (!param->mirror) 1244 src_x_offset = x_pos - (cursor_width - x_hotspot); 1245 1246 src_y_offset = y_pos - (cursor_height - y_hotspot); 1247 } 1248 1249 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1250 dst_x_offset *= param->ref_clk_khz; 1251 dst_x_offset /= param->pixel_clk_khz; 1252 1253 ASSERT(param->h_scale_ratio.value); 1254 1255 if (param->h_scale_ratio.value) 1256 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1257 dc_fixpt_from_int(dst_x_offset), 1258 param->h_scale_ratio)); 1259 1260 if (src_x_offset >= (int)param->viewport.width) 1261 cur_en = 0; /* not visible beyond right edge*/ 1262 1263 if (src_x_offset + cursor_width <= 0) 1264 cur_en = 0; /* not visible beyond left edge*/ 1265 1266 if (src_y_offset >= (int)param->viewport.height) 1267 cur_en = 0; /* not visible beyond bottom edge*/ 1268 1269 if (src_y_offset + cursor_height <= 0) 1270 cur_en = 0; /* not visible beyond top edge*/ 1271 1272 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1273 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1274 1275 REG_UPDATE(CURSOR_CONTROL, 1276 CURSOR_ENABLE, cur_en); 1277 1278 REG_SET_2(CURSOR_POSITION, 0, 1279 CURSOR_X_POSITION, pos->x, 1280 CURSOR_Y_POSITION, pos->y); 1281 1282 REG_SET_2(CURSOR_HOT_SPOT, 0, 1283 CURSOR_HOT_SPOT_X, pos->x_hotspot, 1284 CURSOR_HOT_SPOT_Y, pos->y_hotspot); 1285 1286 REG_SET(CURSOR_DST_OFFSET, 0, 1287 CURSOR_DST_X_OFFSET, dst_x_offset); 1288 /* TODO Handle surface pixel formats other than 4:4:4 */ 1289 } 1290 1291 /** 1292 * hubp1_clk_cntl - Disable or enable clocks for DCHUBP 1293 * 1294 * @hubp: hubp struct reference. 1295 * @enable: Set true for enabling gate clock. 1296 * 1297 * When enabling/disabling DCHUBP clock, we affect dcfclk/dppclk. 1298 */ 1299 void hubp1_clk_cntl(struct hubp *hubp, bool enable) 1300 { 1301 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1302 uint32_t clk_enable = enable ? 1 : 0; 1303 1304 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1305 } 1306 1307 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1308 { 1309 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1310 1311 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1312 } 1313 1314 bool hubp1_in_blank(struct hubp *hubp) 1315 { 1316 uint32_t in_blank; 1317 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1318 1319 REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank); 1320 return in_blank ? true : false; 1321 } 1322 1323 void hubp1_soft_reset(struct hubp *hubp, bool reset) 1324 { 1325 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1326 1327 REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0); 1328 } 1329 1330 /** 1331 * hubp1_set_flip_int - Enable surface flip interrupt 1332 * 1333 * @hubp: hubp struct reference. 1334 */ 1335 void hubp1_set_flip_int(struct hubp *hubp) 1336 { 1337 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1338 1339 REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT, 1340 SURFACE_FLIP_INT_MASK, 1); 1341 1342 return; 1343 } 1344 1345 /** 1346 * hubp1_wait_pipe_read_start - wait for hubp ret path starting read. 1347 * 1348 * @hubp: hubp struct reference. 1349 */ 1350 static void hubp1_wait_pipe_read_start(struct hubp *hubp) 1351 { 1352 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 1353 1354 REG_WAIT(HUBPRET_READ_LINE_STATUS, 1355 PIPE_READ_VBLANK, 0, 1356 1, 1000); 1357 } 1358 1359 void hubp1_init(struct hubp *hubp) 1360 { 1361 hubp_reset(hubp); 1362 } 1363 1364 static const struct hubp_funcs dcn10_hubp_funcs = { 1365 .hubp_program_surface_flip_and_addr = 1366 hubp1_program_surface_flip_and_addr, 1367 .hubp_program_surface_config = 1368 hubp1_program_surface_config, 1369 .hubp_is_flip_pending = hubp1_is_flip_pending, 1370 .hubp_setup = hubp1_setup, 1371 .hubp_setup_interdependent = hubp1_setup_interdependent, 1372 .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, 1373 .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, 1374 .set_blank = hubp1_set_blank, 1375 .dcc_control = hubp1_dcc_control, 1376 .hubp_reset = hubp_reset, 1377 .mem_program_viewport = min_set_viewport, 1378 .set_hubp_blank_en = hubp1_set_hubp_blank_en, 1379 .set_cursor_attributes = hubp1_cursor_set_attributes, 1380 .set_cursor_position = hubp1_cursor_set_position, 1381 .hubp_disconnect = hubp1_disconnect, 1382 .hubp_clk_cntl = hubp1_clk_cntl, 1383 .hubp_vtg_sel = hubp1_vtg_sel, 1384 .hubp_read_state = hubp1_read_state, 1385 .hubp_clear_underflow = hubp1_clear_underflow, 1386 .hubp_disable_control = hubp1_disable_control, 1387 .hubp_get_underflow_status = hubp1_get_underflow_status, 1388 .hubp_init = hubp1_init, 1389 .hubp_clear_tiling = hubp1_clear_tiling, 1390 1391 .dmdata_set_attributes = NULL, 1392 .dmdata_load = NULL, 1393 .hubp_soft_reset = hubp1_soft_reset, 1394 .hubp_in_blank = hubp1_in_blank, 1395 .hubp_set_flip_int = hubp1_set_flip_int, 1396 .hubp_wait_pipe_read_start = hubp1_wait_pipe_read_start, 1397 }; 1398 1399 /*****************************************/ 1400 /* Constructor, Destructor */ 1401 /*****************************************/ 1402 1403 void dcn10_hubp_construct( 1404 struct dcn10_hubp *hubp1, 1405 struct dc_context *ctx, 1406 uint32_t inst, 1407 const struct dcn_mi_registers *hubp_regs, 1408 const struct dcn_mi_shift *hubp_shift, 1409 const struct dcn_mi_mask *hubp_mask) 1410 { 1411 hubp1->base.funcs = &dcn10_hubp_funcs; 1412 hubp1->base.ctx = ctx; 1413 hubp1->hubp_regs = hubp_regs; 1414 hubp1->hubp_shift = hubp_shift; 1415 hubp1->hubp_mask = hubp_mask; 1416 hubp1->base.inst = inst; 1417 hubp1->base.opp_id = OPP_ID_INVALID; 1418 hubp1->base.mpcc_id = 0xf; 1419 } 1420 1421 1422