1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26 #include "dce_calcs.h"
27 #include "reg_helper.h"
28 #include "basics/conversion.h"
29 #include "dcn10_hubp.h"
30
31 #define REG(reg)\
32 hubp1->hubp_regs->reg
33
34 #define CTX \
35 hubp1->base.ctx
36
37 #undef FN
38 #define FN(reg_name, field_name) \
39 hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name
40
hubp1_set_blank(struct hubp * hubp,bool blank)41 void hubp1_set_blank(struct hubp *hubp, bool blank)
42 {
43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
44 uint32_t blank_en = blank ? 1 : 0;
45
46 REG_UPDATE_2(DCHUBP_CNTL,
47 HUBP_BLANK_EN, blank_en,
48 HUBP_TTU_DISABLE, blank_en);
49
50 if (blank) {
51 uint32_t reg_val = REG_READ(DCHUBP_CNTL);
52
53 if (reg_val) {
54 /* init sequence workaround: in case HUBP is
55 * power gated, this wait would timeout.
56 *
57 * we just wrote reg_val to non-0, if it stay 0
58 * it means HUBP is gated
59 */
60 REG_WAIT(DCHUBP_CNTL,
61 HUBP_NO_OUTSTANDING_REQ, 1,
62 1, 200);
63 }
64
65 hubp->mpcc_id = 0xf;
66 hubp->opp_id = OPP_ID_INVALID;
67 }
68 }
69
hubp1_disconnect(struct hubp * hubp)70 static void hubp1_disconnect(struct hubp *hubp)
71 {
72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
73
74 REG_UPDATE(DCHUBP_CNTL,
75 HUBP_TTU_DISABLE, 1);
76
77 REG_UPDATE(CURSOR_CONTROL,
78 CURSOR_ENABLE, 0);
79 }
80
hubp1_disable_control(struct hubp * hubp,bool disable_hubp)81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)
82 {
83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
84 uint32_t disable = disable_hubp ? 1 : 0;
85
86 REG_UPDATE(DCHUBP_CNTL,
87 HUBP_DISABLE, disable);
88 }
89
hubp1_get_underflow_status(struct hubp * hubp)90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp)
91 {
92 uint32_t hubp_underflow = 0;
93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
94
95 REG_GET(DCHUBP_CNTL,
96 HUBP_UNDERFLOW_STATUS,
97 &hubp_underflow);
98
99 return hubp_underflow;
100 }
101
102
hubp1_clear_underflow(struct hubp * hubp)103 void hubp1_clear_underflow(struct hubp *hubp)
104 {
105 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
106
107 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
108 }
109
hubp1_set_hubp_blank_en(struct hubp * hubp,bool blank)110 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
111 {
112 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
113 uint32_t blank_en = blank ? 1 : 0;
114
115 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
116 }
117
hubp1_vready_workaround(struct hubp * hubp,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)118 void hubp1_vready_workaround(struct hubp *hubp,
119 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
120 {
121 uint32_t value = 0;
122 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
123
124 /* set HBUBREQ_DEBUG_DB[12] = 1 */
125 value = REG_READ(HUBPREQ_DEBUG_DB);
126
127 /* hack mode disable */
128 value |= 0x100;
129 value &= ~0x1000;
130
131 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width
132 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
133 /* if (eco_fix_needed(otg_global_sync_timing)
134 * set HBUBREQ_DEBUG_DB[12] = 1 */
135 value |= 0x1000;
136 }
137
138 REG_WRITE(HUBPREQ_DEBUG_DB, value);
139 }
140
hubp1_program_tiling(struct hubp * hubp,const union dc_tiling_info * info,const enum surface_pixel_format pixel_format)141 void hubp1_program_tiling(
142 struct hubp *hubp,
143 const union dc_tiling_info *info,
144 const enum surface_pixel_format pixel_format)
145 {
146 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
147
148 REG_UPDATE_6(DCSURF_ADDR_CONFIG,
149 NUM_PIPES, log_2(info->gfx9.num_pipes),
150 NUM_BANKS, log_2(info->gfx9.num_banks),
151 PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
152 NUM_SE, log_2(info->gfx9.num_shader_engines),
153 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
154 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
155
156 REG_UPDATE_4(DCSURF_TILING_CONFIG,
157 SW_MODE, info->gfx9.swizzle,
158 META_LINEAR, info->gfx9.meta_linear,
159 RB_ALIGNED, info->gfx9.rb_aligned,
160 PIPE_ALIGNED, info->gfx9.pipe_aligned);
161 }
162
hubp1_program_size(struct hubp * hubp,enum surface_pixel_format format,const struct plane_size * plane_size,struct dc_plane_dcc_param * dcc)163 void hubp1_program_size(
164 struct hubp *hubp,
165 enum surface_pixel_format format,
166 const struct plane_size *plane_size,
167 struct dc_plane_dcc_param *dcc)
168 {
169 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
170 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
171
172 /* Program data and meta surface pitch (calculation from addrlib)
173 * 444 or 420 luma
174 */
175 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
176 ASSERT(plane_size->chroma_pitch != 0);
177 /* Chroma pitch zero can cause system hang! */
178
179 pitch = plane_size->surface_pitch - 1;
180 meta_pitch = dcc->meta_pitch - 1;
181 pitch_c = plane_size->chroma_pitch - 1;
182 meta_pitch_c = dcc->meta_pitch_c - 1;
183 } else {
184 pitch = plane_size->surface_pitch - 1;
185 meta_pitch = dcc->meta_pitch - 1;
186 pitch_c = 0;
187 meta_pitch_c = 0;
188 }
189
190 if (!dcc->enable) {
191 meta_pitch = 0;
192 meta_pitch_c = 0;
193 }
194
195 REG_UPDATE_2(DCSURF_SURFACE_PITCH,
196 PITCH, pitch, META_PITCH, meta_pitch);
197
198 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
199 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
200 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
201 }
202
hubp1_program_rotation(struct hubp * hubp,enum dc_rotation_angle rotation,bool horizontal_mirror)203 void hubp1_program_rotation(
204 struct hubp *hubp,
205 enum dc_rotation_angle rotation,
206 bool horizontal_mirror)
207 {
208 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
209 uint32_t mirror;
210
211
212 if (horizontal_mirror)
213 mirror = 1;
214 else
215 mirror = 0;
216
217 /* Program rotation angle and horz mirror - no mirror */
218 if (rotation == ROTATION_ANGLE_0)
219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
220 ROTATION_ANGLE, 0,
221 H_MIRROR_EN, mirror);
222 else if (rotation == ROTATION_ANGLE_90)
223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
224 ROTATION_ANGLE, 1,
225 H_MIRROR_EN, mirror);
226 else if (rotation == ROTATION_ANGLE_180)
227 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
228 ROTATION_ANGLE, 2,
229 H_MIRROR_EN, mirror);
230 else if (rotation == ROTATION_ANGLE_270)
231 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
232 ROTATION_ANGLE, 3,
233 H_MIRROR_EN, mirror);
234 }
235
hubp1_program_pixel_format(struct hubp * hubp,enum surface_pixel_format format)236 void hubp1_program_pixel_format(
237 struct hubp *hubp,
238 enum surface_pixel_format format)
239 {
240 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
241 uint32_t red_bar = 3;
242 uint32_t blue_bar = 2;
243
244 /* swap for ABGR format */
245 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
246 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
247 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
248 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
249 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
250 red_bar = 2;
251 blue_bar = 3;
252 }
253
254 REG_UPDATE_2(HUBPRET_CONTROL,
255 CROSSBAR_SRC_CB_B, blue_bar,
256 CROSSBAR_SRC_CR_R, red_bar);
257
258 /* Mapping is same as ipp programming (cnvc) */
259
260 switch (format) {
261 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
262 REG_UPDATE(DCSURF_SURFACE_CONFIG,
263 SURFACE_PIXEL_FORMAT, 1);
264 break;
265 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
266 REG_UPDATE(DCSURF_SURFACE_CONFIG,
267 SURFACE_PIXEL_FORMAT, 3);
268 break;
269 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
270 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
271 REG_UPDATE(DCSURF_SURFACE_CONFIG,
272 SURFACE_PIXEL_FORMAT, 8);
273 break;
274 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
275 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
276 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
277 REG_UPDATE(DCSURF_SURFACE_CONFIG,
278 SURFACE_PIXEL_FORMAT, 10);
279 break;
280 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
281 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/
282 REG_UPDATE(DCSURF_SURFACE_CONFIG,
283 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
284 break;
285 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
286 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
287 REG_UPDATE(DCSURF_SURFACE_CONFIG,
288 SURFACE_PIXEL_FORMAT, 24);
289 break;
290
291 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
292 REG_UPDATE(DCSURF_SURFACE_CONFIG,
293 SURFACE_PIXEL_FORMAT, 65);
294 break;
295 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
296 REG_UPDATE(DCSURF_SURFACE_CONFIG,
297 SURFACE_PIXEL_FORMAT, 64);
298 break;
299 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
300 REG_UPDATE(DCSURF_SURFACE_CONFIG,
301 SURFACE_PIXEL_FORMAT, 67);
302 break;
303 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
304 REG_UPDATE(DCSURF_SURFACE_CONFIG,
305 SURFACE_PIXEL_FORMAT, 66);
306 break;
307 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
308 REG_UPDATE(DCSURF_SURFACE_CONFIG,
309 SURFACE_PIXEL_FORMAT, 12);
310 break;
311 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
312 REG_UPDATE(DCSURF_SURFACE_CONFIG,
313 SURFACE_PIXEL_FORMAT, 112);
314 break;
315 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
316 REG_UPDATE(DCSURF_SURFACE_CONFIG,
317 SURFACE_PIXEL_FORMAT, 113);
318 break;
319 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
320 REG_UPDATE(DCSURF_SURFACE_CONFIG,
321 SURFACE_PIXEL_FORMAT, 114);
322 break;
323 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
324 REG_UPDATE(DCSURF_SURFACE_CONFIG,
325 SURFACE_PIXEL_FORMAT, 118);
326 break;
327 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
328 REG_UPDATE(DCSURF_SURFACE_CONFIG,
329 SURFACE_PIXEL_FORMAT, 119);
330 break;
331 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
332 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
333 SURFACE_PIXEL_FORMAT, 116,
334 ALPHA_PLANE_EN, 0);
335 break;
336 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
337 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
338 SURFACE_PIXEL_FORMAT, 116,
339 ALPHA_PLANE_EN, 1);
340 break;
341 default:
342 BREAK_TO_DEBUGGER();
343 break;
344 }
345
346 /* don't see the need of program the xbar in DCN 1.0 */
347 }
348
hubp1_program_surface_flip_and_addr(struct hubp * hubp,const struct dc_plane_address * address,bool flip_immediate)349 bool hubp1_program_surface_flip_and_addr(
350 struct hubp *hubp,
351 const struct dc_plane_address *address,
352 bool flip_immediate)
353 {
354 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
355
356
357 //program flip type
358 REG_UPDATE(DCSURF_FLIP_CONTROL,
359 SURFACE_FLIP_TYPE, flip_immediate);
360
361
362 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
363 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);
364 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
365
366 } else {
367 // turn off stereo if not in stereo
368 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
369 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
370 }
371
372
373
374 /* HW automatically latch rest of address register on write to
375 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
376 *
377 * program high first and then the low addr, order matters!
378 */
379 switch (address->type) {
380 case PLN_ADDR_TYPE_GRAPHICS:
381 /* DCN1.0 does not support const color
382 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
383 * base on address->grph.dcc_const_color
384 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
385 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
386 */
387
388 if (address->grph.addr.quad_part == 0)
389 break;
390
391 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
392 PRIMARY_SURFACE_TMZ, address->tmz_surface,
393 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
394
395 if (address->grph.meta_addr.quad_part != 0) {
396 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
397 PRIMARY_META_SURFACE_ADDRESS_HIGH,
398 address->grph.meta_addr.high_part);
399
400 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
401 PRIMARY_META_SURFACE_ADDRESS,
402 address->grph.meta_addr.low_part);
403 }
404
405 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
406 PRIMARY_SURFACE_ADDRESS_HIGH,
407 address->grph.addr.high_part);
408
409 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
410 PRIMARY_SURFACE_ADDRESS,
411 address->grph.addr.low_part);
412 break;
413 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
414 if (address->video_progressive.luma_addr.quad_part == 0
415 || address->video_progressive.chroma_addr.quad_part == 0)
416 break;
417
418 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
419 PRIMARY_SURFACE_TMZ, address->tmz_surface,
420 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
421 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
422 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
423
424 if (address->video_progressive.luma_meta_addr.quad_part != 0) {
425 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
426 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
427 address->video_progressive.chroma_meta_addr.high_part);
428
429 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
430 PRIMARY_META_SURFACE_ADDRESS_C,
431 address->video_progressive.chroma_meta_addr.low_part);
432
433 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
434 PRIMARY_META_SURFACE_ADDRESS_HIGH,
435 address->video_progressive.luma_meta_addr.high_part);
436
437 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
438 PRIMARY_META_SURFACE_ADDRESS,
439 address->video_progressive.luma_meta_addr.low_part);
440 }
441
442 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
443 PRIMARY_SURFACE_ADDRESS_HIGH_C,
444 address->video_progressive.chroma_addr.high_part);
445
446 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
447 PRIMARY_SURFACE_ADDRESS_C,
448 address->video_progressive.chroma_addr.low_part);
449
450 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
451 PRIMARY_SURFACE_ADDRESS_HIGH,
452 address->video_progressive.luma_addr.high_part);
453
454 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
455 PRIMARY_SURFACE_ADDRESS,
456 address->video_progressive.luma_addr.low_part);
457 break;
458 case PLN_ADDR_TYPE_GRPH_STEREO:
459 if (address->grph_stereo.left_addr.quad_part == 0)
460 break;
461 if (address->grph_stereo.right_addr.quad_part == 0)
462 break;
463
464 REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
465 PRIMARY_SURFACE_TMZ, address->tmz_surface,
466 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
467 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
468 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
469 SECONDARY_SURFACE_TMZ, address->tmz_surface,
470 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
471 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
472 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
473
474 if (address->grph_stereo.right_meta_addr.quad_part != 0) {
475
476 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
477 SECONDARY_META_SURFACE_ADDRESS_HIGH,
478 address->grph_stereo.right_meta_addr.high_part);
479
480 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
481 SECONDARY_META_SURFACE_ADDRESS,
482 address->grph_stereo.right_meta_addr.low_part);
483 }
484 if (address->grph_stereo.left_meta_addr.quad_part != 0) {
485
486 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
487 PRIMARY_META_SURFACE_ADDRESS_HIGH,
488 address->grph_stereo.left_meta_addr.high_part);
489
490 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
491 PRIMARY_META_SURFACE_ADDRESS,
492 address->grph_stereo.left_meta_addr.low_part);
493 }
494
495 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
496 SECONDARY_SURFACE_ADDRESS_HIGH,
497 address->grph_stereo.right_addr.high_part);
498
499 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
500 SECONDARY_SURFACE_ADDRESS,
501 address->grph_stereo.right_addr.low_part);
502
503 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
504 PRIMARY_SURFACE_ADDRESS_HIGH,
505 address->grph_stereo.left_addr.high_part);
506
507 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
508 PRIMARY_SURFACE_ADDRESS,
509 address->grph_stereo.left_addr.low_part);
510 break;
511 default:
512 BREAK_TO_DEBUGGER();
513 break;
514 }
515
516 hubp->request_address = *address;
517
518 return true;
519 }
520
hubp1_dcc_control(struct hubp * hubp,bool enable,enum hubp_ind_block_size independent_64b_blks)521 void hubp1_dcc_control(struct hubp *hubp, bool enable,
522 enum hubp_ind_block_size independent_64b_blks)
523 {
524 uint32_t dcc_en = enable ? 1 : 0;
525 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
526 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
527
528 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
529 PRIMARY_SURFACE_DCC_EN, dcc_en,
530 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
531 SECONDARY_SURFACE_DCC_EN, dcc_en,
532 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
533 }
534
hubp1_program_surface_config(struct hubp * hubp,enum surface_pixel_format format,union dc_tiling_info * tiling_info,struct plane_size * plane_size,enum dc_rotation_angle rotation,struct dc_plane_dcc_param * dcc,bool horizontal_mirror,unsigned int compat_level)535 void hubp1_program_surface_config(
536 struct hubp *hubp,
537 enum surface_pixel_format format,
538 union dc_tiling_info *tiling_info,
539 struct plane_size *plane_size,
540 enum dc_rotation_angle rotation,
541 struct dc_plane_dcc_param *dcc,
542 bool horizontal_mirror,
543 unsigned int compat_level)
544 {
545 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
546 hubp1_program_tiling(hubp, tiling_info, format);
547 hubp1_program_size(hubp, format, plane_size, dcc);
548 hubp1_program_rotation(hubp, rotation, horizontal_mirror);
549 hubp1_program_pixel_format(hubp, format);
550 }
551
hubp1_program_requestor(struct hubp * hubp,struct _vcs_dpi_display_rq_regs_st * rq_regs)552 void hubp1_program_requestor(
553 struct hubp *hubp,
554 struct _vcs_dpi_display_rq_regs_st *rq_regs)
555 {
556 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
557
558 REG_UPDATE(HUBPRET_CONTROL,
559 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
560 REG_SET_4(DCN_EXPANSION_MODE, 0,
561 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
562 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
563 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
564 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
565 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
566 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
567 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
568 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
569 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
570 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
571 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
572 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
573 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
574 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
575 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
576 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
577 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
578 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
579 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
580 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
581 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
582 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
583 }
584
585
hubp1_program_deadline(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr)586 void hubp1_program_deadline(
587 struct hubp *hubp,
588 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
589 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
590 {
591 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
592
593 /* DLG - Per hubp */
594 REG_SET_2(BLANK_OFFSET_0, 0,
595 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
596 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
597
598 REG_SET(BLANK_OFFSET_1, 0,
599 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
600
601 REG_SET(DST_DIMENSIONS, 0,
602 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
603
604 REG_SET_2(DST_AFTER_SCALER, 0,
605 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
606 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
607
608 REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
609 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
610
611 /* DLG - Per luma/chroma */
612 REG_SET(VBLANK_PARAMETERS_1, 0,
613 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
614
615 if (REG(NOM_PARAMETERS_0))
616 REG_SET(NOM_PARAMETERS_0, 0,
617 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
618
619 if (REG(NOM_PARAMETERS_1))
620 REG_SET(NOM_PARAMETERS_1, 0,
621 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
622
623 REG_SET(NOM_PARAMETERS_4, 0,
624 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
625
626 REG_SET(NOM_PARAMETERS_5, 0,
627 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
628
629 REG_SET_2(PER_LINE_DELIVERY, 0,
630 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
631 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
632
633 REG_SET(VBLANK_PARAMETERS_2, 0,
634 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
635
636 if (REG(NOM_PARAMETERS_2))
637 REG_SET(NOM_PARAMETERS_2, 0,
638 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
639
640 if (REG(NOM_PARAMETERS_3))
641 REG_SET(NOM_PARAMETERS_3, 0,
642 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
643
644 REG_SET(NOM_PARAMETERS_6, 0,
645 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
646
647 REG_SET(NOM_PARAMETERS_7, 0,
648 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
649
650 /* TTU - per hubp */
651 REG_SET_2(DCN_TTU_QOS_WM, 0,
652 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
653 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
654
655 /* TTU - per luma/chroma */
656 /* Assumed surf0 is luma and 1 is chroma */
657
658 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
659 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
660 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
661 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
662
663 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
664 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
665 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
666 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
667
668 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
669 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
670 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
671 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
672 }
673
hubp1_setup(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr,struct _vcs_dpi_display_rq_regs_st * rq_regs,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)674 static void hubp1_setup(
675 struct hubp *hubp,
676 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
677 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
678 struct _vcs_dpi_display_rq_regs_st *rq_regs,
679 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
680 {
681 /* otg is locked when this func is called. Register are double buffered.
682 * disable the requestors is not needed
683 */
684 hubp1_program_requestor(hubp, rq_regs);
685 hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
686 hubp1_vready_workaround(hubp, pipe_dest);
687 }
688
hubp1_setup_interdependent(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr)689 static void hubp1_setup_interdependent(
690 struct hubp *hubp,
691 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
692 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
693 {
694 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
695
696 REG_SET_2(PREFETCH_SETTINS, 0,
697 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
698 VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
699
700 REG_SET(PREFETCH_SETTINS_C, 0,
701 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
702
703 REG_SET_2(VBLANK_PARAMETERS_0, 0,
704 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
705 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
706
707 REG_SET(VBLANK_PARAMETERS_3, 0,
708 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
709
710 REG_SET(VBLANK_PARAMETERS_4, 0,
711 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
712
713 REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
714 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
715 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
716
717 REG_SET(DCN_SURF0_TTU_CNTL1, 0,
718 REFCYC_PER_REQ_DELIVERY_PRE,
719 ttu_attr->refcyc_per_req_delivery_pre_l);
720 REG_SET(DCN_SURF1_TTU_CNTL1, 0,
721 REFCYC_PER_REQ_DELIVERY_PRE,
722 ttu_attr->refcyc_per_req_delivery_pre_c);
723 REG_SET(DCN_CUR0_TTU_CNTL1, 0,
724 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
725
726 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
727 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
728 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
729 }
730
hubp1_is_flip_pending(struct hubp * hubp)731 bool hubp1_is_flip_pending(struct hubp *hubp)
732 {
733 uint32_t flip_pending = 0;
734 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
735 struct dc_plane_address earliest_inuse_address;
736
737 if (hubp && hubp->power_gated)
738 return false;
739
740 REG_GET(DCSURF_FLIP_CONTROL,
741 SURFACE_FLIP_PENDING, &flip_pending);
742
743 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
744 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
745
746 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
747 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
748
749 if (flip_pending)
750 return true;
751
752 if (hubp &&
753 earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
754 return true;
755
756 return false;
757 }
758
759 static uint32_t aperture_default_system = 1;
760 static uint32_t context0_default_system; /* = 0;*/
761
hubp1_set_vm_system_aperture_settings(struct hubp * hubp,struct vm_system_aperture_param * apt)762 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,
763 struct vm_system_aperture_param *apt)
764 {
765 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
766 PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
767 PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
768 PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
769
770 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
771 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12;
772 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12;
773
774 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,
775 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */
776 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
777 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
778 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
779
780 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0,
781 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part);
782 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0,
783 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part);
784
785 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0,
786 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part);
787 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0,
788 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part);
789 }
790
hubp1_set_vm_context0_settings(struct hubp * hubp,const struct vm_context0_param * vm0)791 static void hubp1_set_vm_context0_settings(struct hubp *hubp,
792 const struct vm_context0_param *vm0)
793 {
794 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
795 /* pte base */
796 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,
797 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part);
798 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0,
799 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part);
800
801 /* pte start */
802 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0,
803 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part);
804 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0,
805 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part);
806
807 /* pte end */
808 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0,
809 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part);
810 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0,
811 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part);
812
813 /* fault handling */
814 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
815 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part,
816 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system);
817 REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
818 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);
819
820 /* control: enable VM PTE*/
821 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
822 ENABLE_L1_TLB, 1,
823 SYSTEM_ACCESS_MODE, 3);
824 }
825
min_set_viewport(struct hubp * hubp,const struct rect * viewport,const struct rect * viewport_c)826 void min_set_viewport(
827 struct hubp *hubp,
828 const struct rect *viewport,
829 const struct rect *viewport_c)
830 {
831 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
832
833 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
834 PRI_VIEWPORT_WIDTH, viewport->width,
835 PRI_VIEWPORT_HEIGHT, viewport->height);
836
837 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
838 PRI_VIEWPORT_X_START, viewport->x,
839 PRI_VIEWPORT_Y_START, viewport->y);
840
841 /*for stereo*/
842 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
843 SEC_VIEWPORT_WIDTH, viewport->width,
844 SEC_VIEWPORT_HEIGHT, viewport->height);
845
846 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
847 SEC_VIEWPORT_X_START, viewport->x,
848 SEC_VIEWPORT_Y_START, viewport->y);
849
850 /* DC supports NV12 only at the moment */
851 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
852 PRI_VIEWPORT_WIDTH_C, viewport_c->width,
853 PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
854
855 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
856 PRI_VIEWPORT_X_START_C, viewport_c->x,
857 PRI_VIEWPORT_Y_START_C, viewport_c->y);
858
859 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
860 SEC_VIEWPORT_WIDTH_C, viewport_c->width,
861 SEC_VIEWPORT_HEIGHT_C, viewport_c->height);
862
863 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
864 SEC_VIEWPORT_X_START_C, viewport_c->x,
865 SEC_VIEWPORT_Y_START_C, viewport_c->y);
866 }
867
hubp1_read_state_common(struct hubp * hubp)868 void hubp1_read_state_common(struct hubp *hubp)
869 {
870 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
871 struct dcn_hubp_state *s = &hubp1->state;
872 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
873 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
874 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
875 uint32_t aperture_low_msb, aperture_low_lsb;
876 uint32_t aperture_high_msb, aperture_high_lsb;
877
878 /* Requester */
879 REG_GET(HUBPRET_CONTROL,
880 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
881 REG_GET_4(DCN_EXPANSION_MODE,
882 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
883 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
884 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
885 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
886
887 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB,
888 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, &aperture_low_msb);
889
890 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB,
891 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, &aperture_low_lsb);
892
893 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB,
894 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, &aperture_high_msb);
895
896 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB,
897 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, &aperture_high_lsb);
898
899 // On DCN1, aperture is broken down into MSB and LSB; only keep bits [47:18] to match later DCN format
900 rq_regs->aperture_low_addr = (aperture_low_msb << 26) | (aperture_low_lsb >> 6);
901 rq_regs->aperture_high_addr = (aperture_high_msb << 26) | (aperture_high_lsb >> 6);
902
903 /* DLG - Per hubp */
904 REG_GET_2(BLANK_OFFSET_0,
905 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
906 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
907
908 REG_GET(BLANK_OFFSET_1,
909 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
910
911 REG_GET(DST_DIMENSIONS,
912 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
913
914 REG_GET_2(DST_AFTER_SCALER,
915 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
916 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
917
918 if (REG(PREFETCH_SETTINS))
919 REG_GET_2(PREFETCH_SETTINS,
920 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
921 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
922 else
923 REG_GET_2(PREFETCH_SETTINGS,
924 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
925 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
926
927 REG_GET_2(VBLANK_PARAMETERS_0,
928 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
929 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
930
931 REG_GET(REF_FREQ_TO_PIX_FREQ,
932 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
933
934 /* DLG - Per luma/chroma */
935 REG_GET(VBLANK_PARAMETERS_1,
936 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
937
938 REG_GET(VBLANK_PARAMETERS_3,
939 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
940
941 if (REG(NOM_PARAMETERS_0))
942 REG_GET(NOM_PARAMETERS_0,
943 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
944
945 if (REG(NOM_PARAMETERS_1))
946 REG_GET(NOM_PARAMETERS_1,
947 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
948
949 REG_GET(NOM_PARAMETERS_4,
950 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
951
952 REG_GET(NOM_PARAMETERS_5,
953 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
954
955 REG_GET_2(PER_LINE_DELIVERY_PRE,
956 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
957 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
958
959 REG_GET_2(PER_LINE_DELIVERY,
960 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
961 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
962
963 if (REG(PREFETCH_SETTINS_C))
964 REG_GET(PREFETCH_SETTINS_C,
965 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
966 else
967 REG_GET(PREFETCH_SETTINGS_C,
968 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
969
970 REG_GET(VBLANK_PARAMETERS_2,
971 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
972
973 REG_GET(VBLANK_PARAMETERS_4,
974 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
975
976 if (REG(NOM_PARAMETERS_2))
977 REG_GET(NOM_PARAMETERS_2,
978 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
979
980 if (REG(NOM_PARAMETERS_3))
981 REG_GET(NOM_PARAMETERS_3,
982 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
983
984 REG_GET(NOM_PARAMETERS_6,
985 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
986
987 REG_GET(NOM_PARAMETERS_7,
988 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
989
990 /* TTU - per hubp */
991 REG_GET_2(DCN_TTU_QOS_WM,
992 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
993 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
994
995 REG_GET_2(DCN_GLOBAL_TTU_CNTL,
996 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
997 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
998
999 /* TTU - per luma/chroma */
1000 /* Assumed surf0 is luma and 1 is chroma */
1001
1002 REG_GET_3(DCN_SURF0_TTU_CNTL0,
1003 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
1004 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
1005 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
1006
1007 REG_GET(DCN_SURF0_TTU_CNTL1,
1008 REFCYC_PER_REQ_DELIVERY_PRE,
1009 &ttu_attr->refcyc_per_req_delivery_pre_l);
1010
1011 REG_GET_3(DCN_SURF1_TTU_CNTL0,
1012 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
1013 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
1014 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
1015
1016 REG_GET(DCN_SURF1_TTU_CNTL1,
1017 REFCYC_PER_REQ_DELIVERY_PRE,
1018 &ttu_attr->refcyc_per_req_delivery_pre_c);
1019
1020 /* Rest of hubp */
1021 REG_GET(DCSURF_SURFACE_CONFIG,
1022 SURFACE_PIXEL_FORMAT, &s->pixel_format);
1023
1024 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
1025 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
1026
1027 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
1028 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
1029
1030 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
1031 PRI_VIEWPORT_WIDTH, &s->viewport_width,
1032 PRI_VIEWPORT_HEIGHT, &s->viewport_height);
1033
1034 REG_GET_2(DCSURF_SURFACE_CONFIG,
1035 ROTATION_ANGLE, &s->rotation_angle,
1036 H_MIRROR_EN, &s->h_mirror_en);
1037
1038 REG_GET(DCSURF_TILING_CONFIG,
1039 SW_MODE, &s->sw_mode);
1040
1041 REG_GET(DCSURF_SURFACE_CONTROL,
1042 PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
1043
1044 REG_GET_3(DCHUBP_CNTL,
1045 HUBP_BLANK_EN, &s->blank_en,
1046 HUBP_TTU_DISABLE, &s->ttu_disable,
1047 HUBP_UNDERFLOW_STATUS, &s->underflow_status);
1048
1049 REG_GET(HUBP_CLK_CNTL,
1050 HUBP_CLOCK_ENABLE, &s->clock_en);
1051
1052 REG_GET(DCN_GLOBAL_TTU_CNTL,
1053 MIN_TTU_VBLANK, &s->min_ttu_vblank);
1054
1055 REG_GET_2(DCN_TTU_QOS_WM,
1056 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
1057 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1058
1059 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
1060 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);
1061
1062 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
1063 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);
1064
1065 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
1066 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);
1067
1068 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
1069 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);
1070 }
1071
hubp1_read_state(struct hubp * hubp)1072 void hubp1_read_state(struct hubp *hubp)
1073 {
1074 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1075 struct dcn_hubp_state *s = &hubp1->state;
1076 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1077
1078 hubp1_read_state_common(hubp);
1079
1080 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1081 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1082 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1083 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1084 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
1085 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
1086 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
1087 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1088 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
1089
1090 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1091 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
1092 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
1093 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
1094 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
1095 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
1096 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
1097 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
1098 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
1099
1100 }
hubp1_get_cursor_pitch(unsigned int pitch)1101 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch)
1102 {
1103 enum cursor_pitch hw_pitch;
1104
1105 switch (pitch) {
1106 case 64:
1107 hw_pitch = CURSOR_PITCH_64_PIXELS;
1108 break;
1109 case 128:
1110 hw_pitch = CURSOR_PITCH_128_PIXELS;
1111 break;
1112 case 256:
1113 hw_pitch = CURSOR_PITCH_256_PIXELS;
1114 break;
1115 default:
1116 DC_ERR("Invalid cursor pitch of %d. "
1117 "Only 64/128/256 is supported on DCN.\n", pitch);
1118 hw_pitch = CURSOR_PITCH_64_PIXELS;
1119 break;
1120 }
1121 return hw_pitch;
1122 }
1123
hubp1_get_lines_per_chunk(unsigned int cur_width,enum dc_cursor_color_format format)1124 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk(
1125 unsigned int cur_width,
1126 enum dc_cursor_color_format format)
1127 {
1128 enum cursor_lines_per_chunk line_per_chunk;
1129
1130 if (format == CURSOR_MODE_MONO)
1131 /* impl B. expansion in CUR Buffer reader */
1132 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
1133 else if (cur_width <= 32)
1134 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
1135 else if (cur_width <= 64)
1136 line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
1137 else if (cur_width <= 128)
1138 line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
1139 else
1140 line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
1141
1142 return line_per_chunk;
1143 }
1144
hubp1_cursor_set_attributes(struct hubp * hubp,const struct dc_cursor_attributes * attr)1145 void hubp1_cursor_set_attributes(
1146 struct hubp *hubp,
1147 const struct dc_cursor_attributes *attr)
1148 {
1149 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1150 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
1151 enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk(
1152 attr->width, attr->color_format);
1153
1154 hubp->curs_attr = *attr;
1155
1156 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
1157 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
1158 REG_UPDATE(CURSOR_SURFACE_ADDRESS,
1159 CURSOR_SURFACE_ADDRESS, attr->address.low_part);
1160
1161 REG_UPDATE_2(CURSOR_SIZE,
1162 CURSOR_WIDTH, attr->width,
1163 CURSOR_HEIGHT, attr->height);
1164
1165 REG_UPDATE_3(CURSOR_CONTROL,
1166 CURSOR_MODE, attr->color_format,
1167 CURSOR_PITCH, hw_pitch,
1168 CURSOR_LINES_PER_CHUNK, lpc);
1169
1170 REG_SET_2(CURSOR_SETTINS, 0,
1171 /* no shift of the cursor HDL schedule */
1172 CURSOR0_DST_Y_OFFSET, 0,
1173 /* used to shift the cursor chunk request deadline */
1174 CURSOR0_CHUNK_HDL_ADJUST, 3);
1175 }
1176
hubp1_cursor_set_position(struct hubp * hubp,const struct dc_cursor_position * pos,const struct dc_cursor_mi_param * param)1177 void hubp1_cursor_set_position(
1178 struct hubp *hubp,
1179 const struct dc_cursor_position *pos,
1180 const struct dc_cursor_mi_param *param)
1181 {
1182 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1183 int x_pos = pos->x - param->viewport.x;
1184 int y_pos = pos->y - param->viewport.y;
1185 int x_hotspot = pos->x_hotspot;
1186 int y_hotspot = pos->y_hotspot;
1187 int src_x_offset = x_pos - pos->x_hotspot;
1188 int src_y_offset = y_pos - pos->y_hotspot;
1189 int cursor_height = (int)hubp->curs_attr.height;
1190 int cursor_width = (int)hubp->curs_attr.width;
1191 uint32_t dst_x_offset;
1192 uint32_t cur_en = pos->enable ? 1 : 0;
1193
1194 hubp->curs_pos = *pos;
1195
1196 /*
1197 * Guard aganst cursor_set_position() from being called with invalid
1198 * attributes
1199 *
1200 * TODO: Look at combining cursor_set_position() and
1201 * cursor_set_attributes() into cursor_update()
1202 */
1203 if (hubp->curs_attr.address.quad_part == 0)
1204 return;
1205
1206 // Transform cursor width / height and hotspots for offset calculations
1207 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
1208 swap(cursor_height, cursor_width);
1209 swap(x_hotspot, y_hotspot);
1210
1211 if (param->rotation == ROTATION_ANGLE_90) {
1212 // hotspot = (-y, x)
1213 src_x_offset = x_pos - (cursor_width - x_hotspot);
1214 src_y_offset = y_pos - y_hotspot;
1215 } else if (param->rotation == ROTATION_ANGLE_270) {
1216 // hotspot = (y, -x)
1217 src_x_offset = x_pos - x_hotspot;
1218 src_y_offset = y_pos - (cursor_height - y_hotspot);
1219 }
1220 } else if (param->rotation == ROTATION_ANGLE_180) {
1221 // hotspot = (-x, -y)
1222 if (!param->mirror)
1223 src_x_offset = x_pos - (cursor_width - x_hotspot);
1224
1225 src_y_offset = y_pos - (cursor_height - y_hotspot);
1226 }
1227
1228 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
1229 dst_x_offset *= param->ref_clk_khz;
1230 dst_x_offset /= param->pixel_clk_khz;
1231
1232 ASSERT(param->h_scale_ratio.value);
1233
1234 if (param->h_scale_ratio.value)
1235 dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
1236 dc_fixpt_from_int(dst_x_offset),
1237 param->h_scale_ratio));
1238
1239 if (src_x_offset >= (int)param->viewport.width)
1240 cur_en = 0; /* not visible beyond right edge*/
1241
1242 if (src_x_offset + cursor_width <= 0)
1243 cur_en = 0; /* not visible beyond left edge*/
1244
1245 if (src_y_offset >= (int)param->viewport.height)
1246 cur_en = 0; /* not visible beyond bottom edge*/
1247
1248 if (src_y_offset + cursor_height <= 0)
1249 cur_en = 0; /* not visible beyond top edge*/
1250
1251 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
1252 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
1253
1254 REG_UPDATE(CURSOR_CONTROL,
1255 CURSOR_ENABLE, cur_en);
1256
1257 REG_SET_2(CURSOR_POSITION, 0,
1258 CURSOR_X_POSITION, pos->x,
1259 CURSOR_Y_POSITION, pos->y);
1260
1261 REG_SET_2(CURSOR_HOT_SPOT, 0,
1262 CURSOR_HOT_SPOT_X, pos->x_hotspot,
1263 CURSOR_HOT_SPOT_Y, pos->y_hotspot);
1264
1265 REG_SET(CURSOR_DST_OFFSET, 0,
1266 CURSOR_DST_X_OFFSET, dst_x_offset);
1267 /* TODO Handle surface pixel formats other than 4:4:4 */
1268 }
1269
1270 /**
1271 * hubp1_clk_cntl - Disable or enable clocks for DCHUBP
1272 *
1273 * @hubp: hubp struct reference.
1274 * @enable: Set true for enabling gate clock.
1275 *
1276 * When enabling/disabling DCHUBP clock, we affect dcfclk/dppclk.
1277 */
hubp1_clk_cntl(struct hubp * hubp,bool enable)1278 void hubp1_clk_cntl(struct hubp *hubp, bool enable)
1279 {
1280 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1281 uint32_t clk_enable = enable ? 1 : 0;
1282
1283 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
1284 }
1285
hubp1_vtg_sel(struct hubp * hubp,uint32_t otg_inst)1286 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
1287 {
1288 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1289
1290 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
1291 }
1292
hubp1_in_blank(struct hubp * hubp)1293 bool hubp1_in_blank(struct hubp *hubp)
1294 {
1295 uint32_t in_blank;
1296 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1297
1298 REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank);
1299 return in_blank ? true : false;
1300 }
1301
hubp1_soft_reset(struct hubp * hubp,bool reset)1302 void hubp1_soft_reset(struct hubp *hubp, bool reset)
1303 {
1304 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1305
1306 REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0);
1307 }
1308
1309 /**
1310 * hubp1_set_flip_int - Enable surface flip interrupt
1311 *
1312 * @hubp: hubp struct reference.
1313 */
hubp1_set_flip_int(struct hubp * hubp)1314 void hubp1_set_flip_int(struct hubp *hubp)
1315 {
1316 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1317
1318 REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT,
1319 SURFACE_FLIP_INT_MASK, 1);
1320
1321 return;
1322 }
1323
1324 /**
1325 * hubp1_wait_pipe_read_start - wait for hubp ret path starting read.
1326 *
1327 * @hubp: hubp struct reference.
1328 */
hubp1_wait_pipe_read_start(struct hubp * hubp)1329 static void hubp1_wait_pipe_read_start(struct hubp *hubp)
1330 {
1331 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1332
1333 REG_WAIT(HUBPRET_READ_LINE_STATUS,
1334 PIPE_READ_VBLANK, 0,
1335 1, 1000);
1336 }
1337
hubp1_init(struct hubp * hubp)1338 void hubp1_init(struct hubp *hubp)
1339 {
1340 //do nothing
1341 }
1342 static const struct hubp_funcs dcn10_hubp_funcs = {
1343 .hubp_program_surface_flip_and_addr =
1344 hubp1_program_surface_flip_and_addr,
1345 .hubp_program_surface_config =
1346 hubp1_program_surface_config,
1347 .hubp_is_flip_pending = hubp1_is_flip_pending,
1348 .hubp_setup = hubp1_setup,
1349 .hubp_setup_interdependent = hubp1_setup_interdependent,
1350 .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings,
1351 .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings,
1352 .set_blank = hubp1_set_blank,
1353 .dcc_control = hubp1_dcc_control,
1354 .mem_program_viewport = min_set_viewport,
1355 .set_hubp_blank_en = hubp1_set_hubp_blank_en,
1356 .set_cursor_attributes = hubp1_cursor_set_attributes,
1357 .set_cursor_position = hubp1_cursor_set_position,
1358 .hubp_disconnect = hubp1_disconnect,
1359 .hubp_clk_cntl = hubp1_clk_cntl,
1360 .hubp_vtg_sel = hubp1_vtg_sel,
1361 .hubp_read_state = hubp1_read_state,
1362 .hubp_clear_underflow = hubp1_clear_underflow,
1363 .hubp_disable_control = hubp1_disable_control,
1364 .hubp_get_underflow_status = hubp1_get_underflow_status,
1365 .hubp_init = hubp1_init,
1366
1367 .dmdata_set_attributes = NULL,
1368 .dmdata_load = NULL,
1369 .hubp_soft_reset = hubp1_soft_reset,
1370 .hubp_in_blank = hubp1_in_blank,
1371 .hubp_set_flip_int = hubp1_set_flip_int,
1372 .hubp_wait_pipe_read_start = hubp1_wait_pipe_read_start,
1373 };
1374
1375 /*****************************************/
1376 /* Constructor, Destructor */
1377 /*****************************************/
1378
dcn10_hubp_construct(struct dcn10_hubp * hubp1,struct dc_context * ctx,uint32_t inst,const struct dcn_mi_registers * hubp_regs,const struct dcn_mi_shift * hubp_shift,const struct dcn_mi_mask * hubp_mask)1379 void dcn10_hubp_construct(
1380 struct dcn10_hubp *hubp1,
1381 struct dc_context *ctx,
1382 uint32_t inst,
1383 const struct dcn_mi_registers *hubp_regs,
1384 const struct dcn_mi_shift *hubp_shift,
1385 const struct dcn_mi_mask *hubp_mask)
1386 {
1387 hubp1->base.funcs = &dcn10_hubp_funcs;
1388 hubp1->base.ctx = ctx;
1389 hubp1->hubp_regs = hubp_regs;
1390 hubp1->hubp_shift = hubp_shift;
1391 hubp1->hubp_mask = hubp_mask;
1392 hubp1->base.inst = inst;
1393 hubp1->base.opp_id = OPP_ID_INVALID;
1394 hubp1->base.mpcc_id = 0xf;
1395 }
1396
1397
1398